CN117784516A - Layout splitting method and preparation method of contact holes and through holes - Google Patents
Layout splitting method and preparation method of contact holes and through holes Download PDFInfo
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Abstract
The invention relates to a layout splitting method for preparing contact holes/through holes in an advanced process, which comprises the following steps: (1) For an original layout, grouping all hole patterns according to the hole multiplication capacity of a physical epitaxial method-oriented self-assembly technology, wherein the hole patterns with the distance smaller than or equal to a preset value are paired and grouped; (2) Setting the size and shape of the guide template of each group for each group grouped in step (1); (3) According to the grouping result in the step (1) and the size and shape of each group of guide template set in the step (2), carrying out graphic size adjustment on the original layout to generate a guide template layout; and (4) splitting the guide template layout generated in the step (3) according to a first layout splitting mode to obtain a plurality of splitting layers.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a layout splitting method used in the process of preparing contact holes/through holes of a prior process logic chip.
Background
With the rapid rise of the emerging scientific and technological industries such as 5G, artificial intelligence, meta-universe and the like, massive data are promoted to generate huge calculation power demands, so that high-performance and large calculation power chips are driven to become the driving force and new trend of industry development. The market demand for high-performance chips is increasingly vigorous, and the iteration cycle of the chips is further accelerated, so that chip design enterprises are stimulated to continuously improve the chip technology content and shorten the delivery time, and the core competitiveness is improved.
For example, in process nodes of 7nm and below for logic chips, the minimum design rules for contact/via layers have broken through the resolution limit of the mainstream 193nm immersion lithography. To achieve small cycle contact/via patterns, DUV 193i multiple exposure techniques (Multi-patterning l ithography, MPL) are required to meet the requirements.
The traditional MPL technology is to relatively and uniformly split an original design layout into a plurality of layers (layers) which can be prepared by one-time exposure according to the resolution limit of a photoetching machine, and then sequentially execute key process flows such as photoetching, etching and the like according to the sequence, so that the requirements on the alignment precision and the local line width uniformity of the photoetching machine are very high. For example, in the manufacture of a 7nm node logic chip, for a V0 layer hole array of an SRAM region in a layout, four photomasks are required to realize the preparation of the array when the layout is split according to a layout splitting manner of a conventional multiple exposure technology (see fig. 1).
Disclosure of Invention
However, since the conventional MPL technology has complicated process steps, the increase of the number of exposure layers leads to an increase in cost and difficulty in process control, and thus the number of exposure layers cannot be increased without limitation. In addition, although the number of exposure layers can be reduced after the lithography resolution of the extreme ultraviolet lithography (EUV) technology is improved, the price of the EUV lithography machine is too high and the productivity is too low, which is not an economical high-resolution patterning scheme, and a solution capable of achieving both precision and cost is urgently needed in the industry.
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a layout design for use in the preparation of contact holes/through holes of a prior process logic chip, which is capable of performing a pattern size adjustment on an original layout according to the result of a DSA-based process capability and the size and shape of a guide template set for each group to generate a guide template layout, and splitting the generated guide template layout according to a first layout splitting manner to obtain a plurality of splitting layers, so that the number of masks used is smaller, the process steps are fewer, and the stability of the process, the reduction of the defect rate and the improvement of the yield are facilitated, compared with the conventional multiple exposure process route.
Technical proposal for solving the technical problems
In order to solve the above problem, the layout splitting method according to the first aspect of the present invention includes the following steps:
(1) For an original layout, grouping all hole patterns according to the hole multiplication capacity of a physical epitaxial method-oriented self-assembly technology, wherein the hole patterns with the distance smaller than or equal to a preset value are paired and grouped;
(2) Setting the size and shape of the guide template of each group for each group grouped in step (1);
(3) Performing graphic size adjustment on the original layout according to the grouping result in the step (1) and the size and shape of the guide template of each group set in the step (2), and generating a guide template layout; and
(4) Splitting the guide template layout generated in the step (3) according to a first layout splitting mode to obtain a plurality of splitting layers, wherein the first layout splitting mode comprises the following principles: the minimum spacing between the grouped guide templates of each group in the same split layer is equal to or greater than the resolution of the lithographic machine used to manufacture the guide templates.
Further, the number of the plurality of split layers obtained by splitting in the step (4) is smaller than the number of the plurality of split layers obtained by splitting the original layout according to a second layout splitting mode, and the second layout splitting mode comprises the following principles: the minimum pitch between the hole patterns in the same split layer is equal to or greater than the resolution of the lithography machine used to manufacture the hole patterns.
Further, the shapes of the guide templates of the respective groups after grouping include at least one of a circle, a racetrack, an ellipse, a peanut, a tee, and an L.
Further, the original layout is a layout for manufacturing contact holes or through holes of a process memory below 7 nm.
Further, the method also comprises the following steps:
(5) Checking a plurality of split layers obtained by splitting in the step (4); and
(6) Judging whether the checking result in the step (5) violates a preset splitting rule, and adjusting the rule of the pairing group in the step (1) when the checking result in the step (5) violates the preset splitting rule, and repeatedly executing the step (2), the step (3), the step (4) and the step (5) until the preset splitting rule is met.
Further, the predetermined splitting rule includes the following principles: the plurality of hole patterns having a distance of a predetermined distance or less from each other are not split into one split layer except for the group of the paired groups in step (1).
Further, the predetermined distance is 110nm or 96nm.
In the method for manufacturing a contact hole or a through hole according to the second aspect of the present invention, the method includes the steps of:
(a) Splitting by using the layout splitting method to obtain a plurality of splitting layers;
(b) Performing optical proximity effect correction on each split layer obtained by splitting in the step (a) to obtain a photomask subjected to pairing grouping and a photomask not subjected to pairing grouping;
(c) Transferring a guide template to a substrate by using a physical epitaxy guide self-assembly process for the paired and grouped photomasks to prepare contact holes or through holes; and
(d) For unpaired reticles, the hole pattern is transferred to the substrate using a photolithographic process or using a physical epitaxy directed self-assembly process to make contact holes or vias.
A third aspect of the present invention relates to a computer readable medium having stored thereon a computer program which, when executed by a processor, implements the layout splitting method described above.
In a fourth aspect of the present invention, a computer device includes: the layout splitting method is characterized by comprising a memory, a processor and a computer program which is stored in the memory and can run on the processor, and the layout splitting method is realized when the processor executes the computer program.
Effects of the invention
According to the layout splitting method, compared with the traditional multiple exposure technical route, the number of used photomasks is smaller, the process steps are fewer, and the method is favorable for process stability, defect rate reduction and yield improvement.
In addition, according to the layout splitting method, the DSA technology can be used for forming the contact holes/through holes corresponding to the hole patterns matched with the groups, so that compared with the traditional photoetching multiple exposure technical route, the critical dimension is reduced, and the requirement of the dimension reduction under the prior process can be met.
In addition, according to the layout splitting method, the process of converting the hole pattern pairing grouping into the guiding template layout is added only by one step, and the subsequent processes are the same as the traditional layout splitting mode, so that the traditional layout splitting rule can be directly applied.
Drawings
Fig. 1 is a schematic diagram showing a case of splitting into four split layers in the case of splitting a layout according to a splitting rule of a conventional multiple exposure technique.
Fig. 2 is a schematic diagram showing the conversion of an original layout into a guiding template layout and the splitting into three guiding template layout splitting layers in a layout splitting method according to an embodiment of the present invention.
Fig. 3 is a schematic diagram showing an example of splitting into three split layers in the case of splitting a layout by using the layout splitting method according to the embodiment of the present invention.
Fig. 4 is a schematic diagram showing an example of splitting into two split layers in the case of splitting a layout by using the layout splitting method according to the embodiment of the present invention.
Fig. 5 is a flowchart showing a first example of a layout splitting method according to an embodiment of the present invention.
Fig. 6 is a flowchart showing a second example of the layout splitting method according to the embodiment of the present invention.
Fig. 7 is a schematic diagram showing examples of single hole shrinkage, double hole multiplication, and triple hole multiplication under restricted areas of different shapes and sizes using directed self-assembly techniques.
Description of the reference numerals
1001. First group of
1002. Second group of
1003. Third group of
Detailed Description
The invention will be described in detail below with reference to the drawings and the detailed description. The present embodiment is implemented on the premise of the technical scheme of the present invention, and a detailed embodiment and a specific operation process are given, but the protection scope of the present invention is not limited to the following embodiments.
Spatially relative terms, such as "under," "below," "lower," "over," "upper," and the like, may be used herein for convenience of description to describe one element or feature's relationship to another element or feature as illustrated. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features.
Unless otherwise defined, terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. The terms are to be understood to have meanings consistent with the context of the relevant art and are not to be construed as idealized or overly formal unless expressly so defined herein.
Next, a layout splitting method according to an embodiment of the present invention will be described in detail with reference to fig. 2 to 6.
(first embodiment)
Fig. 5 is a flowchart showing a first example of a layout splitting method according to an embodiment of the present invention. Fig. 2 is a schematic diagram showing the conversion of an original layout into a guiding template layout and the splitting into three guiding template layout splitting layers in a layout splitting method according to an embodiment of the present invention. Fig. 3 is a schematic diagram showing an example of splitting into three split layers in the case of splitting a layout by using the layout splitting method according to the embodiment of the present invention. Fig. 4 is a schematic diagram showing an example of splitting into two split layers in the case of splitting a layout by using the layout splitting method according to the embodiment of the present invention.
As shown in fig. 5, an example of a layout splitting method according to an embodiment of the present invention includes the following steps.
First, in step ST101, for an original layout, individual hole patterns are grouped according to hole multiplication capability of a physical epitaxy-oriented self-assembly technique, wherein hole patterns having a distance of a predetermined value or less from each other are paired and grouped.
Among them, the Directed Self-Assembly (DSA) technology is a new "bottom-up" lithography technology based on Block Copolymers (BCP), which is now receiving high attention from the semiconductor industry, and its principle is quite different from that of conventional optical lithography and electron beam lithography. Guided self-assembly of block copolymers has been listed by the international equipment and system roadmap (IRDS) as a candidate for the next generation semiconductor chip production technology. DSA has the advantages of high throughput, high efficiency, low cost, compatibility with industrial semiconductor processes, and the like. Up to now DSA has been widely used for the fabrication of non-volatile memories, fin field effect transistors, photonic nano-devices, etc.
Block copolymers are a special class of polymers formed from two or more homopolymers of distinct chemical properties joined by covalent bonds. As an example, the block copolymers of the present invention may be of the type A-block-B (type A-B-B), which is also the most widely studied type of block copolymer in the DSA field.
Microphase separation (Microphase Separation) of block copolymers is directly related to χN, where χ is the flory-Hajin interaction parameter between homopolymer A and homopolymer B and N is the total degree of polymerization of the block copolymer. When the χN value of the block copolymer is smaller, microphase separation does not occur, and the molecular chain is in a disordered structure; microphase separation occurs when the χn value is greater than the threshold for disorder to order state conversion, and the molecular chains begin to move and self-assemble to form an ordered structure. The block copolymer undergoes microphase separation to form a periodic structure, the period (Pitch) of which is the period of intrinsic phase separation L 0 And (3) representing.
The self-assembly of the block copolymer to form an ordered structure is a result of the volume fraction f (f) A Or f B ) And (5) determining. The phase diagram of a-block-B block copolymers can be predicted according to Self-consistent field theory (Self-consistent Field Theory, SCFT). With the volume fraction f of homopolymer A A Gradually increasing, self-assembling to form ordered nano-structures which are sequentially: a body centered Cubic (Cubic) spherical phase (BCC), a Hexagonal columnar phase (HEX), a bicontinuous helical phase (Gyroid, GYR), and a Lamellar phase (lamella, LAM). The most widely used in DSA lithography is columnar phase and lamellar phase, which have a vertically penetrating structure, so that selective etching is easier to perform, and high-contrast patterns are obtained. The pattern of holes in the present invention corresponds to the columnar phase therein.
Further, as an example, the block copolymer in the present invention may be Polystyrene-b-polymethyl methacrylate (Polystyrene-b-Poly (methyl methacrylate), abbreviated as PS-b-PMMA), which is the most widely studied block copolymer. The block copolymer in the present invention is not limited to this, and may be polystyrene-b-polyisoprene (PS-b-PI), polystyrene-b-polylactic acid (PS-b-PLA), polystyrene-b-polydimethylsiloxane (PS-b-PDMS), polystyrene-b-polytrimethylene carbonate (PS-b-PTMC), polystyrene-b-polypropylene carbonate (PS-b-PPC), poly (4-t-butylstyrene) -b-polymethyl methacrylate (PtBS-b-PMMA), poly (4-methoxystyrene) -b-poly (4-trimethylsilylstyrene) (PMOST-b-PTMS), polystyrene-b-polyacrylic acid acetonide (PS-b-PSA), polystyrene-b-polylactic acid glycolic acid (PS-b-PLGA), polystyrene-b-polymethyl acrylate (PS-b-PMA), polystyrene-b-polymethacrylate acetonide (PS-b-PPC), polystyrene-b-poly (4-hydroxystyrene) (PS-b-PSM), polystyrene-b-2-PHS, 2-ethyl methacrylate (PSM), poly (4-tert-butylstyrene) -b-poly (2-vinylpyridine) (PtBS-b-P2 VP), polyvinylcyclohexane-b-polymethylmethacrylate (PCHE-b-PMMA), polydimethylsiloxane-b-polymethylmethacrylate (PDMS-b-PMMA), polystyrene-b-poly pentadecafluorooctylmethacrylate (PS-b-PPDFMA), poly (2-vinylpyridine) -b-poly (heptafluorobutyl-2-methylpropan-2-enoic acid ester) (P2 VP-b-PHFBMA), poly (3-hydroxystyrene) -b-polydimethylsiloxane (P3 HS-b-PDMS), polystyrene-b-polyglycerol acrylate (PS-b-PGA), polystyrene-b-polyhydroxyisobutylene (PS-b-PiBOH), polystyrene-b-polyacrylic acid (PS-b-PAA), polystyrene-b-poly (3, 4-dihydroxystyrene) (PS-b-PDHS), poly (4-trimethylstyrene) -b-poly (SS-b-lactic acid) (PTMC-B-PLA), other block copolymers such as polystyrene-b-poly (2, 3-dihydroxypropyl methacrylate) (PS-b-PGM).
In addition, the physical epitaxial method guiding self-assembly technology is to self-assemble the segmented copolymer in the groove type guiding template, so that the segmented copolymer is more applied to line and hole array patterns, and has the advantages of simple process, large tolerance, few defects, accurate pattern positioning and the like. As an example, the above-described groove-type guide template can be prepared by using DUV 193i exposure, and by adjusting the matching degree of the block copolymer material and the limited region, various pattern combinations with feature periods less than or equal to the resolution of the conventional DUV 193i can be formed, which can be used for preparing the contact hole/via layer of the logic chip under the advanced process.
By utilizing a physical epitaxy directed self-assembly technique, miniaturization and number multiplication of pore feature sizes can be achieved in a limited area. Fig. 7 is a schematic diagram showing examples of single hole shrinkage, double hole multiplication, and triple hole multiplication under restricted areas of different shapes and sizes using directed self-assembly techniques. As shown in fig. 7, in the circular hole type limited region, shrinkage of the hole is formed, and as the aspect ratio of the limited region changes, two-fold, three-fold, four-fold, and the like of the hole are gradually formed. Under the condition that the DSA materials are the same, the double-hole spacing after hole multiplication is related to the major axis and the minor axis of the limited space, and can be adjusted within a certain range.
Then, in step ST102, for each group grouped in step ST101, the size and shape of the guide template for each group are set. In the example of fig. 2, for a group consisting of two hole patterns, the shape of the guide template is, for example, elliptical (second group from left to right in fig. 7) or racetrack (third group from left to right in fig. 7); for the group consisting of the individual hole patterns, the shape of the guide templates thereof is, for example, circular (first group from left to right in fig. 7). Furthermore, the shape of the guide templates depends on the grouping requirements of the DSAs and manufacturability of the templates, including, but not limited to, round, racetrack, oval, peanut, t, L, etc. shapes. In addition, the size of each group of guide templates is a size that meets the graphics shrink requirements.
Then, in step ST103, the original layout is subjected to pattern size adjustment based on the result of grouping in step ST101 and the size and shape of the guide template for each group set in step ST102, and a guide template layout is generated. In fig. 2, the second diagram from left to right is an example of the generated guidance template layout.
Then, in step ST104, the guiding template layout generated in step ST103 is split according to the first layout splitting pattern to obtain a plurality of split layers.
The layout splitting technology refers to: and (3) corresponding to the MPL, finding out dense patterns with the pattern spacing smaller than or equal to the reference distance on the layout by taking the resolution limit of lithography as a reference, and splitting the dense patterns into a plurality of groups of sparse patterns according to the conflict relation between the dense patterns, wherein the minimum spacing of each group of patterns is larger than or equal to the resolution limit of a lithography machine and is distributed on different masks (corresponding to splitting layers), so that the mask requirement of the MPL is met. The traditional layout splitting mode only considers the geometric conflict relation among the original graphs, and does not need to consider the conflict relation of combining a plurality of graphs and the combined graphs, which is the largest difference between the traditional layout splitting mode (the second layout splitting mode) and the layout splitting mode (the first layout splitting mode) which is applicable to the DSA technology.
Specifically, the first layout splitting mode comprises the following principles: the minimum spacing between the grouped guide templates of each group in the same split layer is equal to or greater than the resolution of the lithography machine used to make the hole pattern and guide templates. In addition, the first layout splitting pattern also requires that the density of the hole patterns of the respective splitting layers be substantially uniform.
The second layout splitting mode comprises the following principles: the minimum pitch between the hole patterns in the same split layer is equal to or greater than the resolution of the lithography machine used to make the hole patterns. In addition, the second layout splitting pattern also requires that the density of the hole patterns of the respective splitting layers be substantially uniform.
In the example of fig. 3, three split levels, namely split level 1, split level 2, split level 3, are split according to the first layout splitting pattern. The split layer 1 includes a first group 1001, a second group 1002, and a third group 1003 obtained by pairing and grouping the hole patterns in step ST 101. In addition, the first layout splitting manner adopted in the example of fig. 3 includes the following principles: the plurality of hole patterns having a distance from each other equal to or smaller than the predetermined distance (=110 nm) are not split into one split layer except for the group of the pairing group in step ST 101. In the example of fig. 3, the number of split layers (3) obtained by splitting in step ST104 is smaller than the number of split layers (4) obtained by splitting the original layout according to the second layout splitting pattern (fig. 1). The second layout splitting mode refers to a layout splitting mode of a traditional multiple exposure technology.
In the example of fig. 4, according to the first layout splitting pattern, two splitting layers, namely splitting layer 1', splitting layer 2', are split. The split layer 1' includes the first group 1001, the second group 1002, and the third group 1003 obtained by pairing in step ST 101. In addition, the first layout splitting manner adopted in the example of fig. 4 includes the following principles: the plurality of hole patterns having a distance from each other equal to or smaller than the predetermined distance (=96 nm) are not split into one split layer except for the group of the pairing group in step ST 101. In the example of fig. 4, the number of split layers (2) obtained by splitting in step ST104 is smaller than the number of split layers (4) obtained by splitting the original layout according to the second layout splitting pattern (fig. 1).
In addition, in the examples of fig. 3 and 4, the grouped guide templates of each group may be prepared using, for example, a 193nm DUV immersion lithography machine, although the invention is not limited thereto. In addition, in the examples of fig. 3 and 4, the original version is illustrated as a layout for manufacturing a contact/via array of a process memory (SRAM) below 7nm, but the present invention is not limited thereto.
Therefore, compared with the traditional multiple exposure technical route, the layout splitting method according to the first embodiment of the invention can enable the number of used photomasks to be smaller, has fewer process steps, and is beneficial to process stability, defect rate reduction and yield improvement.
In addition, according to the layout splitting method according to the first embodiment of the present invention, since the DSA process can be used to form the contact holes/vias corresponding to the hole patterns paired in groups, compared with the conventional photolithographic multiple exposure technical route, the critical dimension can be reduced, and the requirement of the dimension reduction under the advanced process can be more satisfied.
In addition, according to the layout splitting method related to the first embodiment of the invention, the process of converting the hole pattern pairing grouping into the guiding template layout is added only by one step, and the subsequent processes are the same as the traditional layout splitting mode, so that the traditional layout splitting rule can be directly applied.
(second embodiment)
Fig. 6 is a flowchart showing a second example of the layout splitting method according to the embodiment of the present invention.
As shown in fig. 6, a second example of the layout splitting method according to the embodiment of the present invention includes the following steps.
First, in step ST101, for an original layout, individual hole patterns are grouped according to hole multiplication capability of a physical epitaxy-oriented self-assembly technique, wherein hole patterns having a distance of a predetermined value or less from each other are paired and grouped.
Then, in step ST102, for each group grouped in step ST101, the size and shape of the guide template for each group are set.
Then, in step ST103, the original layout is subjected to pattern size adjustment based on the result of grouping in step ST101 and the size and shape of the guide template for each group set in step ST102, and a guide template layout is generated.
Then, in step ST104, the guiding template layout generated in step ST103 is split according to the first layout splitting pattern to obtain a plurality of split layers.
Steps ST101 to ST104 above are similar to those of the first embodiment.
Then, in step ST105, the plurality of split layers obtained by splitting in step ST104 are inspected.
Then, in step ST106, it is determined whether or not the inspection result violates a predetermined split rule, and in the case where the inspection result in step ST105 violates the predetermined split rule, the rule of the pairing group in step ST101 is adjusted, and step ST102, step ST103, step ST104, and step ST105 are repeatedly executed until the predetermined split rule is satisfied.
Therefore, according to the layout splitting method according to the second embodiment of the present invention, in addition to the effects that can be achieved by the first embodiment, the pairing grouping mode of the original layout can be continuously and iteratively optimized according to the splitting result until the two requirements of the process capability of the DSA and the manufacturability of the guide template can be simultaneously met.
In addition, the invention also provides a preparation method of the contact hole or the through hole, which comprises the following steps:
(a) Splitting by using the layout splitting method to obtain a plurality of splitting layers;
(b) Performing optical proximity effect correction (Optical Proximity Correction; OPC) on each split layer obtained by splitting in the step (a) to obtain a photomask subjected to pairing grouping and a photomask not subjected to pairing grouping;
(c) Transferring a guide template to a substrate by using a physical epitaxy guide self-assembly process for the paired and grouped photomasks to prepare contact holes or through holes; and
(d) For unpaired reticles, the hole pattern is transferred to the substrate using a photolithographic process or using a physical epitaxy directed self-assembly process to make contact holes or vias.
The specific process of transferring the guiding template to the substrate by using the physical epitaxy guiding self-assembly technology to prepare the contact hole or the through hole is as follows: the block copolymer is coated after the molecular brush is coated on the guide template, and the annealing process is utilized to drive the block copolymer to conduct microphase separation, so that the block copolymer is self-assembled on the substrate, then the ordered structure formed after self-assembly is selectively etched, and finally the hole pattern is transferred onto the substrate by utilizing the etching technology or the deposition technology.
In addition, for an unpaired reticle, the specific process of transferring a hole pattern onto a substrate using a photolithographic process to make contact holes or vias is as follows: firstly, ultraviolet light irradiates the surface of a substrate attached with a layer of photoresist film through a photomask which is not matched and grouped, and causes the photoresist in an exposure area to generate chemical reaction; then, dissolving and removing the photoresist in the exposed area or the unexposed area by a developing technology, so that the hole pattern on the photomask is copied to the photoresist film; finally, the hole pattern is transferred to the substrate using etching techniques or deposition techniques.
In addition, for an unpaired reticle, the specific process of transferring a hole pattern onto a substrate using a physical epitaxy directed self-assembly process to make contact holes or vias is as follows: and coating a molecular brush on the hole patterns on the unpaired photomask, coating a block copolymer, driving the block copolymer to conduct microphase separation by using an annealing process, so that the block copolymer is self-assembled on a substrate, selectively etching an ordered structure formed after self-assembly, and finally transferring the hole patterns onto the substrate by using an etching technology or a deposition technology.
Furthermore, the present invention provides a computer readable medium having stored thereon a computer program which, when executed by a processor, implements the layout splitting method described above.
In addition, the present invention also provides a computer device, including: the layout splitting method comprises a memory, a processor and a computer program which is stored in the memory and can run on the processor, wherein the processor realizes the layout splitting method when executing the computer program.
Industrial applicability
The layout splitting method can be applied to the preparation of the contact holes/through holes of the prior process logic chip.
Claims (10)
1. A layout splitting method is characterized by comprising the following steps:
(1) For an original layout, grouping all hole patterns according to the hole multiplication capacity of a physical epitaxial method-oriented self-assembly technology, wherein the hole patterns with the distance smaller than or equal to a preset value are paired and grouped;
(2) Setting the size and shape of the guide template of each group for each group grouped in step (1);
(3) Performing graphic size adjustment on the original layout according to the grouping result in the step (1) and the size and shape of the guide template of each group set in the step (2), and generating a guide template layout; and
(4) Splitting the guide template layout generated in the step (3) according to a first layout splitting mode to obtain a plurality of splitting layers, wherein the first layout splitting mode comprises the following principles: the minimum spacing between the grouped guide templates of each group in the same split layer is equal to or greater than the resolution of the lithographic machine used to manufacture the guide templates.
2. The layout splitting method according to claim 1, wherein,
the number of the plurality of split layers obtained by splitting in the step (4) is smaller than the number of the plurality of split layers obtained by splitting the original layout according to a second layout splitting mode, wherein the second layout splitting mode comprises the following principles: the minimum pitch between the hole patterns in the same split layer is equal to or greater than the resolution of the lithography machine used to manufacture the hole patterns.
3. The layout splitting method according to claim 1 or 2, wherein,
the shape of each group of guide templates after grouping comprises at least one of round shape, racetrack shape, oval shape, peanut shape, T shape and L shape.
4. The layout splitting method according to claim 1 or 2, wherein,
the original layout is a layout for manufacturing contact holes or through holes of a process memory below 7 nm.
5. The layout splitting method according to claim 1 or 2, further comprising the steps of:
(5) Checking a plurality of split layers obtained by splitting in the step (4); and
(6) Judging whether the checking result in the step (5) violates a preset splitting rule, and adjusting the rule of the pairing group in the step (1) when the checking result in the step (5) violates the preset splitting rule, and repeatedly executing the step (2), the step (3), the step (4) and the step (5) until the preset splitting rule is met.
6. The layout splitting method according to claim 5, wherein,
the predetermined splitting rule includes the following principles: the plurality of hole patterns having a distance of a predetermined distance or less from each other are not split into one split layer except for the group of the paired groups in step (1).
7. The layout splitting method according to claim 6, wherein,
the predetermined distance is 110nm or 96nm.
8. The preparation method of the contact hole or the through hole is characterized by comprising the following steps:
(a) Splitting using the layout splitting method of any of claims 1 to 7 to obtain a plurality of split levels;
(b) Performing optical proximity effect correction on each split layer obtained by splitting in the step (a) to obtain a photomask subjected to pairing grouping and a photomask not subjected to pairing grouping;
(c) Transferring a guide template to a substrate by using a physical epitaxy guide self-assembly process for the paired and grouped photomasks to prepare contact holes or through holes; and
(d) For unpaired reticles, the hole pattern is transferred to the substrate using a photolithographic process or using a physical epitaxy directed self-assembly process to make contact holes or vias.
9. A computer readable medium having stored thereon a computer program which, when executed by a processor, implements the layout splitting method of any of claims 1 to 7.
10. A computer device, comprising: memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the layout splitting method according to any of claims 1 to 7 when executing the computer program.
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