CN117766642A - Preparation method of micro-LED chip array based on maskless secondary epitaxy - Google Patents
Preparation method of micro-LED chip array based on maskless secondary epitaxy Download PDFInfo
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Abstract
The invention discloses a preparation method of a micro-LED chip array based on maskless secondary epitaxy. According to the invention, the GaN template is subjected to dry etching to form the stress relaxation graphical GaN template, and then the structures such as the secondary epitaxial multi-quantum well and the like are selected on the basis of the stress relaxation graphical GaN template, so that the dry etching of the multi-quantum well region is effectively avoided, and the side wall etching damage of the multi-quantum well is avoided; stress relaxation patterning the GaN template enables stress on n-type doped GaN to be effectively relaxed; the prestress layer grown on the stress relaxation graphical GaN template is subjected to partial relaxation, and the in-plane lattice constant is expanded, so that the energy required by indium incorporation is reduced, and the incorporation of indium in the multi-quantum well is increased; etching in preparing stress relaxation graphical GaN templates, so that only the top surface of the GaN micron column array is a c-plane and is used as a growth surface; and the selective secondary epitaxial growth does not need an extra mask, so that the complexity of the micro-LED preparation process is reduced.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to a preparation method of a micro-LED chip array based on maskless secondary epitaxy.
Background
Large-sized blue Light Emitting Diodes (LEDs) based on group iii nitride semiconductors play an important role in the field of solid state lighting, thanks to its high efficiency and high stability. When the application scene is switched to the display field, micro-light emitting diode (micro-LED) devices with ultra-small size and full color are important requirements, especially for applications such as augmented reality (augmented reality, AR) and Virtual Reality (VR). Micro-LEDs have significant advantages in terms of brightness, contrast, response speed, stability, etc. compared to liquid crystal displays (liquid crystal display, LCDs) in display applications.
As devices are continuously miniaturized, micro-LEDs have the problem of a gradual decrease in efficiency as the size decreases. Studies have shown that micro-LEDs will be more severely affected by defective recombination as the size decreases. These defects may originate mainly from sidewall dangling bonds and damage from dry etching. Although the damage caused by dry etching is only the nano-scale depth of the micro-LED sidewall surface, there is severe non-radiative recombination in the sidewall region due to carrier diffusion and high recombination rate of the sidewall surface state. For etching damage of the micro-LED chip side wall, currently, a side wall repairing means such as Atomic Layer Deposition (ALD) silicon dioxide layer, KOH solution etching and the like is generally adopted (opt. Express 26,21324 (2018), appl. Phys. Express12,097004 (2019)). However, these means of sidewall repair have difficulty in completely eliminating the etching damage, and micro-LEDs still have a problem of efficiency dip with size reduction. And in the micro-LED process from top to bottom, the damage of the side wall caused by dry etching cannot be avoided.
On the other hand, high indium (In) component, long wavelength micro-LEDs also face the problem of low efficiency due to too large lattice mismatch between indium nitride (InN) and gallium nitride (GaN). This efficiency drop with increasing wavelength results mainly from the high defect density caused by low temperature growth and the strongly polarized electric field caused by InGaN strain. The strongly polarized electric field in the quantum well can spatially separate electrons and holes, which severely reduces the radiative recombination efficiency of long wavelength LEDs. On the other hand, indium incorporation efficiency is related to the strain energy required for In-N bond bonding, and indium incorporation is more difficult when there is a strong compressive strain In the equivalent quantum well due to the higher strain energy required (j. Cryst. Growth 312,735-749 (2010)). Thus, relieving compressive strain in InGaN helps to improve radiative recombination efficiency in the quantum well and increase indium incorporation efficiency.
Eliminating the sidewall etch damage of micro-LEDs and solving the compressive strain problem of InGaN are critical to achieving high efficiency long wavelength LEDs. Currently, the main preparation process of long wavelength micro-LEDs is realized by etching from top to bottom, few methods for preparing LEDs from bottom to top are adopted in the past, the method mainly occurs in the field of molecular beam epitaxy (molecular beam epitaxy, MBE) of nano-pillar LEDs, and a small part of researches relate to the field of metal-organic chemical vapor deposition (metal-organic chemical vapor deposition, MOCVD). The compressive stress of InGaN of the nano-pillar LED obtained by the top-down secondary epitaxy method can be effectively relaxed, which is helpful for realizing the incorporation of indium in the quantum well. The nanopillar LED structure prepared by the secondary epitaxy proved to be effective in improving the luminous efficiency of long wavelength LEDs (photon. Res.10,2809 (2022), appl. Phys. Lett.122,151103 (2023)). However, MBE is difficult to apply to large-scale mass production of micro-LEDs due to low yield, high cost, etc., and the secondary epitaxy method of nanopillar LEDs requires a nanoscale pattern mask, which is difficult to be compatible with the existing micro-LED process. In recent years, the micro LED is also partially researched and adopted on a patterned silicon dioxide mask through MOCVD secondary epitaxy, and the etching damage is effectively avoided in the mode, and the stress relaxation effect is obvious. However, the process conditions for preparing the silicon dioxide mask are complex and costly (ACS Photonics 2020,7,411 (2020), ACS Photonics 9,2073 (2022)). Therefore, there is a need to propose a maskless secondary epitaxy scheme based on MOCVD, reducing cost and process complexity for improving the luminous efficiency of long wavelength micro-LEDs.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a preparation method of a micro-LED chip array based on maskless secondary epitaxy, which is different from the method for preparing the micro-LED chip by top-down etching adopted in the current industry, and the preparation of the micro-LED chip array is completed by performing graphical processing on a GaN template and then performing maskless secondary epitaxy.
The preparation method of the micro-LED chip array based on maskless secondary epitaxy comprises the following steps:
1) Providing a substrate, placing the substrate into a Metal Organic Chemical Vapor Deposition (MOCVD) reaction chamber, and epitaxially growing an unintentionally doped GaN layer and an n-type doped GaN layer on the substrate from bottom to top in sequence by an MOCVD method to obtain a planar GaN template;
2) After the growth is completed, taking out the planar GaN template from the MOCVD reaction chamber, and cleaning;
3) Carrying out dry etching on the planar GaN template by adopting a photoetching or nano-imprinting mode, etching part of the n-type doped GaN layer to form a GaN micron column array, wherein the GaN micron columns are in a truncated cone shape, the side walls are provided with inclination angles, and the bottoms of the adjacent GaN micron columns are connected with each other, so that the stress relaxation graphical GaN template is obtained;
the bottom of the GaN micron column array of the stress relaxation graphical GaN template is connected with each other, no c-plane for growth exists, the side wall of the GaN micron column array is a curved surface, no complete plane crystal face exists, no c-plane for growth exists, and only the top surface of the GaN micron column array is the c-plane and serves as a growth plane;
after the stress relaxation graphical GaN template is used for carrying out graphical treatment on the n-type doped GaN layer, the stress suffered by the n-type doped GaN is effectively relaxed;
4) Cleaning the stress relaxation graphical GaN template, and placing the template back to the MOCVD reaction chamber;
5) On a GaN micro-column array of a stress relaxation patterned GaN template, secondarily epitaxially growing an n-type doped GaN thin layer, wherein the secondarily epitaxially grown n-type doped GaN thin layer and GaN micro-column array jointly form a secondarily grown n-type doped GaN layer, sequentially selecting a secondarily epitaxially grown pre-stress layer, a multi-quantum well layer and a p-type doped GaN layer from bottom to top on the secondarily grown n-type doped GaN layer, and growing the secondarily epitaxially grown n-type doped GaN thin layer, the pre-stress layer, the multi-quantum well layer and the p-type doped GaN layer only on the top surface of the GaN micro-column array serving as a growth surface, wherein the secondarily grown n-type doped GaN layer, the pre-stress layer, the multi-quantum well layer and the p-type doped GaN layer form a micro-LED epitaxial wafer array, and the patterns of the micro-LED epitaxial wafer array are consistent with those of the stress relaxation patterned GaN template, so that a micro-LED epitaxial wafer is obtained; the patterned multi-quantum well layer is not etched by a dry method, so that the side wall etching damage of the multi-quantum well is avoided; the prestress layer grown on the stress relaxation graphical GaN template is subjected to partial relaxation, and the in-plane lattice constant is expanded, so that the energy required by indium incorporation is reduced, and the incorporation of indium in the multi-quantum well is effectively increased;
6) Placing the micro-LED epitaxial wafer subjected to the selective secondary epitaxy into alkaline solution, carrying out side wall corrosion on the micro-LED epitaxial wafer array, and corroding the side wall of the micro-LED epitaxial wafer array into a set shape to obtain micro- -
An array of LED chips.
Wherein in step 1), the substrate is sapphire (Al) 2 O 3 ) A silicon substrate (Si) or silicon carbide (SiC); the thickness of the n-type doped GaN layer is between 1.0 μm and 8 μm.
In the step 2), the cleaning is carried out by acid washing and then organic cleaning. Sulfuric acid (H) is used for pickling 2 SO 4 ): hydrogen peroxide (H) 2 O 2 ) The volume ratio of the water-bath cleaning agent is=3:1-10:1, and the water-bath cleaning agent is cleaned for 3-15 minutes under the water-bath heating condition of 80-100 ℃. The organic cleaning is that the ultrasonic cleaning is sequentially carried out in acetone, absolute ethyl alcohol and water for 3 to 15 minutes at normal temperature.
In the step 3), a stress relaxation graphical GaN template is obtained by adopting a photoetching or nano-imprinting mode, and the method comprises the following steps of:
a) The photoresist is adopted:
i. uniformly spin-coating photoresist on the surface of an n-type doped GaN layer of a planar GaN template, and making a periodic pattern of a micron-sized pattern array on the photoresist in a photoetching mode to obtain patterned photoresist;
etching the GaN template by using the patterned photoresist as a mask to etch part of the n-type doped GaN layer to form a GaN micron column array, removing part of the photoresist while etching, and forming residual photoresist on the growth surface; the GaN micrometer columns are in a truncated cone shape, the side walls are provided with inclination angles, and the bottoms of two adjacent GaN micrometer columns are connected with each other, so that a stress relaxation graphical GaN template is obtained;
b) The nano-imprinting glue is adopted:
i. uniformly spin-coating nano-imprinting glue on the surface of an n-type doped GaN layer of a planar GaN template, and making a periodic pattern of a micron-sized pattern array on the nano-imprinting glue in a nano-imprinting mode to obtain patterned nano-imprinting glue;
etching the GaN template by using the patterned nano-imprinting glue as a mask by adopting a dry etching method, etching part of the n-type doped GaN layer to form a GaN micro-pillar array, removing part of the nano-imprinting glue while etching, and forming residual nano-imprinting glue on the growth surface; the GaN micrometer columns are in a truncated cone shape, the side walls are provided with inclination angles, and bottoms of two adjacent GaN micrometer columns are connected with each other, so that the stress relaxation graphical GaN template is obtained.
In step a) i), the period of the micron-sized pattern array is between 1.5 μm and 50 μm, and the diameter of the micron-sized pattern is between 1 μm and 30 μm; in step a) ii), the etching depth is between 500nm and 5. Mu.m.
In step b), i), the period of the micron-sized pattern array is between 1 μm and 20 μm, and the diameter of the micron-sized pattern is between 500nm and 10 μm; in step b) ii), the etching depth is between 300nm and 5. Mu.m.
In the step 4), the method of acid washing and then organic cleaning is adopted. The acid washing is used for removing residual photoresist or nano-imprinting glue on the growth surface, and the organic cleaning is used for removing organic matters on the surface contamination. Sulfuric acid (H) is used for pickling 2 SO 4 ): hydrogen peroxide (H) 2 O 2 ) The volume ratio of the water-bath cleaning agent is=3:1-10:1, and the water-bath cleaning agent is cleaned for 3-15 minutes under the water-bath heating condition of 80-100 ℃. The organic cleaning is that the ultrasonic cleaning is sequentially carried out in acetone, absolute ethyl alcohol and water for 3 to 15 minutes at normal temperature.
In step 5), the thickness of the n-doped GaN layer is between 1.0 μm and 8 μm, and the n-doped concentration is 1×10 18 cm -3 ～5×10 20 cm -3 Between them; the pre-stress layer adopts In x Ga 1-x N/GaN superlattice or In x Ga 1-x An N single-layer structure, wherein x is an indium component in the prestress layer and is 1% -20%; the multiple quantum well layer is periodic In y Ga 1-y The N/GaN, y is the indium component in the multiple quantum well layer, and is between 10% and 50%; the thickness of the p-type doped GaN layer is 50 nm-300 nm, and the p-type doped GaN layer is dopedThe concentration of impurities is 1×10 18 cm -3 ～5×10 20 cm -3 Between them.
In the step 6), the set shape is a cylinder shape, a truncated cone shape, an inverted truncated cone shape, a trapezoid shape or an inverted trapezoid shape.
The invention has the advantages that:
(1) In the traditional micro-LED chip top-down preparation process, dry etching of an LED quantum well region cannot be avoided; according to the invention, the GaN template is subjected to dry etching to form the stress relaxation graphical GaN template, and then the structures such as the secondary epitaxial multi-quantum well and the like are selected on the basis of the stress relaxation graphical GaN template, so that the dry etching of the multi-quantum well region is effectively avoided, and the side wall etching damage of the multi-quantum well is avoided;
(2) After the stress relaxation graphical GaN template is used for carrying out graphical treatment on the n-type doped GaN layer, the stress suffered by the n-type doped GaN is effectively relaxed; the prestress layer grown on the stress relaxation graphical GaN template is subjected to partial relaxation, and the In-plane lattice constant is expanded, so that the energy required by indium (In) incorporation is reduced, and the incorporation of indium In the multi-quantum well is effectively increased;
(3) In the selective secondary epitaxy process, the selective secondary epitaxy can be realized without an additional mask; in the process of preparing the stress relaxation graphical GaN template, the bottoms of the GaN micro-pillar arrays of the stress relaxation graphical GaN template are connected with each other by etching, c faces for growth are not provided, the side walls of the GaN micro-pillar arrays are curved surfaces, crystal faces without complete planes are also provided with c faces for growth, and only the top faces of the GaN micro-pillar arrays are c faces and serve as growth faces; the selective secondary epitaxy method based on the patterned GaN template does not need an extra mask, and reduces the complexity of the micro-LED preparation process.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a micro-LED chip array based on maskless secondary epitaxy of the present invention;
FIG. 2 is a cross-sectional view of a planar GaN template obtained according to one embodiment of a fabrication method of a micro-LED chip array based on maskless secondary epitaxy, according to the present invention;
FIG. 3 is a cross-sectional view of a stress relaxation patterned GaN template obtained according to one embodiment of a fabrication method of a maskless secondary epitaxial-based micro-LED chip array of the present invention;
fig. 4 is a cross-sectional view of a micro-LED epitaxial wafer array obtained according to one embodiment of a fabrication method of a micro-LED chip array based on maskless secondary epitaxy according to the present invention;
FIG. 5 is a cross-sectional view of a micro-LED chip array according to one embodiment of a fabrication method of a maskless secondary epitaxy based micro-LED chip array of the present invention;
fig. 6 is a graph of results obtained by an embodiment of a fabrication method of a micro-LED chip array based on maskless secondary epitaxy, according to the present invention, wherein (a) is a scanning electron microscope (scanning electron microscope, SEM) graph and (b) is a corresponding cathode fluorescence (CL) graph;
fig. 7 is a Photoluminescence (PL) spectrum at 405nm laser according to an embodiment of a fabrication method of a micro-LED chip array based on maskless secondary epitaxy according to the present invention.
Detailed Description
The invention will be further elucidated by means of specific embodiments in conjunction with the accompanying drawings.
The preparation method of the micro-LED chip array based on maskless secondary epitaxy of the embodiment, as shown in fig. 1, comprises the following steps:
1) Sapphire having a thickness of 430 μm was provided as a substrate 101, and the substrate was put into an MOCVD reactor, and was subjected to an MOCVD method at H 2 Heating to 1000 ℃ under atmosphere, purging for 10 minutes, cooling to 540 ℃, and introducing TMGa and NH 3 And H 2 Growing a nucleation layer on the substrate, then heating to 1040 ℃, and growing an unintentionally doped GaN layer 102 with the thickness of 2 micrometers on the growth nucleation layer; continuing to raise the temperature to 1060 ℃, growing an n-type doped GaN layer 103 with the thickness of 3 micrometers, wherein the concentration of n-type doping is 2 multiplied by 10 19 cm -3 Obtaining a planar GaN template, as shown in FIG. 2;
2) After the growth is finishedAfter formation, the planar GaN template was removed from the MOCVD reactor and sulfuric acid (H 2 SO 4 ): hydrogen peroxide (H) 2 O 2 )
Volume ratio of =5:1, washing for 10 minutes under water bath heating condition at 100 ℃, and then sequentially carrying out ultrasonic washing for 5 minutes in acetone, absolute ethanol and water at normal temperature;
3) The method adopts a nano imprinting mode:
i. uniformly spin-coating nano-imprinting glue with the thickness of 1.0 micron on the surface of an n-type doped GaN layer of a planar GaN template, and adopting a nano-imprinting mode to make a periodic pattern of a micron-sized pattern array on the nano-imprinting glue to obtain patterned nano-imprinting glue, wherein the height of a nano-imprinting glue column is 1.8 microns, the thickness of residual glue at a gap of the nano-imprinting glue column is 150 nanometers, the pattern is cylindrical, the period is 3.0 microns, the diameter is 2.1 microns, and the height is 1.8 microns;
placing a planar GaN template with patterned nano-imprinting glue on the surface into a cavity of an inductively coupled plasma (inductively coupled plasma, ICP) etching machine, etching the GaN template, and etching residual glue with the thickness of 150 nanometers at a pattern gap after imprinting in an oxygen atmosphere; after the etching of the residual glue is completed, the patterned glue column is used as a mask, and the etching is performed on boron trichloride, chlorine and argon (BCl) 3 ,Cl 2 Carrying out ICP etching treatment on the n-type doped GaN layer in Ar) atmosphere, etching part of the n-type doped GaN layer, wherein in FIG. 3, 113 is the n-type doped GaN layer with an unetched pattern, the thickness is 1.3 micrometers, 114 is a GaN micrometer column array which is reserved after etching treatment, the thickness is 1.7 micrometers, residual nanoimprint gum is arranged on a growth surface, the height of the nanoimprint gum column is reduced by 800 nanometers, the residual height of the nanoimprint gum column is 1 micrometer, namely, the etching selection ratio of the nanoimprint gum to the n-type doped GaN layer is about 0.47:1, a GaN micrometer column array is formed, the GaN micrometer column is in a round table shape, the side wall has an inclination angle, the bottoms of two adjacent GaN micrometer columns are connected with each other, namely, the bottoms have no residual or a small amount of residual c-plane GaN, so as to obtain a stress relaxation patterned GaN template;
the bottom of the GaN micron column array of the stress relaxation graphical GaN template is connected with each other, a c-plane for growth is not arranged, the side wall of the GaN micron column array is a curved surface, a crystal face without a complete plane is also not arranged, the c-plane for growth is not arranged, and only the top surface of the GaN micron column array is the c-plane and serves as a growth surface;
after the stress relaxation graphical GaN template is used for carrying out graphical treatment on the n-type doped GaN layer, the stress suffered by the n-type doped GaN is effectively relaxed;
4) The stress relaxation graphical GaN template is firstly adopted with sulfuric acid (H 2 SO 4 ): hydrogen peroxide (H) 2 O 2 ) The volume ratio of the nano imprinting glue to the silicon wafer is 5:1, the nano imprinting glue is cleaned for 10 minutes under the water bath heating condition of 100 ℃, the residual nano imprinting glue on the growth surface is removed, then the nano imprinting glue is sequentially cleaned for 5 minutes by each ultrasonic wave in acetone, absolute ethyl alcohol and water at normal temperature, the organic matters on the surface contamination are removed, and the nano imprinting glue is put back into an MOCVD reaction chamber;
5) On stress relaxation patterned GaN template, on H 2 And NH 3 Heating to 1060 deg.C under atmosphere, introducing TMGa and NH 3 And H 2 A thin layer of n-type doped GaN with the thickness of 0.3 micrometer is continuously grown on the growth surface of the GaN micrometer column array 114 by selective secondary epitaxy, and the concentration of n-type doping is 2 multiplied by 10 19 cm -3 The secondarily epitaxially grown n-type doped GaN layer 124 is formed by the n-type doped GaN thin layer and the GaN micron column array, and the thickness of the secondarily grown n-type doped GaN layer 124 is 2.0 microns; switching the gas atmosphere to N 2 And NH 3 Cooling to 950 deg.C, introducing TEGa, TMIn, NH 3 、SiH 4 And N 2 Growing a pre-stress layer 125 having a thickness of 120 nanometers; a multi-quantum well layer 126 with a thickness of 90 nm is grown again, wherein TEGa, TMIn, NH is introduced 3 And N 2 The growth temperature is 710 ℃, and the InGaN quantum well layer with the growth thickness of 2.5 nanometers is introduced with TEGa and NH 3 And N 2 Growing a GaN barrier layer with the thickness of 12.5 nanometers at the growth temperature of 850 ℃; then the gas atmosphere is switched to H 2 And NH 3 Heating to 950 ℃, and introducing TMGa and NH 3 、Cp 2 Mg and H 2 A p-doped GaN layer 127 having a thickness of 90 nm was grown with a p-doped concentration of 1×10 19 cm -3 As shown In fig. 4, the pre-stress layer 125 is In x Ga 1-x An N/GaN superlattice wherein the indium composition is about 5% and the number of periods is 24; the multiple quantum well layer 126 is In y Ga 1-y N/GaN quantum wells with a number of cycles of 6 and an indium composition of about 28%; the n-type doped GaN thin layer, the pre-stress layer, the multiple quantum well layer and the p-type doped GaN layer which are epitaxially grown only grow on the top surface of the GaN micro-pillar array serving as a growth surface, are patterned, the n-type doped GaN layer 124, the pre-stress layer 125, the multiple quantum well layer 126 and the p-type doped GaN layer 127 which are epitaxially grown form a micro-LED epitaxial wafer array, and the patterns of the micro-LED epitaxial wafer array are consistent with those of the stress relaxation patterned GaN template, so that the micro-LED epitaxial wafer is obtained; the patterned multi-quantum well layer is not etched by a dry method, so that the side wall etching damage of the multi-quantum well is avoided; the prestress layer grown on the stress relaxation graphical GaN template is subjected to partial relaxation, and the in-plane lattice constant is expanded, so that the energy required by indium incorporation is reduced, and the incorporation of indium in the multi-quantum well is effectively increased;
6) And placing the micro-LED epitaxial wafer subjected to the selective secondary epitaxy into a KOH aqueous solution for wet etching, wherein the KOH aqueous solution is prepared by dissolving 10g of KOH solid into 300mL of water, the etching condition is that the etching rate of the side wall of the micro-LED epitaxial wafer array in the KOH aqueous solution is far greater than that of c-plane GaN at the top under the water bath heating condition of 70 ℃, so that the micro-LED chip array is etched into a steep cylindrical shape with the side wall after etching, the array period is 3.0 micrometers, the diameter is 2.0 micrometers, the height is 2.3 micrometers, as shown in fig. 5, 134 is an etched and secondarily grown n-type doped GaN layer, the thickness is 2.0 micrometers, 135 is an etched prestress layer, the thickness is 120 nanometers, 136 is an etched multiple quantum well layer, the indium component is about 28%, the thickness is 90 nanometers, 137 is an etched p-type doped GaN layer, and the thickness is 90 nanometers, so that the micro-LED chip array is obtained.
Fig. 6 is an SEM image of the micro-LED chip array and a corresponding CL image in this embodiment. From SEM images, a closely packed micro-LED chip array with a period of 3 microns and a diameter of about 2 microns was obtained by secondary epitaxy. The number of Pixels Per Inch (PPI) of the chip array may reach 8466PPI. From the CL image, it can be seen that the micro-LED chip array emits light from the mesa region of the pattern, i.e., the top c-plane region where the stress relaxation patterned GaN template remains. The gaps of the pattern do not participate in the luminescence, which means that the selective epitaxy of the micro-LED chip is realized under the condition of no mask. In addition, most micro-LED chips can realize effective light emission and show good brightness uniformity.
Fig. 7 is a PL spectrum of the micro-LED chip under 405nm laser in the present embodiment, in which sample a corresponds to the micro-LED chip when InGaN is not released from stress, sample B corresponds to the micro-LED chip in which InGaN lamination stress is relaxed by patterning secondary epitaxy, and in fig. 7, a broken line represents the PL spectrum of sample a and a solid line represents the PL spectrum of sample B. It can be seen from the graph that the PL peak wavelength of sample a is 485nm, while the PL peak wavelength of sample B is 540nm. The stress relaxation effect brought by the patterned secondary epitaxy enables the luminescence wavelength of the quantum well to be red shifted by 55nm, which shows that the strain relaxation of InGaN effectively improves indium incorporation in the quantum well.
In the preparation process of the micro-LED chip, a patterned GaN array with a periodical micron size is prepared by etching a GaN template, and then a quantum well is grown on the top of the pattern by a maskless secondary epitaxy mode, so that the micro-LED chip array is successfully prepared. In the preparation process, ICP etching of the quantum well region is not designed, and etching damage to the quantum well region of the micro-LED chip is avoided. And after the GaN template is subjected to patterning treatment, residual compressive stress suffered by GaN can be greatly relaxed. The compressive stress of the InGaN structure subjected to secondary epitaxy is also obviously relaxed, so that the incorporation of indium in the quantum well is improved, and the luminescence wavelength of the quantum well is red-shifted. Therefore, the preparation flow of the micro-LED chip has the advantages of secondary epitaxy without a mask, eliminating etching damage, relaxing InGaN compressive stress and the like.
Finally, it should be noted that the examples are disclosed for the purpose of aiding in the further understanding of the present invention, but those skilled in the art will appreciate that: various alternatives and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the disclosed embodiments, but rather the scope of the invention is defined by the appended claims.
Claims (10)
1. The preparation method of the micro-LED chip array based on maskless secondary epitaxy is characterized by comprising the following steps of:
1) Providing a substrate, placing the substrate into a Metal Organic Chemical Vapor Deposition (MOCVD) reaction chamber, and epitaxially growing an unintentionally doped GaN layer and an n-type doped GaN layer on the substrate from bottom to top in sequence by an MOCVD method to obtain a planar GaN template;
2) After the growth is completed, taking out the planar GaN template from the MOCVD reaction chamber, and cleaning;
3) Carrying out dry etching on the planar GaN template by adopting a photoetching or nano-imprinting mode, etching part of the n-type doped GaN layer to form a GaN micron column array, wherein the GaN micron columns are in a truncated cone shape, the side walls are provided with inclination angles, and the bottoms of the adjacent GaN micron columns are connected with each other, so that the stress relaxation graphical GaN template is obtained;
the bottom of the GaN micron column array of the stress relaxation graphical GaN template is connected with each other, no c-plane for growth exists, the side wall of the GaN micron column array is a curved surface, no complete plane crystal face exists, no c-plane for growth exists, and only the top surface of the GaN micron column array is the c-plane and serves as a growth plane;
after the stress relaxation graphical GaN template is used for carrying out graphical treatment on the n-type doped GaN layer, the stress suffered by the n-type doped GaN is effectively relaxed;
4) Cleaning the stress relaxation graphical GaN template, and placing the template back to the MOCVD reaction chamber;
5) On a GaN micro-column array of a stress relaxation patterned GaN template, secondarily epitaxially growing an n-type doped GaN thin layer, wherein the secondarily epitaxially grown n-type doped GaN thin layer and GaN micro-column array jointly form a secondarily grown n-type doped GaN layer, sequentially selecting a secondarily epitaxially grown pre-stress layer, a multi-quantum well layer and a p-type doped GaN layer from bottom to top on the secondarily grown n-type doped GaN layer, and growing the secondarily epitaxially grown n-type doped GaN thin layer, the pre-stress layer, the multi-quantum well layer and the p-type doped GaN layer only on the top surface of the GaN micro-column array serving as a growth surface, wherein the secondarily grown n-type doped GaN layer, the pre-stress layer, the multi-quantum well layer and the p-type doped GaN layer form a micro-LED epitaxial wafer array, and the patterns of the micro-LED epitaxial wafer array are consistent with those of the stress relaxation patterned GaN template, so that a micro-LED epitaxial wafer is obtained; the patterned multi-quantum well layer is not etched by a dry method, so that the side wall etching damage of the multi-quantum well is avoided; the prestress layer grown on the stress relaxation graphical GaN template is subjected to partial relaxation, and the in-plane lattice constant is expanded, so that the energy required by indium incorporation is reduced, and the incorporation of indium in the multi-quantum well is effectively increased;
6) Placing the micro-LED epitaxial wafer subjected to the selective secondary epitaxy into alkaline solution, carrying out side wall corrosion on the micro-LED epitaxial wafer array, and corroding the side wall of the micro-LED epitaxial wafer array into a set shape to obtain the micro-LED chip array.
2. The method of claim 1, wherein in step 1), the substrate is a sapphire substrate, a silicon substrate, or silicon carbide.
3. The method according to claim 1, wherein in step 2), the washing is performed by acid washing followed by organic washing.
4. The preparation method according to claim 1, wherein in step 3), a stress relaxation patterned GaN template is obtained by photolithography or nanoimprint, and the method comprises the following steps:
a) The photoresist is adopted:
i. uniformly spin-coating photoresist on the surface of an n-type doped GaN layer of a planar GaN template, and making a periodic pattern of a micron-sized pattern array on the photoresist in a photoetching mode to obtain patterned photoresist;
etching the GaN template by using the patterned photoresist as a mask to etch part of the n-type doped GaN layer to form a GaN micron column array, removing part of the photoresist while etching, and forming residual photoresist on the growth surface; the GaN micrometer columns are in a truncated cone shape, the side walls are provided with inclination angles, and the bottoms of two adjacent GaN micrometer columns are connected with each other, so that a stress relaxation graphical GaN template is obtained;
b) The nano-imprinting glue is adopted:
i. uniformly spin-coating nano-imprinting glue on the surface of an n-type doped GaN layer of a planar GaN template, and making a periodic pattern of a micron-sized pattern array on the nano-imprinting glue in a nano-imprinting mode to obtain patterned nano-imprinting glue;
etching the GaN template by using the patterned nano-imprinting glue as a mask by adopting a dry etching method, etching part of the n-type doped GaN layer to form a GaN micro-pillar array, removing part of the nano-imprinting glue while etching, and forming residual nano-imprinting glue on the growth surface; the GaN micrometer columns are in a truncated cone shape, the side walls are provided with inclination angles, and bottoms of two adjacent GaN micrometer columns are connected with each other, so that the stress relaxation graphical GaN template is obtained.
5. The method of claim 4, wherein in step a) i), the period of the array of micro-scale patterns is between 1.5 μm and 50 μm and the diameter of the micro-scale patterns is between 1 μm and 30 μm; in step a) ii), the etching depth is between 500nm and 5. Mu.m.
6. The method of claim 4, wherein in step 5), in step b), the period of the array of micro-scale patterns is between 1 μm and 20 μm and the diameter of the micro-scale patterns is between 500nm and 10 μm; in step b) ii), the etching depth is between 300nm and 5. Mu.m.
7. The method of claim 4, wherein in step 4), the cleaning is performed by acid washing for removing residual photoresist or nanoimprint resist on the growth surface, followed by organic cleaning for removing surface-contaminated organic matter.
8. The method of claim 1, wherein In step 5), the pre-stress layer is In x Ga 1-x N/GaN superlattice or In x Ga 1-x And the N single-layer structure is that x is an indium component in the prestress layer and is 1-20%.
9. The method of claim 1, wherein In step 5), the multiple quantum well layer is periodic In y Ga 1-y And the N/GaN, y is the indium component in the multiple quantum well layer, and the content of the indium component is 10-50%.
10. The method of claim 1, wherein in step 6), the set shape is a cylinder, a truncated cone, an inverted truncated cone, a trapezoid, or an inverted trapezoid.
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