CN117766013A

CN117766013A - DDR and NAND simultaneous aging method, device and computer equipment

Info

Publication number: CN117766013A
Application number: CN202311820980.5A
Authority: CN
Inventors: 梁子凡; 彭云; 王复港
Original assignee: Chengdu Xinyilian Information Technology Co Ltd
Current assignee: Chengdu Xinyilian Information Technology Co Ltd
Priority date: 2023-12-27
Filing date: 2023-12-27
Publication date: 2024-03-26

Abstract

The embodiment of the invention discloses a DDR and NAND aging method, a DDR and NAND aging device and computer equipment. The method comprises the following steps: when the system is powered on, initializing a main control core and a NAND controller, and initializing a memory and a DDR; DDR burn-in is performed by the main control core, and the NAND controller is used for performing burn-in read-write erase scheduling on NAND. By implementing the method provided by the embodiment of the invention, the time occupied by DDR aging can be shortened, and the aging time of NAND can be optimized.

Description

DDR and NAND simultaneous aging method, device and computer equipment

Technical Field

The invention relates to a solid state disk, in particular to a method, a device and computer equipment for simultaneously aging DDR and NAND.

Background

The solid state disk NAND particle occupies DDR space when in read-write operation, so that the solid state disk is aged firstly, then the initialization of the NAND controller and the memory management is carried out, finally the NAND aging test is carried out, the NAND test needs to depend on the dispatching of the main control core, but the aging mode can lead to overlong overall aging time.

Therefore, it is necessary to design a new method to shorten the time taken for aging of DDR and optimize the aging time of NAND.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a DDR and NAND simultaneous aging method, device and computer equipment.

In order to achieve the above purpose, the present invention adopts the following technical scheme: a method for simultaneous DDR and NAND aging comprising:

when the system is powered on, initializing a main control core and a NAND controller, and initializing a memory and a DDR;

DDR burn-in is performed by the main control core, and the NAND controller is used for performing burn-in read-write erase scheduling on NAND.

The further technical scheme is as follows: when the system is powered on, the main control core and the NAND controller are initialized, and before the memory and the DDR are initialized, the system further comprises:

the master core code and the start address of the NAND controller are modified into the on-chip memory space.

The further technical scheme is as follows: the on-chip memory space comprises a main control core code section, a NAND controller code section, a main control core running memory and a NAND controller running memory.

The further technical scheme is as follows: the method comprises the steps that DDR aging is carried out by a main control core, and after NAND is subjected to aging read-write erasing scheduling by a NAND controller, the method further comprises the steps of:

and forwarding the related information of the NAND bad block to the main control core by the NAND controller so as to be reported and recorded by the main control core.

The further technical scheme is as follows: the DDR burn-in is performed by the main control core, and the NAND controller is utilized to perform burn-in read-write erase scheduling on the NAND, comprising:

DDR burn-in is performed by the main control core, memory required by NAND burn-in is allocated from the on-chip memory, and burn-in read-write erase scheduling is performed on the NAND by the NAND controller.

The invention also provides a DDR and NAND aging device, which comprises:

the initialization unit is used for initializing the main control core and the NAND controller and initializing the memory and the DDR when the system is powered on;

and the aging unit is used for performing DDR aging by the main control core and performing aging read-write erasing scheduling on the NAND by using the NAND controller.

The further technical scheme is as follows: further comprises:

and the modifying unit is used for modifying the main control core code and the starting address of the NAND controller into the on-chip memory space.

The further technical scheme is as follows: further comprises:

and the reporting unit is used for forwarding the related information of the NAND bad block to the main control core by the NAND controller so as to be reported and recorded by the main control core.

The further technical scheme is as follows: the simultaneous aging unit is used for performing DDR aging by the main control core, simultaneously distributing memory required by NAND aging from the on-chip memory, and performing aging read-write erasing scheduling on the NAND by using the NAND controller.

The invention also provides a computer device which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the method when executing the computer program.

Compared with the prior art, the invention has the beneficial effects that: according to the invention, the initial addresses of the main control core codes and the NAND controller are modified into the on-chip memory space, all operation codes of the main control chip are operated in the on-chip memory, when DDR and NAND are aged simultaneously after initialization, the dependence of NAND aging read-write erase scheduling on the main control chip is decoupled, and only the NAND controller is used for scheduling, so that the time occupied by DDR aging is shortened, and the aging time of NAND can be optimized.

The invention is further described below with reference to the drawings and specific embodiments.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic flow chart of a method for simultaneously aging DDR and NAND provided by an embodiment of the invention;

FIG. 2 is a flow chart of a method for DDR and NAND simultaneous burn-in provided in another embodiment of the invention;

FIG. 3 is a schematic block diagram of a DDR and NAND device that is simultaneously aged, provided by an embodiment of the present invention;

FIG. 4 is a schematic block diagram of a DDR and NAND device that is concurrently burned-in, as provided by another embodiment of the present invention;

fig. 5 is a schematic block diagram of a computer device according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

Referring to fig. 1, fig. 1 is a flow chart of a method for simultaneously aging DDR and NAND according to an embodiment of the present invention. The DDR and NAND simultaneous aging method is applied to a solid state disk, and all running codes of a main control core are run in an on-chip memory; and decoupling the dependence of NAND aging read-write erase scheduling on the main control core, and scheduling by using only the NAND controller. DDR and NAND aging can be executed in parallel, the time occupied by DDR aging is shortened, NAND aging does not pass through master control core scheduling, and NAND aging time can be optimized in flow. .

FIG. 1 is a flow chart of a method for DDR and NAND simultaneous aging provided by an embodiment of the invention. As shown in fig. 2, the method includes the following steps S110 to S130.

S110, modifying the main control core code and the initial address of the NAND controller into the on-chip memory space.

In this embodiment, the on-chip memory space includes a master core code segment, a NAND controller code segment, a master core running memory, and a NAND controller running memory.

The main control core code section refers to a part of the main control chip responsible for executing program logic, and comprises an instruction set and program codes of the main control core. This portion of the code segment is typically stored in flash memory or ROM of the master chip and is loaded into the instruction register of the master core for execution by the master core upon power-on of the chip. The NAND-controller code segment refers to a portion of code in the NAND flash controller that is responsible for managing and controlling NAND flash operations. The NAND controller is a hardware module for communicating with the NAND flash memory and performing operations of reading, writing, erasing, and the like. The NAND controller code segment is stored in the firmware of the NAND controller, and interacts with the main control core through the corresponding interface and signals to control and manage the NAND flash memory. The main control core running memory refers to a working memory used by the main control core in the main control chip and is used for storing data and temporary results of an executing program. The master core operating memory may be SRAM, DRAM, or the like type of memory that is typically larger than the memory capacity of the code segments and is capable of high speed data exchange with the master core via the bus. The NAND controller operation memory refers to a working memory in the NAND flash memory controller for storing data and buffers required in the operation process of the controller. It is also typically a SRAM or DRAM type memory for temporarily storing information related to NAND flash operations, including read/write data, addresses, status, etc. The NAND controller running memory is connected with a data path in the NAND controller to realize data transmission and processing of the NAND flash memory.

Codes of all cores of the main control chip including the main control core and the NAND controller are operated in the on-chip memory and are not operated in the DDR.

S120, initializing a main control core and a NAND controller when the system is powered on, and initializing a memory and a DDR.

In this embodiment, the starting addresses of the main control core code and the NAND controller are changed into the on-chip memory space, and all the core memory management is completely initialized after power-up.

S130, performing DDR aging by the main control core, and performing aging read-write erasing scheduling on NAND by using the NAND controller.

In this embodiment, DDR burn-in is performed by the master core, and memory required for NAND burn-in is allocated from the on-chip memory at the same time, and burn-in read-write erase scheduling is performed on the NAND by using the NAND controller.

The NAND test is completed by the NAND controller by self without being scheduled by the main control core, and the NAND test does not occupy DDR space resources.

Specifically, DDR and NAND aging are performed simultaneously, and the memory that NAND aging needs to use is allocated from the on-chip memory. Running all running codes of the main control chip in an on-chip memory; the dependence of NAND aging read-write erasing scheduling on the main control chip is decoupled, only the NAND controller is used for scheduling, DDR and NAND aging can be executed in parallel, and the aging time is optimized. And NAND aging does not pass through master control core scheduling, so that the aging time of NAND can be optimized in the process.

In this embodiment, changing the master control core code and the starting address of the NAND controller into the on-chip memory space can reduce the data access delay, thereby improving the overall performance of the system. The access speed of the on-chip memory is generally faster than that of the external memory, so that the loader and the execution instruction will be faster. The power consumption of the on-chip memory is generally lower than that of the external memory, so that the power consumption of the system can be reduced and the battery endurance time can be prolonged by running the main control core code and the NAND controller in the on-chip memory. The integrated master control core code and the NAND controller can simplify hardware design in an on-chip memory, reduce dependence on external memories and interfaces, and reduce complexity and cost of a system. The dependence of NAND aging read-write erasing scheduling on a main control chip is decoupled, and DDR and NAND aging can be executed in parallel only by using a NAND controller for scheduling, so that the overall efficiency and performance of the system are improved. The NAND test is completed by the NAND controller by self without being scheduled by the main control core, so that the occupation of DDR space resources by the NAND test can be avoided, and the stability and the performance of the system are ensured.

By the method, the performance, the power consumption and the reliability of the system can be optimized, the overall working efficiency is improved, and the method is suitable for more complex application scenes.

According to the DDR and NAND simultaneous aging method, the initial addresses of the main control core codes and the NAND controller are modified into the on-chip memory space, all operation codes of the main control chip are operated in the on-chip memory, when DDR and NAND are simultaneously aged after initialization, the dependence of NAND aging read-write erase scheduling on the main control chip is decoupled, only the NAND controller is used for scheduling, the time occupied by DDR aging is shortened, and the aging time of NAND can be optimized.

FIG. 2 is a flow chart of a method for DDR and NAND simultaneous aging according to another embodiment of the invention. As shown in fig. 2, the method of simultaneously aging the DDR and the NAND of the present embodiment includes steps S210 to S240. Steps S210 to S230 are similar to steps S110 to S130 in the above embodiment, and are not described herein. Step S240 added in the present embodiment is described in detail below.

S240, forwarding relevant information of the NAND bad block to the main control core by the NAND controller so as to be reported and recorded by the main control core.

The related information of the NAND bad blocks is reported and recorded by the main control core, so that the NAND bad blocks in the whole system can be managed in a centralized way. The main control core can maintain a bad block table or record file, record the position, state and other information of each bad block, and is convenient for system management personnel or programs to process and maintain.

When the NAND controller detects bad blocks, after relevant information is forwarded to the main control core, the main control core can mark the bad blocks, avoid the bad blocks when data read-write operation is carried out, and ensure the integrity and reliability of data. The main control core can re-plan the data storage space according to the bad block information, so that the bad block is prevented from affecting the normal operation of the file system.

The main control core records the related information of the NAND bad blocks, so that system management personnel can be helped to carry out fault diagnosis and investigation. When abnormal conditions or data loss occurs, possible problem sources can be positioned according to the bad block information, corresponding remedial measures are taken, and maintainability and reliability of the system are improved.

If the main control core records the position information of the NAND bad block, when a new bad block is found, data migration can be performed according to the existing bad block information, and affected data is copied from the bad block to other healthy blocks so as to protect the data from being lost.

The distribution rule and trend of the bad blocks can be analyzed by recording NAND bad block information through the main control core, so that the performance of the system is optimized. For example, the data storage strategy can be adjusted according to the bad block information, so that the area where the bad block is located is avoided as much as possible, and the read-write efficiency and durability of the system are improved.

In summary, relevant information of the NAND bad block is forwarded to the main control core by the NAND controller for reporting and recording, so that the advantages of centralized management, data integrity protection, fault diagnosis, performance optimization and the like of the bad block can be realized.

FIG. 3 is a schematic block diagram of a DDR and NAND simultaneous burn-in device 300 provided in an embodiment of the invention. As shown in fig. 3, the present invention also provides a device 300 for simultaneously aging DDR and NAND, corresponding to the above method for simultaneously aging DDR and NAND. The DDR and NAND simultaneous burn-in apparatus 300, which includes means for performing the above-described DDR and NAND simultaneous burn-in method, may be configured in a solid state disk. Specifically, referring to fig. 3, the apparatus 300 for simultaneously aging DDR and NAND includes a modifying unit 301, an initializing unit 302, and a simultaneous aging unit 303.

The modifying unit 301 is configured to modify the master core code and the start address of the NAND controller into the on-chip memory space. An initialization unit 302, configured to initialize a master control core and a NAND controller and initialize a memory and a DDR when the system is powered on; and the aging unit 303 is used for performing DDR aging by the main control core and performing aging read-write erasing scheduling on the NAND by using the NAND controller.

In an embodiment, the concurrent aging unit 303 is configured to perform DDR aging by the master core, allocate memory required for NAND aging from the on-chip memory, and perform aging read-write erase scheduling on the NAND by using the NAND controller.

FIG. 4 is a schematic block diagram of a DDR and NAND simultaneous burn-in device 300 provided in another embodiment of the invention. As shown in fig. 4, the DDR and NAND simultaneous aging device 300 of the present embodiment is an addition of the reporting unit 304 on the basis of the above embodiment.

And the reporting unit 304 is used for forwarding the relevant information of the NAND bad block to the main control core by the NAND controller so as to be reported and recorded by the main control core.

It should be noted that, as those skilled in the art can clearly understand, the specific implementation process of the apparatus 300 and each unit for simultaneously aging the DDR and the NAND may refer to the corresponding description in the foregoing method embodiment, and for convenience and brevity of description, the description is omitted here.

The DDR and NAND simultaneous aging apparatus 300 described above may be implemented in the form of a computer program that can run on a computer device as shown in FIG. 5.

Referring to fig. 5, fig. 5 is a schematic block diagram of a computer device according to an embodiment of the present application. The computer device 500 may be a solid state disk.

With reference to FIG. 5, the computer device 500 includes a processor 502, memory, and a network interface 505 connected by a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.

The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions that, when executed, cause the processor 502 to perform a method of DDR and NAND aging simultaneously.

The processor 502 is used to provide computing and control capabilities to support the operation of the overall computer device 500.

The internal memory 504 provides an environment for the execution of a computer program 5032 in the non-volatile storage medium 503, which computer program 5032, when executed by the processor 502, causes the processor 502 to perform a method of DDR and NAND aging simultaneously.

The network interface 505 is used for network communication with other devices. Those skilled in the art will appreciate that the architecture shown in fig. 5 is merely a block diagram of a portion of the architecture in connection with the present application and is not intended to limit the computer device 500 to which the present application is applied, and that a particular computer device 500 may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.

Wherein the processor 502 is configured to execute a computer program 5032 stored in a memory to implement the steps of:

when the system is powered on, initializing a main control core and a NAND controller, and initializing a memory and a DDR; DDR burn-in is performed by the main control core, and the NAND controller is used for performing burn-in read-write erase scheduling on NAND.

In one embodiment, the processor 502, when powering up the system, initializes the master core and the NAND controller, and before initializing the memory and DDR steps, further performs the following steps:

The on-chip memory space comprises a main control core code section, a NAND controller code section, a main control core running memory and a NAND controller running memory.

In one embodiment, after implementing the DDR burn-in by the master core and the NAND controller is utilized to schedule the NAND to burn-in, the processor 502 also implements the following steps:

In one embodiment, when the processor 502 performs the DDR burn-in by the master core and performs the burn-in read-write erase scheduling step on the NAND by using the NAND controller, the following steps are specifically implemented:

It should be appreciated that in embodiments of the present application, the processor 502 may be a central processing unit (Central Processing Unit, CPU), the processor 502 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSPs), application specific integrated circuits (Application Specific Integrated Circuit, ASICs), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. Wherein the general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

Those skilled in the art will appreciate that all or part of the flow in a method embodying the above described embodiments may be accomplished by computer programs instructing the relevant hardware. The computer program comprises program instructions, and the computer program can be stored in a storage medium, which is a computer readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.

Accordingly, the present invention also provides a storage medium. The storage medium may be a computer readable storage medium. The storage medium stores a computer program which, when executed by a processor, causes the processor to perform the steps of:

In one embodiment, when the processor executes the computer program to realize the system power-up, the following steps are further realized before initializing the master control core and the NAND controller, and initializing the memory and the DDR steps:

In one embodiment, after executing the computer program to implement the DDR burn-in by the master core and performing the burn-in read-write erase scheduling step on NAND with a NAND controller, the processor further implements the steps of:

In one embodiment, when the processor executes the computer program to implement the DDR burn-in by the master core and the NAND controller is used to perform the burn-in read-write erase scheduling step on the NAND, the following steps are specifically implemented:

The storage medium may be a U-disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, or an optical disk, or other various computer-readable storage media that can store program codes.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed.

The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be combined, divided and deleted according to actual needs. In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The integrated unit may be stored in a storage medium if implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present invention is essentially or a part contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a terminal, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention.

While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

A method for simultaneous aging of ddr and NAND comprising:

when the system is powered on, initializing a main control core and a NAND controller, and initializing a memory and a DDR;

DDR burn-in is performed by the main control core, and the NAND controller is used for performing burn-in read-write erase scheduling on NAND.
2. The method for simultaneously aging the DDR and the NAND according to claim 1, wherein when the system is powered on, initializing the master core and the NAND controller, and before initializing the memory and the DDR, further comprising:

the master core code and the start address of the NAND controller are modified into the on-chip memory space.
3. The method of simultaneous DDR and NAND burn-in of claim 2, wherein the on-chip memory space comprises a master core code segment, a NAND controller code segment, a master core run memory, a NAND controller run memory.
4. The method for simultaneously aging DDR and NAND according to claim 3, wherein the performing DDR aging by the master core, and after performing aging read-write erase scheduling on NAND by the NAND controller, further comprises:

and forwarding the related information of the NAND bad block to the main control core by the NAND controller so as to be reported and recorded by the main control core.
5. The method of simultaneous DDR and NAND burn-in of claim 1, wherein the DDR burn-in by the master core and the NAND is scheduled for burn-in read-write erase with a NAND controller, comprising:

DDR burn-in is performed by the main control core, memory required by NAND burn-in is allocated from the on-chip memory, and burn-in read-write erase scheduling is performed on the NAND by the NAND controller.
A device for simultaneous ddr and NAND burn-in comprising:

the initialization unit is used for initializing the main control core and the NAND controller and initializing the memory and the DDR when the system is powered on;

and the aging unit is used for performing DDR aging by the main control core and performing aging read-write erasing scheduling on the NAND by using the NAND controller.
7. The DDR and NAND simultaneous aging device of claim 6, further comprising:

and the modifying unit is used for modifying the main control core code and the starting address of the NAND controller into the on-chip memory space.
8. The DDR and NAND simultaneous aging device of claim 6, further comprising:

and the reporting unit is used for forwarding the related information of the NAND bad block to the main control core by the NAND controller so as to be reported and recorded by the main control core.
9. The apparatus for simultaneously aging the DDR and the NAND according to claim 6, wherein the simultaneous aging unit is configured to perform DDR aging by the master core, simultaneously allocate memory required for NAND aging from the on-chip memory, and perform aging read-write erase scheduling on the NAND by using the NAND controller.
10. A computer device, characterized in that it comprises a memory on which a computer program is stored and a processor which, when executing the computer program, implements the method according to any of claims 1-5.