CN117762829A - Data reading apparatus, method, device, and storage medium - Google Patents

Abstract

The application relates to a data reading device, a method, a device and a storage medium. The device comprises: the data storage array comprises a plurality of data storage units, and each data storage unit comprises a memory and a buffer which are connected with each other; the output end of the controller is connected with the input end of each memory; the input end of the controller is connected with the output end of each buffer. According to the method and the device, the buffer is used for intermediate buffering, after the data of the same storage address from different memories are all aligned, the data of the same storage address from different memories are obtained from the buffer, and the problem that the data of the same storage address from different memories cannot be read out at the same time and the data cannot be aligned is solved.

Description

Data reading apparatus, method, device, and storage medium

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a data reading device, a data reading method, a data reading device, and a data reading apparatus.

Background

PSRAM (Pseudo static random access memory, pseudo-static random access memory) usually appears as independent particles, the data interface cannot be arbitrarily expanded as embedded SRAM to the data bus width, and the design of IO (Input/Output) under a specific process can limit the highest operating frequency of PSRAM. The limitations of data bus width and operating frequency are such that the bandwidth of a single PSRAM is typically lower than the total bandwidth required by the handset application to store data, which requires an increase in PSRAM to operate in parallel.

After adding the PSRAMs, the two PSRAMs are treated as a whole, with the two PSRAMs combining the stored data, for example: one data is split into D0 and D1, D0 is stored to psram#1, D1 is stored to psram#2. Although the use of two PSRAMs may increase bandwidth when storing data, there is a problem in that data cannot be aligned when reading data from the two PSRAMs. This is because even if the two PSRAMs are identical in model number, the intrinsic physical characteristics of the two PSRAMs are not identical, and the difference in physical characteristics may cause the read delays of the two PSRAMs to be different, in which case there is a problem that the data returned by the two PSRAMs for the same address cannot be read out at the same time.

For example: taking fig. 1 as an example, a read command (INST) and a read address { A2, A1, A0} are simultaneously sent to interface terminals of PSRAM #1 and PSRAM #2, and it is expected to simultaneously read out D0 and D1, so that each 8-bit data D0 and D1 is combined into one 16-bit data, and the 16-bit data is sent to a display module. However, since the read delays of psram#1 and psram#2 are different and the time difference cannot be expected, D0 and D1 cannot be read out at the same time, in which: the reading Delay of the PSRAM #1 is Delay Cycle1, the reading Delay of the PSRAM #2 is Delay Cycle2, the Delay Cycle1 is smaller than the Delay Cycle2, D0 is read out first, D1 is read out later, D0 and D1 are not aligned, so that D0 and D1 cannot be combined into data with larger bit width, D1 and D4 are read out simultaneously due to the existence of the reading Delay, and D1 and D4 are combined into one data, so that the problem of data dislocation finally occurs.

Disclosure of Invention

The application provides a data reading device, a data reading method, data reading equipment and a data storage medium, which are used for solving the problem that data cannot be aligned easily under the condition of reading data by a plurality of PSRAMs.

Aiming at the technical problems, the technical scheme is solved by the following embodiments:

the embodiment of the application provides a data reading device, which comprises: the data storage array comprises a plurality of data storage units, and each data storage unit comprises a memory and a buffer which are connected with each other; the output end of the controller is connected with the input end of each memory; the input end of the controller is connected with the output end of each buffer.

Wherein, the type of the memory includes: pseudo static random access memory PSRAM and double rate DDR memory; the type of the buffer is a first-in first-out FIFO buffer.

The embodiment of the application also provides a data reading method executed based on the device, which comprises the following steps: simultaneously sending a read command and a read address to a plurality of memories; the memory executes the read command for each memory, reads data from the read address and writes the data into a buffer corresponding to the memory; after a preset time length, respectively acquiring data from a plurality of buffers; the preset time length is greater than or equal to the data reading time length; the data reading time length is the sum of a reading command period, a reading address period and a plurality of maximum delay periods corresponding to the memories; and generating alignment data according to the data respectively acquired from the plurality of buffers.

Wherein, a plurality of said buffers are FIFO buffers; wherein, for each memory, the memory reads one data from the read address at each target clock edge and writes the data into the corresponding FIFO buffer; after the preset time length, respectively acquiring data from a plurality of buffers, including: after a preset time length, data are respectively acquired from the same positions of the plurality of FIFO buffers at each target clock edge.

Wherein the generating alignment data based on the data acquired from the plurality of buffers, respectively, includes: data acquired from the same location of a plurality of the FIFO buffers at the same target clock edge is taken as one data combination, and one alignment data is generated using the data combination.

Wherein before the next simultaneous transmission of a read command and a read address to a plurality of memories, the method further comprises: and clearing the redundant data which are not acquired in a plurality of the buffers.

The embodiment of the application also provides a data reading method executed based on the device, which comprises the following steps: receiving a read command and a read address from a controller; executing the read command, and reading data from the read address; and writing the data into a buffer corresponding to the memory every time one data is read, so that the controller can acquire the data from the buffer after a preset time length.

Wherein the buffer is a FIFO buffer; the reading data from the read address includes: starting from the read address, one data is read at each target clock edge and written into the corresponding FIFO buffer.

The embodiment of the application also provides a data reading method executed based on any one of the devices, which comprises the following steps: the controller simultaneously sends a read command and a read address to a plurality of memories; each of the memories receives a read command and a read address from the controller; executing the read command, and reading data from the read address; writing the data into a buffer corresponding to the memory every time one data is read; after the controller is in a preset time length, respectively acquiring data from a plurality of buffers; generating alignment data according to the data respectively acquired from the plurality of buffers; the preset time length is greater than or equal to the data reading time length; the data reading time length is the sum of a reading command period, a reading address period and a plurality of maximum delay periods corresponding to the memories.

The embodiment of the application also provides a data reading device, which comprises: at least one communication interface; at least one bus connected to the at least one communication interface; at least one processor coupled to the at least one bus; at least one memory unit connected to the at least one bus, wherein the processor is configured to: and executing the data reading program stored in the storage unit to realize the data reading method.

The embodiment of the application also provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are executed to implement the data reading method.

Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages: in an embodiment of the present application, the apparatus includes: the data storage array comprises a plurality of data storage units, and each data storage unit comprises a memory and a buffer which are connected with each other; the output end of the controller is connected with the input end of each memory; the input end of the controller is connected with the output end of each buffer. The controller simultaneously sends a read command and a read address to a plurality of memories; the memory executes the read command for each memory, reads data from the read address and writes the data into a buffer corresponding to the memory; after a preset time length, respectively acquiring data from a plurality of buffers; the preset time length is greater than or equal to the data reading time length; the data reading time length is the sum of a reading command period, a reading address period and a plurality of maximum delay periods corresponding to the memories; and generating alignment data according to the data respectively acquired from the plurality of buffers. According to the embodiment of the application, the data read from the memory are firstly cached to the buffer, the buffer is used for intermediate buffering of the data, after the data of the same storage address from different memories are all aligned, the data of the same storage address from different memories are obtained from the buffer, at the moment, the data of the same storage address from different memories are aligned, and the problem that the data cannot be read out at the same time and the data cannot be aligned is avoided.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.

FIG. 1 is a schematic diagram of a data read latency according to an embodiment of the present application;

FIG. 2 is a block diagram of a data reading apparatus according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a data reading apparatus according to an embodiment of the present application;

FIG. 4 is a flow chart of a data reading method according to an embodiment of the present application;

FIG. 5 is a flow chart of a data reading method according to another embodiment of the present application;

fig. 6 is a structural diagram of a data reading apparatus according to an embodiment of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein.

The following disclosure provides many different embodiments, or examples, for implementing different structures of the application. In order to simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The embodiment of the application provides a data reading device. The data reading device is arranged in the data reading equipment for realizing the function of reading data alignment. As shown in fig. 2, a structure diagram of a data reading apparatus according to an embodiment of the present application is shown.

The data reading device includes, but is not limited to: a controller 210 and a data storage array 20, the data storage array 20 comprising a number of data storage units 200. Each of the data storage units 200 includes a memory 220 and a buffer 230 connected to each other. An output terminal of the controller 210 is connected to an input terminal of each of the memories 220; an input of the controller 210 is connected to an output of each of the buffers 230.

Further, the data reading apparatus includes: a plurality of memories 220 and a plurality of buffers 230 in the same number and one-to-one correspondence. That is, one buffer 230 is provided for each memory 220.

In an embodiment of the present application, the plurality of memories 220 may be memories having a DDR (Double Data Rate) interface. The DDR interface has the property that an address is entered from which data will be output consecutively. The plurality of memories 220 may also be memories having a dual-edge sampling interface or a single-edge sampling interface.

In this embodiment, an output terminal of the controller 210 is connected to an input terminal of each of the memories 220. An input of the controller 210 is connected to an output of each of the buffers 230. The output of each memory 220 is connected to the input of its corresponding buffer 230.

The data reading task may be performed based on the above connection relationship, and the data read from the different memories 220 may implement data alignment, and a specific implementation will be described in a method embodiment later, so that a detailed description will be omitted herein.

In order to make the embodiments of the present application easier to understand, the following description will be given with an example of two memories 220 and two buffers 230. Fig. 3 is a schematic diagram of a data reading device according to an embodiment of the present application.

In this example, the type of the memory 220 may be a PSRAM, and the memory 220 includes a first PSRAM221 and a second PSRAM222; the buffer 230 may be a FIFO (First Input First Output, first-in first-out) buffer, and the buffer 230 includes a first FIFO buffer 231 and a second FIFO buffer 232.

The output terminal of the controller 210 is connected to the input terminal of the first PSRAM221 and the input terminal of the second PSRAM222, respectively. The input end of the controller 210 is connected to the output end of the first FIFO buffer 231 and the output end of the second FIFO buffer 232, respectively. The output of the first PSRAM221 is connected to the input of its corresponding first FIFO buffer 231. The output of the second PSRAM222 is coupled to the input of its corresponding second FIFO buffer 232.

Further, the output terminal of the controller 210 is connected to the input terminal of the first PSRAM221 and the input terminal of the second PSRAM222, respectively, and at least includes: the read signal output end of the controller 210 is respectively connected to the read signal input end of each of the memories 220, and the connection relationship is used for the controller 210 to send a read command (INST) and a read address (A) to the plurality of memories 220 (e.g. the first PSRAM221 and the second PSRAM 222) simultaneously, so that each memory 220 can start executing the read command, read data (rdata 1[7:0] and rdata2[7:0 ]) from the read address, and write the read data (rdata 1[7:0] and rdata2[7:0 ]) into the corresponding buffers 230 (e.g. the first FIFO buffer 231 and the second FIFO buffer 232) one by one. The enable signal output terminals of the controller 210 are respectively connected to enable signal input terminals of each of the memories 220, and the connection relationship is used for the controller 210 to simultaneously send CE signals (enable signals) to the memories 220, so that the memories 220 start to be in an operating state based on the CE signals. The clock signal output terminals of the controller 210 are respectively connected to the clock signal input terminals of each of the memories 220, and the connection relationship is used for the controller 210 to simultaneously provide the clock signals (CLK) for the memories 220, so that the memories 220 can use the same clock signal to read data according to clock edges. In general, when writing data into the buffer 230, the memory 220 reads data from the DQS clock edge according to its own memory clock signal DQS, and writes the data into the buffer 230, wherein the memory clock signal DQS and the clock signal CLK are the same frequency signals. For ease of understanding, the present embodiments embody and describe only the clock signal CLK.

Further, an input terminal of the controller 210 is connected to an output terminal of each of the buffers 230, and at least includes: the data input of the controller 210 is connected to the data output of each of the buffers 230.

Further, the output terminal of the memory 220 is connected to the input terminal of the corresponding buffer 230, and at least includes: the data output of the memory 220 is connected to the data input of its corresponding buffer 230.

Further, the apparatus comprises a data processor (not shown). The data processor acts as a user of the data ultimately read out, for example: the data processor is an image processor.

The read signal input of the controller 210 is connected to the read signal output of the data processor, and the connection is used for the data processor to send a PSRAM read command (bus_rdcmd) including a read address to the controller 210, so that the subsequent controller 210 sends a read command and a read address to each memory 220. The valid signal input terminal of the controller 210 is connected to the valid signal output terminal of the data processor, and the connection relationship is used for the data processor to send a bus read valid signal (bus_rden) to the controller 210, so that the controller 210 starts to be in a data reading working state based on the bus read valid signal. The bus data output of the controller 210 is connected to the bus data input of the data processor, and the connection is used for the controller 210 to return data (bus_rdata [15:0 ]) to the data processor, wherein the data is generated by the controller 210 according to the rdata1[7:0] and the rdata2[7:0] obtained from the FIFO buffer.

Further, the types of memory 220 include, but are not limited to: PSRAM and DDR memory; types of the buffer 230 include, but are not limited to: a FIFO buffer; wherein the valid signal output of the controller 210 is connected to the valid signal input of each FIFO buffer, respectively, the connection is used for the controller 210 to send the read data valid signals (rd_en1 and rd_en2) to the respective FIFO buffers, so as to put the respective FIFO buffers into a read data operation state (the connection is not shown in fig. 2).

Embodiments of the present application employ a multiple memory 220 mode to increase data bandwidth. Taking a PSRAM with a data bus bandwidth of 8 bits as an example, at least two PSRAMs can work simultaneously to increase the data bus bandwidth to 16 bits. When storing data, one 16-bit data can be split into two 8-bit data and stored into two PSRAMs respectively. When reading 16-bit data, two 8-bit data need to be read out simultaneously from two PSRAMs and recombined into 16-bit data. In order to avoid the situation that two 8-bit data cannot be aligned (the readout time points of the two 8-bit data are different), and cannot be recombined into 16-bit data, the embodiment of the application normally reads the two 8-bit data, however, because of the fact that two PSRAMs have read delay, the two 8-bit data may be read out after the first one, the embodiment of the application writes the two 8-bit data read out into the two buffers 230 respectively first, ensures that after the two 8-bit data are written into the corresponding buffers 230 respectively, the two 8-bit data are acquired from the two buffers 230, and even if the two 8-bit data are written into the corresponding buffers 230 first and then, the two 8-bit data can be simultaneously taken out from the two buffers 230, so that the alignment and recombination of the two 8-bit data into the original 16-bit data are realized.

The embodiment of the application also provides a data reading method based on the device.

The execution body of the embodiment is a controller. Fig. 4 is a flowchart of a data reading method according to an embodiment of the present application.

In step S410, a read command and a read address are simultaneously sent to a plurality of memories.

And the read command is used for indicating the memory to start to execute the data reading task.

A read address for indicating a first address of the memory read data.

And simultaneously sending a read command to a plurality of memories, and then simultaneously sending a read address to the plurality of memories, so as to ensure that the plurality of memories simultaneously read data of the same address. Each memory performs the following steps: and the memory executes the read command, starts to read data from the read address and writes the data into a buffer corresponding to the memory.

Specifically, the memory of the present embodiment is a memory having a DDR interface, and according to the characteristics of the DDR interface, the memory sequentially reads one data from the first address at each target clock edge, and writes the data into a buffer corresponding to the memory.

Further, the target clock edge is determined from a sampling interface of the memory. When the memory has a dual-edge sampling interface, the target clock edge includes a rising edge and a falling edge. The target clock edge may be a rising edge when the memory has a single-edge sampling interface.

Further, a plurality of the memories of the present embodiment may be PSRAMs. The controller pulls the CE signal low and the respective PSRAM begins to operate. The controller sends out a read command INST and a read address A to each PSRAM, each PSRAM starts to read data from the read address after a delay time cycle, the read address is automatically increased, and reads one data along each target clock edge and writes the data into a corresponding buffer until the CE signal is pulled high. In this way, in the whole CE signal validity period, only one read command and one read address are required to be sent to each PSRAM by the controller, and the data can be read one by one and written into the buffer one by one from the data corresponding to the read address.

Further, the plurality of buffers in this embodiment are all FIFO buffers. For each memory, the memory reads one data from the read address at each target clock edge and writes the data into a corresponding FIFO buffer. The FIFO buffer has a first-in first-out characteristic, so that the data read by the memory first is read from the FIFO buffer, the data read by the memory later is read from the FIFO buffer, and the data read by the memory later is read from the FIFO buffer.

Step S420, after a preset time length, respectively acquiring data from a plurality of the buffers.

The preset time length is used for measuring the time length of the data read at the same address of the memories respectively being written into the corresponding buffer. The time starting point of the preset time length is the sending time of the read command.

The preset time period may be preset. In this embodiment, the preset time length is greater than or equal to the data reading time length; the data reading time length is the sum of a reading command period, a reading address period and a plurality of maximum delay periods corresponding to the memories.

The read command cycle is the length of time that the read command is sent to the memory and the memory begins executing the read command. Typically, the read command period is 0.5 clock cycles.

A read address cycle is the time period during which a read address is sent to the memory and the memory begins addressing according to the read address. In general, the read address period is 1.5 clock cycles, i.e., 3 clock edges, such that the read command period and the read address period together occupy 2 clock cycles.

The maximum delay period is the maximum value in delay periods (delay cycles) corresponding to the memories respectively. The delay period is factory configuration data of the memory and is used for measuring the reading delay of the memory. The delay period is between a maximum and a minimum for a certain fixed clock frequency, for example: at a certain clock frequency, the delay period of the memory is greater than or equal to 14 clock cycles and less than or equal to 15 clock cycles. The maximum end value can be selected as the maximum delay period in delay period intervals corresponding to a plurality of memories respectively according to the currently adopted clock frequency.

Further, clock difference caused by metastable state exists in the synchronization of the asynchronous FIFO, the preset time length can be increased through the configuration register, and the depth of the asynchronous FIFO is increased to ensure that data cannot overflow. It is expected that after a predetermined length of time, the data of the first address of the different memories are all read out and stored in the respective corresponding buffers of the respective memories. Because the delay time of different memories is different, after the preset time length, the data of the first address can be ensured to be written into the buffer memory, but the data corresponding to the subsequent address is not necessarily written into the buffer memory. For example: the first FIFO buffer has been written with 4 data in sequence, while the second FIFO buffer is written with only 2 data in sequence. Thus, after a predetermined length of time, data can be retrieved from the same location of a plurality of said FIFO buffers at each target clock edge. For example: at a first target clock edge, data at a first location of the plurality of FIFO buffers is all fetched, at a second target clock edge, data at a second location of the plurality of FIFO buffers is all fetched, and so on.

Step S430, generating alignment data according to the data acquired from the plurality of buffers respectively.

The alignment data is raw data generated from data from the plurality of buffers, respectively. The generation process is the reverse process of splitting and storing original data into a plurality of memories.

Specifically, data acquired from the same positions (the same depths) of the plurality of FIFO buffers at the same target clock edge is taken as one data combination, and one aligned data is generated using the data combination, thereby obtaining one larger bit width data.

For example: when data of a pixel point is stored, the controller separates RGB three-channel data of the pixel point, and stores 3 single-channel data into 3 memories respectively; when the data of the pixel point is read, 3 memories read single-channel data corresponding to the read address at the same target clock edge and respectively write the single-channel data into the first positions of the corresponding FIFO buffers; the controller acquires single-channel data from the first positions of the plurality of FIFO buffers at a target clock edge, and re-fuses the single-channel data at the first positions of the plurality of FIFO buffers into RGB three-channel data, thereby generating alignment data.

The alignment data may be sent to a data processor, which performs corresponding data processing operations. For example: the alignment data is displayed.

In the embodiment of the application, the data amount of the read data can be controlled. The amount of data acquired from each buffer may be configured at the controller, for example: the configuration obtains 3 data from each buffer so that the controller can generate 3 alignment data. When the number of data acquired from each buffer reaches a preset configuration, the acquisition of data from each buffer is stopped and the transmission of the enable signal to the respective memories is stopped, namely: the CE signal is pulled high.

Since the memory is continuously writing data to the buffer, there may be redundant data in the buffer, such as: to ensure that there is enough data to align, the PSRAM read operation needs to read more than a configured number of data, the controller may be configured to read 3 data, but 5 data is written in the buffer, then 2 redundant data are present, so to not affect the next data read, the non-acquired redundant data in multiple buffers is emptied before the next simultaneous read command and read address is sent to multiple memories.

In the embodiment of the application, the controller simultaneously sends a read command and a read address to a plurality of memories; the memory executes the read command for each memory, reads data from the read address and writes the data into a buffer corresponding to the memory; after a preset time length, respectively acquiring data from a plurality of buffers; the preset time length is greater than or equal to the data reading time length; the data reading time length is the sum of a reading command period, a reading address period and a plurality of maximum delay periods corresponding to the memories; and generating alignment data according to the data respectively acquired from the plurality of buffers. According to the embodiment of the application, the data read from the memory are firstly cached to the buffer, the buffer is used for intermediate buffering of the data, after the data of the same storage address from different memories are all aligned, the data of the same storage address from different memories are obtained from the buffer, at the moment, the data of the same storage address from different memories are aligned, and the problem that the data cannot be read out at the same time and the data cannot be aligned is avoided.

The embodiment of the application also provides a data reading method based on the device. The execution body of the embodiment is a memory. Each memory is to perform the steps of this embodiment. Fig. 5 is a flowchart of a data reading method according to another embodiment of the present application.

Step S510, a read command and a read address are received from the controller.

Step S520, executing the read command, and starting to read data from the read address.

In step S530, each time a piece of data is read, the data is written into a buffer corresponding to the memory, so that the controller obtains the data from the buffer after a preset time length.

The buffer is a FIFO buffer.

And starting from the read address, reading one data at each target clock edge and writing the data into a corresponding FIFO buffer.

According to the embodiment of the application, by combining the characteristics of the PSRAMs, the data alignment of the PSRAMs can be completed through the implementation steps of the method, and because the data written into the same address of the PSRAMs is data alignment, the embodiment of the application can realize the reading alignment of the PSRAMs by using the buffer, so that the purpose of improving the data storage bandwidth can be achieved by reading or writing the PSRAMs based on the application.

The data reading device according to the embodiment of the application may execute the following data reading method, including: the controller simultaneously sends a read command and a read address to a plurality of memories; for each of the memories, each of the memories receives a read command and a read address from the controller; executing the read command, and reading data from the read address; writing the data into a buffer corresponding to the memory every time one data is read; after the controller is in a preset time length, respectively acquiring data from a plurality of buffers; generating alignment data according to the data respectively acquired from the plurality of buffers; the preset time length is greater than or equal to the data reading time length; the data reading time length is the sum of a reading command period, a reading address period and a plurality of maximum delay periods corresponding to the memories.

In this way, the embodiment of the application firstly caches the data read from the memory into the buffer, uses the buffer to make intermediate buffering for the data, and obtains the data from the same storage address of different memories from the buffer after the data from the same storage address of different memories are all aligned, so that the alignment of the data from the same storage address of different memories is realized, and the problem that the data from the same storage address of different memories cannot be read out at the same time and the data cannot be aligned is avoided.

The embodiment of the application also provides a data reading device, as shown in fig. 6, which is a structural diagram of the data reading device according to an embodiment of the application.

The data reading apparatus includes: processor 610, communication interface 620, storage unit 630, and communication bus 640. In which processor 610, communication interface 620, and storage unit 630 communicate with each other via communication bus 640.

The storage unit 630 is used for storing the computer program.

In one embodiment of the present application, the processor 610 is configured to implement the data reading method performed on the controller side according to any one of the foregoing method embodiments when executing the program stored on the storage unit 630, where the method includes: simultaneously sending a read command and a read address to a plurality of memories; the memory executes the read command for each memory, reads data from the read address and writes the data into a buffer corresponding to the memory; after a preset time length, respectively acquiring data from a plurality of buffers; the preset time length is greater than or equal to the data reading time length; the data reading time length is the sum of a reading command period, a reading address period and a plurality of maximum delay periods corresponding to the memories; and generating alignment data according to the data respectively acquired from the plurality of buffers.

Wherein, a plurality of said buffers are FIFO buffers; wherein, for each memory, the memory reads one data from the read address at each target clock edge and writes the data into the corresponding FIFO buffer; after the preset time length, respectively acquiring data from a plurality of buffers, including: after a preset time length, data are respectively acquired from the same positions of the plurality of FIFO buffers at each target clock edge.

Wherein the generating alignment data based on the data acquired from the plurality of buffers, respectively, includes: data acquired from the same location of a plurality of the FIFO buffers at the same target clock edge is taken as one data combination, and one alignment data is generated using the data combination.

Wherein before the next simultaneous transmission of a read command and a read address to a plurality of memories, the method further comprises: and clearing the redundant data which are not acquired in a plurality of the buffers.

In one embodiment of the present application, the processor 610 is configured to implement the data reading method performed on each memory side provided in any one of the foregoing method embodiments when executing the program stored on the storage unit 630, where the method includes: receiving a read command and a read address from a controller; executing the read command, and reading data from the read address; and writing the data into a buffer corresponding to the memory every time one data is read, so that the controller can acquire the data from the buffer after a preset time length.

Wherein the buffer is a FIFO buffer; the reading data from the read address includes: starting from the read address, one data is read at each target clock edge and written into the corresponding FIFO buffer.

The present application also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the data reading method performed on the controller side or the steps of the data reading method performed on each memory side as provided in any one of the method embodiments described above. Since the data reading method performed on the controller side or the data reading method performed on each memory side has been described in detail above, the description of the present embodiment is not exhaustive, and reference may be made to the related description in the foregoing embodiment, which is not repeated herein.

The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

From the above description of embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus a general purpose hardware platform, or may be implemented by hardware. Based on such understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the related art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the method described in the respective embodiments or some parts of the embodiments.

It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including," and "having" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless an order of performance is explicitly stated. It should also be appreciated that additional or alternative steps may be used.

The foregoing is merely a specific embodiment of the application to enable one skilled in the art to understand or practice the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (11)

1. A data reading apparatus, comprising:

the data storage array comprises a plurality of data storage units, and each data storage unit comprises a memory and a buffer which are connected with each other;

the output end of the controller is connected with the input end of each memory;

the input end of the controller is connected with the output end of each buffer.

2. The apparatus of claim 1, wherein the device comprises a plurality of sensors,

the types of the memory include: pseudo static random access memory PSRAM and double rate DDR memory;

the type of the buffer is a first-in first-out FIFO buffer.

3. A data reading method performed on the basis of the apparatus of any one of claims 1-2, comprising:

simultaneously sending a read command and a read address to a plurality of memories; the memory executes the read command for each memory, reads data from the read address and writes the data into a buffer corresponding to the memory;

after a preset time length, respectively acquiring data from a plurality of buffers; the preset time length is greater than or equal to the data reading time length; the data reading time length is the sum of a reading command period, a reading address period and a plurality of maximum delay periods corresponding to the memories;

and generating alignment data according to the data respectively acquired from the plurality of buffers.

4. The method of claim 3, wherein the step of,

the plurality of buffers are all FIFO buffers; wherein, for each memory, the memory reads one data from the read address at each target clock edge and writes the data into the corresponding FIFO buffer;

after the preset time length, respectively acquiring data from a plurality of buffers, including:

after a preset time length, data are respectively acquired from the same positions of the plurality of FIFO buffers at each target clock edge.

5. The method of claim 4, wherein generating alignment data from the data respectively acquired from the plurality of buffers comprises:

data acquired from the same location of a plurality of the FIFO buffers at the same target clock edge is taken as one data combination, and one alignment data is generated using the data combination.

6. The method of claim 3, wherein prior to the next simultaneous transmission of a read command and a read address to a plurality of memories, the method further comprises:

and clearing the redundant data which are not acquired in a plurality of the buffers.

7. A data reading method performed on the basis of the apparatus of any one of claims 1-2, comprising:

receiving a read command and a read address from a controller;

executing the read command, and reading data from the read address;

and writing the data into a buffer corresponding to the memory every time one data is read, so that the controller can acquire the data from the buffer after a preset time length.

8. The method of claim 7, wherein the step of determining the position of the probe is performed,

the buffer is a FIFO buffer;

the reading data from the read address includes:

starting from the read address, one data is read at each target clock edge and written into the corresponding FIFO buffer.

9. A data reading method performed on the basis of the apparatus of any one of claims 1-2, comprising:

the controller simultaneously sends a read command and a read address to a plurality of memories;

each of the memories receives a read command and a read address from the controller; executing the read command, and reading data from the read address; writing the data into a buffer corresponding to the memory every time one data is read;

after the controller is in a preset time length, respectively acquiring data from a plurality of buffers; generating alignment data according to the data respectively acquired from the plurality of buffers; the preset time length is greater than or equal to the data reading time length; the data reading time length is the sum of a reading command period, a reading address period and a plurality of maximum delay periods corresponding to the memories.

10. A data reading apparatus, characterized by comprising: at least one communication interface; at least one bus connected to the at least one communication interface; at least one processor coupled to the at least one bus; at least one memory unit connected to the at least one bus, wherein the processor is configured to: executing the data reading program stored in the storage unit to realize the data reading method of any one of claims 3 to 8.

11. A computer-readable storage medium storing computer-executable instructions that are executed to implement the data reading method of any one of claims 3-8.