CN116959523A - Control circuit of memory, pseudo-static random access memory and control method thereof - Google Patents

Control circuit of memory, pseudo-static random access memory and control method thereof Download PDF

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Publication number
CN116959523A
CN116959523A CN202310943735.7A CN202310943735A CN116959523A CN 116959523 A CN116959523 A CN 116959523A CN 202310943735 A CN202310943735 A CN 202310943735A CN 116959523 A CN116959523 A CN 116959523A
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China
Prior art keywords
data
command
read
write
instruction
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Inventor
李乾男
杜利祥
李敏娜
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Xi'an Ziguang Guoxin Semiconductor Co ltd
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Xi'an Ziguang Guoxin Semiconductor Co ltd
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Priority to CN202310943735.7A priority Critical patent/CN116959523A/en
Publication of CN116959523A publication Critical patent/CN116959523A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

The application provides a control circuit of a memory, a pseudo-static random access memory and a control method thereof. The control circuit of the memory includes: the command controller is used for judging whether a read/write command and a refresh command are received at the same time; a data buffer; and the command controller is connected, and the command controller is used for responding to the judgment of the command controller and receiving the read/write command and the refresh command simultaneously, caching the data to be processed corresponding to the read/write command in the data buffer, and executing the read/write command after the execution of the refresh command is completed. When the read instruction or the write instruction collides with the refresh, the response of the read instruction and the write instruction is delayed; the data is cached by the data cache, the refreshing operation is executed firstly, and then the reading instruction or the writing instruction is executed after the refreshing operation is finished, so that the timely execution of the refreshing operation is ensured, the loss of the stored data caused by untimely refreshing operation is avoided, and the correct writing of the data is ensured.

Description

Control circuit of memory, pseudo-static random access memory and control method thereof
Technical Field
The application relates to the technical field of storage devices, in particular to a control circuit of a memory, a pseudo-static random access memory and a control method thereof.
Background
PSRAM (Pseudo static random access memory, pseudo-static random access memory) employs the same capacitive storage structure as DRAM (Dynamic Random Access Memory ), which requires periodic replenishment of the capacitance charge in order to maintain data integrity, due to the loss of charge stored on the capacitance over time, a process known as refresh. Compared with the method that a DRAM refresh command needs to be sent by a memory controller, the PSRAM simplifies interface design, and a refreshed control module is embedded into the PSRAM, for example, the PSRAM of the Xccela protocol, so that the refresh command is not sent by the memory controller any more, but is automatically managed by the memory, and the memory controller only sends the self-needed command to the memory (such as read-write operation), thereby greatly simplifying the design of the memory controller.
However, since the refresh operation is embedded in the PSRAM, the internal refresh command and the external read/write command received from the outside are completely asynchronous, and there may be a case where the internal refresh command and the external read/write command collide, which may cause damage of refreshing the data that is not stored in time or data that needs to be written may not be written into the memory array correctly.
Disclosure of Invention
The application solves the technical problem of how to effectively solve the problem of abnormal read-write operation caused by conflict between the refresh instruction in the pseudo-static random access memory and the external read-write instruction.
In order to solve the above problems, a first aspect of the present application provides a control circuit of a memory, comprising: the command controller is used for judging whether a read/write command and a refresh command are received at the same time; a data buffer; and the command controller is connected, the read/write command and the refresh command are received simultaneously in response to the judgment of the command controller, the data to be processed corresponding to the read/write command is cached in the data buffer, and the read/write command is executed after the execution of the refresh command is completed.
In one possible embodiment, the method further comprises: the refresh command generating device is connected with the command controller and used for generating the refresh command; the command decoding device is connected with the command controller and is used for analyzing the received command, and the command comprises a read/write command; the transmission interface is connected with the command decoding device and the data buffer, and is used for receiving the external command and the data to be processed, and buffering the data to be processed in the data buffer when the command controller judges that the read/write command and the refresh command are received simultaneously.
In a possible implementation manner, the data buffer is reused for a read operation, and in response to the command controller judging that a write command and the refresh command are received simultaneously, the data buffer is used for buffering write data corresponding to the write command; and responding to the command controller to judge that the read command and the refresh command are received simultaneously, wherein the data buffer is used for buffering the read data fetched from the storage unit.
In one possible embodiment, the method further comprises: and the transmission interface is connected with the data buffer through the serial-parallel conversion device.
In one possible implementation, the data buffer is a data memory of a first-in first-out queue.
In order to solve the above-mentioned problems, a second aspect of the present application provides a pseudo static random access memory, including the control circuit of the above-mentioned memory; further comprises: the storage unit is connected with the command controller and the data buffer, and is used for storing data to be processed corresponding to a read command and storing data to be processed corresponding to a write command.
In order to solve the above problems, a third aspect of the present application provides a control method of a pseudo-static random access memory, which is applied to the pseudo-static random access memory described above, and includes: responding to the pseudo-static random access memory to acquire a refreshing instruction and a read/write instruction at the same time, executing the refreshing instruction, and caching data to be processed corresponding to the read/write instruction; the read/write instruction is executed in response to completion of the refresh instruction execution.
In a possible implementation manner, the step of executing the refresh instruction and caching the data to be processed corresponding to the read/write instruction in response to the pseudo static random access memory simultaneously acquiring the refresh instruction and the read/write instruction specifically includes: and caching the data to be processed corresponding to the read/write instruction into a data buffer, wherein the data buffer is used for caching the write data corresponding to the write instruction, and the data buffer is also used for caching the read data taken out from the storage unit when the read instruction is executed.
In one possible implementation, if the received instruction is a write instruction, the step of executing the read/write instruction in response to completion of execution of the refresh instruction includes: and acquiring a write address of the write instruction, adjusting the propagation direction of the data bus into a write data direction, and transmitting the write data cached on the data buffer to the data bus, wherein the write data is transmitted to a storage unit with the address of the write address through the data bus for storage.
In one possible implementation, if the received instruction is a read instruction, the step of executing the read/write instruction in response to completion of execution of the refresh instruction includes: and acquiring a read address of the read instruction, adjusting the propagation direction of the data bus into a read data direction, outputting the content of a storage unit with the address of the read address to the data buffer memory through the data bus, and outputting the cached content to a transmission interface after reading delay.
Unlike the prior art, the application provides a control circuit of a memory, a pseudo-static random access memory and a control method thereof, wherein the control circuit of the memory comprises: the command controller is used for judging whether a read/write command and a refresh command are received at the same time; a data buffer; and the command controller is connected, and the command controller is used for responding to the judgment of the command controller and receiving the read/write command and the refresh command simultaneously, caching the data to be processed corresponding to the read/write command in the data buffer, and executing the read/write command after the execution of the refresh command is completed. When the read instruction or the write instruction collides with the refresh, the response of the read instruction and the write instruction is deferred, the write data is cached through the data cache, the refresh operation is preferentially executed, and after the refresh is completed, the read instruction or the write instruction with the delayed response is executed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a control circuit of a memory according to an embodiment of the present application;
FIG. 2 is a schematic diagram illustrating control of a data buffer in a control circuit of the memory of FIG. 1;
FIG. 3 is a timing diagram of operations performed by the data buffer in the control circuit of the memory of FIG. 1 without a write command conflicting with a refresh;
FIG. 4 is a timing diagram illustrating operation of the data buffer in the control circuit of the memory of FIG. 1 when a write command and refresh conflict;
FIG. 5 is a flow chart of a control method of a pseudo-static random access memory according to a first embodiment of the application;
FIG. 6 is a flowchart illustrating an embodiment of step S12 in FIG. 1;
FIG. 7 is a flow chart of a second embodiment of a method for controlling a pseudo-static random access memory according to the present application;
FIG. 8 is a schematic diagram of a control system for a pseudo-static random access memory according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a pseudo-static random access memory according to one embodiment of the application;
FIG. 10 is a schematic diagram of a frame of an embodiment of a computer-readable storage medium of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to fall within the scope of the present application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two, but does not exclude the case of at least one.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
It should be understood that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The pseudo-static random access memory embeds the refresh operation, the internal refresh command and the external read-write command are completely asynchronous, and the internal refresh command and the external read-write command can collide, which can cause damage of data which are not stored in time to be refreshed or data which need to be written can not be written into the memory array correctly.
Based on the above problems, the application provides a control circuit of a memory, a pseudo-static random access memory and a control method thereof, when a read/write instruction collides with refresh, the refresh is preferably executed, write data is cached by a data buffer, and the read instruction and the write instruction are executed after the refresh is completed, thereby effectively solving the problems. The following describes a control circuit of a memory, a pseudo-static random access memory and a control method thereof in detail with reference to the drawings and embodiments.
Referring to fig. 1, fig. 1 is a schematic diagram of a control circuit of a memory according to an embodiment of the application. In one embodiment, the memory control circuit 100 includes a command controller 140 and a data register 170.
And a command controller 140, wherein the command controller 140 is used for judging whether the read/write command and the refresh command are received at the same time. A data buffer 170. The command controller 140 is connected, and when the command controller 140 determines that the read/write command and the refresh command are received simultaneously, the data to be processed corresponding to the read/write command is cached in the data buffer 170, and the read/write command is executed after the refresh command is executed. Specifically, when the received read instruction or write instruction and refresh conflict are analyzed, the refresh is selected to be executed, and the response of the read instruction and the write instruction is deferred. And the write data corresponding to the write instruction is cached, and the refresh operation is performed first, so that the data loss caused by untimely refresh can be avoided, wherein the response of the write instruction is delayed, the write data is cached on the data buffer 170, and the loss of the data to be written is avoided.
Unlike the prior art, when the read command or the write command collides with the refresh, the control circuit 100 of the memory performs the refresh first, and buffers the write data of the write command through the data buffer 170, and after the refresh is completed, performs the read command or the write command again, thereby ensuring that the timely refresh is performed to avoid the loss of the stored data caused by untimely refresh, and also avoiding the loss of the write data to ensure that the data can be correctly written.
In the present embodiment, the control circuit 100 of the memory further includes: the command decoding device 120 is configured to parse the received command, where the command includes a read/write command. Refresh instruction generating means 130 for generating a refresh instruction. The command controller 140 is connected to the command decoding device 120, and the command controller 140 is also connected to the refresh command generating device 130. The command decoding device 120 transmits the parsed read command or write command to the command controller 140, and when the command controller 140 determines that the read/write command and the refresh command are received at the same time, the command controller 140 controls the data buffer 170 to buffer the write data corresponding to the write command.
In this embodiment, the control circuit 100 of the memory further includes a transmission interface. The transmission interface is connected to the command decoding device 120 and also connected to the data buffer 170, and is used for receiving an external command and data to be processed, and buffering the data to be processed in the data buffer 170 when the command controller 140 determines that a read/write command and a refresh command are received at the same time. Specifically, the transmission interface is used for receiving the instruction and the write data, and transmitting the instruction to the command decoding device 120, and the command decoding device 120 parses the instruction. When the instruction conflict is judged, the write data is transmitted to the data buffer 170 for buffering by the transmission interface.
The data buffer 170 is reused for a read operation, and in response to the command controller 140 determining that a write command and a refresh command are received simultaneously, the data buffer 170 is used for buffering write data corresponding to the write command. In response to the command controller 140 determining that the read command and the refresh command are received simultaneously, the data buffer 170 is configured to buffer read data fetched from an external memory unit. Specifically, when a read instruction collides with a refresh instruction, read data needs to be temporarily stored out of the memory cell. The data buffer 170 is not additionally arranged to buffer the write data, but the write data is buffered by the data buffer 170 which is commonly arranged in the memory of the control circuit 100 of the original memory and used for storing the read data, and the data buffer 170 for buffering the read data is multiplexed with the write data, so that the number of the data buffers 170 required to be arranged is reduced, and the volume and the cost of the control circuit 100 of the memory are reduced.
Further, the command controller 140 and the data buffer 170 of the control circuit 100 are also connected to external memory units, when the write command collides with the refresh, the write data is temporarily stored in the data buffer 170, and when the refresh finishes executing the write command, the write data is fetched from the data buffer 170 and stored in the external memory units. When the read command collides with the refresh, the read data corresponding to the read command is taken out from the external storage unit and temporarily stored in the data buffer 170, and when the read command is executed after being delayed to respond after the refresh is completed, the read data is taken out from the data buffer 170 and transmitted to the transmission interface. The data buffer 170 is multiplexed with the temporary storage write data and the read data, so that timely execution of refreshing is ensured, the loss of storage data caused by untimely refreshing is avoided, and the loss of write data is avoided, so that correct write of data is ensured. And the data buffer 170 is not required to be separately set for the write data and the read data, so that the number of the data buffers 170 required to be set is reduced.
When the refresh is completed and the write command is executed, the command controller 140 performs write control on the external storage unit according to the write command, so that the external storage unit can store data, wherein the column address corresponding to the write address of the storage unit is activated, so that the write data cached by the data buffer 170 can be stored in the column address corresponding to the external storage unit. Upon receiving the read command, the command controller 140 performs read data control on the external storage unit according to the read command, and activates a row address corresponding to the corresponding read address of the external storage unit, so as to store the read data in the row address into the data buffer 170 temporarily.
Further, in the present embodiment, the data buffer 170 is a data memory of a first-in first-out queue. Specifically, the data buffer 170 may be, for example, a FIFO (First Input First Output, first-in first-out queue) memory, where the FIFO is selected as the data buffer 170 to buffer the write data, when more than one of the buffered write data is output, the write data buffered in the FIFO is output first, the write data buffered in the FIFO is output later, and when the data is written into the FIFO, the input pointer is incremented, and when the data is fetched, the output pointer is incremented. This can also help to execute instructions in order.
The control circuit 100 of the memory further includes a serial-parallel conversion device 160, and the transmission interface is connected to the data buffer 170 through the serial-parallel conversion device 160. Specifically, the control circuit 100 of the memory needs to store data in the form of parallel data in an external storage unit, and also needs to convert the parallel data into serial data before outputting the data on the data buffer 170 to the transmission interface. When the control circuit 100 of the memory receives the read command, the read data corresponding to the read command is serial data, and the serial data needs to be converted into parallel data before the read data is buffered in the data buffer 170.
Referring to fig. 2 in combination, fig. 2 is a schematic diagram illustrating the control of the data register 170 in the control circuit 100 of the memory of fig. 1. The data buffer 170 is a FIFO. The command controller 140 performs buffer control on the data buffer 170, specifically, the data buffer 170 receives an input pointer signal and an output pointer signal transmitted by the command controller 140 to implement buffer control, when the command controller 140 transmits the input pointer control signal to the data buffer 170, if a write command is executed, the data buffer 170 can receive data of the transmission interface to write data, and if a read command is received, the data buffer 170 can receive read data of an external storage unit to write data. When the command controller 140 transmits the output pointer control signal to the data buffer 170, if a write command is executed, the data buffer 170 outputs write data to the external memory unit, and if a read command is executed, the data buffer 170 outputs the read command to the external interface 110.
Referring to fig. 3 and fig. 4 in combination, fig. 3 is a timing diagram illustrating the operation of the data buffer 170 in the control circuit 100 of the memory of fig. 1 without the conflict between the write command and the refresh command. Fig. 4 is a timing diagram illustrating operations performed by the data buffer 170 in the control circuit 100 of the memory of fig. 1 when performing a write command and a refresh collision. In this embodiment, the data buffer 170 is a FIFO. Specifically, when the write instruction is received without generating a refresh instruction, the control circuit 100 of the memory directly executes the write instruction. The write data is serially converted to parallel at the serial-to-parallel conversion device 160. Then, the command controller 140 controls the line activation of the external memory unit, the command controller 140 transmits an input pointer control signal to the data buffer 170 to enable the write data to be buffered in the data buffer 170, and then the command controller 140 transmits an output pointer control signal to the data buffer 170 to enable the write data to be output from the data buffer 170 and stored in the line address corresponding to the external memory unit. When the refresh command is generated while the write command is received, the refresh command is executed first, and when the refresh command is executed, the input pointer control signal is transmitted to the data buffer 170, so that the write data corresponding to the write command is buffered in the data buffer 170 first, and after the refresh is completed, the output pointer control signal is transmitted to the data buffer 170, so that the write data is output from the data buffer 170 and stored in the external memory unit.
Unlike the prior art, when the read command or the write command collides with the refresh, the control circuit 100 of the memory performs the refresh first, and buffers the write data of the write command through the data buffer 170, and after the refresh is completed, performs the read command or the write command again, thereby ensuring that the timely refresh is performed to avoid the loss of the stored data caused by untimely refresh, and also avoiding the loss of the write data to ensure that the data can be correctly written.
Correspondingly, the application also provides a pseudo-static random access memory, which comprises the control circuit of the memory, and a storage unit, wherein the storage unit is connected with the command controller and the data buffer, and is used for storing data to be processed corresponding to the read command and storing data to be processed corresponding to the write command.
Correspondingly, the application also provides a control method of the pseudo-static random access memory. The control method is applied to the pseudo static random access memory or the control circuit of the memory described above. Referring to fig. 5, fig. 5 is a flowchart illustrating a control method of a pseudo-static random access memory according to a first embodiment of the application.
S11: and responding to the pseudo-static random access memory to acquire the refresh command and the read/write command at the same time, executing the refresh command, and caching the data to be processed corresponding to the read/write command.
Pseudo-static random access memories employ capacitive storage cells, specifically to cache information by storing charge through a gate capacitance. Since the charge stored on the capacitor leaks out with time, in order to ensure the integrity of the data, the gate capacitor must be charged according to a certain rule to supply the information charge, and the process is refresh. The pseudo-static random access memory is internally embedded with a refreshing control module, the refreshing is automatically managed by the inside of the memory, the control module can generate a refreshing request according to a constant time interval, for example, the refreshing request is carried out once at a time interval of 2 milliseconds, 3 milliseconds and the like, and the control module can also carry out the refreshing request once when the memory reads and writes data for a designated number of times. Since the refresh request is generated by internal control and the read/write command is generated by external, the refresh request and the read/write command cannot be guaranteed to be generated one by one, and a conflict may exist.
In this embodiment, when the read instruction or the write instruction collides with the refresh, the refresh is selected to be executed, and the response of the read instruction and the write instruction is deferred. And the write data corresponding to the write instruction is cached, and the refreshing operation is carried out first, so that the data loss caused by untimely refreshing can be avoided, wherein the response of the write instruction is delayed, the write data is cached on the data cache, and the loss of the data to be written is avoided.
Wherein, the conflict between refreshing and reading/writing instruction means that the memory generates a refreshing instruction and receives an external reading instruction or writing instruction at the same time; or the memory is being refreshed when the memory receives an external read or write command. That is, when there is both a refresh command and a read/write command, the response of the read/write command is deferred, and when the read/write command is received, the response of the read/write command is deferred if a refresh is being performed.
In this step, in response to the refresh conflicting with the read instruction, the response to the read instruction is delayed, and the refresh is performed. And responding to conflict between refreshing and writing instructions, delaying responding to the writing instructions, executing refreshing, utilizing a data buffer to buffer the writing data corresponding to the writing instructions, executing the writing instructions after refreshing is completed, and outputting the writing data from the data buffer.
In this step, when each time a read instruction or a write instruction is received, it is first determined whether the instruction collides with the refresh, if not, the received read instruction and write instruction are directly executed, and if so, the response to the read instruction and write instruction is delayed. And the following steps are performed.
S12: the read/write instruction is executed in response to completion of the execution of the refresh instruction.
In this step, before executing the read/write instruction, the method further includes: no refresh command is generated. And executing the instruction of delaying response again when the current refresh is completed and no new refresh instruction is generated.
When the conflict delay response is a read instruction, the read instruction is executed, the memory adjusts the propagation direction of the data bus to be the read data direction, and the content of the memory unit with the address being the read address is output to the transmission interface through the data bus. When the conflict delay response is a write instruction, executing the write instruction, adjusting the propagation direction of the data bus into the direction of write data by the memory, sending the write data cached by the data buffer to the data bus, and sending the write data to a storage unit with a write address for storage through the data bus.
Compared with the prior art, the control method of the pseudo-static random access memory is characterized in that when a read instruction or a write instruction collides with refresh, the refresh is executed first, write data of the write instruction is cached through the data buffer, and after the refresh is completed, the read instruction or the write instruction is executed again, so that the timely execution of the refresh is ensured, the loss of storage data caused by untimely refresh is avoided, and the loss of the write data is avoided, so that the correct writing of the data is ensured.
Further, in an application scenario, when the pseudo-static random access memory executes a write instruction or a read instruction, the pseudo-static random access memory internally responds to a refresh request, and then the refresh is performed after the current execution instruction is executed.
When executing the read command, the pseudo-static random access memory sends data to the transmission interface for sampling by the controller after the read delay, but the time required for reading the data from the read command to the storage unit in the memory is not fixed, the length of the time is changed along with parameters such as the process procedure, the voltage temperature and the like, and generally, the time required for reading the data from the read command to the storage unit is smaller than the read delay time, so that the conventional pseudo-static random access memory needs to be additionally provided with a storage structure to buffer the data read from the storage unit, and then the data buffered in the storage structure is sent to the transmission interface after the read delay. In the above embodiment, the write data corresponding to the write instruction needs to be cached by the data buffer, and the data read by the storage structure needs to be temporarily cached by the cache structure. The common arrangement of the data buffer and the buffer structure violates the characteristics of small capacity and low cost of the pseudo-static random access memory. To solve this problem, please refer to fig. 6, fig. 6 is a flowchart illustrating an embodiment of step S12 in fig. 5. In a specific embodiment, the step S12 may specifically include:
s121: after the refreshing is completed, judging whether the instruction to be executed is a read instruction, if so, executing S122; if not, S123 is executed.
S122: and acquiring a read address of the read instruction, adjusting the propagation direction of the data bus into a read data direction, outputting the content of a storage unit with the address of the read address to a data buffer through the data bus for buffering, and outputting the buffered content to a transmission interface after reading delay.
Specifically, when the memory executes a read instruction and a write instruction, both data input and data output are transmitted through the same data bus. In this embodiment, the storage unit is connected to the data buffer via a data bus, and the data buffer is also connected to the transmission interface via the data bus. When a read instruction is carried out, the memory adjusts the data transmission direction of the data bus to be the read data direction through the read/write control switch, and at the moment, the data transmission direction is as follows: the data buffer is connected with the data storage unit, and the transmission interface is connected with the data storage unit. After the read address of the read instruction is determined, the content of the storage unit with the address being the read address is output to the data buffer through the data bus for buffering, and after the read delay time, the content buffered in the data buffer is output to the transmission interface.
The data buffer is used for buffering write data of the write command during collision, and is also used for buffering data content which needs to be temporarily stored when the read command is executed due to overlong read delay time, the data to be read is temporarily stored in the data buffer, and the data to be read on the data buffer is output to the transmission interface through the data bus after the read delay time.
The data buffer is not additionally arranged to buffer the write data to be buffered due to collision, but the write data is buffered by the data buffer for storing the read data commonly arranged in the original pseudo-static random access memory, the data buffer for buffering the read data is multiplexed with the write data, and the data buffer multiplexes the read operation. Therefore, no additional data buffer is needed, which is beneficial to reducing the volume and the cost of the pseudo-static random access memory.
The data stored in the storage unit of the pseudo-static random access memory is parallel data, and the parallel data is required to be converted into serial data before the data on the data buffer is output to the transmission interface.
S123: the method comprises the steps of obtaining a write address of a write instruction, adjusting the propagation direction of a data bus to be a write data direction, sending write data cached by a data buffer to the data bus, and sending the write data to a storage unit with the address of the write address through the data bus for storage.
Specifically, when executing a write instruction with delayed response, the memory adjusts the data transmission direction of the data bus to be the data writing direction through the read/write control switch, and at the moment, the propagation direction of the data is as follows: from the data buffer to the memory unit. After determining the write address, the write data is sent to a memory unit with the address as the write address through a data bus for storage.
In this embodiment, the data buffer is not additionally provided to buffer the write data, but the write data is buffered by the data buffer for storing the read data commonly provided in the original pseudo-static random access memory, and the data buffer for buffering the read data is multiplexed with the write data, so that the number of the data buffers required to be set is reduced, which is beneficial to reducing the volume and the cost of the pseudo-static random access memory.
When the pseudo-static random access memory receives a read instruction, the read data corresponding to the read instruction is serial data, and the serial data is required to be converted into parallel data before the read data is cached in the data buffer.
The pseudo-static random access memory may receive a read instruction or a write instruction more than once when performing refresh. To execute instructions correctly in order, conflicts are avoided. Referring to fig. 7, fig. 7 is a flowchart illustrating a control method of a pseudo-static random access memory according to a second embodiment of the application. In yet another specific embodiment, the control method includes:
s21: and responding to conflict between refreshing and a read/write instruction, delaying responding to the read/write instruction, executing refreshing, and caching write data by utilizing a data buffer, wherein the response is delayed after a plurality of read/write instruction numbers.
In particular, during a refresh process, the pseudo-static random access memory may receive a read instruction or a write instruction more than once. I.e. there are a number of read or write instructions that are delayed in response. The data buffer is also not limited to buffering a set of write data. And delaying response of a plurality of read instructions or write instructions received by the pseudo-static random access memory when refreshing is executed, wherein when a plurality of instructions are delayed, the instructions are numbered according to the sequence.
S22: after the refreshing is completed, a new refreshing instruction is not generated; and executing the read/write instructions one by one according to the serial number sequence.
It will be appreciated that the instructions that delay the response first execute to ensure orderly execution of the instructions by the pseudo static random access memory.
In an application scenario, if the read/write instruction of the delayed response is not completely executed, the pseudo static random access memory receives new read instructions and write instructions again, then the read instructions and write instructions of the numbered delayed response are executed first, and the read instructions and write instructions received again are numbered continuously and then delayed to respond, and the subsequent execution is waited.
In another application scenario, when the read/write instruction of the delayed response of the serial number is not completely executed when a new refresh instruction is generated in the memory, the current read/write instruction is executed, then the refresh is performed, and the instruction of the delayed response of the serial number is executed again after the refresh is completed. The pseudo-static random access memory is guaranteed to carry out refreshing processing preferentially, and instructions are executed orderly.
Further, in this embodiment, the data buffer is preferably a data memory of a first-in first-out queue, such as a FIFO (First Input First Output, first-in first-out queue) memory, and the FIFO is selected as the data buffer to buffer the write data, when the buffered write data is more than one, the write data buffered in the FIFO is output first when the buffered write data is output in the FIFO, the write data buffered later in the FIFO is output later, and when the data is written into the FIFO, the input pointer is incremented, and when the data is fetched, the output pointer is incremented. This can also help to execute instructions in order.
Compared with the prior art, the read-write and refresh control method of the pseudo-static random access memory is characterized in that when a read instruction or a write instruction collides with refresh, the refresh is executed first, and response to the read instruction and the write instruction is delayed. And the data buffer buffers the write data corresponding to the write instruction, and after the refreshing is finished, the read instruction or the write instruction with delayed response is executed, so that the timely execution of the refreshing is ensured, the loss of the stored data caused by untimely refreshing is avoided, and the loss of the write data is avoided, so that the correct write of the data is ensured. On the other hand, the data buffer is not additionally arranged to buffer the write data, but the data buffer for storing the read data is generally arranged through the original pseudo-static random access memory, and the data buffer for buffering the read data is multiplexed with the write data, so that the data buffer is not additionally arranged, and the volume and the cost of the pseudo-static random access memory are reduced. And meanwhile, the data buffer is selected as a data memory FIFO of a first-in first-out queue, when more than one write data is buffered, the buffered write data in the FIFO is output first, and the buffered write data in the FIFO is output later, so that the method can help to execute the buffered instructions in the data buffer more orderly.
The application also provides a control system of the pseudo-static random access memory, please refer to fig. 8, fig. 8 is a schematic diagram of a framework of an embodiment of the control system of the pseudo-static random access memory of the application. In a specific embodiment, the control system of the pseudo-static random access memory includes a receiving module 1, a judging module 2, a buffering module 3 and an executing module 4.
The receiving module 1 is used for receiving a read/write instruction; the judging module 2 judges whether the received instruction collides with refreshing; the buffer module 3 buffers the data to be processed corresponding to the read/write instruction when in conflict; and the execution module 4 executes the read/write instruction after refreshing is completed.
In some embodiments, the step of the buffer module 3, in response to the pseudo-static random access memory simultaneously obtaining a refresh instruction and a read/write instruction, executing the refresh instruction and buffering the data to be processed corresponding to the read/write instruction specifically includes: and caching the data to be processed corresponding to the read/write instruction into a data buffer, wherein the data buffer multiplexes the read operation.
In some embodiments, if the received instruction is a write instruction, the step of executing the read/write instruction by the execution module 4 in response to the completion of the execution of the refresh instruction includes: and acquiring a write address of the write instruction, adjusting the propagation direction of the data bus into a write data direction, and transmitting the write data cached on the data buffer to the data bus, wherein the write data is transmitted to a storage unit with the address of the write address through the data bus for storage.
In some embodiments, the data buffer multiplexes the read operation, specifically including: the data buffer is used for buffering write data corresponding to the write instruction, and is also used for buffering read data taken out from the storage unit when executing the read instruction.
In some embodiments, if the received instruction is a read instruction, the step of executing the read/write instruction by the execution module 4 in response to the completion of the execution of the refresh instruction includes: and acquiring a read address of the read instruction, adjusting the propagation direction of the data bus into a read data direction, outputting the content of a storage unit with the address of the read address to the data buffer memory through the data bus, and outputting the cached content to a transmission interface after reading delay.
In some embodiments, the data in the data buffer and the storage unit are parallel data, and the transmission interface and the external data transmission are serial data transmission; when the data to be processed is write data, before the step of caching the write data in the data cache, the method further comprises the following steps: converting the write data from serial to parallel; before the step of outputting the buffered content to the transmission interface, the method further comprises: the data is changed from parallel to serial.
In some embodiments, the data buffer is a first-in first-out queue data memory.
The application also provides a pseudo-static random access memory (pseudo-static random access memory), and please refer to fig. 9. FIG. 9 is a schematic diagram of a pseudo-static random access memory according to an embodiment of the application. The pseudo-static random access memory 50 comprises a memory 51 and a processor 52 coupled to each other, the processor 52 being adapted to execute program instructions stored in the memory 51 to implement the steps of any of the above-described embodiments of the control method of the pseudo-static random access memory 50. In one particular implementation scenario, pseudo-static random access memory 50 may include, but is not limited to: microcomputer, server.
In particular, the processor 52 is configured to control itself and the memory 51 to implement the steps of any of the above-described embodiments of the method of controlling the pseudo-static random access memory 50. The processor 52 may also be referred to as a CPU (Central Process ing Unit ). The processor 52 may be an integrated circuit chip having signal processing capabilities. The processor 52 may also be a general purpose processor 52, a digital signal processor 52 (Digital Signal Processor, DSP), an application specific integrated circuit (Appl icat ion Specific Integrated Circui t, ASIC), a Field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The general purpose processor 52 may be a microprocessor 52 or the processor 52 may be any conventional processor 52 or the like. In addition, the processor 52 may be commonly implemented by an integrated circuit chip.
The application also proposes a computer readable storage medium. Referring to fig. 10, fig. 10 is a schematic diagram of a frame of an embodiment of a computer readable storage medium according to the present application. The computer readable storage medium 60 stores program instructions 600 that can be executed by a processor, the program instructions 600 being configured to implement the steps of any of the above-described embodiments of a method for controlling a pseudo-static random access memory.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of modules or units is merely a logical functional division, and there may be additional divisions of actual implementation, e.g., units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical, or other forms.
The elements illustrated as separate elements may or may not be physically separate, and elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over network elements. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the methods of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Claims (10)

1. A control circuit of a memory, comprising:
the command controller is used for judging whether a read/write command and a refresh command are received at the same time;
a data buffer; and the command controller is connected, the read/write command and the refresh command are received simultaneously in response to the judgment of the command controller, the data to be processed corresponding to the read/write command is cached in the data buffer, and the read/write command is executed after the execution of the refresh command is completed.
2. The control circuit of claim 1, further comprising:
the refresh command generating device is connected with the command controller and used for generating the refresh command;
the command decoding device is connected with the command controller and is used for analyzing the received command, and the command comprises a read/write command;
the transmission interface is connected with the command decoding device and the data buffer, and is used for receiving the external command and the data to be processed, and buffering the data to be processed in the data buffer when the command controller judges that the read/write command and the refresh command are received simultaneously.
3. The control circuit of claim 1, wherein,
the data buffer is used for reading operation, and is used for buffering write data corresponding to the write instruction in response to the fact that the command controller judges that the write instruction and the refresh instruction are received simultaneously; and responding to the command controller to judge that the read command and the refresh command are received simultaneously, wherein the data buffer is used for buffering the read data fetched from the storage unit.
4. A control circuit according to claim 3, further comprising:
and the transmission interface is connected with the data buffer through the serial-parallel conversion device.
5. The control circuit of claim 1, wherein,
the data buffer is a data memory of a first-in first-out queue.
6. A pseudo-static random access memory comprising the control circuit of the memory of any one of claims 1-5; further comprises:
the storage unit is connected with the command controller and the data buffer, and is used for storing data to be processed corresponding to a read command and storing data to be processed corresponding to a write command.
7. A control method of a pseudo-static random access memory, applied to the pseudo-static random access memory according to claim 6, comprising:
responding to the pseudo-static random access memory to acquire a refreshing instruction and a read/write instruction at the same time, executing the refreshing instruction, and caching data to be processed corresponding to the read/write instruction;
the read/write instruction is executed in response to completion of the refresh instruction execution.
8. The control method according to claim 7, wherein the step of executing the refresh command and caching the data to be processed corresponding to the read/write command in response to the pseudo-static random access memory simultaneously acquiring the refresh command and the read/write command, specifically comprises:
and caching the data to be processed corresponding to the read/write instruction into a data buffer, wherein the data buffer is used for caching the write data corresponding to the write instruction, and the data buffer is also used for caching the read data taken out from the storage unit when the read instruction is executed.
9. The control method according to claim 7, wherein,
if the received instruction is a write instruction, the step of executing the read/write instruction in response to completion of execution of the refresh instruction includes: and acquiring a write address of the write instruction, adjusting the propagation direction of the data bus into a write data direction, and transmitting the write data cached on the data buffer to the data bus, wherein the write data is transmitted to a storage unit with the address of the write address through the data bus for storage.
10. The control method according to claim 7, wherein,
if the received instruction is a read instruction, the step of executing the read/write instruction in response to completion of execution of the refresh instruction includes: and acquiring a read address of the read instruction, adjusting the propagation direction of the data bus into a read data direction, outputting the content of a storage unit with the address of the read address to the data buffer memory through the data bus, and outputting the cached content to a transmission interface after reading delay.
CN202310943735.7A 2023-07-28 2023-07-28 Control circuit of memory, pseudo-static random access memory and control method thereof Pending CN116959523A (en)

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