CN117750769A - Method for manufacturing flash memory device - Google Patents
Method for manufacturing flash memory device Download PDFInfo
- Publication number
- CN117750769A CN117750769A CN202311369546.XA CN202311369546A CN117750769A CN 117750769 A CN117750769 A CN 117750769A CN 202311369546 A CN202311369546 A CN 202311369546A CN 117750769 A CN117750769 A CN 117750769A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- peripheral
- voltage device
- region
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 230000002093 peripheral effect Effects 0.000 claims abstract description 111
- 238000003860 storage Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
The application provides a preparation method of a flash memory device, which comprises the following steps: etching the second dielectric layer and part of the first dielectric layer of the peripheral high-voltage device region and the peripheral low-voltage device region; removing the residual first dielectric layers of the peripheral high-voltage device region and the peripheral low-voltage device region, and forming a side-cut opening in the first dielectric layer of the storage region; forming a third dielectric layer; and etching the third dielectric layer, part of the second dielectric layer of the storage area and the pad oxide layer of the peripheral low-voltage device area to remove the second dielectric layer and the third dielectric layer at the top end of the side-cut opening. According to the method, the third dielectric layer is formed on the side face of the second dielectric layer of the storage area, the third dielectric layer of the storage area and the second dielectric layer with partial thickness are removed through etching, the second dielectric layer at the top end of the side-digging opening can be completely removed under the condition that the side-digging opening is not further enlarged, hidden danger that the second dielectric layer falls off is eliminated, and the conditions that the surface of the substrate of the peripheral logic area is damaged and the yield of devices is affected due to the falling of the second dielectric layer are avoided.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a preparation method of a flash memory device.
Background
In the conventional flash memory device manufacturing process, stacked oxide layers, a first dielectric layer and a second dielectric layer are formed on substrates of a peripheral logic area and a storage area adjacent to the peripheral logic area, and then the second dielectric layer and the first dielectric layer of the peripheral logic area need to be removed when the peripheral logic area process is continued, however, after the second dielectric layer and the first dielectric layer of the peripheral logic area are removed, the first dielectric layer on the side surface of the storage area is mistakenly etched to form a side-cut opening, and the second dielectric layer on the top end of the side-cut opening easily sags due to a certain weight, so that the second dielectric layer on the top end of the side-cut opening has a falling (peeling) risk, and the dropped second dielectric layer not only damages the surface of the substrate of the peripheral area, but also has a certain influence on the device yield.
Disclosure of Invention
The application provides a preparation method of a flash memory device, which can solve the problem that after a first dielectric layer of a peripheral logic area is etched and removed, a second dielectric layer on the side surface of the storage area is mistakenly etched and a side-cut opening is formed, so that the second dielectric layer on the top end of the side-cut opening is caused to have a falling risk.
The embodiment of the application provides a preparation method of a flash memory device, which comprises the following steps:
providing a substrate, the substrate including a memory region and a peripheral logic region, the peripheral logic region comprising: a plurality of shallow trench isolation structures for isolating the storage area, the peripheral high-voltage device area and the peripheral low-voltage device area are formed in the substrate, and a pad oxide layer, a first dielectric layer and a second dielectric layer are formed on the substrate;
etching the second dielectric layer and the first dielectric layer with partial thickness of the peripheral high-voltage device region and the peripheral low-voltage device region;
removing the first dielectric layers with the residual thicknesses of the peripheral high-voltage device region and the peripheral low-voltage device region, wherein part of the first dielectric layers of the storage regions adjacent to the peripheral high-voltage device region are mistakenly removed to form a side-cut opening;
forming a third dielectric layer, wherein the third dielectric layer covers the upper surface and the side surface of the second dielectric layer of the storage area, the pad oxide layer of the peripheral high-voltage device area and the pad oxide layer of the peripheral low-voltage device area;
forming a patterned photoresist layer, wherein the patterned photoresist layer covers the third dielectric layer of the peripheral high-voltage device region;
etching the third dielectric layer of the storage area, the second dielectric layer with partial thickness, the third dielectric layer of the peripheral low-voltage device area and the pad oxide layer by taking the patterned photoresist layer as a mask, wherein the second dielectric layer and the third dielectric layer at the top end of the side-digging opening are removed; and
and removing the patterned photoresist layer.
Optionally, in the method for manufacturing a flash memory device, the material of the second dielectric layer and the material of the third dielectric layer are both silicon dioxide.
Optionally, in the method for manufacturing a flash memory device, a high-temperature furnace tube oxidation process is used to form the third dielectric layer.
Optionally, in the method for manufacturing the flash memory device, a wet cleaning process is used to remove the first dielectric layer with the residual thickness of the peripheral high-voltage device region and the peripheral low-voltage device region.
Optionally, in the method for manufacturing the flash memory device, a dry etching process is used to etch the second dielectric layer and the first dielectric layer with partial thickness in the peripheral high-voltage device region and the peripheral low-voltage device region.
Optionally, in the method for manufacturing a flash memory device, the material of the first dielectric layer is silicon nitride.
Optionally, in the method for manufacturing a flash memory device,the thickness of the third dielectric layer is
Optionally, in the method for manufacturing a flash memory device, after etching the third dielectric layer and the second dielectric layer with partial thickness of the storage area and the third dielectric layer and the pad oxide layer of the peripheral low-voltage device area with the patterned photoresist layer as a mask, a remaining thickness of the second dielectric layer of the storage area is not more than
The technical scheme of the application at least comprises the following advantages:
in the method for manufacturing the flash memory device, firstly, etching a second dielectric layer and a first dielectric layer with partial thickness of a peripheral high-voltage device region and a peripheral low-voltage device region; then, removing the first dielectric layers with the residual thicknesses of the peripheral high-voltage device region and the peripheral low-voltage device region, and forming a side-digging opening in the first dielectric layer of the storage region; then, forming a third dielectric layer; and finally, etching the third dielectric layer and the second dielectric layer with partial thickness of the storage area, and the third dielectric layer and the pad oxide layer of the peripheral low-voltage device area, wherein the second dielectric layer and the third dielectric layer at the top end of the side-cut opening are removed. According to the method, the third dielectric layer is formed in the side-digging opening of the side face of the second dielectric layer of the storage area, the third dielectric layer of the storage area and the second dielectric layer with partial thickness are removed through etching, the second dielectric layer at the top end of the side-digging opening can be completely removed under the condition that the side-digging opening is not further enlarged, hidden danger that the second dielectric layer falls off is eliminated, and the conditions that the surface of the substrate of the peripheral logic area is damaged and the yield of devices is affected due to the fact that the second dielectric layer falls are avoided.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method of manufacturing a flash memory device according to an embodiment of the present invention;
FIGS. 2-8 are schematic views of semiconductor structures at various process steps for fabricating a flash memory device according to embodiments of the present invention;
wherein reference numerals are as follows:
10-substrate, 11-shallow trench isolation structure, 20-pad oxide layer, 30-first dielectric layer, 31-first dielectric layer of residual thickness of peripheral logic region, 32-side-cut opening, 40-second dielectric layer, 41-second dielectric layer of residual thickness of storage region, 50-patterned photoresist layer one, 60-third dielectric layer, 70-patterned photoresist layer two.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
The inventor researches and discovers that in order to prevent the ACT (active area) from being damaged, a dry etching process and a wet etching process are generally adopted to remove the second dielectric layer of the peripheral logic area, namely, dry etching is adopted to remove the second dielectric layer with most of the thickness, and wet etching is adopted to remove the remaining second dielectric layer, but the process of the wet etching process is isotropic, so that part of the second dielectric layer in the storage area at the junction of the peripheral logic area and the storage area is mistakenly etched, a side-cut opening is formed, the second dielectric layer at the top end of the side-cut opening easily sags due to a certain weight, and therefore the second dielectric layer at the top end of the side-cut opening has the risk of falling off (peeling), and the fallen second dielectric layer not only damages the substrate surface of the peripheral area, but also has a certain influence on the yield of a device.
Based on the above-mentioned problems, the embodiment of the present application provides a method for manufacturing a flash memory device, referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a flash memory device according to an embodiment of the present invention, where the method for manufacturing a flash memory device includes:
step S1: providing a substrate, the substrate including a memory region and a peripheral logic region, the peripheral logic region comprising: a plurality of shallow trench isolation structures for isolating the storage area, the peripheral high-voltage device area and the peripheral low-voltage device area are formed in the substrate, and a pad oxide layer, a first dielectric layer and a second dielectric layer are formed on the substrate;
step S2: etching the second dielectric layer and the first dielectric layer with partial thickness of the peripheral high-voltage device region and the peripheral low-voltage device region;
step S3: removing the first dielectric layers with the residual thicknesses of the peripheral high-voltage device region and the peripheral low-voltage device region, wherein part of the first dielectric layers of the storage regions adjacent to the peripheral high-voltage device region are mistakenly removed to form a side-cut opening;
step S4: forming a third dielectric layer, wherein the third dielectric layer covers the upper surface and the side surface of the second dielectric layer of the storage area, the pad oxide layer of the peripheral high-voltage device area and the pad oxide layer of the peripheral low-voltage device area;
step S5: forming a patterned photoresist layer, wherein the patterned photoresist layer covers the third dielectric layer of the peripheral high-voltage device region;
step S6: etching the third dielectric layer of the storage area, the second dielectric layer with partial thickness, the third dielectric layer of the peripheral low-voltage device area and the pad oxide layer by taking the patterned photoresist layer as a mask, wherein the second dielectric layer and the third dielectric layer at the top end of the side-digging opening are removed; and
step S7: and removing the patterned photoresist layer.
Referring to fig. 2-8, fig. 2-8 are schematic views of semiconductor structures in various process steps for fabricating a flash memory device according to an embodiment of the present invention.
First, step S1 is performed: as shown in fig. 2, fig. 2 is a schematic diagram of a semiconductor structure after forming a second dielectric layer according to an embodiment of the present invention, a substrate 10 is provided, the substrate 10 includes a memory area and a peripheral logic area, and the peripheral logic area includes: a peripheral high-voltage device region and a peripheral low-voltage device region, wherein a plurality of shallow trench isolation structures 11 are formed in the substrate 10, the shallow trench isolation structures 11 are used for isolating the storage region, the peripheral high-voltage device region and the peripheral low-voltage device region from each other, and a pad oxide layer 20, a first dielectric layer 30 and a second dielectric layer 40 are formed on the substrate 10.
In this embodiment, the peripheral high-voltage device region is adjacent to the storage region, the storage region is located on the left side of the peripheral high-voltage device region, and the peripheral low-voltage device region is located on the right side of the peripheral high-voltage device region.
Further, in the present embodiment, the peripheral high-voltage device region may be a 5V device region; the peripheral low voltage device region may be a 1.5V device region.
In this embodiment, the shallow trench isolation structure 11 is made of silicon dioxide; the first dielectric layer 30 is made of silicon nitride; the second dielectric layer 40 is made of silicon dioxide.
It should be noted that, the present application does not describe a memory cell (cell) structure far from the junction between the memory area and the peripheral logic area, and the specific structure of the memory cell in the present application may refer to the existing conventional flash memory device, for example, the memory cell structure in the split gate flash memory device sharing the word line, and so on.
Then, step S2 is performed: as shown in fig. 3 and 4, fig. 3 is a schematic diagram of a semiconductor structure after forming a patterned photoresist layer on a memory region according to an embodiment of the present invention, and fig. 4 is a schematic diagram of a semiconductor structure after etching a second dielectric layer and a partial thickness first dielectric layer of a peripheral high voltage device region and a peripheral low voltage device region, and etching a second dielectric layer 40 and a partial thickness first dielectric layer 30 of the peripheral high voltage device region and the peripheral low voltage device region according to an embodiment of the present invention.
Specifically, step S2 may specifically include:
step S2.1: as shown in fig. 3, a photoresist layer is coated on the second dielectric layer 40, the photoresist layer is exposed and developed through a photolithography process, the photoresist layers of the peripheral high-voltage device region and the peripheral low-voltage device region are opened to obtain a patterned photoresist layer one 50, and the patterned photoresist layer one 50 covers the second dielectric layer 40 of the storage region;
step S2.2: as shown in fig. 4, the second dielectric layer 40 of the peripheral high-voltage device region and the peripheral low-voltage device region and the first dielectric layer 30 of a partial thickness are etched by using the patterned photoresist layer one 50 as a mask;
step S2.3: with continued reference to fig. 4, ashing removes patterned photoresist layer one 50.
Preferably, the second dielectric layer 40 and a portion of the thickness of the first dielectric layer 30 of the peripheral high voltage device region and the peripheral low voltage device region are etched using a dry etching process.
Next, step S3 is performed: as shown in fig. 5, fig. 5 is a schematic diagram of a semiconductor structure after forming a side-cut opening according to an embodiment of the present invention, a remaining thickness of a first dielectric layer (a remaining thickness of a first dielectric layer 31 in a peripheral logic region) in a peripheral high-voltage device region and a peripheral low-voltage device region is removed, wherein a portion of the first dielectric layer 30 in a storage region adjacent to the peripheral high-voltage device region is erroneously removed, so as to form a side-cut opening 32. At this time, in the storage area, the thicker second dielectric layer 40 is suspended at the top end of the side-cut opening 32.
Preferably, in order not to damage the surface of the active region, a wet cleaning process is used to remove the remaining thickness of the first dielectric layer 31 of the peripheral high voltage device region and the peripheral low voltage device region (peripheral logic region).
Further, step S4 is performed: as shown in fig. 6, fig. 6 is a schematic diagram of a semiconductor structure after forming a third dielectric layer according to an embodiment of the present invention, a third dielectric layer 60 is formed, and the third dielectric layer 60 covers the upper surface and the side surface of the second dielectric layer 40 of the storage area, the pad oxide layer 20 of the peripheral high-voltage device area, and the pad oxide layer 20 of the peripheral low-voltage device area.
In this embodiment, the material of the third dielectric layer 60 is silicon dioxide.
In this embodiment, a high temperature furnace tube oxidation process is used to form the third dielectric layer 60, silane gas is introduced into the furnace tube, and high temperature oxidation is performed on the upper surface and side surface of the second dielectric layer 40 in the storage region, the surface of the pad oxide layer 20 in the peripheral high voltage device region, and the surface of the pad oxide layer 20 in the peripheral low voltage device region to generate SiO 2 。
Preferably, the thickness of the third dielectric layer 60 isIn this embodiment, the thickness of the third dielectric layer 60 may be +.>
Next, step S5 is performed: as shown in fig. 7, fig. 7 is a schematic diagram of a semiconductor structure after forming a patterned second photoresist layer according to an embodiment of the present invention, a patterned second photoresist layer 70 is formed, and the patterned second photoresist layer 70 covers the third dielectric layer 60 of the peripheral high voltage device region.
Further, step S6 is performed: as shown in fig. 8, fig. 8 is a schematic diagram of a semiconductor structure after removing the second patterned photoresist layer, in which the second patterned photoresist layer 70 is used as a mask to etch the third dielectric layer 60 and a part of the thickness of the second dielectric layer 40 in the storage area, and the third dielectric layer 60 and the pad oxide layer 20 in the peripheral low-voltage device area, wherein the second dielectric layer 40 and the third dielectric layer 60 at the top of the undercut opening 32 are removed.
In this embodiment, a dry etching process may be used to etch the third dielectric layer 60 and a portion of the thickness of the second dielectric layer 40 of the storage region and the third dielectric layer 60 and the pad oxide layer 20 of the peripheral low voltage device region.
Preferably, after etching the third dielectric layer 60 and a portion of the thickness of the second dielectric layer 40 of the storage region and the third dielectric layer 60 and the pad oxide layer 20 of the peripheral low voltage device region using the patterned photoresist layer two 70 as a mask, the remaining thickness of the second dielectric layer 41 of the remaining thickness of the storage region does not exceedIn this embodiment, the remaining thickness of the second dielectric layer 41 of the storage region remaining thickness is +.>
In the application, the third dielectric layer is formed in the side-digging opening of the side surface of the second dielectric layer of the storage area, and the third dielectric layer of the storage area and the second dielectric layer with partial thickness are removed through etching, so that the second dielectric layer at the top end of the side-digging opening can be completely removed under the condition that the side-digging opening is not further enlarged, the hidden danger of falling of the second dielectric layer is eliminated, and the conditions that the surface of the substrate of the peripheral logic area is damaged and the device yield is influenced due to the falling of the second dielectric layer are avoided.
Finally, step S7 is performed: with continued reference to fig. 8, the patterned photoresist layer two 70 is removed. Specifically, an ashing process may be used to remove the patterned photoresist layer two 70.
Further, after step S7 is performed, the second dielectric layer 40 and the first dielectric layer 30 with the remaining thicknesses of the storage area may be further removed conventionally, and the process steps after step S7 in this application may be conventional process steps of the existing NOR FLASH.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.
Claims (8)
1. A method of manufacturing a flash memory device, comprising:
providing a substrate, the substrate including a memory region and a peripheral logic region, the peripheral logic region comprising: a plurality of shallow trench isolation structures for isolating the storage area, the peripheral high-voltage device area and the peripheral low-voltage device area are formed in the substrate, and a pad oxide layer, a first dielectric layer and a second dielectric layer are formed on the substrate;
etching the second dielectric layer and the first dielectric layer with partial thickness of the peripheral high-voltage device region and the peripheral low-voltage device region;
removing the first dielectric layers with the residual thicknesses of the peripheral high-voltage device region and the peripheral low-voltage device region, wherein part of the first dielectric layers of the storage regions adjacent to the peripheral high-voltage device region are mistakenly removed to form a side-cut opening;
forming a third dielectric layer, wherein the third dielectric layer covers the upper surface and the side surface of the second dielectric layer of the storage area, the pad oxide layer of the peripheral high-voltage device area and the pad oxide layer of the peripheral low-voltage device area;
forming a patterned photoresist layer, wherein the patterned photoresist layer covers the third dielectric layer of the peripheral high-voltage device region;
etching the third dielectric layer of the storage area, the second dielectric layer with partial thickness, the third dielectric layer of the peripheral low-voltage device area and the pad oxide layer by taking the patterned photoresist layer as a mask, wherein the second dielectric layer and the third dielectric layer at the top end of the side-digging opening are removed; and
and removing the patterned photoresist layer.
2. The method of manufacturing a flash memory device according to claim 1, wherein the material of the second dielectric layer and the material of the third dielectric layer are both silicon dioxide.
3. The method of manufacturing a flash memory device of claim 2, wherein the third dielectric layer is formed using a high temperature furnace tube oxidation process.
4. The method of manufacturing a flash memory device of claim 1, wherein the remaining thickness of the first dielectric layer in the peripheral high voltage device region and the peripheral low voltage device region is removed by a wet cleaning process.
5. The method of manufacturing a flash memory device according to claim 1, wherein the second dielectric layer and the first dielectric layer having a partial thickness of the peripheral high voltage device region and the peripheral low voltage device region are etched by a dry etching process.
6. The method of manufacturing a flash memory device of claim 1, wherein the first dielectric layer is silicon nitride.
7. The method of manufacturing a flash memory device according to claim 1, wherein the thickness of the third dielectric layer is
8. The method of manufacturing a flash memory device according to claim 1, wherein after etching the third dielectric layer and a part of the thickness of the second dielectric layer of the memory region and the third dielectric layer and the pad oxide layer of the peripheral low voltage device region with the patterned photoresist layer as a mask, a remaining thickness of the second dielectric layer of the memory region is not more than
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311369546.XA CN117750769A (en) | 2023-10-20 | 2023-10-20 | Method for manufacturing flash memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311369546.XA CN117750769A (en) | 2023-10-20 | 2023-10-20 | Method for manufacturing flash memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117750769A true CN117750769A (en) | 2024-03-22 |
Family
ID=90257981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311369546.XA Pending CN117750769A (en) | 2023-10-20 | 2023-10-20 | Method for manufacturing flash memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117750769A (en) |
-
2023
- 2023-10-20 CN CN202311369546.XA patent/CN117750769A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6159823A (en) | Trench isolation method of semiconductor device | |
| CN112259541A (en) | Method for manufacturing NORD flash memory | |
| JP2002100675A (en) | Trench element isolation type semiconductor device and its manufacturing method | |
| CN111524800B (en) | Preparation method of field plate | |
| JP4984579B2 (en) | High voltage semiconductor integrated circuit device | |
| US6355538B1 (en) | Method of forming isolation material with edge extension structure | |
| KR20120004212A (en) | Method for fabricating capacitor | |
| CN117750769A (en) | Method for manufacturing flash memory device | |
| US6617223B2 (en) | Semiconductor-on-insulator structure fabrication having a temporary plug | |
| US6548373B2 (en) | Method for forming shallow trench isolation structure | |
| EP0506473B1 (en) | Method of producing isoplanar isolated active regions | |
| US20040266118A1 (en) | Method for manufacturing a semiconductor device | |
| CN111900125A (en) | Method for forming isolation structure | |
| CN114496902A (en) | Method for fabricating STI structure with TCR | |
| CN110854073B (en) | Method for manufacturing grid | |
| US6204107B1 (en) | Method for forming multi-layered liner on sidewall of node contact opening | |
| CN113782418A (en) | Method for manufacturing semiconductor device | |
| CN111900124A (en) | Method for forming isolation structure | |
| JP3748867B2 (en) | Manufacturing method of semiconductor device | |
| KR100510772B1 (en) | Formation method of silicon on insulator substrate for semiconductor | |
| US6344415B1 (en) | Method for forming a shallow trench isolation structure | |
| JP2008124399A (en) | Manufacturing method of semiconductor device | |
| JP2007012697A (en) | Method of manufacturing semiconductor device | |
| CN117715423A (en) | Method for manufacturing flash memory device | |
| US11961740B2 (en) | Manufacturing method for integrating gate dielectric layers of different thicknesses |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |