CN117748947A - Quick start charge pump circuit with wide input voltage range and high pumping efficiency - Google Patents

Abstract

The invention discloses a fast starting charge pump circuit with wide input voltage range and high pumping efficiency, which consists of a ring oscillator, a differential buffer circuit, a positive and negative clock generating circuit, a clock multiplying circuit and a charge pump main body circuit. The charge pump main circuit realizes the inverse dynamic control of the grid electrode of the PMOS transistor by the high voltage obtained by internal boosting through the inverter structure, can effectively control the on-off of the PMOS transistor, and is beneficial to reducing the conduction loss of the PMOS transistor. When the PMOS transistor is turned off, the grid voltage of the PMOS transistor is increased, so that the VGS is increased, the PMOS transistor is turned off more effectively, and the purpose of reducing the reverse charge of the PMOS transistor is achieved. Meanwhile, the positive and negative clock generating circuit is used for dynamically biasing the substrate when the NMOS transistor in the charge pump is turned on and turned off, the threshold voltage of the NMOS transistor is reduced when the NMOS transistor is turned on, so that the conduction loss of the NMOS transistor is reduced, and the reverse charge of the NMOS transistor can be effectively reduced by increasing the threshold voltage of the NMOS transistor when the NMOS transistor is turned off. The PMOS transistor substrate is subjected to body bias through the control signal to achieve the same effect, so that the power consumption of the charge pump is reduced, and the pumping efficiency is improved.

Description

Quick start charge pump circuit with wide input voltage range and high pumping efficiency

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a fast starting charge pump circuit with wide input voltage range and high pumping efficiency.

Background

With the development of society and the advancement of technology, realizing self-power supply by using environmental energy sources such as thermoelectric cells (TEGs) and energy collecting circuits gradually becomes one of the important trends of wearable electronic equipment development. But the voltage of the ambient energy source is typically low and most circuit loads need to operate at higher voltages, so a boost converter is required to boost the low voltage power supply to a high voltage output. When the boost circuit is in steady state operation, the boost converter can use the high voltage output of the boost converter to supply power for the control circuit to realize self-maintenance, but the boost converter needs to apply high enough voltage to start the system when starting, namely, a charge pump needs to be started to generate high voltage pulses from a low-voltage environment energy source to guide the boost converter to start. Unlike conventional charge pumps, the start-up charge pump operates only during start-up of the boost converter and only supports capacitive loading. Thus, key parameters for a self-starting boost charge pump are input voltage, pumping efficiency, charge transfer capability, and capacitive driving capability. The starting charge pump circuit is a key module of a low-voltage self-starting circuit in the energy collecting system, and is also an important precondition for miniaturization and self-power supply of wearable electronic equipment.

Common boost circuit types in integrated circuits include switched capacitor boost circuits, switched inductor boost circuits and charge pump boost circuits, and compared with switched inductor or switched capacitor boost circuits, the charge pump boost circuits have the advantages of simple circuit principle, easy realization of control circuits, small chip layout area and the like. Therefore, this circuit is often used as a pre-stage booster circuit of a subthreshold self-starting booster circuit. In the low-power self-powered energy harvesting technology, a typical representative of a conventional boost charge pump circuit structure is a Dickson charge pump and various linear charge pump structures developed based on the Dickson charge pump, and the characteristic is that the voltage difference between stages is relatively constant. The input energy and clocking signals for the charge pump boost circuit in the energy harvesting system may be provided by an ambient energy source. However, the voltage provided by the ambient energy source is low, and conventional boost circuits require a long time to transfer sufficient output charge to the load capacitor, thus requiring a long start-up time. Pumping efficiency (Vout/visual, vout being the output voltage of the charge pump circuit, visual being the ideal output voltage of the charge pump circuit, where visual= (2n+1) Vin), pumping efficiency being a critical parameter of the charge pump, reflects the difference in losses of the different circuit structures. As the output voltage increases in the charge pump circuit, the charge transfer capability of the capacitor decreases, resulting in a decrease in pumping efficiency. In view of the foregoing, there is a need for improvement in the start-up time, pumping efficiency and charge transfer capability of conventional charge pump circuits.

Disclosure of Invention

The invention aims to solve the problems of low efficiency of the traditional grid cross-coupled charge pump and poor charge transfer capability of the charge pump at present and provides a quick start charge pump circuit with wide input voltage range and high pumping efficiency.

In order to solve the problems, the invention is realized by the following technical scheme:

a fast start charge pump circuit with wide input voltage range and high pumping efficiency comprises a ring oscillator, a differential buffer circuit, a positive and negative clock generating circuit, a clock multiplying circuit and a charge pump main body circuit. The power end of the ring oscillator is connected with VDD, the ground end is connected with GND, and the output end is connected with the input end of the differential buffer circuit; the ring oscillator generates a clock signal by oscillating. The differential buffer circuit consists of a buffer chain module and a differential clock module, wherein a power end of the differential buffer circuit is connected with VDD, and a ground end of the differential buffer circuit is connected with GND; the clock signal provided by the ring oscillator generates a pair of clock signals CLK1 and CLK2 with opposite phases and equal amplitudes through a differential buffer circuit; the output end of the differential buffer circuit is connected with the input ends of the positive and negative clock generating circuit and the clock multiplying circuit. The positive and negative clock generation circuits generate corresponding positive and negative voltage clock signals clka_1 and clkb_1, which serve as substrate bias voltages for the charge pump body circuit. The power supply end of the clock multiplication circuit is connected with VDD, the ground end is connected with GND, corresponding voltage doubling clock signals CLKA and CLKB are generated through input clock signals CLK1 and CLK2, and the charge pump main body circuit utilizes the two clock signal control circuits to complete boosting. The input end of the charge pump main body circuit is connected with a power supply VDD; the output end of the charge pump is used as the output end of the boost circuit.

In the scheme, the charge pump is mainly formed by connecting two stages of charge pumps; the first-stage power pump consists of an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3, an NMOS tube MN4, a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a capacitor C1 and a capacitor C2; the second stage charge pump is composed of an NMOS tube MN5, an NMOS tube MN6, a PMOS tube MP5, a PMOS tube MP6, a capacitor C3 and a capacitor C4. The substrate of the NMOS tube MN1 and the substrate of the NMOS tube MN6 are connected and then connected to one output CLKB_1 of the positive and negative clock generating circuit; the substrate of the NMOS tube MN2 and the substrate of the NMOS tube MN5 are connected and then connected to the other output CLKA_1 of the positive and negative clock generating circuit; the substrate of NMOS tube MN4, the source of NMOS tube MN4, the upper plate of capacitor C1 and the lower plate of capacitor C4 are connected to one output CLKA of the clock multiplication circuit; the substrate of NMOS tube MN3, the source of NMOS tube MN4, the lower plate of capacitor C2 and the upper plate of capacitor C3 are connected to the other output CLKB of the clock multiplication circuit; the source electrode of the NMOS tube MN1 is connected with the source electrode of the NMOS tube MN2 and then used as the input end of a charge pump to be connected to a power supply VDD; the lower polar plate of the capacitor C1, the drain electrode of the NMOS tube MN1, the drain electrode of the PMOS tube MP1, the grid electrode of the NMOS tube MN2, the grid electrode of the NMOS tube MN3 and the grid electrode of the PMOS tube MP3 are connected to serve as a node V1; the upper polar plate of the capacitor C2, the drain electrode of the NMOS tube MN2, the drain electrode of the PMOS tube MP2, the grid electrode of the NMOS tube MN1, the grid electrode of the NMOS tube MN4 and the grid electrode of the PMOS tube MP4 are connected to be used as a node V2; the drain electrode of the NMOS tube MN3, the drain electrode of the PMOS tube MP3 and the grid electrode of the PMOS tube MP1 are connected; the drain electrode of the NMOS tube MN4, the drain electrode of the PMOS tube MP4 and the grid electrode of the PMOS tube MP2 are connected; the source electrode of the PMOS tube MP1, the substrate of the PMOS tube MP1 and the source electrode of the NMOS tube MN5 are connected; the source electrode of the PMOS tube MP2, the substrate of the PMOS tube MP2 and the source electrode of the NMOS tube MN6 are connected; the lower polar plate of the capacitor C3, the drain electrode of the NMOS tube MN5, the drain electrode of the PMOS tube MP5, the grid electrode of the NMOS tube MN6, the grid electrode of the PMOS tube MP6, the substrate of the PMOS tube MP6, the grid electrode of the PMOS tube MP3 and the substrate of the PMOS tube MP3 are connected to serve as a node V4; the upper polar plate of the capacitor C4, the drain electrode of the NMOS tube MN6, the drain electrode of the PMOS tube MP6, the grid electrode of the NMOS tube MN5, the grid electrode of the PMOS tube MP5, the substrate of the PMOS tube MP5, the grid electrode of the PMOS tube MP4 and the substrate of the PMOS tube MP4 are connected to serve as a node V3; the source electrode of the PMOS tube MP5 is connected with the source electrode of the PMOS tube MP6 to be used as output OUT;

in the above scheme, the positive and negative clock generating circuit is composed of a PMOS tube MP7, a PMOS tube MP8, a capacitor C5, a capacitor C6, an NMOS tube MN7, an NMOS tube MN8, an NMOS tube MN9 and an NMOS tube MN 10; the differential clock output CLK1 of the differential buffer circuit is connected to the grid electrode of the PMOS tube MP8, the grid electrode of the NMOS tube MN9 and the lower polar plate of the capacitor C5 of the positive and negative clock generation circuit; the differential clock output CLK2 of the differential buffer circuit is connected to the grid electrode of the PMOS tube MP7, the grid electrode of the NMOS tube MN10 and the lower polar plate of the capacitor C6 of the positive and negative clock generation circuit; the source electrode and the substrate of the PMOS tube MP7 are connected with a power supply VDD, and the drain electrode of the NMOS tube MN10 is grounded; the lower polar plate of the capacitor C6 is connected with the grid electrode of the NMOS tube MN10, the grid electrode of the NMOS tube MN7 and the grid electrode of the PMOS tube MP 7; the drain electrode of the PMOS tube MP7 is connected with the drain electrode of the NMOS tube MN7 and then is used as an output end CLKA_1 of the positive and negative clock generation circuit to be connected with the substrate of the NMOS tube MN2 and the substrate of the NMOS tube MN5 of the charge pump; the upper polar plate of the capacitor C6 is connected with the source electrode and the substrate of the NMOS tube MN8 and the drain electrode of the NMOS tube MN 10; the source electrode and the substrate of the PMOS tube MP8 are connected with a power supply VDD, and the drain electrode of the NMOS tube MN9 is grounded; the lower polar plate of the capacitor C5 is connected with the grid electrode of the NMOS tube MN9, the grid electrode of the NMOS tube MN8 and the grid electrode of the PMOS tube MP 8; the drain electrode of the PMOS tube MP8 and the drain electrode of the NMOS tube MN8 are connected and then used as the other output end CLKB_1 of the positive and negative clock generation circuit to be connected to the substrate of the NMOS tube MN1 and the substrate of the NMOS tube MN6 of the charge pump; the upper polar plate of the capacitor C5 is connected with the source electrode and the substrate of the NMOS tube MN8 and the drain electrode of the NMOS tube MN 9.

In the above scheme, the differential clock signals CLKA and CLKB output by the output terminals CLKA and CLKB of the clock multiplication circuit are opposite in phase and equal in amplitude.

In the scheme, the differential buffer circuit consists of a buffer chain module and a differential clock module; the output end of the ring oscillator is connected to the input end of the differential buffer circuit; the input end of the buffer chain module is used as the input end of the differential buffer circuit, the output end of the buffer chain module is connected with the input end of the differential clock module, the two output ends of the differential clock module are respectively used as the differential clock output ends CLK1 and CLK2 of the differential buffer circuit, and the differential clock signals output by the differential buffer circuit are opposite in phase and equal in amplitude.

Compared with the prior art, the invention has the following characteristics:

1. the positive and negative clock generating circuit is combined with the charge pump, the positive and negative clock generating circuit is used for providing dynamic body bias for the charge transfer tube of the charge pump, and the threshold voltage of the charge transfer tube is dynamically changed.

2. The circuit structure based on the inverter is combined with the charge pump, and the grid voltage of the charge transmission tube is improved through the structure, so that the on-resistance of the charge transmission tube is reduced, the grid cross-coupled charge pump has better pumping efficiency, and the boosting speed of the circuit is improved.

Drawings

FIG. 1 is a schematic block diagram of a high pumping efficiency fast start charge pump circuit with a wide input voltage range.

Fig. 2 is a waveform diagram of the control signals CLKA, CLKB, CLKA _1 and clkb_1.

Fig. 3 is a diagram showing a comparison of boosting effect of the boosting circuit according to the present invention and a conventional gate cross-coupled boosting circuit.

Fig. 4 is a diagram showing pumping efficiency (Vout/video) of the boost circuit according to the present invention.

Detailed Description

The present invention will be further described in detail with reference to specific examples in order to make the objects, technical solutions and advantages of the present invention more apparent.

A fast start charge pump circuit with wide input voltage range and high pumping efficiency is composed of ring oscillator, differential buffer circuit, positive and negative clock generating circuit, clock multiplying circuit and charge pump main body circuit as shown in figure 1. The power supply is connected to the power supply VDD terminal of the ring oscillator, the power supply VDD terminal of the differential buffer circuit, the power supply VDD terminal of the positive and negative clock generation circuit, the power supply VDD terminal of the clock multiplication circuit, and the input terminal (VDD) of the charge pump main body circuit. The output end of the ring oscillator is connected to the input end of the differential buffer circuit; the output end of the differential buffer circuit is connected with the input ends of the positive and negative clock generating circuit and the clock multiplying circuit; the clock multiplication circuit provides a clock control signal for the charge pump main body circuit; the positive and negative clock generation circuit generates a substrate bias voltage of the charge pump main body circuit; the output end of the charge pump main body circuit is used as the output end of the booster circuit.

A pair of differential clock signals CLK1 and CLK2 generated by the differential buffer circuit, which are opposite in phase and equal in amplitude, are connected to the clock multiplying circuit and the positive and negative clock generating circuit. The differential clock signals CLKA and CLKB output by the output ends CLKA and CLKB of the clock multiplication circuit have opposite phases and equal amplitudes; the differential clock signals clka_1 and clkb_1 output by the positive and negative clock generation circuit output terminals clka_1 and clkb_1 are opposite in phase and approximate in amplitude. The ring oscillator provides a clock signal which generates a pair of clock signals CLK1 and CLK2 with opposite phases and equal amplitudes as input signals to the positive and negative clock generating circuits and the clock multiplying circuit through the differential buffer circuit. The clock signals CLK1 and CLK2 act on the positive and negative clock generation circuits to generate corresponding positive and negative voltage clock signals CLKA_1 and CLKB_1, which serve as substrate bias voltages for the charge pump body circuit; at the same time, CLK1 and CLK2 also act on the clock multiplier circuit to generate corresponding two-voltage-doubler clock signals CLKA and CLKB, which are used by the charge pump main body circuit to control the circuit to complete the boosting.

The positive and negative clock generating circuits, as shown in fig. 1, include MP7, MP8, C5, C6, MN7, MN8, MN9, and MN10. When the positive and negative clock generating circuit works, MN9 is conducted when CLK1 is high level, and the upper electrode of capacitor C5The lower electrode plate of the capacitor C5 is charged to VDD, and the voltage difference between the upper electrode plate and the lower electrode plate of the capacitor C5 is V _{Upper part} －V _{Lower part(s)} = -VDD. When CLK1 is low level, NMOS MN9 turns off, the lower plate of capacitor C5 is connected to the low level of the clock signal, and at this time, capacitor C5 has no discharging path and the voltage cannot be suddenly changed, so the voltage of the upper plate of C5 is-VDD, thereby generating negative pressure. Then through the inverter structure selection circuit composed of MN7 and MP7, the voltage selection is carried out, and the positive and negative voltage clock signals with the same time sequence as CLK1 and CLK2 can be obtained. The gate of the NMOS tube MN7 is connected with the gate of the PMOS tube MP7 and is connected with the clock signal CLK2, the drain of the NMOS tube MN7 is connected with the drain of the PMOS tube MP7, the source of the PMOS tube MP7 is connected with VDD, and the source of the NMOS tube MN7 is connected with the output of the negative voltage circuit. When the clock signal of the grid electrode is at a high level, the NMOS tube is connected with the PMOS tube and is disconnected, and negative pressure is output; when the clock signal of the grid electrode is at a low level, the PMOS tube is conducted with the NMOS tube, and VDD is output to generate CLKA_1 positive and negative voltage clock signals. Similarly, clkb_1 is generated by C6, MN8, MP8 and MN10 in the same manner, and the positive and negative clock generation circuits thereby provide two positive and negative voltage clock signals clka_1 and clkb_1.

The charge pump main body circuit, as shown in FIG. 1, comprises NMOS transistors MN 1-6, PMOS transistors MP 1-6 and capacitors C1-4. When the charge pump main body circuit works, when CLKA is in a low level and CLKB is in a high level, MN1 is conducted, VDD transfers charge to C1 through MN1 to charge, and the voltage difference between the upper polar plate and the lower polar plate of the capacitor is equal to the input voltage Vin (VDD). When CLKA is at high level and CLKB is at low level, NMOS transistor MN1 is turned off and MN2 is turned on, capacitor C1 has no discharge path and the voltage cannot be suddenly changed instantaneously, so that the voltage of the lower plate (i.e., node V1) of capacitor C1 becomes 3VDD; at the same time, the upper plate of capacitor C2 (i.e., node V2) charges to VDD. Meanwhile, the MOS transistor MN3 is turned on and the MP3 is turned off, so that the gate of MP1 is at a low level, and MP1 is turned on. Since CLKA is high and MN5 is on, the voltage at node V1 is transmitted to the lower plate of capacitor C3 (i.e., node V4) via MP1 and MN5, so V4 is 3VDD. When the next cycle CLKA is low and CLKB is high, MP5 is turned off, the voltage of the upper plate of the capacitor C3 (i.e. the connection point between C3 and CLKB) is 2VDD, and C3 has no discharge path, the voltage cannot be suddenly changed, the voltage of the node V4 in the previous cycle is 3VDD, and thus the voltage of the lower plate of the capacitor C3 becomes 5VDD. Since CLKA is low, MP6 is turned on, so the voltage of V4 charges load capacitor CL through MP 5; meanwhile, the auxiliary MOS tube MN3 is turned off and the MP3 is turned on, the node voltage of V4 is transmitted to the grid electrode of MP1, and MP1 is turned off completely through the voltage of 5VDD. Reverse dynamic control using internally boosted high voltages is achieved, with higher control voltages transmitting more charge per clock cycle and more efficient opening of the switch to reduce conduction losses.

The differential buffer circuit is composed of a buffer chain module and a differential clock module. The power supply end of the buffer chain module and the power supply end of the differential clock module are connected with the power supply VDD, and the ground end of the buffer chain module and the ground GND are connected. The output end of the ring oscillator is connected to the input end of the differential buffer circuit; the input end of the buffer chain module is used as the input end of the differential buffer circuit, the output end of the buffer chain module is connected with the input end of the differential clock module, the two output ends of the differential clock module are respectively used as the differential clock output ends CLK1 and CLK2 of the differential buffer circuit, and the differential clock signals output by the differential buffer circuit are opposite in phase and equal in amplitude.

The clock multiplication circuit is controlled by inputs CLK1 and CLK2 of the differential buffer circuit; the power supply terminal of the clock multiplication circuit is connected with the power supply VDD, and the ground terminal is connected with the ground GND. The differential clock signals output by the two output terminals CLKA and CLKB are opposite in phase and equal in amplitude.

The working principle of the invention is as follows:

the low direct current power supply voltage generated by environmental energy sources such as TEG of the wearable device is connected to the power end of the ring oscillator, and two differential clock signals are generated through the differential buffer circuit. The two clock signals are processed by a clock multiplication circuit to generate differential clock signals CLKA and CLKB with high level of 2VDD and low level of GND; meanwhile, the positive and negative clock generating circuits generate square wave differential clock signals clka_1 and clkb_1 having high levels of VDD and low levels of about-VDD/2 by the two clock signals. As shown in fig. 2, CLKA and CLKB are a pair of differential clock signals that are equal in magnitude and opposite in phase; clka_1 and clkb_1 are differential clock signals generated by positive and negative clock generating circuits. The gate cross-coupled charge pump is dynamically body biased with the two inverted clocks clka_1 and clkb_1, thereby reducing the reverse shared charge of the charge pump. The stacked inverter structure is adopted in the invention, so that the ring oscillator can work normally under the environmental energy source voltage of TEG and the like as low as 230mV, and higher output voltage can be obtained under the low input power source voltage.

The loss of the grid cross-coupled charge pump mainly comprises reverse feed-through loss and conduction loss caused by the back grid effect of the MOS tube. (1) Reverse charge sharing brings reverse feed-through loss, and when MOS management is required to be closed, the MOS tube is not completely closed due to non-ideal grid control level or short channel length of the MOS tube, so that reverse leakage occurs between adjacent nodes, and further, the charges reversely flow back to the upper stage. (2) Because the MOS tube has a back gate effect, when the charge transfer tube is conducted, conduction loss exists in the channel. And taking an NMOS tube as an example to analyze the loss of the circuit caused by the substrate voltage. In a common process, the substrate of the NMOS tube is made of a P-type semiconductor material, the channel is n-type, and the threshold voltage of the NMOS is expressed as:

wherein V is _T0 Is the gate voltage, gamma is the bulk effect coefficient,is a strongly inverted surface potential, V _SB Is the voltage difference between the device source and the substrate. When the transistor is turned on, the turn-on loss can be reduced by increasing the gate-source voltage or the device width. However, increasing the width of the transistor increases its threshold voltage, which is detrimental to sub-threshold charge pumps operating in the low voltage domain. Another way to improve the back gate effect and reduce the conduction loss of the MOS transistor is to increase the gate-source voltage. However, in the energy harvesting application, since the harvested voltage is often lower than the threshold voltage, the invention applies a dynamic body bias technique to reduce or increase the threshold voltage of the MOS transistor when it is turned on or off, respectively.

According to the analysis, the invention designs two grid bias circuits based on the phase inverter and a positive and negative clock generating circuit, and uses the substrate bias and grid bias technology to enhance the charge transfer capability of the charge pump and shorten the voltage rising time of the charge pump boosting circuit. The positive and negative clock generation circuit is used for providing positive and negative voltage clock signals for the dynamic bias of the substrate when the NMOS tube in the charge pump works and is turned off. When the NMOS tube works, a voltage about VDD is input to the substrate of the NMOS tube, so that the threshold voltage of the NMOS tube is reduced, and the forward conduction loss is reduced; when the NMOS tube needs to be turned off, a negative voltage is input to the substrate of the NMOS tube so as to increase the threshold voltage of the NMOS tube and reduce the loss caused by reverse conduction. The substrates of the first stage PMOS transistors MP1 and MP2 are connected with the output of the stage, the substrates of the output stage PMOS transistors MP5 and MP6 are connected with the grid electrode of the output stage PMOS transistors MP5 and MP6, and the voltage V of the grid electrode-substrate is changed _SB To control the threshold voltage. The two grid bias circuits based on the phase inverters control the PMOS tubes MP1 and MP2 by introducing higher voltage of a later stage, and the reverse dynamic control can achieve better conduction effect.

The working principle of the charge pump is now analyzed in detail: (1) when CLKA is low and CLKB is high, MN1 is turned on, VDD charges C1 by MN1, and the voltage difference between the upper and lower plates of the capacitor is equal to the input voltage Vin (VDD). (2) When CLKA is high and CLKB is low, MN1 is turned off, the voltage of the upper plate of the capacitor C1 (i.e. the connection point between C1 and CLKA) is 2VDD, and C1 has no discharge path, the voltage cannot be suddenly changed, so that the voltage of the lower plate of the capacitor C1 (i.e. the node V1) becomes Vin plus a clock signal amplitude 2VDD (V) _IN +2vdd=3vdd). The voltage at node V1 is 3VDD, so MN2 is on and the upper plate of capacitor C2 (i.e., node V2) is charged to VDD. Meanwhile, the MOS tube MN3 is turned on and the MP3 is turned off, so that the MP1 grid electrode is at a low level, and MP1 is turned on; meanwhile, since CLKA is high level, MN5 is turned on. The voltage at node V1 is transferred to the lower plate of capacitor C3 (i.e., node V4) through MP1, MN5, whereupon V4 is at 3VDD. (3) When the next cycle CLKA is low and CLKB is high, MP5 is turned off, the upper plate of capacitor C3 (i.e. the connection point between C3 and CLKB) is 2VDD, and C3 is not discharged onThe voltage cannot instantaneously change suddenly, and the voltage at the node V4 in the previous cycle is 3VDD, so that the voltage at the bottom plate of the capacitor C3 (i.e., the node V4) becomes 5VDD. Since CLKA is low, MP6 is turned on, so the voltage of V4 charges load capacitor CL through MP 5; meanwhile, the MOS tube MN3 is turned off, the MP3 is turned on, the node voltage of the V4 is transmitted to the grid electrode of the MP1, and the MP1 is turned off completely through the voltage of 5VDD. The working process realizes reverse dynamic control by using higher high voltage of internal boosting, so that higher control voltage can transmit more charges in each clock period, and the conduction loss of the MOS tube is reduced more effectively.

As shown in fig. 1, in the gate cross-coupled charge pump structure, the charge pump body circuit includes an upper half boost circuit and a lower half boost circuit. The upper half booster circuit is controlled by referring to the rear-stage high voltage of the lower half booster circuit through the inverter structure, and the lower half booster circuit also realizes the self-boosting high voltage control in the same way, so that the rear-stage self-boosting high voltage cross control is realized through the inverter structure. The upper half boost circuit consisting of the capacitors C1 and C3 and their control MOS transistors was analyzed above, while the lower half boost circuit and the upper half boost circuit operate simultaneously in the same manner, but with one clock cycle difference. In the charge pump main body circuit, a symmetrical structure formed by an upper boost circuit and a lower boost circuit alternately opens and closes a charge transmission tube, so that two charge pump branches alternately charge a load capacitor CL. Thus, during each time interval, charge is always supplied to the load capacitor CL at the output terminal through one of the charge pump body circuits, thereby reducing output voltage ripple.

The working principle of the positive and negative clock generating circuit is analyzed in detail: when CLK1 is at high level, MN9 is turned on, the upper plate of capacitor C5 is grounded, the lower plate of capacitor C5 is charged to VDD, and the voltage difference between the upper and lower plates of capacitor C5 is vbatt-vbatt = -VDD. When CLK1 is low level, NMOS MN9 turns off, the lower plate of capacitor C5 is connected to the low level of the clock signal, and at this time, capacitor C5 has no discharging path and the voltage cannot be suddenly changed, so the voltage of the upper plate of C5 is-VDD, thereby generating negative pressure. Then through the inverter structure selection circuit composed of MN7 and MP7, the voltage selection is carried out, and the positive and negative voltage clock signals with the same time sequence as CLK1 and CLK2 can be obtained. The gate of the NMOS tube MN7 is connected with the gate of the PMOS tube MP7 and is connected with the clock signal CLK2, the drain of the NMOS tube MN7 is connected with the drain of the PMOS tube MP7, the source of the PMOS tube MP7 is connected with VDD, and the source of the NMOS tube MN7 is connected with the output of the negative voltage circuit. When the clock signal of the grid electrode is at a high level, the NMOS tube is connected with the PMOS tube and is disconnected, and negative pressure is output; when the clock signal of the grid electrode is at a low level, the PMOS tube is conducted with the NMOS tube, and VDD is output to generate CLKA_1 positive and negative voltage clock signals. Similarly, clkb_1 is generated by C6, MN8, MP8 and MN10 in the same manner, and the positive and negative clock generation circuits thereby provide two positive and negative voltage clock signals clka_1 and clkb_1.

The positive and negative clock generating circuit is used for providing positive and negative voltage clock signals for the dynamic bias of the substrate when the NMOS tube in the charge pump is turned on and turned off. Clka_1 and clkb_1 are clock signals whose positive voltage supplied from the positive and negative clock generating circuit is VDD negative voltage of about-VDD/2, and the two clocks are in phase with CLKA and CLKB, respectively. Taking the MN1 pipe as an example, when CLKB is at a high level, MN1 needs to be turned on, and in order to reduce the threshold voltage of the NMOS pipe, a voltage greater than zero needs to be input to the substrate to reduce the forward conduction loss; thus, clkb_1 is turned on at a positive voltage of VDD. When CLKB is low, MN1 needs to be turned off, and a voltage smaller than zero is input to the substrate to increase its threshold voltage, so MN1 can be completely turned off to prevent the electric charge from flowing back to the power supply, thereby reducing the loss caused by reverse conduction. Regarding the dynamic substrate bias of the PMOS transistor, the input stage PMOS is connected to the high level of the stage; the output stage PMOS substrate is connected to its gate. Taking MP5 as an example, the substrate is at a low voltage when turned on, and the voltage difference with the gate is zero, and the bulk voltage of MP5 is 1 x VDD lower than the source voltage. The threshold voltage is reduced by the body bias, thereby helping MP1 turn on to reduce turn on losses. When the base signal is high MP5, which needs to be turned off, the bulk voltage of MP5 is 1 VDD higher than the source voltage, so the threshold voltage of MP5 is increased by the bulk bias, helping MP5 turn off to prevent charge from flowing back from the output.

The present invention is a start-up charge pump circuit that operates during start-up of a boost converter that supports only capacitive loads. In the charge pump, the high voltage formed by the internal booster circuit is used for carrying out inverse dynamic control and dynamic substrate bias on the transistor in the charge pump, so that the purposes of faster starting, smaller power consumption and larger slope current are realized. Fig. 3 is a diagram showing a comparison of boosting effect of the boosting circuit according to the present invention and a conventional gate cross-coupled boosting circuit. The grid cross-coupled charge pump main body circuit realizes self-boosting high-voltage control by an inverter-based structure, and simulation results prove that the boosting time of the traditional grid cross-coupled charge pump is far longer than that of the novel charge pump. After combining the reverse high voltage control and the dynamic substrate bias, the simulation result shows that the circuit can finally generate 1.49V output voltage under the condition that the total capacitance is the same. The output voltage of the charge pump is basically the same as that of the traditional charge pump, but the starting time is greatly shortened, and the boosting effect is obviously improved. Meanwhile, the simulation result shows that the boosting time (90% Vout) of the circuit is about 6 mu S, and the circuit has better charge transfer capability. Fig. 4 is a diagram showing pumping efficiency (Vout/video) of the boost circuit according to the present invention. The detailed information of the pumping efficiency measured by the circuit under different voltage power supplies can be seen through simulation results. Meanwhile, compared with two references ([ 1]Peng H,Tang N,Yang Y,et al.CMOS Startup Charge Pump With Body Bias and Backward Control for Energy Harvesting Step-Up Converters [ J ]. IEEE Transactions on Circuits and Systems I: regular paper, 2014:1618-1628 ] [2]Reddy K K,Rao P S.A DT-MOS switched-capacitor based step-Up DC/DC converter for energy harvesting applications [ A ].2020IEEE International Symposium on Sustainable Energy,Signal Processing and Cyber Security (ISSSC) [ C ].2020 ]), the minimum working voltage of the circuit provided by the invention is lower, the peak pumping efficiency is higher than that of the traditional structure under the condition of low voltage input below 376mV, and the circuit has a wider input voltage range.

It should be noted that, although the examples described above are illustrative, this is not a limitation of the present invention, and thus the present invention is not limited to the above-described specific embodiments. Other embodiments, which are apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein, are considered to be within the scope of the invention as claimed.

Claims (5)

1. The charge pump circuit is characterized by comprising a ring oscillator, a differential buffer circuit, a positive and negative clock generating circuit, a clock multiplying circuit and a charge pump main body circuit;

the input end of the charge pump main body circuit is connected with a power supply VDD; the output terminal OUT of the charge pump main body circuit serves as an output terminal of the booster circuit. The charge pump main body circuit is formed by connecting two stages of charge pumps; the first-stage power pump consists of an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3, an NMOS tube MN4, a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a capacitor C1 and a capacitor C2; the second stage charge pump is composed of an NMOS tube MN5, an NMOS tube MN6, a PMOS tube MP5, a PMOS tube MP6, a capacitor C3 and a capacitor C4.

The substrate of the NMOS tube MN1 and the substrate of the NMOS tube MN6 are connected and then connected to one output CLKB_1 of the positive and negative clock generating circuit; the substrate of the NMOS tube MN2 and the substrate of the NMOS tube MN5 are connected and then connected to the other output CLKA_1 of the positive and negative clock generating circuit; the substrate of NMOS tube MN4, the source of NMOS tube MN4, the upper plate of capacitor C1 and the lower plate of capacitor C4 are connected to one output CLKA of the clock multiplication circuit; the substrate of NMOS tube MN3, the source of NMOS tube MN4, the lower plate of capacitor C2 and the upper plate of capacitor C3 are connected to the other output CLKB of the clock multiplication circuit; the source electrode of the NMOS tube MN1 is connected with the source electrode of the NMOS tube MN2 and then used as the input end of a charge pump to be connected to a power supply VDD;

the lower polar plate of the capacitor C1, the drain electrode of the NMOS tube MN1, the drain electrode of the PMOS tube MP1, the grid electrode of the NMOS tube MN2, the grid electrode of the NMOS tube MN3 and the grid electrode of the PMOS tube MP3 are connected to serve as a node V1; the upper polar plate of the capacitor C2, the drain electrode of the NMOS tube MN2, the drain electrode of the PMOS tube MP2, the grid electrode of the NMOS tube MN1, the grid electrode of the NMOS tube MN4 and the grid electrode of the PMOS tube MP4 are connected to be used as a node V2;

the drain electrode of the NMOS tube MN3, the drain electrode of the PMOS tube MP3 and the grid electrode of the PMOS tube MP1 are connected; the drain electrode of the NMOS tube MN4, the drain electrode of the PMOS tube MP4 and the grid electrode of the PMOS tube MP2 are connected; the source electrode of the PMOS tube MP1, the substrate of the PMOS tube MP1 and the source electrode of the NMOS tube MN5 are connected; the source electrode of the PMOS tube MP2, the substrate of the PMOS tube MP2 and the source electrode of the NMOS tube MN6 are connected;

the lower polar plate of the capacitor C3, the drain electrode of the NMOS tube MN5, the drain electrode of the PMOS tube MP5, the grid electrode of the NMOS tube MN6, the grid electrode of the PMOS tube MP6, the substrate of the PMOS tube MP6, the grid electrode of the PMOS tube MP3 and the substrate of the PMOS tube MP3 are connected to serve as a node V4; the upper polar plate of the capacitor C4, the drain electrode of the NMOS tube MN6, the drain electrode of the PMOS tube MP6, the grid electrode of the NMOS tube MN5, the grid electrode of the PMOS tube MP5, the substrate of the PMOS tube MP5, the grid electrode of the PMOS tube MP4 and the substrate of the PMOS tube MP4 are connected to serve as a node V3;

the source electrode of the PMOS tube MP5 is connected with the source electrode of the PMOS tube MP6 to be used as output OUT.

2. The rapid start charge pump circuit with wide input voltage range and high pumping efficiency according to claim 1, wherein the positive and negative clock generating circuit comprises a PMOS tube MP7, a PMOS tube MP8, a capacitor C5, a capacitor C6, an NMOS tube MN7, an NMOS tube MN8, an NMOS tube MN9 and an NMOS tube MN 10;

the differential clock output CLK1 of the differential buffer circuit is connected to the grid electrode of the PMOS tube MP8, the grid electrode of the NMOS tube MN9 and the lower polar plate of the capacitor C5 of the positive and negative clock generation circuit; the differential clock output CLK2 of the differential buffer circuit is connected to the grid electrode of the PMOS tube MP7, the grid electrode of the NMOS tube MN10 and the lower polar plate of the capacitor C6 of the positive and negative clock generation circuit;

the source electrode and the substrate of the PMOS tube MP7 are connected with a power supply VDD, and the drain electrode of the NMOS tube MN10 is grounded; the lower polar plate of the capacitor C6 is connected with the grid electrode of the NMOS tube MN10, the grid electrode of the NMOS tube MN7 and the grid electrode of the PMOS tube MP 7; the drain electrode of the PMOS tube MP7 is connected with the drain electrode of the NMOS tube MN7 and then is used as an output end CLKA_1 of the positive and negative clock generation circuit to be connected with the substrate of the NMOS tube MN2 and the substrate of the NMOS tube MN5 of the charge pump; the upper polar plate of the capacitor C6 is connected with the source electrode and the substrate of the NMOS tube MN8 and the drain electrode of the NMOS tube MN 10;

the source electrode and the substrate of the PMOS tube MP8 are connected with a power supply VDD, and the drain electrode of the NMOS tube MN9 is grounded; the lower polar plate of the capacitor C5 is connected with the grid electrode of the NMOS tube MN9, the grid electrode of the NMOS tube MN8 and the grid electrode of the PMOS tube MP 8; the drain electrode of the PMOS tube MP8 and the drain electrode of the NMOS tube MN8 are connected and then used as the other output end CLKB_1 of the positive and negative clock generation circuit to be connected to the substrate of the NMOS tube MN1 and the substrate of the NMOS tube MN6 of the charge pump; the upper polar plate of the capacitor C5 is connected with the source electrode and the substrate of the NMOS tube MN8 and the drain electrode of the NMOS tube MN 9.

3. The high pumping efficiency fast start-up charge pump circuit of claim 1, wherein the ring oscillator employs a stacked inverter circuit.

4. The rapid start charge pump circuit of claim 1, wherein the power supply terminal of the clock multiplication circuit is connected to the power supply VDD, and the ground terminal is connected to the ground GND; the differential clock signals CLKA and CLKB output by the clock multiplier circuit outputs CLKA and CLKB are opposite in phase and equal in amplitude.

5. The rapid start charge pump circuit with wide input voltage range and high pumping efficiency as set forth in claim 1, wherein the differential buffer circuit is composed of a buffer chain module and a differential clock module;

the output end of the ring oscillator is connected to the input end of the differential buffer circuit; the input end of the buffer chain module is used as the input end of the differential buffer circuit, the output end of the buffer chain module is connected with the input end of the differential clock module, the two output ends of the differential clock module are respectively used as the differential clock output ends CLK1 and CLK2 of the differential buffer circuit, and the differential clock signals output by the differential buffer circuit are opposite in phase and equal in amplitude.