CN117747423A - Method for polishing bulk silicon device - Google Patents

Abstract

The present disclosure relates to methods for polishing bulk silicon devices. Methods for polishing bulk silicon are disclosed. In one aspect, mechanical polishing is facilitated by cycling between a silicon reactive slurry and deionized water as the mechanical polishing head operates on the surface. In an exemplary aspect, the polishing head polishes a bulk silicon carrier wafer to expose the back side of a Radio Frequency (RF) Complementary Metal Oxide Semiconductor (CMOS) switch, although other semiconductors may also benefit from exemplary aspects of the present disclosure. When a silicon slurry is present, a reaction occurs between the bulk silicon and the slurry such that the polishing head removes the bulk silicon. The deionized water can interrupt this reaction and help prevent overpolishing that might otherwise damage the device.

Description

Method for polishing bulk silicon device

Priority application

The present application claims the benefit of U.S. provisional patent application No. 63/376,463 filed on month 21 of 2022, the disclosure of which is hereby incorporated by reference in its entirety.

Technical Field

The technology of the present disclosure relates generally to semiconductor fabrication technology, and more particularly to polishing silicon wafers.

Background

In modern society, computing devices are of all kinds, and more particularly mobile communication devices are becoming more and more common. The popularity of these mobile communication devices is driven in part by the many functions that are currently enabled on such devices. The increase in processing power in such devices means that mobile communication devices evolve from pure communication tools to complex mobile entertainment centers, enabling enhanced user experience. The development of computing devices has been driven to a large extent by advances in semiconductor technology for creating integrated circuits capable of providing such functionality. Commercial pressures to minimize power consumption, reduce size, reduce cost, or increase processing power continue to provide room for innovation in this area.

Disclosure of Invention

Aspects disclosed in the detailed description include methods for polishing bulk silicon devices. Specifically, when the mechanical polishing head is operated on a surface, mechanical polishing is promoted by cycling between a silicon reactive slurry and deionized water. In an exemplary aspect, the polishing head polishes a bulk silicon carrier wafer to expose the back side of a Radio Frequency (RF) Complementary Metal Oxide Semiconductor (CMOS) switch, although other semiconductors may also benefit from exemplary aspects of the present disclosure. When a silicon slurry is present, a reaction occurs between the bulk silicon and the slurry such that the polishing head removes the bulk silicon. Deionized water can interrupt this reaction and help prevent overpolishing of thin silicon layers (e.g., in the trench regions) that might otherwise damage the device.

In this regard, in one aspect, a method for exposing a device for backside processing is disclosed. The method includes polishing the device with a silicon slurry and a polishing head. The method further includes rinsing the device with deionized water to remove the silicon slurry.

In another aspect, a method for exposing a device for backside processing is disclosed. The method includes polishing a back side of a device having a thin device layer by running a continuous cycle of reactive silicon slurry and deionized water.

In another aspect, a mobile terminal is disclosed that includes an integrated circuit including a device formed by a method for exposing a device for backside processing. The method includes polishing the device with a silicon slurry and a polishing head. The method further includes rinsing the device with deionized water to remove the silicon slurry.

Drawings

Fig. 1A is a cross-sectional elevation view of a semiconductor device;

FIG. 1B is a top plan view of a semiconductor wafer undergoing a conventional Chemical Mechanical Polishing (CMP) step;

FIG. 1C is a top plan view of a damaged doped silicon device in the semiconductor wafer of FIG. 1B;

FIG. 2 is a flowchart illustrating an exemplary process for polishing a semiconductor wafer in accordance with exemplary aspects of the present disclosure;

3A-3D are cross-sectional elevation views showing steps of the process of FIG. 2;

FIG. 3E is a stylized representation of a polishing tool that may be used in the process of FIG. 2;

FIG. 3F is a graph showing the circulation of alternating slurry and deionized water according to the process of FIG. 2;

FIG. 3G is a graph showing how incubation period (incubation period) varies with silicon thickness versus removal rate, and a cross-sectional view of a wafer having different thicknesses corresponding to the curve on the graph;

FIG. 4 is a graph showing removal rates compared to highly juxtaposed cycles of silicon material, showing how disruption of chemical reactions can result in softer polishing of a semiconductor wafer;

5A-5D illustrate top plan views of a semiconductor wafer after various cycles of the present disclosure; and is also provided with

Fig. 6 is a block diagram of a mobile computing device that may include a semiconductor device fabricated in accordance with exemplary aspects of the present disclosure.

Detailed Description

The embodiments set forth below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly extending onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "over" or "extending over" another element, it can extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Relative terms, such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Aspects disclosed in the detailed description include methods for polishing bulk silicon devices. Specifically, when the mechanical polishing head is operated on a surface, mechanical polishing is promoted by cycling between a silicon reactive slurry and deionized water. In an exemplary aspect, the polishing head polishes a bulk silicon carrier wafer to expose the back side of a Radio Frequency (RF) Complementary Metal Oxide Semiconductor (CMOS) switch, although other semiconductors may also benefit from exemplary aspects of the present disclosure. When a silicon slurry is present, a reaction occurs between the bulk silicon and the slurry such that the polishing head removes the bulk silicon. Deionized water can interrupt this reaction and help prevent overpolishing of thin silicon layers (e.g., in the trench regions) that might otherwise damage the device.

Before explaining exemplary aspects of the present disclosure, some limitations and problems of conventional processes are briefly reviewed with reference to fig. 1A-1C. Exemplary aspects of the present disclosure are discussed initially below with reference to fig. 2.

Fig. 1A is a cross-sectional side elevation view of a semiconductor device 100 that may have a carrier wafer 102 attached to a metallization layer 104 by an adhesive 106. The metallization layer 104 may have therein metal layers 108 (1) -108 (N) (only two shown) coupled by vias 110 that provide an option for coupling external pads or contacts (not shown) to elements within the doped silicon material 112 (e.g., gate, source, drain within a transistor). Silicon oxide (SiO) ₂ ) The insulator 114 may provide a potential barrier between different transistors and the like.

Conventionally, the semiconductor device 100 may be mounted on a silicon on insulator (SoI) carrier. The insulator material in the SoI carrier achieves the desired performance characteristics without further processing (e.g., back-side Chemical Mechanical Polishing (CMP)). By the time this document was written, soI materials were somewhat scarce, with only two major suppliers meeting global needs. In addition, soI materials are relatively expensive. Such a combination of factors makes it desirable to transfer to a different carrier.

One such alternative carrier is a bulk silicon substrate. However, to achieve the same performance, some backside processing typically must be performed on devices mounted on or formed from the bulk silicon substrate. When bulk silicon is treated to expose the backside, such as by a CMP process, silicon irregularities make uneven polishing not uncommon, as best seen in fig. 1B, where wafer 120 has residual silicon 122 covering portions of wafer 120, while already having exposed portions 124. Generally, the wafer 120 will undergo additional polishing until the residual silicon 122 is completely removed. As best seen in fig. 1C, this overpolishing may cause damage 130 (i.e., ovalization) to devices 132 on wafer 120.

Exemplary aspects of the present disclosure provide an improved polishing process that alternately polishes and flushes a wafer to interrupt chemical reactions, thereby slowing or preventing polishing of portions of the wafer having a relatively thin silicon cap. More specifically, chemical reactions are easier to initiate on thicker silicon, and thus, by controlling the time that the silicon slurry is present on the silicon during polishing, it is possible to control what thickness of silicon is polished, leaving thinner silicon portions that do not react with the slurry and are therefore not polished.

In this regard, fig. 2 is a flow chart of a process 200 according to an exemplary aspect of the present disclosure. Fig. 3A-3D illustrate various steps of process 200 and are referred to as an explanation of process 200.

Process 200 begins by forming a device or structure 300 in bulk silicon (block 202). The bulk silicon may have an initial thickness of 770 micrometers (μm), for example. Portions that may include doped silicon are formed to create insulators, gates, drains, sources, channels, etc. The structure 300 is then attached to a carrier wafer 302 (block 204, see fig. 3A). It should be noted that the active elements of structure 300 are adjacent to carrier wafer 302 and the opposite side can be considered the back side. That is, the structure 300 may include a back surface 304 formed from unused silicon material 306. The process 200 continues with grinding away a portion of the backside 304 (block 206). Such grinding may trim the unused silicon material 306 to about 5-10 μm (see fig. 3B). Notably, the polishing step of block 206 does not expose any active elements of structure 300.

Process 200 continues as follows: CMP is started (block 208) by first using a silicon slurry that is chemically reactive with the silicon material 306 (block 210) for a predetermined amount of time, and then cleaning or rinsing the back side 304 with Deionized (DI) water (block 212). As best seen in fig. 3E and 3F, CMP may be accomplished using a polishing head 330 rotating on a rotating polishing pad 332. The silicon slurry may be applied by opening the valve 334 to place the silicon slurry on the polishing pad 332 for a first amount of time 336 (i.e., block 210). At block 212, valve 334 is closed and valve 338 is opened such that DI water flushes the silicon slurry from polishing pad 332 for a second amount of time 340. Together times 336 and 340 form a single cycle 342. In an exemplary aspect, the valves 334, 338 may be pneumatic valves.

With continued reference to fig. 2, the control system (not shown) may determine whether a predetermined number of cycles have been completed (block 214). If the answer to block 214 is no, the process 200 returns to another slurry and flush cycle (i.e., returns to block 210, see FIG. 3C). However, if the answer to block 214 is yes, then process 200 ends with any additional processing (block 216, see FIG. 3D).

Exemplary aspects of the present disclosure control how much unused silicon material 306 is removed by controlling how long the silicon slurry reacts with the unused silicon material 306 before flushing with DI water. That is, as better seen in fig. 3G, curve 350 corresponds to a relatively thick unused silicon material 306A. Curve 350 reflects a shorter incubation period 352 due to the thickness of unused silicon material 306A. That is, the unused silicon material 306A begins to react relatively quickly with the silicon slurry and polishing by the polishing head 330 is able to remove some portion of the silicon. In contrast, the relatively thin unused silicon material 306B reacts more slowly with the silicon slurry and has a correspondingly longer incubation period 354 as shown by curve 356. By selecting a slurry time 358 corresponding to time 336 to be a certain time before a incubation period of a particular thickness occurs, the present disclosure may not cause a reaction and not polish a thickness less than the thickness corresponding to slurry time 358. That is, each curve on the graph corresponds to a particular thickness (and many curves are not shown), so selecting slurry time 358 at a particular point allows polishing all thicknesses having a curve with a incubation time less than the slurry time, and allows not reacting and therefore not polishing all thicknesses having a curve with a incubation time greater than the slurry time.

By selecting the appropriate slurry time 358, process 200 avoids polishing silicon oxide insulator 314 while polishing trench 316 (see fig. 3C, 3D). Graph 400 in fig. 4 may provide an alternative view of how incubation times work. When the silicon is thicker (i.e., the step height is little or no (curve 402)), the removal rate is higher (i.e., faster, see curve 404). As the number of cycles increases (x-axis), the step height increases, but the removal rate decreases. Empirically, the silicon slurry may react faster with thick silicon than with thin silicon, making thicker silicon easier to remove by the polishing head 330. The reaction of the silicon paste with the thin silicon takes a longer time, and since the second part 340 of the time removes the silicon paste by washing with DI water, there is not enough time for a large reaction to occur. The net effect of this is to stop removing the thin silicon on top of the silicon oxide insulator 314 when the thickness of the silicon is reduced beyond the incubation period. Conversely, thicker silicon in trench 316 is more easily removed as long as such silicon in trench 316 has a thickness that has a incubation period less than slurry time 358. Thus, damage to structure 300 is avoided. The exact thickness of silicon left after polishing is determined by the choice of slurry time 358.

Fig. 5A-5D show exemplary photographs of a test silicon wafer 500 after different numbers of cycles. Specifically, in fig. 5A, after five cycles, the silicon material 306 is still removed. After twenty cycles, some of the silicon has been completely removed, exposing the device 502, but leaving some silicon 504, as shown in fig. 5B. After thirty-five cycles, most of the silicon 504 disappeared as shown in fig. 5C. Finally, after three hundred forty-five cycles, as shown in FIG. 5D, any unwanted silicon 504 disappears, leaving a predetermined thickness corresponding to the thickness selected for the slurry time 358. Testing indicated that device 502 was not damaged.

Further testing has shown that by selecting the appropriate slurry reactants and properly adjusting the slurry flow, DI water flow, duty cycle, cycle time, and other process parameters, silicon can be removed by atomic layer-by-atomic layer precise control.

In this regard, fig. 6 is a system level block diagram of an exemplary mobile terminal 600, such as a smartphone, mobile computing device, tablet, or the like. Exemplary aspects of the present disclosure are well suited to constructing integrated circuits, such as RF switches or couplers operating in mobile terminal 600.

With continued reference to fig. 6, the mobile terminal 600 includes an application processor 604 (sometimes referred to as a host) that communicates with a mass storage element 606 over a universal flash memory (UFS) bus 608. The application processor 604 may further be connected to a display 610 through a Display Serial Interface (DSI) bus 612 and to a camera 614 through a Camera Serial Interface (CSI) bus 616. Various audio elements, such as a microphone 618, a speaker 620, and an audio codec 622, may be coupled to the application processor 604 through a serial low power inter-chip multimedia bus (SLIMbus) 624. In addition, the audio elements may communicate with each other over SOUNDWIRE bus 626. The modem 628 may also be coupled to the SLIMbus 624 and/or the SOUNDWIRE bus 626. The modem 628 may further be connected to the application processor 604 via a Peripheral Component Interconnect (PCI) or PCI express (PCIe) bus 630 and/or a System Power Management Interface (SPMI) bus 632.

With continued reference to fig. 6, the spmi bus 632 may also be coupled to a local area network (LAN or WLAN) IC (LAN or WLAN IC) 634, a Power Management Integrated Circuit (PMIC) 636, a companion IC (sometimes referred to as a bridge chip) 638, and a Radio Frequency IC (RFIC) 640. It should be appreciated that separate PCI buses 642 and 644 may also couple the application processor 604 to the companion IC 638 and the WLAN IC 634. The application processor 604 may further be connected to a sensor 646 via a sensor bus 648. The modem 628 and the RFIC 640 may communicate using the bus 650.

With continued reference to fig. 6, rfic 640 may be coupled to one or more Radio Frequency Front End (RFFE) elements, such as an antenna tuner 652, a switch 654, and a power amplifier 656, which may comprise an IC formed in accordance with exemplary aspects of the present disclosure, through an RFFE bus 658. In addition, the RFIC 640 may be coupled to an Envelope Tracking Power Supply (ETPS) 660 via a bus 662, and the ETPS 660 may be in communication with a power amplifier 656. In general terms, RFFE elements that comprise RFIC 640 may be considered RFFE system 664. It should be appreciated that RFFE bus 658 may be formed from clock and data lines (not shown).

It should also be noted that the operational steps described in any of the exemplary aspects herein are described for purposes of providing examples and discussion. The described operations may be performed in a number of different orders than that illustrated. Furthermore, operations described in a single operational step may actually be performed in many different steps. Additionally, one or more of the operational steps discussed in the exemplary aspects may be combined. It will be readily apparent to those skilled in the art that the operational steps illustrated in the flow diagrams may be subject to a number of different modifications. Those of skill in the art would also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (19)

1. A method for exposing a device for backside processing, the method comprising:

polishing the device with a silicon slurry and a polishing head; and

the apparatus is rinsed with deionized water to remove the silicon slurry.

2. The method of claim 1, further comprising repeating the polishing and rinsing over a plurality of cycles.

3. The method of claim 1, wherein polishing the device with the polishing head comprises rotating the polishing head.

4. The method of claim 1, further comprising first forming a structure of the device in bulk silicon.

5. The method of claim 4, wherein polishing the device removes a portion of the bulk silicon.

6. The method of claim 4, wherein forming the structure comprises forming a complementary metal oxide semiconductor.

7. The method of claim 4, wherein forming the structure comprises forming a radio frequency switch comprising a plurality of transistors.

8. The method of claim 4, further comprising adhering the structure to a carrier wafer.

9. The method of claim 3, wherein polishing the device comprises rotating a polishing pad.

10. The method of claim 1, further comprising opening a valve to apply the silicon slurry.

11. The method of claim 1, further comprising opening a valve to apply the deionized water.

12. The method of claim 2, further comprising selecting a residual thickness present after the plurality of cycles by setting a slurry time.

13. The method of claim 12, wherein setting the slurry time comprises opening a valve to release the silicon slurry during the slurry time.

14. The method of claim 13, further comprising closing the valve after the slurry time has ended.

15. The method of claim 1, further comprising timing the rinsing relative to polishing to remove a single atomic layer.

16. A method for exposing a device for backside processing, the method comprising:

the back side of a device having a thin device layer is polished by running a continuous cycle of reactive silicon slurry and deionized water.

17. The method of claim 16, wherein the thin device layer is a trench.

18. The method of claim 16, wherein polishing comprises removing an atomic layer of silicon by adjusting a time within the cycle of reactive silicon slurry and rinsing with deionized water.

19. A mobile terminal comprising an integrated circuit comprising the apparatus formed by the method of claim 1.