CN117743249A

CN117743249A - Multi-motherboard power-on control device and method for VPX complete machine

Info

Publication number: CN117743249A
Application number: CN202311770178.XA
Authority: CN
Inventors: 方维; 江广浪; 符运杰; 匡雯慧; 陈裘骏
Original assignee: Yanxiang Smart Iot Technology Co ltd
Current assignee: Yanxiang Smart Iot Technology Co ltd
Priority date: 2023-12-21
Filing date: 2023-12-21
Publication date: 2024-03-22

Abstract

The invention discloses a device and a method for controlling power-on of multiple mainboards of a VPX complete machine, wherein the device comprises an MCU chip, multiple VPX mainboards, multiple GPU cards and multiple VPX mainboard control switches; the VPX mainboards are connected with the MCU chip; the VPX main board control switches are connected with the MCU chip, the number of the VPX main board control switches is larger than or equal to that of the VPX main boards, and each VPX main board control switch is used for controlling the switch of at least one VPX main board. According to the invention, a corresponding VPX main board control switch is arranged for each VPX main board in the plurality of VPX main boards, and a master switch for unified switch control in the plurality of VPX main boards is also arranged, so that isolated independent switch control on power-on of each VPX main board and unified switch control on the plurality of VPX main boards can be realized through MCU monitoring.

Description

Multi-motherboard power-on control device and method for VPX complete machine

Technical Field

The invention relates to the technical field of VPX computers, in particular to a device and a method for powering up multiple mainboards of a VPX complete machine.

Background

VPX, also known as VITA46, is an ANSI standard (ANSI/VITA 46.0-2019) that provides support for VMEbus (a general purpose computer bus) based systems to support switching fabrics through new high speed connectors. The VPX type reinforcement computer can provide computing resources, network communication resources and data storage resources required by parallel operation of 12 items of special software of the simulator, ensure smooth operation of various software and communication of software and hardware equipment, timely response, high efficiency of data storage and sufficient margin.

However, when the current VPX type reinforcement computer adopts a plurality of VPX mainboards, unified power-on and power-off power-on control is adopted at present, so that accurate power-on control cannot be performed on the plurality of VPX mainboards respectively.

Disclosure of Invention

The invention aims to solve the defects in the prior art, and the embodiment of the invention provides a VPX complete machine multi-mainboard power-on control device and a VPX complete machine multi-mainboard power-on control method, which can set a corresponding VPX mainboard control switch for each VPX mainboard in a plurality of VPX mainboards, and also set a total switch for unified switch control in the plurality of VPX mainboards, so that isolated independent switch control on power-on of each VPX mainboard can be realized through MCU monitoring, and unified switch control on the plurality of VPX mainboards can be realized.

In a first aspect, an embodiment of the present invention provides a VPX complete machine multi-motherboard power-on control device, including: the device comprises an MCU chip, a plurality of VPX mainboards, a plurality of GPU cards and a plurality of VPX mainboard control switches; the VPX mainboards are connected with the MCU chip; the VPX main board control switches are connected with the MCU chip, the number of the VPX main board control switches is larger than or equal to that of the VPX main boards, and each VPX main board control switch is used for controlling the switch of at least one VPX main board.

In a second aspect, an embodiment of the present invention provides a VPX complete machine multi-motherboard power-on control device, which includes an MCU chip, a first VPX motherboard, a second VPX motherboard, a third VPX motherboard, a first GPU card, a second GPU card, a third GPU card, a first VPX motherboard control switch, a second VPX motherboard control switch, a third VPX motherboard control switch, and a fourth VPX motherboard control switch; the first GPU is arranged on the first VPX main board in a clamping mode, the second GPU is arranged on the second VPX main board in a clamping mode, and the third GPU is arranged on the third VPX main board in a clamping mode; the first VPX main board, the second VPX main board and the third VPX main board are all connected with the MCU chip; the first VPX main board control switch, the second VPX main board control switch, the third VPX main board control switch and the fourth VPX main board control switch are all connected with the MCU chip; the first VPX main board control switch is used for controlling the switch of the first VPX main board, the second VPX main board control switch is used for controlling the switch of the second VPX main board, the third VPX main board control switch is used for controlling the switch of the third VPX main board, and the fourth VPX main board control switch is used for being used as a main switch of the first VPX main board, the second VPX main board and the third VPX main board.

In a third aspect, an embodiment of the present invention further provides a method for controlling power-on of multiple main boards of a VPX complete machine, which is applied to the device for controlling power-on of multiple main boards of a VPX complete machine according to the second aspect, and includes:

the MCU chip detects any one or more pressing signals of a first VPX main board control switch, a second VPX main board control switch, a third VPX main board control switch and a fourth VPX main board control switch, and then respectively detects and acquires a first target pin state corresponding to the first VPX main board, a second target pin state corresponding to the second VPX main board and a third target pin state corresponding to the third VPX main board; the switching-on/off control signal priority corresponding to the fourth VPX main board control switch, the switching-on/off control signal priority corresponding to the first VPX main board control switch, the switching-on/off control signal priority corresponding to the second VPX main board control switch and the switching-on/off control signal priority corresponding to the third VPX main board control switch are arranged in sequence from high to low;

when the MCU chip determines that the pressing time corresponding to each pressing signal in any one or any plurality of pressing signals does not exceed a preset pressing time threshold, determining common on-off control signals corresponding to the first VPX main board, the second VPX main board and the third VPX main board respectively according to the first target pin state, the second target pin state and the third target pin state so as to form a current common on-off control signal set;

And correspondingly controlling the on/off states of the first VPX main board, the second VPX main board and the third VPX main board according to the current common on/off control signal set.

The embodiment of the invention provides a device and a method for controlling power-on of multiple mainboards of a VPX complete machine, wherein the device comprises an MCU chip, multiple VPX mainboards, multiple GPU cards and multiple VPX mainboard control switches; the VPX mainboards are connected with the MCU chip; the VPX main board control switches are connected with the MCU chip, the number of the VPX main board control switches is larger than or equal to that of the VPX main boards, and each VPX main board control switch is used for controlling the switch of at least one VPX main board. According to the invention, a corresponding VPX main board control switch is arranged for each VPX main board in the plurality of VPX main boards, and a master switch for unified switch control in the plurality of VPX main boards is also arranged, so that isolated independent switch control on power-on of each VPX main board and unified switch control on the plurality of VPX main boards can be realized through MCU monitoring.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic block diagram of a VPX complete machine multi-motherboard power-on control device according to an embodiment of the present invention;

FIG. 2 is a schematic block diagram of a power-on control device for multiple mainboards of a VPX complete machine according to another embodiment of the present invention;

fig. 3 is a schematic flow chart of a method for controlling power-on of multiple mainboards of a VPX whole machine according to an embodiment of the invention;

fig. 4 is another flow chart of a VPX complete machine multi-motherboard power-on control method according to an embodiment of the present invention;

fig. 5 is a schematic sub-flowchart of a VPX complete machine multi-motherboard power-on control method according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

Referring to fig. 1, fig. 1 is a schematic block diagram of a VPX whole machine multi-motherboard power-on control device according to an embodiment of the invention. As shown in fig. 1, the VPX complete machine multi-motherboard power-on control device provided by the embodiment of the invention includes: the MCU chip 10, a plurality of VPX mainboards 20, a plurality of GPU cards 30 and a plurality of VPX mainboard control switches 40; the plurality of VPX mainboards 20 are connected with the MCU chip 10; the plurality of VPX motherboard control switches 40 are all connected with the MCU chip 10, and the number of the plurality of VPX motherboard control switches 40 is greater than or equal to the number of the plurality of VPX motherboards 20, and each VPX motherboard control switch is used for controlling the switch of at least one VPX motherboard.

In this embodiment, in order to realize accurate power-on control of a VPX complete machine including a plurality of VPX mainboards, one MCU chip 10 needs to be provided as a control center to accurately control on or off of each of the plurality of VPX mainboards 20 connected to the MCU chip 10. For example, the number of the plurality of VPX main board control switches 40 may be set to be equal to the number of the plurality of VPX main boards 20, more specifically, the number of the plurality of VPX main board control switches 40 is 3 and the number of the plurality of VPX main boards 20 is 3, so that each VPX main board control switch may be correspondingly controlled to be a unique corresponding VPX main board after the specific setting.

Of course, in implementation, the number of the plurality of VPX main board control switches 40 may be greater than the number of the plurality of VPX main boards 20, more specifically, the number of the plurality of VPX main board control switches 40 is 4 and the number of the plurality of VPX main boards 20 is 3, so that after the implementation, 3 VPX main board control switches may be selected to make each VPX main board control switch correspondingly control a VPX main board which corresponds only, and the remaining 1 VPX main board control switches may be used as a total switch common to the plurality of VPX main boards 20. Therefore, after the corresponding VPX main board control switch is arranged for each VPX main board in the plurality of VPX main boards, the isolated control of the electrification of each VPX main board can be realized.

In an embodiment, as shown in fig. 1, the VPX complete machine multi-motherboard power-on control device further includes an ATX power supply 50 and a VPX power supply 60, where the ATX power supply 50 and the VPX power supply 60 are connected to the MCU chip 10.

In this embodiment, the power-on control device for multiple main boards of the VPX complete machine is further provided with an ATX power supply 50 (ATX is generally called Advanced Technology Extended, and represents a main board specification) and a VPX power supply 60, so that any one of the two power supply supplies power to the MCU chip 10 and the multiple VPX main boards 20, thereby realizing the diversity of power supply selection.

In order to monitor the working states of the VPX power supply 60 and the ATX power supply 50, a power supply monitoring module 80 may be further provided to be connected to the VPX power supply 60 and the ATX power supply 50, and the power supply monitoring module 80 is further connected to the MCU chip 10. When the MCU chip 10 sends PS_ON# signal to the ATX power supply 50, if the voltage of the ATX power supply 50 is normal, it sends ATX_PWROK signal to the power monitoring module 80. Also, when the power monitoring module 80 monitors that the power voltage in the VPX power supply 60 is normal, the VPX power supply 60 transmits a vpx_pwrok signal to the power monitoring module 80.

Then, the POWER monitor module 80 performs an or logic operation on the atx_pwrok signal and the vpx_pwrok signal in an or gate to obtain a PWROK signal (specifically, one of the atx_pwrok signal and the vpx_pwrok signal corresponds to a normal POWER supply, and the PWROK signal corresponds to a POWER OK signal) and sends the PWROK signal to the MCU chip 10 through the POWER monitor module 80. When the MCU chip 10 receives the PWROK signal, it indicates that the voltage of the back panel is normal, and the VPX motherboard can be further controlled to be powered on. Therefore, through the above arrangement, the VPX whole machine multi-motherboard is electrified to be powered by any one of the VPX power supply 60 and the ATX power supply 50 to the MCU chip 10 and the multiple VPX motherboards 20, thereby realizing the diversity of power supply selection.

The power monitoring module and the VPX main boards 20 are provided with IPMI interfaces (IPMI is IntelligentPlatform Management Interface, which is a standard interface for managing hardware devices in servers and other computer systems, and can be implemented through a network port or a serial port). The MCU chip 10 is connected to the power monitoring module and the IPMI interfaces on the VPX main boards 20 through an IPMB bus (the generic name of IPMB is IntelligentPlatform Management Bus, an intelligent platform management bus). The MCU chip 10 may be used as a CHMC device (i.e. a master control device for manager identity), and the power supply monitoring module, the VPX mainboards 20, and the like may be used as slave devices of the MCU chip 10. Since the MCU chip 10 is used as the main control device, the VPX motherboard can be used continuously even if it is replaced.

Therefore, the device is provided with the corresponding VPX main board control switch for each VPX main board in the plurality of VPX main boards, and can realize isolated independent switch control on power on each VPX main board.

The embodiment of the invention also provides another VPX whole machine multi-motherboard power-up control device, which is a preferred embodiment of the VPX whole machine multi-motherboard power-up control device, and specifically, please refer to fig. 2, fig. 2 is a schematic block diagram of the VPX whole machine multi-motherboard power-up control device provided by another embodiment of the invention. As shown in fig. 2, the VPX complete machine multi-motherboard power-on control device provided by the embodiment of the invention includes: the MCU chip 10, the first VPX main board 21, the second VPX main board 22, the third VPX main board 23, the first GPU card 31, the second GPU card 32, the third GPU card 33, the first VPX main board control switch SW1, the second VPX main board control switch SW2, the third VPX main board control switch SW3 and the fourth VPX main board control switch SW4_main; the first GPU card 31 is disposed on the first VPX motherboard 21, the second GPU card 32 is disposed on the second VPX motherboard 22, and the third GPU card 33 is disposed on the third VPX motherboard 23; the first VPX main board 21, the second VPX main board 22 and the third VPX main board 23 are all connected with the MCU chip 10; the first VPX main board control switch SW1, the second VPX main board control switch SW2, the third VPX main board control switch SW3 and the fourth VPX main board control switch SW4 main are all connected with the MCU chip 10; the first VPX main board control switch SW1 is used for controlling the switch of the first VPX main board 21, the second VPX main board control switch SW2 is used for controlling the switch of the second VPX main board 22, the third VPX main board control switch SW3 is used for controlling the switch of the third VPX main board 23, and the fourth VPX main board control switch sw4_main is used as the total switch of the first VPX main board 21, the second VPX main board 22 and the third VPX main board 23.

In this embodiment, the VPX whole machine multi-motherboard power-on control device is a preferred embodiment of the foregoing VPX whole machine multi-motherboard power-on control device, specifically, the total number of VPX motherboards is defined to be 3, and the total number of VPX motherboard control switches is defined to be 4.

The MCU chip 10 specifically adopts a microcontroller of CH588L type, and PIN of the core is as follows in table 1:

TABLE 1

After the MCU chip having the core PIN (PIN can also be understood as PIN) shown in table 1 is used, the power-on control process of the 3 VPX main boards is described below with reference to a specific example.

Since the 3 VPX main boards are turned on simultaneously, which results in the problems of large instantaneous impact current of the power supply and the like, the power supply cannot be turned on stably, and the different conditions that the 4 VPX main board control switches are pressed down are respectively described.

A1 When only one of the first VPX main board control switch SW1, the second VPX main board control switch SW2, the third VPX main board control switch SW3 and the fourth VPX main board control switch sw4_main is pressed, if it is determined that the fourth VPX main board control switch sw4_main is pressed, the first VPX main board 21, the second VPX main board 22 and the third VPX main board 23 are sequentially controlled to be powered on; if one of the first VPX main board control switch SW1, the second VPX main board control switch SW2 and the third VPX main board control switch SW3 is determined to be pressed, controlling the VPX main board corresponding to the pressed VPX main board control switch to be electrified;

A2 When two or more VPX main board control switches among the first VPX main board control switch SW1, the second VPX main board control switch SW2, the third VPX main board control switch SW3 and the fourth VPX main board control switch sw4_main are pressed, the switch priority order is sequentially responded to sw4_main > SW1 > SW2 > SW3, that is, the pressing signal of the fourth VPX main board control switch sw4_main is processed first, the pressing signal of the first VPX main board control switch SW1 is processed second, the pressing signal of the second VPX main board control switch SW2 is processed third, and the pressing signal of the third VPX main board control switch SW3 is processed fourth.

More specifically, the VPX complete machine multi-motherboard power-on control device is initially in the S3 state (S3 state is a sleep state), and in the S3 state, only the standby voltage is provided for the MCU chip 10 to work, so as to detect whether the first VPX motherboard 21, the second VPX motherboard 22 and the third VPX motherboard 23 are in place.

When the VPX complete machine multi-motherboard power-up control device is initially in the S3 state, if any one of the first VPX motherboard control switch SW1, the second VPX motherboard control switch SW2, and the third VPX motherboard control switch SW3 is detected to be pressed, for example, the power-up process is described by taking the case that the first VPX motherboard control switch SW1 is detected to be pressed: the MCU chip 10 detects the level state of the slot1_s3# pin (slot1_s3# pin may be equivalently referred to as the P2.1 pin in table 1), if it is initially determined that the slot1_s3# pin is at a high level, it indicates that the first VPX motherboard 21 is in a turned-on state, at this time, the P2.4 pin of the MCU chip 10 sends a slot1_pwr_ btn # signal to the first VPX motherboard 21 until it is detected that the level of the slot1_s3# pin becomes a low level, which indicates that the first VPX motherboard 21 is turned off successfully; if the slot1_s3# pin is initially determined to be low, it indicates that the first VPX motherboard 21 is in a power-off state, at this time, the level state of the P3.6 pin (which is connected to the inhibit# pin of the VPX power supply) of the MCU chip 10 is obtained first, and if the P3.6 pin is determined to be high (at this time, the inhibit# pin is also high), it indicates that the power supply module supplying power to the MCU chip 10 is in a state that all voltages are output, and then the MCU chip 10 sends a pwr_btn1# signal to the first VPX motherboard 21 to enable the first VPX motherboard 21 to be powered on.

In the process of initially determining that the slot1_s3# pin is at the high level, the MCU chip 10 sends a slot1_pwr_ btn # signal to the P2.4 pin of the first VPX motherboard 21 until the detection that the level of the slot1_s3# pin becomes the low level indicates that the first VPX motherboard 21 is powered off successfully, or it may happen that the MCU chip 10 continuously sends the slot1_pwr_ btn # signal three times to the first VPX motherboard 21 and then the level of the slot1_s3# pin does not become the low level, which indicates that the first VPX motherboard 21 is not powered off successfully, and at this time, the MCU chip 10 is required to report an external error (for example, send error report information to a management port connected to the MCU chip 10).

When the VPX complete machine multi-motherboard power-on control device is initially in the S3 state, if the fourth VPX motherboard control switch sw4_main is detected to be pressed, the MCU chip 10 detects the level states of three pins, namely, a slot1_s3# pin, a slot2_s3# pin and a slot3_s3# pin, if any one of the slot1_s3# pin, the slot2_s3# pin and the slot3_s3# pin is initially determined to be in the high level, the VPX motherboard corresponding to the corresponding pin is indicated to be in the on state, and if the first VPX motherboard is determined to be in the on state, the MCU chip 10 sends a pwr_btn1# signal to the first VPX motherboard to turn off the first VPX motherboard; if the second VPX motherboard is determined to be in the on state, the MCU chip 10 sends a pwr_btn2# signal to the second VPX motherboard to turn it off; if the third VPX motherboard is determined to be in the on state, the MCU chip 10 sends a pwr_btn3# signal to the third VPX motherboard to turn it off. If it is initially determined that all of the slot1_s3# pin, the slot2_s3# pin and the slot3_s3# pin are low, it indicates that all of the three VPX mainboards are in a shutdown state, at this time, the MCU chip 10 sends a pwr_btn1# signal to the first VPX mainboard to power on the first VPX mainboard, then sends a pwr_btn2# signal to the second VPX mainboard to power on the second VPX mainboard, and finally sends a pwr_btn3# signal to the third VPX mainboard to power on the third VPX mainboard.

In the two cases listed above (i.e., in the case where the VPX whole multi-board power-on control device is initially in the S3 state, if any one of the first VPX main board control switch SW1, the second VPX main board control switch SW2, and the third VPX main board control switch SW3 is detected to be pressed, and in the case where the VPX whole multi-board power-on control device is initially in the S3 state, if the fourth VPX main board control switch sw4_main is detected to be pressed, a short press condition in which the duration of the pressing of the first VPX main board control switch, the second VPX main board control switch, the third VPX main board control switch, and the fourth VPX main board control switch is not more than 5 seconds is considered. And when the duration of the pressed VPX main board control switch in the first VPX main board control switch, the second VPX main board control switch and the third VPX main board control switch exceeds 5 seconds, the VPX main board corresponding to the VPX main board control switch is forced to be turned off. And when the duration of the fourth VPX main board control switch being pressed exceeds 5 seconds, the first VPX main board, the second VPX main board and the third VPX main board are all forced to be powered off.

In an embodiment, as shown in fig. 2, the VPX complete machine multi-motherboard power-on control device further includes an ATX power supply 50 and a VPX power supply 60, where the ATX power supply 50 and the VPX power supply 60 are connected to the MCU chip 10.

In an embodiment, as shown in fig. 2, the VPX complete machine multi-motherboard power-on control device further includes a management port 70, the management port 70 is connected with the MCU chip 10 through a UART serial port or a LAN network port, and the management port 70 is configured to receive a user operation instruction and send the user operation instruction to the MCU chip 10.

In this embodiment, the control device is further provided with a management port 70 on the multi-motherboard of the VPX whole machine, and the management port 70 is connected with the MCU chip 10 through a UART serial port or a LAN network port. The management port 70 may provide a system management interface to the user, such as connecting the management port 70 to a user terminal. The UART serial port may be used for local management of the MCU chip 10, and the LAN port may be used for remote platform management of the MCU chip 10.

The user may operate the user terminal connection management port 70 (specifically, a CONSOLE management port, which is also referred to as a CONSOLE interface, is an interface type of network device), and then send some simple query or operation instructions, such as SEL query and clear, query of SDR and FRU information, query of sensor list and status, setting of RTC clock, FRU Control operation, etc., to the MCU chip 10; wherein SEL is the abbreviation for Select instruction; SDR is known in full as Sensor Data Record, representing a sensor data record; FRU, collectively Field Replaceable Unit, represents a field replaceable component; the RTC is collectively referred to as real_Time Clock, representing the Real Time Clock.

In one embodiment, as shown in fig. 2, the VPX complete machine multi-motherboard power-on control device further includes a power supply monitoring module 80, the power supply monitoring module 80 is connected with the VPX power supply 60 and the ATX power supply 50, and the power supply monitoring module 80 is further connected with the MCU chip; the power supply monitoring module 80 is configured to obtain a power supply voltage of the VPX power supply and a power supply voltage of the ATX power supply.

In this embodiment, the power-on control device for multiple main boards of the VPX complete machine is further provided with an ATX power supply 50 (ATX is generally called Advanced Technology Extended, and represents a main board specification) and a VPX power supply 60, so that any one of the two power supply supplies power to the MCU chip 10 and the multiple VPX main boards 20, thereby realizing the diversity of power supply selection. The dual power redundancy system supplies power.

Therefore, the device is provided with the corresponding VPX main board control switch for each of the three VPX main boards, and is also provided with a main switch for unified switch control in the three VPX main boards, so that isolated independent switch control on power-on of each VPX main board can be realized, and unified switch control on the three VPX main boards can also be realized.

The embodiment of the invention also provides a VPX whole machine multi-motherboard power-on control method, which is applied to any embodiment corresponding to the VPX whole machine multi-motherboard power-on control device comprising three VPX motherboards, specifically referring to fig. 3, fig. 3 is a schematic flow chart of the VPX whole machine multi-motherboard power-on control method provided by an embodiment of the invention, and the VPX whole machine multi-motherboard power-on control method provided by the embodiment of the invention comprises steps S110-S130.

And S110, detecting and acquiring a first target pin state corresponding to the first VPX main board, a second target pin state corresponding to the second VPX main board and a third target pin state corresponding to the third VPX main board by the MCU chip when detecting any one or more pressing signals of the first VPX main board control switch, the second VPX main board control switch, the third VPX main board control switch and the fourth VPX main board control switch.

The switching-on/off control signal priority corresponding to the fourth VPX main board control switch, the switching-on/off control signal priority corresponding to the first VPX main board control switch, the switching-on/off control signal priority corresponding to the second VPX main board control switch and the switching-on/off control signal priority corresponding to the third VPX main board control switch are arranged in order from large to small.

In this embodiment, please continue to refer to the VPX complete machine multi-motherboard power-on control device shown in fig. 2, since 3 VPX motherboards are turned on simultaneously to cause problems of large power supply impact current and the like, and cannot be turned on stably, different situations of the 4 VPX motherboard control switches being pressed will be described respectively.

B1 When only one of the first VPX main board control switch SW1, the second VPX main board control switch SW2, the third VPX main board control switch SW3 and the fourth VPX main board control switch sw4_main is pressed to generate a pressing signal, if the fourth VPX main board control switch sw4_main is determined to be pressed and the pressing time corresponding to the pressing signal does not exceed the preset pressing time threshold value, the first VPX main board 21, the second VPX main board 22 and the third VPX main board 23 are sequentially controlled to be electrified; if it is determined that one of the first VPX main board control switch SW1, the second VPX main board control switch SW2 and the third VPX main board control switch SW3 is pressed, and the pressing time corresponding to the pressing signal does not exceed the preset pressing time threshold, controlling the VPX main board corresponding to the pressed VPX main board control switch to be powered on;

B2 When two or more VPX main board control switches among the first VPX main board control switch SW1, the second VPX main board control switch SW2, the third VPX main board control switch SW3 and the fourth VPX main board control switch sw4_main are pressed, the switch priority order is sequentially responded to sw4_main > SW1 > SW2 > SW3, that is, the pressing signal of the fourth VPX main board control switch sw4_main is processed first, the pressing signal of the first VPX main board control switch SW1 is processed second, the pressing signal of the second VPX main board control switch SW2 is processed third, and the pressing signal of the third VPX main board control switch SW3 is processed fourth.

In this application, when the first VPX main board control switch SW1, the second VPX main board control switch SW2, the third VPX main board control switch SW3, and the fourth VPX main board control switch sw4_main are all pressed, the operation is regarded as an operation of effectively pressing the switch once only when at least more than 25ms is pressed and a pulse of 25ms or more is generated. If there is a pulse that does not exceed 25ms and does not generate at least 25ms when pressing is performed on the first VPX main board control switch SW1, the second VPX main board control switch SW2, the third VPX main board control switch SW3, and the fourth VPX main board control switch sw4_main, it is regarded as an invalid switch pressing operation.

In one embodiment, as shown in fig. 5, step S110 includes:

s111, the MCU chip acquires the high-low level state of the P2.1 pin to determine a first target pin state;

s112, the MCU chip acquires the high-low level state of the P2.2 pin to determine a second target pin state;

s113, the MCU chip acquires the high-low level state of the P2.3 pin to determine a third target pin state.

In this embodiment, the P2.1 pin of the MCU chip is specifically used to detect the state of the first target pin corresponding to the first VPX motherboard, if the P2.1 pin is at a high level, the state of the first target pin is at a high level, and if the P2.1 pin is at a low level, the state of the first target pin is at a low level. The state of the second VPX motherboard corresponding to the second target pin is detected through the P2.2 pin of the MCU chip, if the P2.2 pin is high, the state of the second target pin is high, and if the P2.2 pin is low, the state of the second target pin is low. And detecting the state of the third VPX main board corresponding to the third target pin through the P2.3 pin of the MCU chip, wherein if the P2.3 pin is high, the state of the third target pin is high, and if the P2.3 pin is low, the state of the third target pin is low.

Any one of the first target pin state, the second target pin state and the third target pin state is a high level, the VPX host corresponding to the target pin state is a power-on state, and at this time, the power-off control signal is corresponding to the pressing signal of any one or more of the first VPX main board control switch, the second VPX main board control switch, the third VPX main board control switch and the fourth VPX main board control switch in step S110.

All the target pin states in the first target pin state, the second target pin state and the third target pin state are low levels, which indicates that the first VPX main board 21, the second VPX main board 22 and the third VPX main board 23 are all in the off state, and at this time, in step S110, the start-up control signal is corresponding to the pressing signal of any one or more of the first VPX main board control switch, the second VPX main board control switch, the third VPX main board control switch and the fourth VPX main board control switch.

And S120, when the MCU chip determines that the pressing time corresponding to each pressing signal in any one or any plurality of pressing signals does not exceed a preset pressing time threshold, determining common on-off control signals corresponding to the first VPX main board, the second VPX main board and the third VPX main board respectively according to the first target pin state, the second target pin state and the third target pin state so as to form a current common on-off control signal set.

In this embodiment, still referring to the above example, when the VPX complete machine multi-motherboard power-on control device is initially in the S3 state (S3 state, i.e. sleep state), only the standby voltage is used for the MCU chip 10 to work in the S3 state to detect whether the first VPX motherboard 21 is in place through the P0.4 pin of the MCU chip 10, whether the second VPX motherboard 22 is in place through the P0.5 pin of the MCU chip 10, and whether the third VPX motherboard 23 is in place through the P0.6 pin of the MCU chip 10, respectively. And on the premise that the first VPX main board, the second VPX main board and the third VPX main board are in place, determining common on-off control signals corresponding to the first VPX main board, the second VPX main board and the third VPX main board respectively based on the first target pin state, the second target pin state and the third target pin state. The preset pressing time threshold is set to 5S in the implementation, and is not limited to 5S, but may be other time periods set by the user in a user-defined manner.

In an embodiment, if the MCU chip determines that the first target pin state, the second target pin state, and the third target pin state are all low-level states, the MCU chip obtains a target VPX motherboard control switch that generates a pressing signal from the first VPX motherboard control switch, the second VPX motherboard control switch, the third VPX motherboard control switch, and the fourth VPX motherboard control switch, and obtains a target VPX motherboard corresponding to the target VPX motherboard control switch;

If the MCU chip determines that the target VPX main board is a first VPX main board, generating a first common starting control signal aiming at the first VPX main board;

if the MCU chip determines that the target VPX main board is a second VPX main board, generating a second common starting control signal aiming at the second VPX main board;

if the MCU chip determines that the target VPX main board is a third VPX main board, generating a third common starting control signal aiming at the third VPX main board;

if the MCU chip determines that the target VPX main board comprises a first VPX main board, a second VPX main board and a third VPX main board, generating a first common starting control signal for the first VPX main board, generating a second common starting control signal for the second VPX main board and generating a third common starting control signal for the third VPX main board.

In this embodiment, after the MCU chip obtains the high-low level conditions corresponding to the first target pin state, the second target pin state and the third target pin state, the three conditions may be determined by combining the three conditions, so that the MCU chip can more accurately determine whether to generate the power-on control signal or the power-off control signal. .

Specifically, when the VPX complete machine multi-motherboard power-on control device is initially in the S3 state, if any one of the first VPX motherboard control switch SW1, the second VPX motherboard control switch SW2, and the third VPX motherboard control switch SW3 is detected through the P3.1 pin, the P3.2 pin, and the P3.3 pin of the MCU chip 10 to be pressed to generate pressing information, and the pressing time corresponding to the pressing signal does not exceed the preset pressing time threshold, for example, the power-on process is described by taking the example that the first VPX motherboard control switch SW1 is detected to be pressed to not exceed 5S: the MCU chip 10 detects the level state of the slot1_s3# pin (slot1_s3# pin may be equivalently referred to as the P2.1 pin in table 1), if it is initially determined that the slot1_s3# pin is at a high level, it indicates that the first VPX motherboard 21 is in a turned-on state, at this time, the P2.4 pin of the MCU chip 10 sends a slot1_pwr_ btn # signal to the first VPX motherboard 21 until it is detected that the level of the slot1_s3# pin becomes a low level, which indicates that the first VPX motherboard 21 is turned off successfully; if the slot1_s3# pin is initially determined to be low, it indicates that the first VPX motherboard 21 is in a power-off state, at this time, the level state of the P3.6 pin (which is connected to the inhibit# pin of the VPX power supply) of the MCU chip 10 is obtained first, and if the P3.6 pin is determined to be high (at this time, the inhibit# pin is also high), it indicates that the power supply module supplying power to the MCU chip 10 is in a state that all voltages are output, and then the MCU chip 10 sends a pwr_btn1# signal to the first VPX motherboard 21 to enable the first VPX motherboard 21 to be powered on.

When the VPX complete machine multi-motherboard power-on control device is initially in the S3 state, if it is detected through the P3.4 pin of the MCU chip 10 that the fourth VPX motherboard control switch sw4_main is pressed to generate a pressing signal, and when the pressing time corresponding to the pressing signal does not exceed a preset pressing time threshold, the MCU chip 10 detects the level states of three pins, namely, the slot1_s3# pin, the slot2_s3# pin and the slot3_s3# pin, and if it is initially determined that any one pin of the slot1_s3# pin, the slot2_s3# pin and the slot3_s3# pin is at a high level, the VPX motherboard corresponding to the corresponding pin is in a power-on state, and if it is determined that the first VPX motherboard is in the power-on state, the MCU chip 10 sends a pwr_btn1# signal to the first VPX motherboard to power off the first VPX motherboard; if the second VPX motherboard is determined to be in the on state, the MCU chip 10 sends a pwr_btn2# signal to the second VPX motherboard to turn it off; if the third VPX motherboard is determined to be in the on state, the MCU chip 10 sends a pwr_btn3# signal to the third VPX motherboard to turn it off. If it is initially determined that all of the slot1_s3# pin, the slot2_s3# pin and the slot3_s3# pin are low, it indicates that all of the three VPX mainboards are in a shutdown state, at this time, the MCU chip 10 sends a pwr_btn1# signal to the first VPX mainboard to power on the first VPX mainboard, then sends a pwr_btn2# signal to the second VPX mainboard to power on the second VPX mainboard, and finally sends a pwr_btn3# signal to the third VPX mainboard to power on the third VPX mainboard.

S130, correspondingly controlling the on/off states of the first VPX main board, the second VPX main board and the third VPX main board according to the current common on/off control signal set.

In this embodiment, in the two cases (that is, in the case where the VPX whole-machine multi-motherboard power-up control device is initially in the S3 state, if any one of the first VPX motherboard control switch SW1, the second VPX motherboard control switch SW2, and the third VPX motherboard control switch SW3 is detected to be pressed, and in the case where the VPX whole-machine multi-motherboard power-up control device is initially in the S3 state, if the fourth VPX motherboard control switch sw4_main is detected to be pressed, a short press condition in which the duration of the pressing of the first VPX motherboard control switch, the second VPX motherboard control switch, the third VPX motherboard control switch, and the fourth VPX motherboard control switch is not more than 5 seconds is considered. Under the condition that the switch is pressed short, after the current common on-off control signal set is obtained, accurate on-off control of each VPX mainboard is realized through the mode.

In an embodiment, as shown in fig. 4, as another embodiment of the VPX whole machine multi-motherboard power-on control method, step S110 further includes:

And S140, when the MCU chip determines that the pressing time corresponding to the pressing signal in any one or any plurality of pressing signals exceeds the preset pressing time threshold, acquiring the corresponding pressing signal as a target pressing signal, and acquiring a target pin state corresponding to the target pressing signal and a target VPX main board so as to determine a forced on-off control signal for the target VPX main board.

S150, the on-off of the target VPX mainboard is correspondingly controlled according to the forced on-off control signal.

The target VPX mainboard comprises one or more of a first VPX mainboard, a second VPX mainboard and a third VPX mainboard;

in this embodiment, when the duration of pressing the VPX main board control switch in the first VPX main board control switch, the second VPX main board control switch, and the third VPX main board control switch exceeds 5 seconds, the VPX main board corresponding to the VPX main board control switch is forced to be turned off. And when the duration of the fourth VPX main board control switch being pressed exceeds 5 seconds, the first VPX main board, the second VPX main board and the third VPX main board are all forced to be powered off. Under the condition that the switch is pressed for a long time, the accurate on-off control of each VPX mainboard is realized through the mode.

According to the VPX complete machine multi-mainboard power-on control method provided by the embodiment of the invention, corresponding VPX mainboard control switches are arranged for each of three VPX mainboards, and a master switch for unified switch control in the three VPX mainboards is also arranged, so that isolated independent switch control on power-on of each VPX mainboard can be realized through MCU monitoring, and unified switch control on the three VPX mainboards can be realized.

The present invention is not limited to the above embodiments, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the present invention, and these modifications and substitutions are intended to be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

1. A VPX complete machine multi-motherboard power-on control device is characterized by comprising: the device comprises an MCU chip, a plurality of VPX mainboards, a plurality of GPU cards and a plurality of VPX mainboard control switches; the VPX mainboards are connected with the MCU chip; the VPX main board control switches are connected with the MCU chip, the number of the VPX main board control switches is larger than or equal to that of the VPX main boards, and each VPX main board control switch is used for controlling the switch of at least one VPX main board.

2. The VPX complete machine multi-motherboard power-on control device according to claim 1, further comprising an ATX power supply and a VPX power supply, wherein the ATX power supply and the VPX power supply are connected with the MCU chip.

3. A VPX complete machine multi-motherboard power-on control device is characterized by comprising: the MCU chip, the first VPX main board, the second VPX main board, the third VPX main board, the first GPU card, the second GPU card, the third GPU card, the first VPX main board control switch, the second VPX main board control switch, the third VPX main board control switch and the fourth VPX main board control switch; the first GPU is arranged on the first VPX main board in a clamping mode, the second GPU is arranged on the second VPX main board in a clamping mode, and the third GPU is arranged on the third VPX main board in a clamping mode; the first VPX main board, the second VPX main board and the third VPX main board are all connected with the MCU chip; the first VPX main board control switch, the second VPX main board control switch, the third VPX main board control switch and the fourth VPX main board control switch are all connected with the MCU chip; the first VPX main board control switch is used for controlling the switch of the first VPX main board, the second VPX main board control switch is used for controlling the switch of the second VPX main board, the third VPX main board control switch is used for controlling the switch of the third VPX main board, and the fourth VPX main board control switch is used for being used as a main switch of the first VPX main board, the second VPX main board and the third VPX main board.

4. The VPX complete machine multi-motherboard power-on control device according to claim 3, further comprising an ATX power supply and a VPX power supply, wherein the ATX power supply and the VPX power supply are connected with the MCU chip.

5. The VPX complete machine multi-motherboard power-on control device according to claim 3, further comprising a management port, wherein the management port is connected with the MCU chip through a UART serial port or a LAN network port, and the management port is configured to receive a user operation instruction and send the user operation instruction to the MCU chip.

6. The VPX complete machine multi-motherboard power-on control device according to claim 4, further comprising a power supply monitoring module, wherein the power supply monitoring module is connected with the VPX power supply and the ATX power supply, and the power supply monitoring module is further connected with the MCU chip; the power supply monitoring module is used for acquiring the power supply voltage of the VPX power supply and the power supply voltage of the ATX power supply.

7. A VPX complete machine multi-motherboard power-on control method, which is applied to the VPX complete machine multi-motherboard power-on control device as claimed in any one of claims 3-6, the method comprising:

8. The method of claim 7, wherein after the MCU chip detects a pressing signal of any one or more of the first VPX main board control switch, the second VPX main board control switch, the third VPX main board control switch, and the fourth VPX main board control switch, the method further comprises, after detecting the step of acquiring a first target pin state corresponding to the first VPX main board, a second target pin state corresponding to the second VPX main board, and a third target pin state corresponding to the third VPX main board, respectively:

The MCU chip obtains a corresponding pressing signal as a target pressing signal when determining that the pressing time corresponding to the pressing signal in any one or any plurality of pressing signals exceeds the preset pressing time threshold, and obtains a target pin state and a target VPX main board corresponding to the target pressing signal so as to determine a forced on-off control signal for the target VPX main board; wherein the target VPX motherboard comprises one or more of the first VPX motherboard, the second VPX motherboard, and the third VPX motherboard;

and correspondingly controlling the on-off of the target VPX mainboard according to the forced on-off control signal.

9. The method of claim 7, wherein detecting the first target pin state corresponding to the first VPX motherboard, the second target pin state corresponding to the second VPX motherboard, and the third target pin state corresponding to the third VPX motherboard, respectively, comprises:

the MCU chip obtains the high-low level state of the P2.1 pin to determine the state of the first target pin;

the MCU chip obtains the high-low level state of the P2.2 pin to determine the second target pin state;

the MCU chip obtains the high-low level state of the P2.3 pin to determine the third target pin state.

10. The method of claim 7, wherein determining the normal power on/off control signals respectively corresponding to the first VPX motherboard, the second VPX motherboard, and the third VPX motherboard according to the first target pin state, the second target pin state, and the third target pin state comprises:

if the MCU chip determines that the first target pin state, the second target pin state and the third target pin state are all in a low-level state, acquiring a target VPX main board control switch for generating the pressing signal from the first VPX main board control switch, the second VPX main board control switch, the third VPX main board control switch and the fourth VPX main board control switch, and acquiring a target VPX main board corresponding to the target VPX main board control switch;

if the MCU chip determines that the target VPX main board is the first VPX main board, generating a first common starting control signal aiming at the first VPX main board;

if the MCU chip determines that the target VPX main board is the second VPX main board, generating a second common starting control signal aiming at the second VPX main board;

if the MCU chip determines that the target VPX main board is the third VPX main board, generating a third common starting control signal aiming at the third VPX main board;

And if the MCU chip determines that the target VPX main board comprises the first VPX main board, the second VPX main board and the third VPX main board, generating a first common starting control signal for the first VPX main board, generating a second common starting control signal for the second VPX main board and generating a third common starting control signal for the third VPX main board.