CN117741257A

CN117741257A - Capacitance detection circuit, detection method, detection device and detection equipment

Info

Publication number: CN117741257A
Application number: CN202311738706.3A
Authority: CN
Inventors: 许欢; 程涛; 李翔
Original assignee: Shanghai Awinic Technology Co Ltd
Current assignee: Shanghai Awinic Technology Co Ltd
Priority date: 2023-12-15
Filing date: 2023-12-15
Publication date: 2024-03-22

Abstract

The application relates to the technical field of capacitance detection, in particular to a capacitance detection circuit, a detection method, a detection device and detection equipment. The method comprises the following steps: the charging and discharging unit is used for providing a mirror current source to charge or discharge the capacitor to be tested and providing a power supply voltage for the trigger, the mirror current source at least comprises a first current source and a second current source, the first current source provides a charging compensation current for the second current source, the charging and discharging unit is further used for controlling the first charging time of the first current source to the capacitor to be tested to be smaller than or equal to the second charging time of the second current source to the capacitor to be tested, and the first charging time is the same as the initial time of the second charging time. The two paths of charging currents can reduce the charging and discharging period of the capacitance detection end, so that the oscillation period of the capacitance detection circuit is reduced. Finally, the count value of the counter is increased in the sampling time, so that the sensitivity of capacitance detection is improved.

Description

Capacitance detection circuit, detection method, detection device and detection equipment

Technical Field

The application relates to the technical field of capacitance detection, in particular to a capacitance detection circuit, a detection method, a detection device and detection equipment.

Background

Capacitive touch screens or keys and the like are widely applied to electronic products because of good performance and long service life. The scheme of adopting the oscillator in the analog front-end circuit is commonly used for realizing capacitive touch detection due to low cost, simple realization and the like. When a user touches or approaches the capacitance detection end, the capacitance value of the capacitance detection end is caused to change, so that the count value correspondingly changes. And obtaining a count value variation by making a difference between the count value in the sampling time and the count value in the previous sampling time, and further judging the touch action by comparing the count value variation with a preset threshold value.

However, the capacitance value of the capacitor to be measured is often larger, the charging and discharging time is longer, and the period of the output signal of the corresponding oscillator is longer, so that the number of square waves of the output signal counted in the sampling time is also smaller. Therefore, the change rate of the count value is small, and accordingly the sensitivity of the capacitor to be detected of the capacitor detection element is reduced, and finally the judgment result based on the capacitor detection result is affected. Therefore, how to improve the sensitivity of capacitance detection is a problem to be solved.

Disclosure of Invention

The embodiment of the application provides a capacitance detection circuit, a detection method, a detection device and detection equipment, which reduce the charge and discharge period of a capacitor to be detected, so that the change amount of a count value is increased, and the sensitivity of capacitance detection is improved.

In a first aspect, embodiments of the present application provide a capacitance detection circuit, applied to a capacitance detection device, including: the charging and discharging unit is used for providing a mirror current source to charge or discharge the capacitor to be tested and providing a power supply voltage for the trigger, the mirror current source at least comprises a first current source and a second current source, the first current source is used for providing a charging compensation current for the second current source, the charging and discharging unit is also used for controlling the first charging time of the first current source to the capacitor to be tested to be smaller than the second charging time of the second current source to the capacitor to be tested, and the first charging time is the same as the initial time of the second charging time; the trigger is used for determining the type of the turnover control signal output to the oscillation control unit according to the comparison result of the received power supply voltage and the voltage threshold of the input end; the oscillation control unit is used for determining the type of the oscillation control signal output to the counting unit according to the type of the received overturning control signal; the counting unit is used for counting a counting value in the sampling time, the counting value is the number of the collected oscillation periods, the oscillation periods are the time length required by the type change of the oscillation control signal, and the size of the counting value is related to the charging current value provided by the first current source and the length of the first charging time.

It can be understood that when the user touches the capacitance detection terminal, the magnitude of the capacitance Cx to be measured of the capacitance detection terminal changes. Correspondingly, the charge and discharge period of the capacitor detection end can be reduced by the two paths of charge currents, so that the voltage change period of the capacitor detection end is correspondingly reduced, and the oscillation period of the trigger is reduced. Finally, the counting value variation of the counter is increased in the sampling time, so that the sensitivity of capacitance detection is improved.

In a possible implementation of the first aspect, the circuit further includes: the first current source and the second current source are mirror image current sources based on the same power supply, and the same power supply comprises a constant voltage power supply in the capacitance detection circuit.

In a possible implementation of the first aspect, the circuit further includes: the charge-discharge unit is also used for controlling the first discharge time and the first charge time of the circuit where the first current source is located to be equal, and controlling the second discharge time and the second charge time of the circuit where the second current source is located to be equal.

It will be appreciated that the first discharge time and the first charge time described above are controlled by the on-times of the first switch and the second switch.

In a possible implementation of the first aspect, the circuit further includes: the voltage threshold includes a first flip voltage and a second flip voltage, wherein the first flip voltage is less than the second flip voltage, and the flip-flop is further configured to: determining to output a first turnover signal to the oscillation control unit according to a comparison result that the power supply voltage is smaller than or equal to a first turnover voltage, wherein the first turnover signal is used for indicating that the oscillation control signal output by the oscillation control unit is switched from the first control signal to an inverted second control signal, the first control signal is a high-level signal, and the second control signal is a low-level signal; and determining to output a second turnover signal to the oscillation control unit according to a comparison result that the power supply voltage is greater than or equal to the first turnover voltage, wherein the second turnover signal is used for indicating that the oscillation control signal output by the oscillation control unit is switched from the second control signal to the inverted first control signal.

It can be understood that the first control signal is used for controlling the on-off of the first switch and the third switch, and charging the capacitor to be tested; the second control signal is used for controlling the on-off of the second switch and the third switch, and discharging the capacitor to be tested.

In a possible implementation of the first aspect, the circuit further includes: the counting value change amount is a difference value between a first counting value and a second counting value counted by the counting unit in the same sampling time, wherein the first counting value is the number of oscillation periods acquired during the period that a user touches the capacitor to be detected, and the second counting value is the number of oscillation periods acquired during the period that the user does not touch the capacitor to be detected.

In one possible implementation of the first aspect, the count value change amount is related to a charging current value provided by the first current source and the first charging time, and includes: calculating to obtain a first count value or a second count value based on the ratio of the sampling time to the oscillation period; the magnitude of the oscillation period is inversely related to a first product, which is a product of a charging current value provided by the first current source and a first charging time.

In a possible implementation manner of the first aspect, the data processing unit further includes: determining a detection result of the capacitance change to be detected based on the count value change; and determining whether the capacitance change quantity to be detected corresponds to the touch operation result of the user according to the comparison result between the count value change quantity and the preset change quantity threshold value.

In a possible implementation of the first aspect, the circuit further includes: the flip-flop is a schmitt trigger.

In a possible implementation of the first aspect, the method further includes: generating a mirror current source based on a power supply, wherein the mirror current source at least comprises a first current source and a second current source, and the first current source provides a charging compensation current for the second current source; the method comprises the steps of controlling a first charging time of a first current source to a capacitor to be tested to be smaller than or equal to a second charging time of a second current source to the capacitor to be tested, wherein the first charging time is identical to the initial time of the second charging time; and detecting the capacitance change of the capacitor to be detected, and counting the count value in the sampling time.

In a possible implementation of the first aspect, the circuit further includes: and determining a detection result of the capacitor to be detected according to the count value change quantity, wherein the count value change quantity is the change degree of the count value caused by the touch of a user, and the count value change quantity is related to the charging current value provided by the first current source and the length of the first charging time.

It can be understood that the first current source and the second current source start to charge the capacitor to be tested at the same time, the first charging time is changed according to the change of the on time of the first switch, and the second charging time is the time when the voltage across the capacitor to be tested is increased from the first flipping voltage to the second flipping voltage. It can be seen that the longer the first charging time is, the shorter the second charging time is, and the shorter the charging and discharging period of the capacitor to be measured is. Wherein the first charging time is less than or equal to the second charging time.

In a possible implementation of the first aspect, the circuit further includes: the count value variation is related to a charging current value provided by the first current source and a first charging time, and includes: calculating to obtain a first count value or a second count value based on the ratio of the sampling time to the oscillation period; the magnitude of the oscillation period is inversely related to a first product, which is a product of a charging current value provided by the first current source and a first charging time.

It can be understood that the larger the product of the charging current value provided by the first current source and the first charging time is, the smaller the charging and discharging period of the capacitor to be detected is, and the smaller the corresponding oscillation period is, the larger the count value variation in the sampling time is, so that the sensitivity of the capacitor detection is improved.

In a possible implementation of the first aspect, the method further includes: determining a detection result of the capacitor to be detected according to the count value variation, including: and determining whether the capacitance change quantity to be detected corresponds to the touch operation result of the user according to the comparison result between the count value change quantity and the preset change quantity threshold value.

It can be understood that when the above count value variation is greater than the preset variation threshold, the touch operation of the user is determined. In some embodiments, the touch operation of the user may be further determined to be clicking, long pressing, or the like according to the count value variation, which is not limited herein.

In a second aspect, embodiments of the present application provide a capacitance detection device, including any one of the foregoing capacitance detection circuits, where the capacitance detection circuit is configured to perform the capacitance detection method according to any one of the foregoing claims.

In a third aspect, embodiments of the present application provide a capacitance detection device, including: the register is used for storing various instructions or configuration information, and the instructions are used for controlling the sampling time of the capacitance detection circuit to the oscillation period number; a processor, one of the processors of the integrated circuit, for performing the capacitance detection method of any one of the above.

Drawings

Fig. 1 is a schematic diagram of a conventional capacitance detection circuit according to this embodiment.

Fig. 2 is a schematic diagram showing a configuration of a capacitance detection circuit capable of improving detection sensitivity according to the present embodiment.

Fig. 3 shows a flow chart of an implementation of a capacitance detection method according to the present embodiment.

Fig. 4 shows an operation timing chart of a capacitance detection circuit for improving sensitivity according to the present embodiment.

Fig. 5 is a schematic diagram showing another configuration of a capacitance detection circuit capable of improving detection sensitivity according to the present embodiment.

Fig. 6 shows a flowchart of another implementation of the capacitance detection method according to the present embodiment.

Fig. 7 shows another circuit operation timing diagram for improving the capacitance detection sensitivity according to the present embodiment.

Detailed Description

The following detailed description of the present application will be made with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. Based on the embodiments herein, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of the present application.

In order to understand the schemes in the embodiments of the present application more clearly, the following explanation will be given first on terms in the embodiments of the present application.

(1) MOS transistors are abbreviations for MOSFET transistors, i.e. Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFETs).

(2) VTH is the high flip-flop voltage of the flip-flop and VTL is the low flip-flop voltage of the flip-flop.

A capacitance detection method capable of improving detection and a corresponding capacitance detection circuit will be described in detail below by way of example 1.

As shown in fig. 1, in the conventional capacitive detection scheme, in the oscillation scanning period, the counter counts the sampling value Δn by counting the number of square waves of the output oscillation signal, and when Δn is greater than a preset touch threshold value, it can be determined that the capacitive detection scheme is a touch operation. However, since the capacitance to be detected of the common capacitance detection end is relatively large, only two paths of charge-discharge current pairs exist, and since the capacitance value of the capacitance to be detected is relatively large, the charge-discharge period is relatively long, and the sampling values before and after touching are affected, the sensitivity of the capacitance detection device is reduced.

Oscillation period T in existing capacitive detection schemes:

wherein k' is a factor related to parameters of related components of the circuit, and Cx represents the capacitance value of the capacitor to be tested; Δt (delta t) _LH Indicating the charging time, Δt _HL Indicating the discharge time; r2, R3 and R4 are all adjusting resistors for outputting a reference voltage in the circuit shown in fig. 1.

Within the sampling time Tmear, the count value N counted by the counter:

therefore, before and after touching, the capacitance to be measured increases, resulting in a count value change:

where Δcx represents the amount of change in capacitance to be measured before and after touch.

As can be seen from the above formula, the magnitude of the count value N and the count value Δn in the sampling time are related to the magnitude of the capacitance Cx to be detected, and the larger the capacitance Cx to be detected is, the smaller the count value N and the count value variation Δn before and after touch are, so that the sensitivity of capacitance detection is lower. It can be understood that the larger the count value variation Δn, the higher the sensitivity of the capacitance detection.

However, as before, in the conventional capacitive sensing scheme, the resistor R1 is used to charge and discharge the capacitor to be measured by controlling the charge and discharge of positive feedback formed at the output end and the input end of the comparator. When the capacitance value of the parasitic capacitor contained in the capacitor to be detected is larger, the charge and discharge period of the capacitor detection end is longer, and the period of the oscillation control signal output by the comparator is longer. The delta N value of the sampling value before and after touching is small, and the sensitivity of capacitance detection is reduced.

In order to solve the above problems, the present application provides a capacitance detection method capable of improving detection sensitivity, which is applied to a capacitance detection device or apparatus. Specifically, the charging and discharging unit of the method comprises a plurality of MOS tube forming current mirror circuits, and two paths of charging currents are provided for the capacitor to be tested, wherein one path of charging current is the compensation current of the other path of charging current. When the capacitor to be tested is charged, two or more paths of charging currents are provided. The trigger turns over according to the voltage value output by the capacitor detection end, outputs an oscillation control signal, and the counter counts the oscillation control signal.

It can be understood that, when the user performs a touch operation, the capacitance Cx to be measured at the capacitance detecting end changes in size. Correspondingly, the charge and discharge period of the capacitor detection end can be reduced by the two paths of charge currents, so that the voltage change period of the capacitor detection end is correspondingly reduced, and the oscillation period of the trigger is reduced. Finally, the count value of the counter is increased in the sampling time, so that the sensitivity of capacitance detection is improved.

In order to more clearly describe the capacitance detection scheme provided by the embodiment of the present application, the structure, the working principle and the detailed implementation process of the capacitance detection method of the capacitance detection circuit provided by the embodiment of the present application are respectively described below in conjunction with specific embodiments. The following describes, with reference to the embodiments, a capacitive detection scheme capable of improving detection sensitivity provided in the embodiments of the present application.

Example 1

As shown in fig. 2, the capacitance detection circuit of the present embodiment includes: an oscillation module 110, a counting module 120 and a capacitance detection terminal. The oscillation module 110 and the counting module 120 are directly connected by a wire. In other embodiments, the capacitance detection circuit further includes a data processing module, connected to the counting module 120, for processing the count value of the counting module.

The oscillation module 110 includes: a charge and discharge unit 111, a flip-flop 112, and an oscillation control unit 113. The counting module 120 includes a counter 121. The oscillation module 110 is configured to output an oscillation signal that varies with the capacitance to be measured, and the counting module 120 is configured to count the oscillation signal. The capacitance Cx to be measured includes: the intrinsic capacitance of the capacitance detection end and the parasitic capacitance inside the capacitance detection end. In other embodiments, the capacitance Cx to be measured further includes an external parasitic capacitance generated by the capacitance detection ground, and the like.

Referring to fig. 2, the charge and discharge unit 111 is connected to an input terminal of the trigger 112, an input terminal of the oscillation control unit 113 is connected to an output terminal of the trigger 112, and an output terminal is connected to an input terminal of the counter 121.

With continued reference to fig. 2, the charge-discharge unit 111 is composed of a first MOS transistor MN1, a second MOS transistor MN2, a third MOS transistor MN3, a fourth MOS transistor MN4, a fifth MOS transistor MP1, a sixth MOS transistor MP2, and a seventh MOS transistor MP 3. Ib1 introduces a path of reference current source from the outside, current flows from the power supply voltage VDD to the fifth MOS tube MP1, the current is copied to the sixth MOS tube MP2 and the seventh MOS tube MP3, then copied to the second MOS tube MN2 through the sixth MOS tube MP2, and then copied to the first MOS tube MN1, the third MOS tube MN3 and the fourth MOS tube MN4 through the second MOS tube MN 2. And copying the current acquired from the VDD to the adjacent MOS tubes through copying among the MOS tubes. The current copied by each MOS tube is determined by the size of each MOS tube.

The first MOS transistor MN1, the second MOS transistor MN2, the third MOS transistor MN3, and the fourth MOS transistor MN4 are all NMOS transistors; the fifth MOS tube MP1, the sixth MOS tube MP2 and the seventh MOS tube MP3 are PMOS tubes. The MOS transistors form a compensation circuit, which is called a current mirror circuit, and the circuit can mirror the currents i1 and i2 to the fifth MOS transistor MP1 and the first MOS transistor MN1 through the Ib 1. The capacitance Cx to be measured is charged and discharged, respectively, by the control of the first switch SW1 and the second switch SW 2. Similarly, by controlling the on-off of the third switch SW3 and the fourth switch SW4, the currents i3 and i4 can also be controlled to charge and discharge the capacitance Cx to be measured. Wherein, i1 and i3 can charge the capacitance to be measured Cx, and i2 and i4 can discharge the capacitance to be measured Cx.

The oscillation control unit 113 is configured to output an oscillation control signal to a signal output from the flip-flop 112. For controlling the on-off state of the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW 4. It will be appreciated that the oscillation control unit 113 further includes a control terminal. For inputting an oscillation enable signal, and controlling an enable state of the oscillation module 110.

The input end of the trigger 112 is connected to a capacitance detection end, wherein the capacitance detection end is connected to a capacitance Cx to be detected, and the output end of the trigger 112 is connected to the oscillation control unit 113. It can be understood that the flip-flop 112 may be a schmitt trigger, when the input voltage v=vth of the flip-flop, the flip-flop 112 turns high, the first switch SW1 and the third switch SW3 are opened, the second switch SW3 and the fourth switch SW4 are closed, and the capacitance Cx to be measured is discharged; when the input voltage v=vtl of the flip-flop, the flip-flop 112 turns low, the first switch SW1 and the third switch SW3 are closed, the second switch SW3 and the fourth switch SW4 are opened, and the capacitance Cx to be measured is charged. Wherein VTH is the high flip-flop voltage of the flip-flop 112 and VTL is the low flip-flop voltage v of the flip-flop 112

Further, the oscillation control unit 113 further includes an inverter 113a, and an output terminal of the inverter 113a is configured to output a second control signal DOUT1-B for controlling the fourth switch to discharge the capacitance Cx to be measured.

Specifically, the oscillation control unit 113 may output a corresponding oscillation control signal according to the output square wave signal DOUT1 of the flip-flop 112. Wherein the oscillation control signal includes a first control signal DOUT1-A and a second control signal DOUT1-B. It is understood that the first control signal DOUT1-A and the second control signal DOUT1-B may be inverted signals.

When DOUT1 is at a high level, the first switch SW1 and the third switch SW3 are turned on, and the capacitance Cx to be measured is charged. It can be understood that the first switch SW1 and the third switch SW3 control on-off of the currents i1 and i3, where the charging time tc1 of the capacitor to be tested i1 may be less than or equal to the charging time t1 of the capacitor to be tested i 3. When DOUT1 is at a low level, the second switch SW2 and the third switch SW4 are turned on, and the capacitance Cx to be measured is discharged. Similarly, the discharge time tc2 of the capacitor to be measured is smaller than or equal to the discharge time t2 of the capacitor to be measured of i 4. The charging time t1 corresponding to the current i3 is the total charging time of the capacitance Cx to be measured, and the charging time t2 corresponding to the current i4 is the total discharging time of the capacitance Cx to be measured.

It will be appreciated that tc1 and tc2 are controlled by the on-off times of the first switch SW1 and the second switch SW 2. In some embodiments, the total charge-discharge time of the capacitor to be measured can be reduced by increasing the currents i1 and i2 or only increasing the current i1 or i2, so as to further reduce the charge-discharge period of the capacitor to be measured; the total charge and discharge time of the capacitor to be measured can be reduced by increasing tc1 and tc2 or only increasing tc1 or tc2, and the charge and discharge period of the capacitor to be measured is further reduced, which is not limited herein.

It can be understood that, in the capacitance detection process, when the voltage across the capacitance Cx to be detected is at VTL, the output signal DOUT1 of the trigger 112 is at a high level, the oscillation control signal is also at a high level, and the first switch SW1 and the third switch SW3 are closed, so as to charge the capacitance Cx to be detected. When the voltage at two ends of the capacitance Cx to be detected is increased to VTH, the signal output by the trigger 112 is overturned, namely VTH is the high overturned voltage of the trigger 112; at this time, the second switch SW2 and the fourth switch SW4 are turned on, the capacitor Cx to be tested discharges, the voltage across the capacitor Cx to be tested decreases from VTH to VTL, and when the voltage across the capacitor Cx decreases to VTL, the signal output by the flip-flop 112 is inverted again, i.e., VTL is the low flip-flop voltage of the flip-flop 112. The circuit is reciprocated, so that the voltage at two ends of the capacitance Cx to be measured oscillates between VTH and VTL, the trigger 112 outputs a square wave oscillation control signal, the oscillation control unit 113 outputs an oscillation control signal with the same frequency as the voltage change at two ends of the capacitance Cx to be measured, and the counter 121 counts DOUT 1. And counting the vibration cycle number N of DOUT1 in the appointed detection time, and taking the vibration cycle number N as capacitance sampling data.

When there are no currents i1 and i2, due to conservation of charge, it is deduced from the formula q=c×u and q=i×t:

when in charging: cx (VTH-VTL) =i3×t1 (4)

When discharging, the following steps are carried out: cx (VTH-VTL) =i4×t2 (5)

When the fourth MOS transistor MN4 and the seventh MOS transistor MP1 are equal in size, that is, the mirrored current i3=i4, the following equation (6) may be referred to for the calculation equation of the oscillation period:

T _mear the count value in the sampling time can be calculated by the following formula:

it will be appreciated that the sampling time may be controlled by the enable signal EN output by a chip or digital circuit or the like to which the capacitance detection circuit is connected. For example, the control procedure: the time of the output enable signal en=1 is equal to the sampling time, and the time of the output enable signal en=0 is equal to the non-sampling time.

When a user touches the capacitance detection terminal, the capacitance Δcx of the capacitance Cx to be detected increases, and thus the count value before and after touch can be calculated by the following formula:

it can be understood that the larger the count value variation Δn before and after the user touches, the higher the sensitivity of the capacitance detection. Thus, the first and second substrates are bonded together,

in this embodiment, the charging and discharging period of the capacitance Cx to be measured is further reduced by increasing the currents i1 and i 2. Wherein i1 is a charging current controlled by the first switch SW1 to the capacitance Cx to be measured; i2 is a discharge current controlled by the first switch SW2 to the capacitance Cx to be measured.

In the process of charging the voltage at two ends of the capacitance Cx to be measured from the VTL to the VTH, after the charge compensation current i1 is increased according to the charge conservation principle, the following relational expression is obtained:

Cx*(VTH-VTL)＝i1*tc1+i3*t1 (9)

the calculation formula for the charging time evolved from the above formula (8) is as follows:

according to the deduction process of the charge time formula, the calculation formula for obtaining the discharge time is as follows:

when the first MOS transistor MN1 and the fifth MOS transistor MP1 are equal in size, and the fourth MOS transistor MN4 and the seventh MOS transistor MP1 are equal in size, that is, the mirrored current i1=i2, i3=i4, a calculation formula of the charge-discharge period of the capacitance Cx to be measured can be obtained as follows:

T _mear the calculation formula of the count value in the sampling time can be:

when a user touches the capacitance detection end, the capacitance of the change of the capacitance Cx to be detected is delta Cx, so that the change amount of the count value before and after touch is as follows:

wherein, the above

As can be seen from the comparison between the above equation (6) and equation (12), increasing the currents i1 and i2 decreases the charge-discharge period of the capacitance Cx to be measured, and from the comparison between the above equation (8) and equation (14), the value of Δn increases, and the sensitivity of the corresponding capacitance detection increases.

When a user operates, the size of the capacitance Cx to be detected changes, so that the charge and discharge rate of the capacitance detection end changes, the voltage change frequency of the capacitance detection end changes, the frequency of the first control signal DOUT1-A changes finally, the count value of the counter changes, and whether touch operation exists or not is judged.

Based on the capacitance detection circuit shown in fig. 2, a specific implementation procedure of the capacitance detection method provided in the embodiment of the present application is described below with reference to a flow shown in fig. 3.

As shown in fig. 3, the process includes the steps of:

301: based on the sampling time, the capacitance detection circuit starts to work and generates an oscillation control signal.

It can be understood that the capacitance detection circuit starts to operate based on a preset sampling time, and in the capacitance detection process, the output enable signal EN has two states. When the output enable signal en=0, a preparation phase is provided for capacitance detection, at this time, the trigger outputs a stable signal, the oscillation control unit is in an inactive state, and the counter does not count. When the output enable signal en=1, the detection circuit starts to perform capacitance detection, the size of the capacitor to be detected changes, the charge and discharge period of the capacitor detection end changes, the voltage period of the capacitor detection end correspondingly changes, and the trigger periodically outputs an oscillation control signal according to the voltage change frequency of the capacitor detection end. Wherein the oscillation control signal comprises a first control signal DOUT1-A and a second control signal DOUT1-B

302: the capacitance detection circuit determines the generated oscillation control signal as a first control signal, and charges the capacitance to be detected.

For example, if the oscillation control signal output from the capacitance detection circuit is a high level signal, it may be determined that the control signal is a control signal that triggers charging of the capacitance to be measured. In this embodiment of the present application, the control signal may be denoted as a first control signal DOUT1-a, and is used for controlling charging of the capacitor to be tested. At this time, DOUT1 is at a high level, and the first switch SW1 and the third switch SW3 are turned on to charge the capacitor to be tested. When the voltage across the capacitor to be tested increases to VTH, the signal output by the flip-flop is flipped, i.e., VTH is the high flipped voltage of the flip-flop 112.

It can be understood that the first switch SW1 and the third switch SW3 are turned on, and the currents i1 and i3 are controlled to charge the capacitor to be tested, so that the charging time is shortened.

303: the capacitance detection circuit determines that the generated oscillation control signal is a second control signal, and discharges the capacitance to be detected.

For example, if the oscillation control signal output from the capacitance detection circuit is a high level signal, it may be determined that the control signal is a control signal that triggers charging of the capacitance to be measured. In this embodiment of the present application, the control signal may be denoted as a second control signal DOUT1-B, which is used to control discharging of the capacitor to be tested. At this time, DOUT1 is low. The second switch SW2 and the fourth switch SW4 are closed, the capacitor to be tested discharges, the voltage at two ends of the capacitor to be tested is reduced from VTH to VTL, and when the voltage at two ends is reduced to VTL, the signal output by the trigger 112 is inverted again, i.e. VTL is the low inverted voltage of the trigger 112.

It can be understood that the second switch SW2 and the fourth switch SW4 are turned on, so as to control the currents i2 and i4 to discharge the capacitor to be tested, thereby accelerating the discharge time.

304: the capacitance detection circuit counts the output oscillation control signals to obtain count values of the oscillation control signals at all times.

Based on the contents shown in the above steps 303 and 304, the voltage across the capacitor to be tested oscillates reciprocally between VTH and VTL, and the trigger outputs the square wave signal DOUT1 accordingly. The counter counts DOUT1, i.e. counts the number of square waves of DOUT1.

It can be understood that after the compensation current is increased, the charge and discharge time of the capacitor to be measured is reduced, the charge and discharge period of the capacitor to be measured is reduced, and the period of the output oscillation control signal is also reduced, so that the change delta N of the count value is increased according to the above formula, and the sensitivity of the capacitor detection is improved.

305: the capacitance detection circuit counts the counting value variation in the sampling time, and determines whether the touch operation of the user is detected according to the comparison result of the counting value variation and the preset threshold value.

It will be appreciated that in other embodiments, the capacitance sensing circuit further comprises a data processing unit for processing the sampled count value to obtain a count value variation. For example, the change amount Δn of the count value before and after the user touches is obtained according to the above formula, and Δn is compared with a preset threshold value, and when Δn is greater than the threshold value, the touch operation of the user is determined, and in some embodiments, the type of the touch operation may be clicking, long-pressing, or the like.

The above-described process of changing the capacitance Cx to be measured in steps 301 to 305 may refer to the timing diagram shown in fig. 4.

As shown in fig. 4, the broken line portion in the figure is an operation timing chart when the currents i1 and i2 are not increased, and the solid line portion is an operation timing chart when the currents i1 and i2 are increased, as shown in fig. 4. After the currents i1 and i2 are increased, the charge-discharge period of the capacitance Cx to be measured is significantly smaller than that of the capacitor having no current i1 and i 2. Therefore, the count value change amount Δn of the counter 121 becomes large within the same sampling time Tmear, thereby improving the sensitivity of the capacitance detection.

With continued reference to fig. 4, according to the circuit operation timing diagram shown in fig. 4, the complete capacitive detection process is divided into two stages, the first stage is a detection preparation stage, and at this time, the output enable signal en=0, and the oscillation control module 110 is in a non-operating state. The second stage is a capacitive detection stage, and at this time, the output enable signal en=1, and the oscillating module 110 outputs a stable square wave signal according to the signal output by the trigger 112. The count module 120 begins counting DOUT 1.

In other embodiments, the complete capacitive sensing process further includes a third stage as a capacitive sensing result processing module, where the operating state of the oscillating module 120 is the same as that of the second stage, but the counting module 120 is not counting the number N of square waves.

It can be understood that, when the user performs a touch operation, the capacitance Cx to be measured at the capacitance detecting end changes in size. In the capacitance detection circuit provided by the embodiment of the application, two paths of charging current and discharging current can effectively reduce the charging and discharging period of the capacitance detection end, so that the voltage change period of the capacitance detection end is correspondingly reduced, and the oscillation period of the trigger is reduced. Finally, the count value of the counter in the sampling time can be changed to a larger extent, and the sensitivity of capacitance detection is further improved.

Another capacitive detection scheme capable of improving detection sensitivity provided by the embodiments of the present application is described below with reference to another embodiment.

Example 2

In this embodiment, referring to fig. 5, fig. 5 shows a schematic diagram of another capacitive detection circuit capable of improving detection sensitivity according to this embodiment. As shown in fig. 5, the capacitance detection circuit of the present embodiment includes a reference voltage module 210, an oscillation module 220, a counting module 230, and a capacitance detection terminal. In other embodiments, the capacitance detection circuit further includes a data processing unit connected to the counting module, and configured to process the count value collected by the counting module. The reference voltage module 210, the oscillation module 220 and the counting module 230 are directly connected by wires according to the connection mode shown in fig. 5.

The reference voltage module 210 is connected to the power voltage VDD, and is configured to convert the power voltage VDD to output a first reference voltage VTH and a second reference voltage VTL; the oscillation module 220 is configured to output an oscillation signal that varies with the capacitance to be measured; the counting module 230 is used to count DOUT 2; the capacitance Cx to be measured includes: the intrinsic capacitance of the capacitance detection end and the parasitic capacitance inside the capacitance detection end. In other embodiments, the capacitance Cx to be measured further includes an external parasitic capacitance between the capacitance sensing terminal and ground, and so on.

It can be understood that the reference voltage module 210 includes a second resistor R2, a third resistor R3, and a fourth resistor R4 serially connected between the voltage source and the ground in sequence; the connection ends of the second resistor R2 and the third resistor R3 are used as output ends of the first reference voltage VTH and are used for outputting the first reference voltage VTH; the connection ends of the third resistor R3 and the fourth resistor R4 are used as output ends of the second reference voltage VTL for outputting the second reference voltage VTL. The second resistor R2, the third resistor R3, and the fourth resistor R4 serve as voltage dividing resistors.

The circuit logic of the reference voltage module 140 can know that the first reference voltage Second reference voltage->The values of the first reference voltage VTH and the second reference voltage VTL may be changed by adjusting the resistances of the second resistor R2, the third resistor R3, and the fourth resistor R4.

With continued reference to fig. 5, as shown in fig. 5, the reference voltage output module 210 further includes a first capacitor C1 and a second capacitor C2. It can be understood that the first capacitor C1 has one end grounded and the other end connected to the output end of the first reference voltage VTH; one end of the second capacitor C2 is grounded, and the other end of the second capacitor C is connected with the output end of the second reference voltage VTL. The first capacitor C1, the second capacitor C2, the second resistor R2, the third resistor R3 and the fourth resistor R4 form a low-pass filter, and high-frequency interference of the output first reference voltage VTH and the output second reference voltage VTL is filtered. In other embodiments, the second resistor R2, the third resistor R3, and the fourth resistor R4 may be formed by one or more resistors connected in series and/or parallel, and the like, which is not limited herein.

It is understood that the oscillation module 210 includes a charge/discharge control unit 211, a comparator 212, and an oscillation control unit 213.

The charge-discharge control unit 211 is connected between the second input terminal of the comparator 212 and the output terminal of the oscillation control unit 213.

In other embodiments, the charge and discharge control unit 211 is connected between the second input terminal and the output terminal of the comparator 212, which is not limited herein. The charge-discharge control unit 211 includes a first resistor R1 and a current mirror connected between the power supply voltage VDD and the ground and composed of an eighth MOS transistor MN4, a ninth MOS transistor MN5, a tenth MOS transistor MN6, an eleventh MOS transistor MP4, and a twelfth MOS transistor MP5.

The first resistor R1 is used for charge and discharge control that forms positive feedback between the second input terminal of the comparator 212 and the output terminal of the oscillation control unit 213. The compensation current i5 is controlled by the fifth switch SW5 to charge the capacitor to be tested. The sixth switch SW6 controls the current i6 to discharge the capacitance to be measured.

One path of reference current source is obtained from the external current source module through Ib1, current flows from the power voltage VDD to the eleventh MOS tube MP4, and is copied to the twelfth MOS tube MP5 from the eleventh MOS tube MP 4. And then the current is copied to the eighth MOS transistor MN4, the ninth MOS transistor MN5 and the tenth MOS transistor MN6. And copying the current acquired from the VDD to the adjacent MOS tubes through copying among the MOS tubes. The current copied by each MOS tube is determined by the size of each MOS tube.

When charging, the fifth switch SW5 is closed, and the current i5 and the first resistor R1 charge the capacitor to be tested; when discharging, the sixth switch SW6 is closed, and the current i6 and the first resistor R1 discharge the capacitance to be measured. And the charge-discharge control unit 211 is connected to the input terminal of the comparator 212. In other embodiments, the charge/discharge control unit 211 may be connected between the output terminal and the second input terminal of the comparator 212, which is not limited herein.

A first input terminal of the comparator 212 is connected to an output terminal of the first reference voltage VTH through a seventh switch S1; the second input end is connected with the capacitance detection end. The first input terminal is a positive input terminal of the comparator 212, and the second input terminal is a negative input terminal of the comparator.

The oscillation control unit 213 outputs an oscillation control signal for controlling the on/off states of the fifth, sixth, and seventh switches SW5, SW6, SW7, and SW8 according to the output signal of the comparator 212.

It is understood that the oscillation control unit 213 may output a corresponding oscillation control signal according to the signal DOUT2 output by the comparator 212, wherein the oscillation control signal includes a first control signal DOUT2-a and a second control signal DOUT2-B. The first control signal DOUT2-A and the comparator 212 output in-phase signals.

It will be appreciated that the first control signal DOUT2-a is used to control the on/off of the fifth switch SW5 and the seventh switch S1, the second control signal DOUT2-B is used to control the on/off of the sixth switch SW6 and the eighth switch S8, and the first control signal DOUT2-a and the second control signal DOUT2-B are inverted signals. At the same time, only one set of the fifth switch SW5 and the seventh switch SW7 or the sixth switch SW6 and the eighth switch SW8 is turned on.

With further reference to fig. 5, the oscillation control unit 213 further includes an inverter 213a for outputting the second control signal DOUT2-B. It is understood that the first control signal DOUT2-B and the second control signal DOUT2-a are inverted signals.

The counting module 230 includes a counter 231 for sampling and counting the oscillation control signal DOUT2 output from the oscillation module 220.

It is understood that the oscillation control unit 213 may further include a control terminal, wherein the control terminal may be a chip or a digital circuit, and in this embodiment, when the output enable signal en=0, corresponds to a non-sampling time. The oscillation control unit 213 is in a non-start state, and the counter 231 does not count. When the output enable signal en=1, the sampling time corresponds. At this time, the comparator 212 outputs a high level, the oscillation control signal is also a high level, that is, the first control signal DOUT2-a, the voltage at two ends of the capacitance Cx to be measured is VTL, and at this time, the fifth switch SW5 and the seventh switch SW7 are closed, so as to charge the capacitance Cx to be measured. When the voltage across the capacitance Cx to be measured increases to VTH, the signal output from the comparator 212 is inverted to 0. At this time, the sixth switch SW6 and the eighth switch SW8 are turned on, the capacitance Cx to be measured is discharged, the voltage across the capacitance Cx to be measured is reduced from VTH to VTL, and when the voltage across the capacitance Cx is reduced to VTL, the signal output from the comparator 212 is inverted to 1 at a second time. The voltage at two ends of the capacitance Cx to be measured oscillates reciprocally between VTH and VTL, the comparator 212 outputs a square wave signal, and the oscillation control unit 213 outputs an oscillation control signal of the same frequency as the voltage change at two ends of the capacitance Cx to be measured, and the counter 231 counts DOUT 2. And counting the vibration period number N of DOUT2 in the sampling time, and taking the vibration period number N as capacitance sampling data.

Based on the capacitance detection circuit shown in fig. 5, a specific implementation procedure of the capacitance detection method provided in the embodiment of the present application is described below with reference to a flow shown in fig. 6.

As shown in fig. 6, the flow includes the steps of:

601: based on the sampling time, the capacitance detection circuit starts to work and generates an oscillation control signal.

The difference from step 302 described above is that: in this step, the voltage reference module outputs the first reference voltage and the second reference voltage for inverting reference of the comparator output signal. When the input voltage of the second input end of the comparator is the same as the voltage of the first input end, signal inversion occurs. The voltage input by the first input end comprises a first reference voltage VTH and a second reference voltage VTL. The voltage input by the second input end is the voltage of the capacitor detection end.

602: the capacitance detection circuit determines the generated oscillation control signal as a first control signal, and charges the capacitance to be detected.

The difference from step 302 described above is that: in this step, the first resistor R1 is used for charge-discharge control that forms positive feedback between the second input terminal of the comparator and the output terminal of the oscillation control unit, and the first resistor R1 is used for charge control at this time in response to the first control signal. When the capacitor to be measured is charged, the first circuit R1 and the current i5 charge the capacitor to be measured together.

603: the capacitance detection circuit determines that the generated oscillation control signal is a second control signal, and discharges the capacitance to be detected.

The difference from step 303 above is that: in this step, the first resistor R1 is used for charge-discharge control that forms positive feedback between the second input terminal of the comparator and the output terminal of the oscillation control unit. The first resistor R1 is used for discharge control at this time in response to the second control signal. When the capacitor to be tested is discharged, the first circuit R1 and the current i6 jointly discharge the capacitor to be tested.

604: the capacitance detection circuit counts the output oscillation control signals to obtain count values of the oscillation control signals at all times.

605: the capacitance detection circuit counts the counting value variation in the sampling time, and determines whether the touch operation of the user is detected according to the comparison result of the counting value variation and the preset threshold value.

It will be appreciated that steps 605 to 605 are described with reference to steps 304 to 305, and are not described herein. The above-described process of changing the capacitance Cx to be measured in steps 601 to 605 may refer to the timing diagram shown in fig. 7.

Referring to fig. 7, the dotted line portion is an operation timing chart when the compensation current is not increased, and the solid line portion is an operation timing chart when the compensation current is increased. After the compensation current is increased, the charge-discharge period of the capacitance Cx to be measured is obviously smaller than that of the capacitor without the compensation current. When the oscillation control signal is at a high level, namely DOUT 2-a=1 and DOUT 2-b=0, the detection resistor is charged together by the current i5 and the first resistor R1, so that the charging time of the capacitance Cx to be measured is reduced. Similarly, when the oscillation control signal is at a high level, namely DOUT 2-a=0 and DOUT 2-b=1, the current i6 and the first resistor R1 charge the detection resistor Cx together, so that the discharge time of the capacitance Cx to be measured is reduced. Correspondingly, the charge-discharge period T of the capacitance Cx to be measured is reduced, the sampling count value is increased, and the sensitivity of capacitance detection is improved within the same sampling time Tmear.

Referring further to fig. 7, according to the circuit operation timing diagram shown in fig. 7, the complete capacitive detection process is also divided into two phases, similar to the above-mentioned fig. 4 operation phase, in which the first phase is a detection preparation phase, and in this case, enable en=0 of the oscillation control unit 213, and the oscillation control module 210 is in a non-operation state. The second phase is a capacitance detection phase, when the oscillation control unit 213 enables en=1, the oscillation module 210 outputs a stable square wave signal, i.e. DOUT2, according to the signal output by the comparator 212. The count module 230 begins counting DOUT2. In other embodiments, the complete capacitive sensing process further includes a third stage as a capacitive sensing result processing module, where the operating state of the oscillating module 210 is the same as that of the second stage, but the counting module 230 is not counting the number N of square waves.

In some alternative embodiments, the present application provides a capacitance detection device, which is suitable for the capacitance detection circuit, wherein the capacitance detection circuit is used for implementing a capacitance detection method. In addition, the present application also provides a capacitance detection device, including: a register for storing various instructions or configuration information; an instruction for controlling sampling time of the capacitance detection circuit to the oscillation period number; the processor, which is one of the processors of the integrated circuit, is used to execute the capacitance detection method.

It should be noted that in the examples and descriptions of this patent, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

While the present application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A capacitance detection circuit, comprising: a charge-discharge unit, a trigger, an oscillation control unit and a counting unit, wherein,

the charging and discharging unit is used for providing a mirror current source to charge or discharge the capacitor to be tested and providing a power supply voltage for the trigger, the mirror current source at least comprises a first current source and a second current source, the first current source is used for providing a charging compensation current for the second current source, the charging and discharging unit is also used for controlling the first charging time of the first current source to the capacitor to be tested to be smaller than the second charging time of the second current source to the capacitor to be tested, and the first charging time is the same as the initial time of the second charging time;

the trigger is used for determining the type of the turnover control signal output to the oscillation control unit according to the comparison result of the received power supply voltage and the voltage threshold value of the input end;

the oscillation control unit is used for determining the type of the oscillation control signal output to the counting unit according to the type of the received overturning control signal;

The counting unit is used for counting a counting value in the sampling time, the counting value is the number of the collected oscillation periods, the oscillation periods are the time length required by the type change of the oscillation control signal, and the size of the counting value is related to the charging current value provided by the first current source and the length of the first charging time.

2. The capacitance sensing circuit of claim 1 wherein the first current source and the second current source are mirrored current sources based on the same power supply, the same power supply comprising a constant voltage power supply in the capacitance sensing circuit.

3. The capacitance detecting circuit according to claim 1, wherein the charge-discharge unit is further configured to control a first discharge time of the circuit in which the first current source is located to be equal to the first charge time, and control a second discharge time of the circuit in which the second current source is located to be equal to the second charge time.

4. The capacitance detection circuit of claim 1, wherein the voltage threshold comprises a first flip voltage and a second flip voltage, wherein the first flip voltage is less than the second flip voltage, and the flip-flop is further configured to:

determining to output a first turnover signal to the oscillation control unit according to a comparison result that the power supply voltage is smaller than or equal to a first turnover voltage, wherein the first turnover signal is used for indicating that the oscillation control signal output by the oscillation control unit is switched from the first control signal to an inverted second control signal, the first control signal is a high-level signal, and the second control signal is a low-level signal;

And determining to output a second turnover signal to the oscillation control unit according to a comparison result that the power supply voltage is greater than or equal to the first turnover voltage, wherein the second turnover signal is used for indicating that the oscillation control signal output by the oscillation control unit is switched from the second control signal to the inverted first control signal.

5. The capacitance detection circuit according to claim 1, further comprising: the data processing unit is used for processing the counted value counted in the sampling time to obtain a counted value variation;

the counting value change amount is a difference value between a first counting value and a second counting value counted by the counting unit in the same sampling time, wherein the first counting value is the number of oscillation periods acquired during the period that a user touches the capacitor to be detected, and the second counting value is the number of oscillation periods acquired during the period that the user does not touch the capacitor to be detected.

6. The capacitance sensing circuit of claim 5 wherein the count value change is related to a charge current value provided by the first current source and the first charge time, comprising:

calculating to obtain a first count value or a second count value based on the ratio of the sampling time to the oscillation period;

the magnitude of the oscillation period is inversely related to a first product, which is a product of a charging current value provided by the first current source and a first charging time.

7. The capacitance detection circuit according to claim 5, wherein the data processing unit further comprises:

determining a detection result of the capacitance change to be detected based on the count value change;

and determining whether the capacitance change quantity to be detected corresponds to the touch operation result of the user according to the comparison result between the count value change quantity and the preset change quantity threshold value.

8. The capacitance detection circuit according to claim 1, wherein the flip-flop is a schmitt trigger.

9. A capacitance detection method, characterized by being applied to an apparatus or device including the capacitance detection circuit of any one of claims 1 to 8, the method comprising:

generating a mirror current source based on a power supply, wherein the mirror current source at least comprises a first current source and a second current source, and the first current source provides a charging compensation current for the second current source;

the method comprises the steps of controlling a first charging time of a first current source to a capacitor to be tested to be smaller than or equal to a second charging time of a second current source to the capacitor to be tested, wherein the first charging time is identical to the initial time of the second charging time;

and detecting the capacitance change of the capacitor to be detected, and counting the count value in the sampling time.

10. The method according to claim 9, wherein the method further comprises:

And determining a detection result of the capacitor to be detected according to the count value change quantity, wherein the count value change quantity is the change degree of the count value caused by the touch of a user, and the count value change quantity is related to the charging current value provided by the first current source and the length of the first charging time.

11. The method of claim 9, wherein the count value change is a difference between a first count value and a second count value counted by the data processing unit in the same sampling time, wherein the first count value is a number of oscillation periods acquired during a period when the user touches the capacitor to be measured, and the second count value is a number of oscillation periods acquired during a period when the user does not touch the capacitor to be measured.

12. The method of claim 11, wherein the count value change is related to a charge current value provided by the first current source and the first charge time, comprising:

13. The method of claim 10, wherein determining the detection result of the capacitor to be detected based on the count value variation comprises:

14. A capacitance detecting device, characterized by comprising the capacitance detecting circuit according to any one of claims 1 to 8, wherein the capacitance detecting circuit is configured to perform the capacitance detecting method according to any one of claims 9 to 13.

15. A capacitance detecting apparatus, comprising:

the capacitance detection circuit of any one of claims 1 to 7, and,

the register is used for storing various instructions or configuration information, and the instructions are used for controlling the sampling time of the capacitance detection circuit to the oscillation period number;

a processor, being one of the processors of an integrated circuit, for performing the capacitance detection method of any of claims 8-11.