CN117728780A

CN117728780A - Power amplifier and radio frequency front end module

Info

Publication number: CN117728780A
Application number: CN202311855219.5A
Authority: CN
Inventors: 雷传球; 林少鑫; 张滔; 陈炉星; 曹原; 倪建兴
Original assignee: Radrock Shenzhen Technology Co Ltd
Current assignee: Radrock Shenzhen Technology Co Ltd
Priority date: 2023-12-29
Filing date: 2023-12-29
Publication date: 2024-03-19

Abstract

The application discloses a power amplifier and a radio frequency front end module. The power amplifier may include a first stage power amplifying circuit, a second stage power amplifying circuit, a choke unit, and a stabilizing unit. The power supply end of the second-stage power amplifying circuit is connected to the first power supply end, and the choke unit is connected between the power supply end of the first-stage power amplifying circuit and the first power supply end. The stabilizing unit is connected in parallel with the choke unit and comprises at least one resistor. Specifically, the stabilizing unit may be resistive, so that a part of out-of-band low-frequency signals in the radio frequency signals coupled to the first-stage power amplifying circuit via the second-stage power amplifying circuit and the subsequent stage passes through the stabilizing unit, the stabilizing unit may inhibit the out-of-band low-frequency signals, thereby reducing signal gain caused by the out-of-band low-frequency signals, and reducing signal coupling between the first-stage power amplifying circuit and the second-stage power amplifying circuit, so as to improve stability of the power amplifier during operation.

Description

Power amplifier and radio frequency front end module

Technical Field

The present application relates to the field of radio frequency technologies, and in particular, to a power amplifier and a radio frequency front end module.

Background

The existing radio frequency front end module is widely applied to the fields of wireless communication, internet of things, intelligent home and the like, wherein a power amplifier is used as a core unit of the radio frequency front end module, and the performance of the power amplifier has a larger influence on the signal output index of the radio frequency front end module.

When the power amplifier is implemented by the power amplifying circuit, a choke inductor is arranged between the power supply end of the transistor in the power amplifying circuit and the power supply, and the choke inductor can prevent the radio frequency signal output by the transistor from leaking to the power supply.

However, in the case where the power amplifying circuit is implemented using a multi-stage amplifying architecture, there is often signal coupling between the first stage power amplifying circuit and the second stage power amplifying circuit, which results in poor stability of the power amplifier.

Disclosure of Invention

The embodiment of the application provides a power amplifier and a radio frequency front-end module.

According to a first aspect of the present application, an embodiment of the present application provides a power amplifier provided with a signal input terminal, a signal output terminal, and a first power supply terminal, the power amplifier including a first stage power amplifying circuit, a second stage power amplifying circuit, a choke unit, and a stabilizing unit. The input end of the first-stage power amplifying circuit is connected with the signal input end, and the output end of the first-stage power amplifying circuit is connected with the input end of the second-stage power amplifying circuit; the output end of the second-stage power amplifying circuit is connected with the signal output end. The first end of the choke unit is connected with the power end of the first-stage power amplifying circuit, and the second end of the choke unit and the power end of the second-stage power amplifying circuit are respectively connected with the first power supply end. The stabilizing unit is connected in parallel with the choke unit and comprises at least one resistor.

The present application provides a power amplifier that may include a first stage power amplifying circuit, a second stage power amplifying circuit, a choke unit, and a stabilizing unit. The power supply end of the second-stage power amplifying circuit is connected to the first power supply end, and the choke unit is connected between the power supply end of the first-stage power amplifying circuit and the first power supply end.

The stabilizing unit is connected in parallel with the choke unit and comprises at least one resistor. For example, the stabilizing unit may be resistive, so that a portion of the out-of-band low frequency signal in the radio frequency signal coupled to the first stage power amplifying circuit via the second stage power amplifying circuit and the subsequent stage passes through the stabilizing unit, the stabilizing unit may suppress the out-of-band low frequency signal, thereby reducing signal gain caused by the out-of-band low frequency signal, and reducing signal coupling between the first stage power amplifying circuit and the second stage power amplifying circuit, so as to improve stability of the power amplifier during operation. When the output terminal and the power supply terminal of the second-stage power amplifying circuit share the same signal port, the stabilizing unit and the choke unit can also suppress the output signal fed back from the second-stage power amplifying circuit to the first-stage power amplifying circuit to avoid oscillation of the power amplifier 100.

According to a second aspect of the present application, embodiments of the present application further provide a power amplifier provided with a signal input terminal, a signal output terminal, and a power supply terminal, the power amplifier including a power amplifying circuit, a choke unit, and a stabilizing unit. The input end of the power amplifying circuit is connected with the signal input end, and the output end of the power amplifying circuit is connected with the signal output end. The first end of the choke unit is connected with the power supply end of the power amplifying circuit, and the second end of the choke unit is connected with the power supply end. The stabilizing unit is connected in parallel with the choke unit and comprises at least one resistor.

The application also provides a power amplifier which can comprise a power amplifying circuit, a choke unit and a stabilizing unit, wherein a first end of the choke unit is connected to a power supply end of the power amplifying circuit, and a second end of the choke unit is connected to a power supply end. The stabilizing unit is connected in parallel with the choke unit and comprises at least one resistor.

Since the two sides of the choke unit are connected with the stabilizing unit in parallel, the stabilizing unit can be resistive, and the quality factor (i.e., Q value) of the choke unit is reduced. Therefore, when the parasitic capacitance of the transistor in the power amplification circuit is coupled with the choke unit, the Q value of the choke unit is reduced, so that the amplification gain of the power amplifier can be reduced, the risk of oscillation of the power amplifier is further reduced, and the stability of the power amplifier in operation is improved.

According to a third aspect of the present application, an embodiment of the present application further provides a radio frequency front end module, where the radio frequency front end module includes a substrate and the above power amplifier. The power amplifier is arranged on the substrate.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a first structure of a power amplifier according to an embodiment of the present application.

Fig. 2 is a schematic diagram of a structure of a stabilizing unit in the power amplifier shown in fig. 1.

Fig. 3 is a schematic diagram of another structure of the stabilizing unit in the power amplifier shown in fig. 1.

Fig. 4 is a schematic diagram of a second configuration of the power amplifier shown in fig. 1.

Fig. 5 is a schematic diagram of a third configuration of the power amplifier shown in fig. 1.

Fig. 6 is a schematic diagram of the first balun, the third-stage power amplifying circuit and the second balun in the power amplifier shown in fig. 5.

Fig. 7 is a fourth structural schematic diagram of the power amplifier shown in fig. 1.

Fig. 8 is a fifth structural schematic diagram of the power amplifier shown in fig. 1.

Fig. 9 is a sixth structural schematic diagram of the power amplifier shown in fig. 1.

Fig. 10 is a seventh structural schematic diagram of the power amplifier shown in fig. 1.

Fig. 11 is an eighth structural schematic diagram of the power amplifier shown in fig. 1.

Fig. 12 is a ninth structural schematic diagram of the power amplifier shown in fig. 1.

Fig. 13 is a schematic structural diagram of a power amplifier according to another embodiment of the present application.

Fig. 14 is a schematic diagram of another configuration of the power amplifier shown in fig. 13.

Fig. 15 is a schematic structural diagram of a rf front-end module according to an embodiment of the present disclosure.

Detailed Description

In order to enable those skilled in the art to better understand the present application, the following description will make clear and complete descriptions of the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

The embodiment of the application provides a power amplifier 100, and the power amplifier 100 is a device for improving the output power of a radio frequency signal. The power amplifier 100 in this embodiment is provided with a signal input end 12, a signal output end 14 and a first power supply end 16, wherein the signal input end 12 is used for inputting a radio frequency signal to be power amplified, and the signal output end 14 is used for outputting the radio frequency signal after power amplification by the power amplifier 100. The first power supply terminal 16 is used to supply power to elements or chips in the power amplifier 100, and in particular, the first power supply terminal 16 may provide a first power supply voltage (Volt Current Condenser, VCC 1). For example, VCC1 may be 3V, 5V, 8V, or the like, and the present embodiment is not particularly limited.

Referring to fig. 1, a power amplifier 100 may include a first stage power amplifying circuit 10, a second stage power amplifying circuit 20, a choke unit 30, and a stabilizing unit 40. The input terminal 101 of the first stage power amplifying circuit 10 is connected to the signal input terminal 12, the output terminal 103 of the first stage power amplifying circuit 10 is connected to the input terminal 201 of the second stage power amplifying circuit 20, and the output terminal 203 of the second stage power amplifying circuit 20 is connected to the signal output terminal 14.

Therefore, the first-stage power amplifying circuit 10 and the second-stage power amplifying circuit 20 in the present embodiment form a two-stage amplifying circuit to raise the power amplification upper limit of the radio frequency signal. Of course, more power amplifying circuits, for example, a third stage power amplifying circuit, a fourth stage power amplifying circuit, etc., may be cascaded between the output terminal 203 of the second stage power amplifying circuit 20 and the signal output terminal 14, and the embodiment is not particularly limited.

The first terminal 301 of the choke unit 30 is connected to the power supply terminal 105 of the first stage power amplifying circuit 10, and the second terminal 303 of the choke unit 30 and the power supply terminal 205 of the second stage power amplifying circuit 20 are connected to the first power supply terminal 16, respectively. Therefore, the power supply terminal 105 of the first-stage power amplifying circuit 10 and the power supply terminal 205 of the second-stage power amplifying circuit 20 in this embodiment are both connected to the same power supply terminal, i.e., the first power supply terminal 16. The second stage power amplifying circuit 20 and other circuits are electromagnetically coupled to the first stage power amplifying circuit 10, so that an out-of-band low frequency signal is generated in the first stage power amplifying circuit 10, and if the out-of-band low frequency signal is amplified by the first stage power amplifying circuit and the second stage power amplifying circuit according to normal gain, the output of the power amplifier 100 will be interfered, and the stability of the power amplifier 100 is reduced.

The stabilizing unit 40 and the choke unit 30 are connected in parallel, the stabilizing unit 40 comprising at least one resistor 410. Illustratively, the stabilization unit 40 may be implemented with a purely resistive circuit, such that the stabilization unit 40 is resistive. When a part of the out-of-band low frequency signal of the radio frequency signal coupled to the first stage power amplifying circuit 10 via the second stage power amplifying circuit 20 and the subsequent stage circuit passes through the stabilizing unit 40, the stabilizing unit 40 can suppress the out-of-band low frequency signal, thereby reducing the signal gain of the out-of-band low frequency signal, and reducing the signal coupling between the first stage power amplifying circuit 10 and the second stage power amplifying circuit 20, so as to improve the stability of the power amplifier 100 during operation.

The various blocks in the power amplifier 100 are described in detail below.

In the present embodiment, the choke unit 30 is used to suppress leakage of the radio frequency signal at the first stage power amplifying circuit 10 to the first power supply terminal 16, so as to ensure normal operation of the power amplifier 100. In addition, the choke unit 30 can also prevent the ac component (i.e., the interference signal) in the first power supply voltage VCC1 output from the first power supply terminal 16 from entering the first-stage power amplifying circuit 10.

In the embodiment shown in fig. 1, the choke unit 30 may comprise a first inductance 310, the first inductance 310 being connected between the power supply terminal 105 and the first power supply terminal 16 of the first stage power amplifying circuit 10. Specifically, the first inductor 310 may be a chip inductor, a plug-in inductor, or the like, and the first inductor 310 may also be a section of metal wire wound on a substrate or a chip, and the metal wire may be equivalently the first inductor 310.

In the present embodiment, the stabilizing unit 40 and the choke unit 30 are connected in parallel. Specifically, the first end 401 of the stabilizing unit 40 is connected to the first end 301 of the choke unit 30, the second end 403 of the stabilizing unit 40 is connected to the second end 303 of the choke unit 30, and the stabilizing unit 40 is configured to suppress a portion of the out-of-band low frequency signal in the radio frequency signal of the second stage power amplifying circuit 20 and the radio frequency signal of the subsequent stage coupled to the first stage power amplifying circuit 10, so as to reduce the out-of-band low frequency gain of the radio frequency signal, and improve the stability of the power amplifier 100 during operation.

In some possible embodiments, the output terminal 203 of the second stage power amplifying circuit 20 and the power supply terminal 205 of the second stage power amplifying circuit 20 may share the same signal port. In this case, the output terminal 203 of the second stage power amplifying circuit 20 is further connected to the first power supply terminal 16, so that the output signal of the second stage power amplifying circuit 20 is fed back to the first stage power amplifying circuit 10. At this time, a part of the output signal of the second stage power amplifying circuit 20 is fed back to the first stage power amplifying circuit 10 through the choke unit 30 and the stabilizing unit 40, wherein the choke unit 30 presents a higher impedance to the in-band signal, so that the signal fed back from the second stage power amplifying circuit 20 to the first stage power amplifying circuit 10 can be reduced, and even if a small amount of in-band signal is fed back to the first stage power amplifying circuit 10, the gain of the feedback signal can be reduced through the choke unit 30 and the stabilizing unit 40, and the interference to the output signal of the power amplifier 100 can be reduced, thereby improving the stability of the power amplifier 100.

It will be understood herein that the "out-of-band low frequency signal" refers to a low frequency signal outside the operating frequency band of the power amplifier 100, mainly generated by electromagnetic coupling, and the "in-band signal" refers to a signal within the operating frequency band of the power amplifier 100, including a fundamental wave signal fed back to the first stage power amplifying circuit 10 via the second stage power amplifying circuit 20.

As an embodiment, the stabilizing unit 40 may include a resistor 410, where the resistor 410 is connected in parallel with the first inductor 310.

As another embodiment, the stabilizing unit 40 may include M resistors 410 and M switches 430 in one-to-one correspondence with the M resistors 410, wherein M is an integer greater than 1. Specifically, the resistances of the M resistors 410 may be the same or different from each other. Switch 430 may be a transistor switch. Therefore, in the present embodiment, the switch 430 corresponding to the resistor 410 is opened or closed to control whether the resistor 410 is connected to the resistor network corresponding to the stabilizing unit 40, so as to adjust the equivalent resistance value of the stabilizing unit 40.

Referring to fig. 2, m resistors 410 are connected in series, and a switch 430 is connected in parallel with the corresponding resistor 410. One end of the M resistors 410 formed in series is the first end 401 of the stabilizing unit 40, and the other end of the M resistors 410 formed in series is the second end 403 of the stabilizing unit 40. Referring to fig. 3, m resistors 410 are connected in parallel, and a switch 430 is connected in series in a branch where the corresponding resistor 410 is located. One end of the M resistors 410 formed in parallel with each other is the first end 401 of the stabilizing unit 40, and the other end of the M resistors 410 formed in parallel with each other is the second end 403 of the stabilizing unit 40. Of course, other connection manners may be adopted for the M resistors 410 and the M switches 430, which are not specifically limited in this embodiment.

In the embodiment shown in fig. 2 and 3, the power amplifier 100 may further include a control unit 50, where the control unit 50 is connected to the M switches 430, and the control unit 50 is configured to adjust the equivalent resistance value of the stabilizing unit 40 based on the inductance value of the first inductor 310 and the signal frequency of the radio frequency signal to be suppressed. Specifically, the inductance value of the first inductor 310 and the equivalent resistance value of the stabilizing unit 40 satisfy the following formulas.

Where f is the signal frequency of the radio frequency signal to be suppressed, R is the equivalent resistance value of the stabilizing unit 40, and L is the inductance value of the first inductor 310. Therefore, in the case where L is a fixed value, f and R are in positive correlation.

Specifically, the control unit 50 may determine the signal frequency of the radio frequency signal to be suppressed according to the operating frequency band of the power amplifier 100, and control the on/off states of the M switches 430 to adjust the equivalent resistance value of the stabilizing unit 40. For example, the operating frequency band of the power amplifier 100 may be an N77 frequency band, that is, the frequency band of the in-band signal is 3.3GHz to 4.2GHz, and the corresponding out-of-band low frequency signal is a radio frequency signal less than 3.3GHz, that is, the radio frequency signal to be suppressed may include a signal having a frequency less than 3.3 GHz. For example, the signal frequency of the radio frequency signal to be suppressed may be 2.5GHz, 3GHz, or the like.

Of course, the radio frequency signal frequency to be suppressed may also include the frequency of the in-band signal. Also taking the N77 frequency band as an example of the operating frequency band of the power amplifier 100, the radio frequency signal to be suppressed may include a signal having a frequency greater than or equal to 3.3GHz and less than 4.2 GHz. For example, the signal frequency of the radio frequency signal to be suppressed may be 3.5GHz, 4GHz, or the like. Therefore, the present embodiment can attenuate the positive feedback of the in-band signal between the first stage power amplifying circuit 10 and the second stage power amplifying circuit 20 by suppressing the in-band signal, so as to improve the stability of the power amplifier 100 in operation.

It will be appreciated here that in the case of signal suppression by the choke unit 30 and the stabilizing unit 40, a "wideband" suppression is produced, i.e. a suppression effect is produced for signals in the vicinity of the frequency of the radio frequency signal to be suppressed. When the frequency of the out-of-band low frequency signal generated due to signal coupling is relatively close to that of the in-band signal, the choke unit 30 and the stabilization unit 40 can suppress both the out-of-band low frequency signal and the in-band signal.

Specifically, the signal frequency of the rf signal to be suppressed may also be directly stored in the memory of the electronic device in which the power amplifier 100 is located, and the control unit 50 may determine the signal frequency of the rf signal to be suppressed by directly reading the data in the memory.

As an embodiment, when determining the signal frequency of the radio frequency signal to be suppressed, the control unit 50 may determine the open/close states of the M switches 430 based on the pre-stored switch state mapping relationship, and further control the M switches 430 to operate based on the open/close states of the M switches 430, so as to adjust the equivalent resistance value of the stabilizing unit 40. Wherein, the pre-stored switch state mapping relationship characterizes the corresponding relationship between different signal frequencies and different opening and closing states of the M switches 430. Specifically, the switching state mapping relationship may be a mapping table, which may be summarized by a developer based on a large amount of test data of the power amplifier 100, which is not limited in detail in this embodiment.

Therefore, in the case that the stabilizing unit 40 includes M resistors 410, the control unit 50 can dynamically adjust the equivalent resistance value of the stabilizing unit 40, so that the stabilizing unit 40 can suppress a part of out-of-band low-frequency signals in the radio-frequency signals when the power amplifier 100 is used for amplifying radio-frequency signals in different frequency bands, so that the application scenarios of the power amplifier 100 are more diverse.

In the present embodiment, the first stage power amplifying circuit 10 and the second stage power amplifying circuit 20 are used to sequentially power amplify the radio frequency signal inputted to the power amplifier 100. Referring to fig. 4, the first stage power amplifying circuit 10 and the second stage power amplifying circuit 20 are single-ended power amplifying circuits, respectively. In the embodiment shown in fig. 4, the output terminal 103 of the first stage power amplifying circuit 10 and the power supply terminal 105 of the first stage power amplifying circuit 10 share the same signal port. Therefore, the output terminal 103 of the first stage power amplifying circuit 10 in this embodiment is not only used for outputting the radio frequency signal amplified by the first stage power amplifying circuit 10, but also used for inputting the first power supply voltage VCC1 provided by the first power supply terminal 16, so as to realize multiplexing of the signal ports.

Similarly, the output terminal 203 of the second stage power amplifying circuit 20 and the power supply terminal 205 of the second stage power amplifying circuit 20 share the same signal port. Therefore, the output terminal 203 of the second-stage power amplifying circuit 20 in this embodiment is not only used for outputting the radio frequency signal amplified by the second-stage power amplifying circuit 20, but also used for inputting the first supply voltage VCC1 provided by the first supply terminal 16, so as to realize multiplexing of the signal ports.

Specifically, the first stage power amplifying circuit 10 may include a first transistor 120, and the second stage power amplifying circuit 20 may include a second transistor 210. The control terminal 1201 of the first transistor 120 is connected to the input terminal 101 of the first stage power amplifying circuit 10, the first terminal 1203 of the first transistor 120 is connected to the output terminal 103 of the first stage power amplifying circuit 10, and the second terminal 1205 of the first transistor 120 is grounded. The control terminal 2101 of the second transistor 210 is connected to the input terminal 201 of the second stage power amplifying circuit 20, the first terminal 2103 of the second transistor 210 is connected to the output terminal 203 of the second stage power amplifying circuit 20, and the second terminal 2105 of the second transistor 210 is grounded.

As an embodiment, the first transistor 120 and the second transistor 210 may be implemented by heterojunction bipolar transistors (Heterojunction Bipolar Transistor, HBT transistors), respectively. Wherein the control terminal 1201 of the first transistor 120 and the control terminal 2101 of the second transistor 210 are the base of the HBT-transistor, the first terminal 1203 of the first transistor 120 and the first terminal 2103 of the second transistor 210 are the collector of the HBT-transistor, and the second terminal 1205 of the first transistor 120 and the second terminal 2105 of the second transistor 210 are the emitter of the HBT-transistor.

As other embodiments, the first transistor 120 and the second transistor 210 may be implemented by bipolar junction transistors (Bipolar Junction Transistor, BJT transistors), respectively. Alternatively, the first transistor 120 and the second transistor 210 may be respectively formed of Metal-Oxide-Semiconductor Field-Effect Transistor (MOS transistors), which is not particularly limited in this embodiment.

In the embodiment shown in fig. 4, the power amplifier 100 may further include a first blocking capacitor 121 and a second blocking capacitor 212. The first blocking capacitor 121 is connected between the signal input terminal 12 and the control terminal 1201 of the first transistor 120, and is used for preventing the dc bias signal applied to the control terminal 1201 of the first transistor 120 from flowing to the signal input terminal 12, so as to ensure that the first transistor 120 can operate smoothly. The second blocking capacitor 212 is connected between the first terminal 1203 of the first transistor 120 and the control terminal 2101 of the second transistor 210, and is used for preventing a direct current bias signal applied at the control terminal 2101 of the second transistor 210 from flowing to the first transistor 120, so as to ensure that the second transistor 210 can work smoothly. Specifically, the first blocking capacitor 121 and the second blocking capacitor 212 may be patch capacitors, plug capacitors, or the like, respectively.

In the embodiment shown in fig. 4, the power amplifier 100 may also include a choke inductance 214. The choke inductor 214 is connected between the first end 2103 of the second transistor 210 and the first power supply end 16, and is used for preventing the radio frequency signal output by the second transistor 210 from leaking to the first power supply end 16, so as to ensure the normal operation of the power amplifier 100. In addition, the choke inductor 214 may also prevent the ac component (i.e., the interference signal) in the first supply voltage VCC1 output by the first supply terminal 16 from entering the second stage power amplifying circuit 20. Specifically, the choke inductor 214 may be a chip inductor, a plug-in inductor, or the like, and the choke inductor 214 may also be a section of metal wire wound on a substrate or a chip, and the metal wire may be equivalently the choke inductor 214.

In the embodiment shown in fig. 4, the power amplifier 100 may further include a first bypass capacitor 416, where one end of the first bypass capacitor 416 is connected to the first power supply terminal 16 and the other end is grounded. The first bypass capacitor 416 may filter out noise signals in the first supply voltage VCC1 to ensure the power supply safety of the power amplifier 100. Specifically, the first bypass capacitor 416 may be a patch capacitor, a plug-in capacitor, or the like.

In some possible embodiments, the power amplifier 100 may further include a first isolation unit 312 and a second isolation unit 314. Wherein, the first end 3121 of the first isolation unit 312 is connected to the second end 303 of the choke unit 30, and the second end 3123 of the first isolation unit 312 is connected to the first power supply end 16. The first end 3141 of the second isolation unit 314 is connected to the power supply end 205 of the second stage power amplifying circuit 20, and the second end 3143 of the second isolation unit 314 is connected to the first power supply end 16. The first isolation unit 312 and the second isolation unit 314 are used for isolating radio frequency signals between the first stage power amplifying circuit 10 and the second stage power amplifying circuit 20 to improve the operation stability of the power amplifier 100. Specifically, in the embodiment shown in fig. 4, the first isolation unit 312 and the second isolation unit 314 may be implemented by using inductors, for example, a patch inductor, a plug-in inductor, or an inductor formed by metal wires wound on a substrate, which are equivalent.

In some possible embodiments, the power amplifier 100 may further include a first decoupling unit 412 and a second decoupling unit 414. One end of the first decoupling unit 412 is connected to the first end of the first isolation unit 312, and the other end is grounded. One end of the second decoupling unit 414 is connected to the first end of the second isolation unit 314, and the other end is grounded. Specifically, in the embodiment shown in fig. 4, the first decoupling unit 412 and the second decoupling unit 414 may be implemented using capacitors, for example, a patch capacitor, a plug-in capacitor, or the like, respectively.

It will be understood herein that the output signal (i.e., the in-band fundamental wave signal) of the second stage power amplifying circuit 20, if fed back to the first stage power amplifying circuit 10, will form positive feedback amplification of the signal, thereby causing the operational oscillation of the power amplifier 100. Therefore, in order to solve the above-mentioned problems, the first decoupling unit 412 and the second decoupling unit 414 are provided to filter most of the output signals coupled to the first stage power amplifying circuit 10, and the unfiltered signals reach the branches where the choke unit 30 and the stabilizing unit 40 are located, and the choke unit 30 and the stabilizing unit 40 are used to suppress the signals, so as to avoid the oscillation of the power amplifier 100, and improve the working stability of the power amplifier 100.

In some possible embodiments, referring to fig. 5, the power amplifier 100 may further include a first balun 60, a third-stage power amplification circuit 70, and a second balun 80. The second stage power amplifying circuit 20 is a single-ended power amplifying circuit, and the third stage power amplifying circuit 70 is a differential power amplifying circuit. The output terminal 203 of the second stage power amplifying circuit 20 is connected to the signal output terminal 14 through the first balun 60, the third stage power amplifying circuit 70 and the second balun 80 in sequence. Therefore, in the present embodiment, three-stage amplification of the radio frequency signal is achieved by providing the first balun 60, the third-stage power amplification circuit 70, and the second balun 80, and the power amplification gain of the power amplifier 100 is further improved.

Referring to fig. 6, the first balun 60 may include a first primary side 610 and a first secondary side 630 coupled together, wherein a first end 6101 of the first primary side 610 is connected to the output terminal 203 of the second stage power amplifying circuit 20, and a second end 6103 of the first primary side 610 is grounded. The first secondary side 630 is connected between the first input 701 and the second input 703 of the third stage power amplifying circuit 70. Therefore, the first balun 60 in the present embodiment adopts a single-ended to differential architecture, which can convert a radio frequency signal outputted from the output end 203 of the second-stage power amplifying circuit 20 into a pair of differential signals. Specifically, the first balun 60 may be implemented by a special balun chip, and the first primary side 610 and the first secondary side 630 included in the first balun 60 may also be formed by metal wires wound on a substrate, which is not limited to a specific implementation manner of the first balun 60.

In the embodiment shown in fig. 6, the third stage power amplifying circuit 70 may include a third transistor 720 and a fourth transistor 740. The control terminal 7201 of the third transistor 720 is connected to the first input terminal 701 of the third stage power amplifying circuit 70, the first terminal 7203 of the third transistor 720 is connected to the first output terminal 705 of the third stage power amplifying circuit 70, and the second terminal 7205 of the third transistor 720 is grounded. The control terminal 7401 of the fourth transistor 740 is connected to the second input terminal 703 of the third stage power amplifying circuit 70, the first terminal 7403 of the fourth transistor 740 is connected to the second output terminal 707 of the third stage power amplifying circuit 70, and the second terminal 7405 of the fourth transistor 740 is grounded.

As an embodiment, the third transistor 720 and the fourth transistor 740 may be implemented by heterojunction bipolar transistors (Heterojunction Bipolar Transistor, HBT transistors), respectively. The control terminal 7201 of the third transistor 720 and the control terminal 7401 of the fourth transistor 740 are HBT transistor base stages, the first terminal 7203 of the third transistor 720 and the first terminal 7403 of the fourth transistor 740 are HBT transistor collector stages, and the second terminal 7205 of the third transistor 720 and the second terminal 7405 of the fourth transistor 740 are HBT transistor emitter stages.

As other embodiments, the third transistor 720 and the fourth transistor 740 may be implemented by bipolar junction transistors (Bipolar Junction Transistor, BJT transistors), respectively. Alternatively, the third transistor 720 and the fourth transistor 740 may be Metal-Oxide-Semiconductor Field-Effect Transistor (MOS transistors), respectively, which is not particularly limited in this embodiment.

Alternatively, the third transistor 720 and the fourth transistor 740 may be two identical model transistors. For example, NPN HBT tubes more suitable for high power circuits are used. The third transistor 720 and the fourth transistor 740 may also be two transistors of opposite types. For example, one of them is an NPN type HBT tube, and the other is a PNP type HBT tube.

The third stage power amplification circuit 70 in this embodiment is implemented by employing a differential power amplification circuit that, in one aspect, provides a higher power output than a single-ended power amplification circuit. On the other hand, the operation efficiency and the anti-interference capability of the power amplifier 100 may be improved to improve the stability of the radio frequency signal output from the power amplifier 100.

In the embodiment shown in fig. 6, the second balun 80 may include a second primary side 810 and a second secondary side 830 coupled together, where the second primary side 810 is connected between the first output 705 and the second output 707 of the third stage power amplifying circuit 70, and the second secondary side 830 has one end connected to the signal output 14 and the other end grounded. Therefore, the second balun 80 in the present embodiment adopts a differential-to-single-ended architecture, which can convert a pair of differential signals output by the third-stage power amplifying circuit 70 into a radio frequency signal. Specifically, the second balun 80 may be implemented by a special balun chip, and the second primary side 810 and the second secondary side 830 included in the second balun 80 may also be formed by metal wires wound on the substrate, which are equivalent, and the specific implementation manner of the second balun 80 is not limited in this embodiment.

In the embodiment shown in fig. 6, the power amplifier 100 may also be provided with a second supply terminal 18. The second power supply terminal 18 is used for supplying power to the components or chips in the power amplifier 100, wherein the second power supply terminal 18 and the first power supply terminal 16 are two different power supply ports. Specifically, the second supply terminal 18 may provide a second supply voltage (Volt Current Condenser, VCC 2). For example, VCC2 may be 3V, 5V, 8V, or the like, and the present embodiment is not particularly limited.

In particular, the second primary 810 can include a first coil 8120 and a second coil 8140. The first coil 8120 and the second coil 8140 are connected in series and then between the first terminal 7203 of the third transistor 720 and the first terminal 7403 of the fourth transistor 740. Thus, the first coil 8120 and the second coil 8140 in this embodiment can be understood as two parts of the second primary side 810, the first coil 8120 and the second coil 8140 being connected in series to form the second primary side 810.

The common terminal of the first coil 8120 and the second coil 8140 is connected to the second power supply terminal 18. Accordingly, the second power supply voltage VCC2 outputted from the second power supply terminal 18 flows to the first terminal 7203 of the third transistor 720 through the first coil 8120 to supply power to the third transistor 720. The first coil 8120 may perform a choke function to prevent an ac component (i.e., an interference signal) in the second power supply voltage VCC2 outputted from the second power supply terminal 18 from entering the third transistor 720, so as to ensure the normal operation of the third transistor 720.

Similarly, the second power supply voltage VCC2 output from the second power supply terminal 18 flows to the first terminal 7403 of the fourth transistor 740 through the second coil 8140 to supply power to the fourth transistor 740. The second coil 8140 may also function as a choke, preventing the ac component (i.e., the interference signal) in the second power supply voltage VCC2 output by the second power supply terminal 18 from entering the fourth transistor 740, so as to ensure the normal operation of the fourth transistor 740.

In summary, the first coil 8120 may be used as a choke inductance between the third transistor 720 and the second power supply terminal 18, and the second coil 8140 may be used as a choke inductance between the fourth transistor 740 and the second power supply terminal 18, so as to implement structural multiplexing of the second primary side 810, simplify a hardware structure of the power amplifier 100, and save a hardware cost of the power amplifier 100.

In some possible embodiments, the power amplifier 100 may further include a third blocking capacitance 650 and a fourth blocking capacitance 670. One end of the first secondary side 630 is connected to the control end 7201 of the third transistor 720 through the third blocking capacitor 650, and the third blocking capacitor 650 can prevent the dc bias signal applied to the control end 7201 of the third transistor 720 from flowing to the first secondary side 630, so as to ensure that the third transistor 720 can operate smoothly. The other end of the first secondary side 630 is connected to the control end 7401 of the fourth transistor 740 through a fourth blocking capacitor 670, and the fourth blocking capacitor 670 can prevent the dc bias signal applied to the control end 7201 of the fourth transistor 740 from flowing to the first secondary side 630, so as to ensure that the fourth transistor 740 can operate smoothly. In addition, the third blocking capacitor 650 and the fourth blocking capacitor 670 may also participate in impedance matching together with the first balun 60 to improve the transmission efficiency of the radio frequency signal. Specifically, the third blocking capacitor 650 and the fourth blocking capacitor 670 may be patch capacitors, plug capacitors, or the like, respectively.

In some possible embodiments, the power amplifier 100 may further include a second bypass capacitor 850, wherein one end of the second bypass capacitor 850 is connected to the second power supply terminal 18, and the other end is grounded. The second bypass capacitor 850 can filter out the noise signal in the second supply voltage VCC2 to ensure the power supply safety of the power amplifier 100. In particular, the second bypass capacitance 850 may be a patch capacitance, a plug-in capacitance, or the like.

In some possible embodiments, referring to fig. 7, in the case that the output terminal 203 of the second stage power amplifying circuit 20 and the power source terminal 205 of the second stage power amplifying circuit 20 share the same signal port, the second terminal 6103 of the first primary side 610 is further connected to the first power supply terminal 16. Therefore, the first primary side 610 in this embodiment may also be used as a choke inductance between the second transistor 210 and the first power supply terminal 16, that is, the first primary side 610 may replace the choke inductance 214 in fig. 4, so as to implement structural multiplexing of the first primary side 610, simplify the hardware structure of the power amplifier 100, and save the hardware cost of the power amplifier 100.

Of course, in other possible embodiments, implementation of providing additional choke inductance may be used, i.e. the circuit configuration in the embodiment shown in fig. 4. Specifically, the power supply terminal 16 is connected to the first terminal 2103 of the second transistor 210 through the second isolation unit 314 and the choke inductor 214 in sequence. In this case, the developer can adjust the inductance value of the choke inductor 214 more flexibly, so that the hardware parameters of the power amplifier 100 are more flexible in debugging.

In the embodiment shown in fig. 7, the power amplifier 100 may further include a first capacitor 690, where one end of the first capacitor 690 is connected to the second end 6103 of the first primary side 610, and the other end is grounded. Since the first power supply voltage VCC1 outputted from the first power supply terminal 16 flows to the first terminal 2103 of the second transistor 210 through the first primary side 610 to supply power to the second transistor 210. Therefore, to avoid the first power supply voltage VCC1 from shorting to the ground at the second end 6103 of the first primary side 610, the present embodiment can perform a "blocking" function by providing the first capacitor 690 between the second end 6103 of the first primary side 610 and the ground, so as to ensure the smooth operation of the second transistor 210. In particular, the first capacitance 690 may be a patch capacitance, a plug capacitance, or the like. In addition, the first capacitor 690 may also participate in impedance matching with the first balun 60 to improve the transmission efficiency of the radio frequency signal.

In some possible embodiments, referring to fig. 8, the first stage power amplifying circuit 10, the second stage power amplifying circuit 20, the choke unit 30, the stabilizing unit 40, the first balun 60, the third stage power amplifying circuit 70, and the second balun 80 form one power amplifying module 19, wherein the number of power amplifying modules 19 is two.

Specifically, the input terminals 101 of the first stage power amplifying circuits 10 in the two power amplifying modules 19 are respectively connected to the signal input terminals 12. The secondary sides 830 of the second balun 80 in the two power amplification modules 19 are connected in series to form an output combining circuit 8320, one end of the output combining circuit 8320 is connected to the signal output end 14, and the other end is grounded. It will be understood herein that the first power supply terminal 16 in fig. 8 supplies power to the first stage power amplifying circuit 10 and the second stage power amplifying circuit 20 of the two power amplifying modules 19, respectively, and the second power supply terminal 18 supplies power to the third stage power amplifying circuit 70 of the two power amplifying modules 19, respectively. Therefore, the power amplifier 100 shown in fig. 8 adopts a circuit structure of two-way differential amplification, so that the maximum output power and the working efficiency of the power amplifier 100 can be further improved, and the power amplifier can be applied to an application scenario with higher transmission power, such as a satellite communication scenario.

In other possible embodiments, referring to fig. 9, the power amplifier 100 may further include a transformer 45, and the output terminal 203 of the second stage power amplifying circuit 20 is connected to the signal output terminal 14 through the transformer 45. Therefore, the transformer 45 in this embodiment can play a role of matching output impedance, so as to improve the transmission efficiency of the radio frequency signal.

Referring to fig. 10, the transformer 45 may include a third primary side 452 and a third secondary side 454 coupled together, wherein a first end 4521 of the third primary side 452 is connected to the output terminal 203 of the second stage power amplifying circuit 20, and a second end 4523 of the third primary side 452 is grounded. The third secondary side 454 has one end connected to the signal output terminal 14 and the other end grounded. Specifically, the transformer 45 may be implemented by using a special chip, for example, an integrated passive device (IPD, integrated Passive Device), and the third primary side 452 and the third secondary side 454 included in the transformer 45 may also be respectively formed by metal wires wound on a substrate, which is not limited to the specific implementation manner of the transformer 45 in this embodiment.

In some possible embodiments, where the output terminal 203 of the second stage power amplifying circuit 20 and the power source terminal 205 of the second stage power amplifying circuit 20 share the same signal port, the second terminal 4523 of the third primary side 452 is also connected to the first power supply terminal 16. Therefore, the third primary 452 in the present embodiment may also be used as a choke inductance between the second transistor 210 and the first power supply terminal 16, that is, the third primary 452 may replace the choke inductance 214 in fig. 4, so as to implement structural multiplexing of the third primary 452, simplify the hardware structure of the power amplifier 100, and save the hardware cost of the power amplifier 100.

In the embodiment shown in fig. 10, the power amplifier 100 may further include a second capacitor 470, where one end of the second capacitor 470 is connected to the second end 4523 of the third primary side 452, and the other end is grounded. Since the first power supply voltage VCC1 outputted from the first power supply terminal 16 flows to the first terminal 2103 of the second transistor 210 through the third primary side 452, so as to supply power to the second transistor 210. Therefore, to avoid the first power supply voltage VCC1 from shorting to ground at the second terminal 4523 of the third primary side 452, the present embodiment may perform a "blocking" function by providing the second capacitor 470 between the second terminal 4523 of the third primary side 452 and the ground terminal, so as to ensure the smooth operation of the second transistor 210. In particular, the second capacitor 470 may be a patch capacitor, a plug-in capacitor, or the like.

In some possible embodiments, referring to fig. 11, the first stage power amplifying circuit 10 may be a single-ended power amplifying circuit, the second stage power amplifying circuit 20 may be a differential power amplifying circuit, and the power amplifier 100 may further include a third balun 34 and a fourth balun 36. Wherein the third balun 34 is connected between the output 103 of the first stage power amplifying circuit 10 and the input 201 of the second stage power amplifying circuit 20, wherein the input 201 of the second stage power amplifying circuit 20 comprises a third input 2012 and a fourth input 2014. The output 203 of the second stage power amplifying circuit 20 is connected to the signal output 14 through a fourth balun 36, wherein the output 203 of the second stage power amplifying circuit 20 comprises a third output 2032 and a fourth output 2034. Therefore, the output terminal 103 of the first-stage power amplifying circuit 10 in the present embodiment is connected to the signal output terminal 14 through the third balun 34, the second-stage power amplifying circuit 20, and the fourth balun 36 in this order.

Specifically, the third balun 34 may include a fourth primary side 341 and a fourth secondary side 343 coupled to each other, where one end of the fourth primary side 341 is connected to the output terminal 103 of the first stage power amplifying circuit 10, and the other end is grounded. The fourth secondary 343 is connected between the third input 2012 and the fourth input 2014. Therefore, the third balun 34 in the present embodiment adopts a single-ended to differential architecture, which can convert a radio frequency signal outputted from the output end 103 of the first-stage power amplifying circuit 10 into a pair of differential signals. Specifically, the third balun 34 may be implemented by a special balun chip, and the fourth primary side 341 and the fourth secondary side 343 included in the third balun 34 may be respectively formed by metal wires wound on the substrate, which is not limited to the specific implementation manner of the third balun 34 in this embodiment.

In the embodiment shown in fig. 11, the second stage power amplifying circuit 20 may include a fifth transistor 230 and a sixth transistor 250. The control terminal of the fifth transistor 230 is connected to the third input terminal 2012 of the second stage power amplifying circuit 20, the first terminal of the fifth transistor 230 is connected to the third output terminal 2032 of the second stage power amplifying circuit 20, and the second terminal of the fifth transistor 230 is grounded. The control terminal of the sixth transistor 250 is connected to the fourth input terminal 2014 of the second stage power amplifying circuit 20, the first terminal of the sixth transistor 250 is connected to the fourth output terminal 2034 of the second stage power amplifying circuit 20, and the second terminal of the sixth transistor 250 is grounded.

As an embodiment, the fifth transistor 230 and the sixth transistor 250 may be implemented by heterojunction bipolar transistors (Heterojunction Bipolar Transistor, HBT transistors), respectively. As other embodiments, the fifth transistor 230 and the sixth transistor 250 may be implemented by bipolar junction transistors (Bipolar Junction Transistor, BJT transistors), respectively. Alternatively, the fifth transistor 230 and the sixth transistor 250 may be Metal-Oxide-Semiconductor Field-Effect Transistor (MOS transistors), respectively, which is not particularly limited in this embodiment.

Alternatively, the fifth transistor 230 and the sixth transistor 250 may be two identical model transistors. For example, NPN HBT tubes more suitable for high power circuits are used. The fifth transistor 230 and the sixth transistor 250 may be two transistors of opposite types. For example, one of them is an NPN type HBT tube, and the other is a PNP type HBT tube.

The second stage power amplifying circuit 20 in this embodiment is realized by employing a differential power amplifying circuit which can provide a higher power output than a single-ended power amplifying circuit in one aspect. On the other hand, the operation efficiency and the anti-interference capability of the power amplifier 100 may be improved to improve the stability of the radio frequency signal output from the power amplifier 100.

In the embodiment shown in fig. 11, the fourth balun 36 may include a fifth primary side 361 and a fifth secondary side 363 that are coupled, where the fifth primary side 361 is connected between the third output terminal 2032 and the fourth output terminal 2034, and the fifth secondary side 363 has one end connected to the signal output terminal 14 and the other end grounded. Therefore, the fourth balun 36 in the present embodiment adopts a differential-to-single-ended architecture, which can convert a pair of differential signals output by the second-stage power amplifying circuit 20 into a radio-frequency signal. Specifically, the fourth balun 36 may be implemented by a special balun chip, and the fifth primary side 361 and the fifth secondary side 363 included in the fourth balun 36 may also be respectively formed by metal wires wound on the substrate, which is not limited to the specific implementation manner of the fourth balun 36 in this embodiment.

Specifically, the fifth primary 361 may include a third coil 3612 and a fourth coil 3614. The third coil 3612 and the fourth coil 3614 are connected in series and then connected between the third output terminal 2032 and the fourth output terminal 2034. Thus, the third coil 3612 and the fourth coil 3614 in the present embodiment can be understood as two portions of the fifth primary 361, and the third coil 3612 and the fourth coil 3614 are connected in series to form the fifth primary 361.

The common terminal of the third coil 3612 and the fourth coil 3614 is connected to the first power supply terminal 16. Accordingly, the first power supply voltage VCC1 outputted from the first power supply terminal 16 flows to the first terminal of the fifth transistor 230 through the third coil 3612 to supply power to the fifth transistor 230. Therefore, the third coil 3612 in this embodiment can suppress the leakage of the radio frequency signal output by the third transistor 720 to the first power supply terminal 16 on one hand, so as to ensure the normal operation of the power amplifier 100. On the other hand, the ac component (i.e., the interference signal) in the first power supply voltage VCC1 outputted from the first power supply terminal 16 may be prevented from entering the fifth transistor 230 to ensure the normal operation of the fifth transistor 230.

Similarly, the first power supply voltage VCC1 outputted from the first power supply terminal 16 flows to the first terminal of the sixth transistor 250 through the fourth coil 3614 to supply power to the sixth transistor 250. Accordingly, the fourth coil 3614 in the present embodiment can suppress leakage of the radio frequency signal output from the sixth transistor 250 to the first power supply terminal 16 in order to ensure normal operation of the power amplifier 100. On the other hand, the ac component (i.e., the interference signal) in the first power supply voltage VCC1 outputted from the first power supply terminal 16 may be prevented from entering the sixth transistor 250 to ensure the normal operation of the sixth transistor 250.

In summary, the third coil 3612 may be used as a choke inductance between the fifth transistor 230 and the first power supply terminal 16, and the fourth coil 3614 may be used as a choke inductance between the sixth transistor 250 and the first power supply terminal 16, so as to implement the structural multiplexing of the fifth primary 361, simplify the hardware structure of the power amplifier 100, and save the hardware cost of the power amplifier 100.

In some possible embodiments, the power amplifier 100 may further include a fifth blocking capacitor 680 and a sixth blocking capacitor 690, wherein one end of the fifth secondary side 363 is connected to the control terminal of the fifth transistor 230 through the fifth blocking capacitor 680, and the fifth blocking capacitor 680 may prevent a dc bias signal applied at the control terminal of the fifth transistor 230 from flowing to the fifth secondary side 363, so as to ensure that the fifth transistor 230 can operate smoothly. The other end of the fifth secondary 363 is connected to the control terminal of the sixth transistor 250 through a sixth blocking capacitor 690, and the sixth blocking capacitor 690 can prevent the dc bias signal applied to the control terminal of the sixth transistor 250 from flowing to the fifth secondary 363, so as to ensure smooth operation of the sixth transistor 250. In addition, the fifth blocking capacitor 680 and the sixth blocking capacitor 690 may also participate in impedance matching together with the third balun 34 to improve the transmission efficiency of the radio frequency signal. Specifically, the fifth blocking capacitor 680 and the sixth blocking capacitor 690 may be patch capacitors, plug capacitors, and the like, respectively.

Referring to fig. 12, the power amplifier 100 may further include a filtering unit 49, and the output terminal 203 of the second stage power amplifying circuit 20 is connected to the signal output terminal 14 through the filtering unit 49. Wherein the filtering unit 49 may be configured to filter out harmonic signals (e.g., second order harmonic signals, third order harmonic signals, etc.) in the radio frequency signal. Specifically, the filtering unit 49 may include at least one LC harmonic suppression circuit formed by an inductor and a capacitor, and the LC harmonic suppression circuit may operate at a specified operating frequency to filter out the corresponding harmonic signal. For example, the LC harmonic rejection circuit may resonate at a frequency corresponding to the second order harmonic signal to filter out the second order harmonic signal in the radio frequency signal. Of course, the number of LC harmonic suppression circuits may be plural, and the operating frequencies of the plural LC harmonic suppression circuits may be the same or different, and the specific implementation of the filtering unit 49 is not specifically limited in this embodiment.

It is to be understood herein that, as shown in fig. 5, in the case where the power amplifier 100 includes the first balun 60, the third-stage power amplifying circuit 70, and the second balun 80, the filtering unit 49 may be connected between the output terminal of the second balun 80 and the signal output terminal 14. As shown in fig. 9, in the case where the power amplifier 100 includes the transformer 45, the filtering unit 49 may be connected between the output terminal of the transformer 45 and the signal output terminal 14. As shown in fig. 11, in case the power amplifier 100 comprises the third balun 34 and the fourth balun 36, the filtering unit 49 may be connected between the output of the fourth balun 36 and the signal output 14.

The embodiment of the application also provides a power amplifier 900, wherein the power amplifier 900 is a device for improving the output power of a radio frequency signal. The power amplifier 900 in this embodiment is provided with a signal input terminal 902, a signal output terminal 904 and a power supply terminal 906, wherein the relevant features of the signal input terminal 902, the signal output terminal 904 and the power supply terminal 906 in this embodiment can be referred to and used for the features of the signal input terminal 12, the signal output terminal 14 and the first power supply terminal 16 in the above embodiment respectively, which are not described in detail herein for the sake of saving space.

Referring to fig. 13, the power amplifier 900 may include a power amplifying circuit 910, a choke unit 920, and a stabilizing unit 930. The input terminal 9101 of the power amplifying circuit 910 is connected to the signal input terminal 902, and the output terminal 9103 of the power amplifying circuit 910 is connected to the signal output terminal 904. The first end 9201 of the choke unit 920 is connected to the power supply end 9015 of the power amplifying circuit 910, and the second end 9203 of the choke unit 920 is connected to the power supply end 906. The stabilizing unit 930 is connected in parallel with the choke unit 920, the stabilizing unit 930 comprising at least one resistor 9320.

Since the stabilizing units 930 are connected in parallel to both sides of the choke unit 920 in the present embodiment, the stabilizing units 930 can be resistive, and thus the quality factor (i.e., Q value) of the choke unit 920 is reduced. Therefore, when the parasitic capacitance of the transistor itself in the power amplifying circuit 910 is coupled to the choke unit 920, the Q value of the choke unit 920 is reduced, so as to reduce the amplification gain of the power amplifier 900, further reduce the risk of oscillation of the power amplifier 900, and improve the stability of the power amplifier 900 during operation.

In the present embodiment, the power amplifying circuit 910 is a first stage amplifying circuit of the power amplifier 900. As one implementation, the power amplification circuit 910 may be a single-ended power amplification circuit. As another implementation, the power amplification circuit 910 may be a differential power amplification circuit. Referring to fig. 14, fig. 14 shows a circuit structure of the power amplifying circuit 910 as a single-ended power amplifying circuit. The output terminal 9103 of the power amplifying circuit 910 and the power terminal 9105 share the same signal port. Therefore, the output terminal 9103 of the power amplifying circuit 910 is not only used for outputting the radio frequency signal amplified by the power amplifying circuit 910, but also used for inputting the power supply voltage provided by the power supply terminal 906, so as to realize multiplexing of the signal ports.

Specifically, the power amplifying circuit 910 may include a transistor 9120, a control terminal 9121 of the transistor 9120 is connected to an input terminal 9101 of the power amplifying circuit 910, a first terminal 9123 of the transistor 9120 is connected to an output terminal 9103 of the power amplifying circuit 910, and a second terminal 9125 of the transistor 9120 is grounded. The relevant features of the transistor 9120 may be referred to and used for the features of the first transistor 120 in the above embodiments, and are not described herein for brevity.

In the embodiment shown in fig. 14, the power amplifying circuit 910 may further include a blocking capacitor 9140, where the blocking capacitor 9140 is connected between the signal input terminal 902 and the control terminal 9121 of the transistor 9120, and is used to prevent a dc bias signal applied at the control terminal 9121 of the transistor 9120 from flowing to the signal input terminal 902, so as to ensure that the transistor 9120 can operate smoothly. Specifically, the blocking capacitor 9140 may be a patch capacitor, a plug-in capacitor, or the like.

In this embodiment, the choke unit 920 may include the first inductor 9210, and the related features of the choke unit 920 and the first inductor 9210 may refer to and use the features of the choke unit 30 and the first inductor 310 in the above embodiment, respectively, which are not described herein for brevity.

In this embodiment, the stabilizing unit 930 may include one resistor 9320, or may include a plurality of resistors 9320, and the relevant features of the stabilizing unit 930 and the resistor 9320 may refer to and use the features of the stabilizing unit 40 and the resistor 410 in the above embodiment, respectively, which are not described herein in detail for the sake of brevity.

In this embodiment, the power amplifying circuit 910 may further include a filtering unit (not shown in the drawings), where the filtering unit is connected between the output terminal 9103 of the power amplifying circuit 910 and the signal output terminal 904, and the relevant features of the filtering unit may refer to and use the features of the filtering unit 49 in the above embodiment respectively, which is not described herein for brevity.

Referring to fig. 15, the embodiment of the present application further provides a rf front-end module 950, where the rf front-end module 950 is a component that integrates two or more discrete devices such as an rf switch, a low noise amplifier, a filter, a duplexer, a power amplifier, etc. into a single module, so as to improve the integration level and the hardware performance, and reduce the size. Specifically, the rf front-end module 950 may be applied to 4G and 5G communication devices such as smart phones, tablet computers, smart watches, and the like. In this embodiment, the rf front-end module 200 may include the substrate 9520 and the power amplifier 100 in the above embodiment, or the power amplifier 900 in the above embodiment.

In this embodiment, the substrate 9520 is substantially rectangular and is used to provide a fixed support for components (e.g., the power amplifier 100, etc.) in the rf front-end module 950. Specifically, the substrate 9520 may be a copper clad laminate, and a circuit may be printed on the surface of the substrate 9520 by performing processing such as hole processing, electroless copper plating, electrolytic copper plating, etching, and the like on the copper clad laminate.

In some possible embodiments, the power amplifier 100 is disposed on the substrate 9520. As an embodiment, the power amplifier 100 may be integrated into the same chip, and the chip may be fixed on the substrate 9520 by using a wire bonding process or a flip-chip process, so as to improve the integration of the rf front-end module 950. As another embodiment, a portion of the components (e.g., transistors) in the power amplifier 100 may be integrated in the same chip, which is mounted on the substrate 9520. Another part of the components (e.g., capacitors, inductors, etc.) may be attached to the substrate 9520, for example, the inductors in the power amplifier 100 may be wound on the substrate 9520 in the form of metal wires, and the capacitors in the power amplifier 100 may be attached to the substrate 9520 in the form of chip capacitors, so that the hardware layout of the rf front-end module 950 is more compact and reasonable.

In other possible embodiments, the power amplifier 900 is disposed on the substrate 9520. The arrangement of the power amplifier 900 on the substrate 9520 may refer to the arrangement of the power amplifier 100 on the substrate 9520, and will not be described herein.

The present application provides a power amplifier 100 and a radio frequency front end module 950 configured with the power amplifier 100, the power amplifier 100 may include a first stage power amplifying circuit 10, a second stage power amplifying circuit 20, a choke unit 30, and a stabilizing unit 40. The input terminal 101 of the first stage power amplifying circuit 10 is connected to the signal input terminal 12, the output terminal 103 of the first stage power amplifying circuit 10 is connected to the input terminal 201 of the second stage power amplifying circuit 20, and the output terminal 203 of the second stage power amplifying circuit 20 is connected to the signal output terminal 14.

The first terminal 301 of the choke unit 30 is connected to the power supply terminal 105 of the first stage power amplifying circuit 10, and the second terminal 303 of the choke unit 30 and the power supply terminal 205 of the second stage power amplifying circuit 20 are connected to the first power supply terminal 16, respectively. Therefore, the power supply terminal 105 of the first-stage power amplifying circuit 10 and the power supply terminal 205 of the second-stage power amplifying circuit 20 in this embodiment are both connected to the same power supply terminal, that is, the first power supply terminal 16, so that there is signal coupling between the first-stage power amplifying circuit 10 and the second-stage power amplifying circuit 20.

The stabilizing unit 40 and the choke unit 30 are connected in parallel, the stabilizing unit 40 comprising at least one resistor 410. Illustratively, the stabilization unit 40 may be implemented with a purely resistive circuit, such that the stabilization unit 40 is resistive. When a part of the out-of-band low frequency signal in the radio frequency signal coupled to the first stage power amplifying circuit 10 via the second stage power amplifying circuit 20 and the subsequent stage passes through the stabilizing unit 40, the stabilizing unit 40 can suppress the out-of-band low frequency signal, thereby reducing the signal gain caused by the out-of-band low frequency signal, and reducing the signal coupling between the first stage power amplifying circuit 10 and the second stage power amplifying circuit 20, so as to improve the stability of the power amplifier 100 during operation.

In this specification, certain terms are used throughout the description and claims to refer to particular components. Those of skill in the art will appreciate that a hardware manufacturer may refer to the same component by different names. The description and claims do not take the difference in name as a way of distinguishing between components, but rather take the difference in functionality of the components as a criterion for distinguishing. As used throughout the specification and claims, the word "comprise" and "comprises" are to be construed as "including, but not limited to"; by "substantially" is meant that a person skilled in the art can solve the technical problem within a certain error range, essentially achieving the technical effect.

In the description of the present application, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "inner," and the like indicate an orientation or a positional relationship based on that shown in the drawings, and are merely for convenience of description of the present application, but do not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.

In this application, the terms "mounted," "connected," "secured," and the like are to be construed broadly, unless otherwise specifically indicated or defined. For example, the connection can be fixed connection, detachable connection or integral connection; can be mechanically or electrically connected; the connection may be direct, indirect via an intermediate medium, or communication between two elements, or only surface contact. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless explicitly defined otherwise.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, one of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not drive the essence of the corresponding technical solutions to depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. The power amplifier is characterized by comprising a signal input end, a signal output end and a first power supply end, wherein the power amplifier comprises a first-stage power amplifying circuit, a second-stage power amplifying circuit, a choke unit and a stabilizing unit;

The input end of the first-stage power amplifying circuit is connected with the signal input end, and the output end of the first-stage power amplifying circuit is connected with the input end of the second-stage power amplifying circuit; the output end of the second-stage power amplification circuit is connected with the signal output end;

the first end of the choke unit is connected with the power supply end of the first-stage power amplifying circuit, and the second end of the choke unit and the power supply end of the second-stage power amplifying circuit are respectively connected with the first power supply end;

the stabilizing unit and the choke unit are connected in parallel, and the stabilizing unit comprises at least one resistor.

2. The power amplifier according to claim 1, wherein the stabilizing unit includes M resistors and M switches in one-to-one correspondence with the M resistors, wherein M is an integer greater than 1;

m resistors are connected in series, and the switch is connected in parallel with the corresponding resistor; or M resistors are connected in parallel, and the switch is connected in series in the branch where the corresponding resistor is located.

3. The power amplifier of claim 2, wherein the choke unit comprises a first inductance;

the power amplifier further comprises a control unit, wherein the control unit is connected with the M switches and is used for adjusting the equivalent resistance value of the stabilizing unit based on the inductance value of the first inductor and the signal frequency of the radio frequency signal to be suppressed.

4. A power amplifier according to any one of claims 1 to 3, wherein the output terminal of the first stage power amplifying circuit and the power supply terminal of the first stage power amplifying circuit share the same signal port;

and the output end of the second-stage power amplifying circuit and the power supply end of the second-stage power amplifying circuit share the same signal port.

5. The power amplifier of claim 4, wherein the first stage power amplifying circuit comprises a first transistor and the second stage power amplifying circuit comprises a second transistor;

the control end of the first transistor is connected to the input end of the first-stage power amplifying circuit, the first end of the first transistor is connected to the output end of the first-stage power amplifying circuit, and the second end of the first transistor is grounded;

the control end of the second transistor is connected to the input end of the second-stage power amplifying circuit, the first end of the second transistor is connected to the output end of the second-stage power amplifying circuit, and the second end of the second transistor is grounded.

6. A power amplifier according to any one of claims 1 to 3, further comprising a first isolation unit and a second isolation unit;

The first end of the first isolation unit is connected with the second end of the choke unit, and the second end of the first isolation unit is connected with the first power supply end;

the first end of the second isolation unit is connected to the power supply end of the second-stage power amplification circuit, and the second end of the second isolation unit is connected to the first power supply end.

7. The power amplifier of claim 6, further comprising a first decoupling unit and a second decoupling unit;

one end of the first decoupling unit is connected to the first end of the first isolation unit, and the other end of the first decoupling unit is grounded;

one end of the second decoupling unit is connected to the first end of the second isolation unit, and the other end of the second decoupling unit is grounded.

8. A power amplifier according to any one of claims 1 to 3, further comprising a first balun, a third stage power amplifying circuit and a second balun; the second-stage power amplifying circuit is a single-ended power amplifying circuit, and the third-stage power amplifying circuit is a differential power amplifying circuit;

the output end of the second-stage power amplification circuit is connected with the signal output end through the first balun, the third-stage power amplification circuit and the second balun in sequence.

9. The power amplifier of claim 8, wherein the first balun includes a first primary side and a first secondary side coupled; the first end of the first primary side is connected with the output end of the second-stage power amplifying circuit, and the second end of the first primary side is grounded; the first secondary side is connected between a first input end and a second input end of the third-stage power amplification circuit;

the second balun includes a second primary side and a second secondary side coupled; the second primary side is connected between the first output end and the second output end of the third-stage power amplification circuit; one end of the second secondary side is connected with the signal output end, and the other end of the second secondary side is grounded.

10. The power amplifier of claim 9, wherein the output of the second stage power amplifying circuit and the power supply of the second stage power amplifying circuit share the same signal port; the second end of the first primary side is also connected with the first power supply end;

the power amplifier further comprises a first capacitor, one end of the first capacitor is connected to the second end of the first primary side, and the other end of the first capacitor is grounded.

11. The power amplifier of claim 9, wherein the third stage power amplifying circuit comprises a third transistor and a fourth transistor, the control terminal of the third transistor is connected to the first input terminal of the third stage power amplifying circuit, the first terminal of the third transistor is connected to the first output terminal of the third stage power amplifying circuit, and the second terminal of the third transistor is grounded;

The control end of the fourth transistor is connected to the second input end of the third-stage power amplifying circuit, the first end of the fourth transistor is connected to the second output end of the third-stage power amplifying circuit, and the second end of the fourth transistor is grounded.

12. The power amplifier of claim 11, wherein the power amplifier is further provided with a second power supply terminal; the second primary side comprises a first coil and a second coil;

the first coil and the second coil are connected in series and then connected between the first end of the third transistor and the first end of the fourth transistor; the common end of the first coil and the second coil is connected to the second power supply end.

13. A power amplifier according to any one of claims 1 to 3, further comprising a transformer, the output of the second stage power amplifying circuit being connected to the signal output via the transformer.

14. The power amplifier of claim 13, wherein the transformer includes a third primary side and a third secondary side coupled together;

the first end of the third primary side is connected with the output end of the second-stage power amplifying circuit, and the second end of the third primary side is grounded; one end of the third secondary side is connected with the signal output end, and the other end of the third secondary side is grounded.

15. The power amplifier of claim 14, wherein the output of the second stage power amplifying circuit and the power supply of the second stage power amplifying circuit share the same signal port; the second end of the third primary side is also connected with the first power supply end;

the power amplifier further comprises a second capacitor, one end of the second capacitor is connected to the second end of the third primary side, and the other end of the second capacitor is grounded.

16. A power amplifier according to any one of claims 1 to 3, further comprising a filter unit, the output of the second stage power amplifying circuit being connected to the signal output via the filter unit.

17. A power amplifier according to any one of claims 1 to 3, wherein the second stage power amplifying circuit is a differential power amplifying circuit; the input end of the second-stage power amplifying circuit comprises a third input end and a fourth input end; the output end of the second-stage power amplification circuit comprises a third output end and a fourth output end; the power amplifier further comprises a third balun and a fourth balun;

the third balun comprises a fourth primary side and a fourth secondary side which are coupled; one end of the fourth primary side is connected with the output end of the first-stage power amplifying circuit, and the other end of the fourth primary side is grounded; the fourth secondary side is connected between the third input end and the fourth input end;

The fourth balun comprises a fifth primary side and a fifth secondary side which are coupled; the fifth primary side is connected between the third output end and the fourth output end; one end of the fifth secondary side is connected with the signal output end, and the other end of the fifth secondary side is grounded;

the fifth primary side comprises a third coil and a fourth coil; the third coil and the fourth coil are connected in series and then connected between the third output end and the fourth output end; the common end of the third coil and the fourth coil is connected to the first power supply end.

18. The power amplifier of claim 8, wherein the first stage power amplifying circuit, the second stage power amplifying circuit, the choke unit, the stabilizing unit, the first balun, the third stage power amplifying circuit, and the second balun form one power amplifying module, and the number of the power amplifying modules is two;

the input ends of the first-stage power amplifying circuits in the two power amplifying modules are respectively connected with the signal input ends;

the secondary sides of the second balun in the two power amplification modules are connected in series to form an output combination circuit, one end of the output combination circuit is connected to the signal output end, and the other end of the output combination circuit is grounded.

19. The power amplifier is characterized by comprising a signal input end, a signal output end and a power supply end, wherein the power amplifier comprises a power amplifying circuit, a choke unit and a stabilizing unit;

the input end of the power amplifying circuit is connected with the signal input end, and the output end of the power amplifying circuit is connected with the signal output end;

the first end of the choke unit is connected with the power supply end of the power amplifying circuit, and the second end of the choke unit is connected with the power supply end;

20. A radio frequency front end module, comprising:

a substrate; and

the power amplifier of any one of claims 1 to 19, the power amplifier being disposed on the substrate.