CN117727813A - Solar cell and photovoltaic module - Google Patents
Solar cell and photovoltaic module Download PDFInfo
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- CN117727813A CN117727813A CN202410175826.5A CN202410175826A CN117727813A CN 117727813 A CN117727813 A CN 117727813A CN 202410175826 A CN202410175826 A CN 202410175826A CN 117727813 A CN117727813 A CN 117727813A
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- Photovoltaic Devices (AREA)
Abstract
The embodiment of the application relates to the field of photovoltaics, and provides a solar cell and a photovoltaic module, the solar cell includes: a substrate and a passivation layer on the substrate, the substrate having two first boundaries opposite along a first direction; first fine grids and second fine grids alternately arranged along a first direction; the main grids are arranged along the second direction, are positioned on the surface of the passivation layer and are electrically contacted with the thin grids, and comprise first main grids and second main grids which are alternately arranged along the second direction, wherein the first main grids are electrically contacted with the first thin grids, and the second main grids are electrically contacted with the second thin grids; at least one edge gate line extending along the second direction, the edge gate line being adjacent to the first boundary, the edge gate line of a partial region penetrating the passivation layer and being electrically connected to the substrate, the edge gate line being in electrical contact with the first main gate; and/or the edge gate line is in electrical contact with the second main gate. The solar cell and the photovoltaic module provided by the embodiment of the application can improve the yield of the photovoltaic module.
Description
Technical Field
The embodiment of the application relates to the field of photovoltaics, in particular to a solar cell and a photovoltaic module.
Background
The reasons for influencing the photoelectric conversion efficiency and the yield of the solar cell mainly comprise two aspects, namely optical loss, wherein the optical loss comprises shielding loss, carrier recombination loss of a substrate, carrier recombination loss of a highly doped film layer and refraction loss of the film layer; and secondly, the electrical loss comprises the problems of resistance loss of the material, contact loss of an electrode, contact loss between a welding strip and a solar cell, cold joint between the welding strip and the solar cell and the like.
Therefore, there is an urgent need in the art to provide a solar cell and a photovoltaic module capable of reducing electrical loss and optical loss, thereby improving the photoelectric conversion efficiency of the corresponding solar cell and the yield of the photovoltaic module.
Disclosure of Invention
The embodiment of the application provides a solar cell and a photovoltaic module, which are at least beneficial to improving the yield of the photovoltaic module.
According to some embodiments of the present application, an aspect of embodiments of the present application provides a solar cell, including: a substrate and a passivation layer on the substrate, the substrate having two first boundaries opposing in a first direction; the thin grid penetrates through the passivation layer and is electrically connected with the substrate; the fine grids comprise first fine grids and second fine grids which are alternately arranged along the first direction; a plurality of main gates arranged along the second direction, the main gates being positioned on the surface of the passivation layer and being in electrical contact with the thin gate, the main gates comprising m alternately arranged along the second direction 1 First main grid and m 2 A second main gate electrically contacting the first fine gate, the second main gate and the secondFine gate electrical contacts; the first main grid is one of an anode electrode or a cathode electrode, and the second main grid is the other of the anode electrode or the cathode electrode; at least one edge gate line extending along the second direction, the edge gate line being adjacent to the first boundary, the edge gate line of a partial region penetrating the passivation layer and electrically connected to the substrate, the edge gate line being connected to n 1 -said first main gate electrical contacts; and/or the edge grid line and n 2 -said second main gate electrical contacts; wherein 1 < n 1 ≤m 1 ，1＜n 2 ≤m 2 ，n 1 、m 1 、n 2 M 2 Are natural numbers.
In some embodiments, the at least one edge gate line includes: the first edge grid line is positioned between the first boundary and the second thin grid, the first edge grid line is electrically contacted with the first main grid, the second edge grid line is positioned between the other first boundary and the first thin grid, and the second edge grid line is electrically contacted with the second main grid.
In some embodiments, comprising: one of the edge gate lines is in electrical contact with the first main gate or the edge gate line is in electrical contact with the second main gate.
In some embodiments, the first thin gate includes a plurality of first sub-gate lines arranged along the second direction, a passivation layer between two adjacent first sub-gate lines forms a first spacer, the second main gate is located on the first spacer, and the first main gate is in electrical contact with the first sub-gate lines; the second fine grid comprises a plurality of second sub-grid lines which are arranged along the second direction, a passivation layer between two adjacent second sub-grid lines forms a second interval region, and the first main grid is positioned on the second interval region; the second main gate is in electrical contact with the second sub-gate line.
In some embodiments, the width of the edge gate line along the first direction is greater than or equal to the width of the thin gate along the first direction.
In some embodiments, the width of the edge gate line along the first direction includes: 10um to 55um.
In some embodiments, the edge gate line is spaced from the adjacent fine gate by a first spacing that is less than or equal to a distance between the adjacent first fine gate and the second fine gate.
In some embodiments, the first pitch ranges from 0.2mm to 0.7mm.
In some embodiments, the distance between the adjacent first fine grid and the second fine grid is in the range of 0.3 mm-0.8 mm.
In some embodiments, the material of the edge gate line is the same as the material of the fine gate.
In some embodiments, the edge gate line is aligned with n 1 -said first main gate electrical contacts; the edge grid line and n 2 -said second main gate electrical contacts; n is 1 < n 1 ＜m 1 ，1＜n 2 ＜m 2 。
According to some embodiments of the present application, there is also provided a photovoltaic module according to another aspect of the embodiments of the present application, including: a cell string formed by connecting a plurality of solar cells according to any one of the above embodiments; the solar cell comprises an edge grid line, a first main grid and a second main grid; a connection member for electrically connecting the first and second main grids of two adjacent solar cells; the packaging adhesive film is used for covering the surface of the battery string; and the cover plate is used for covering the surface of the packaging adhesive film, which is away from the battery strings.
In some embodiments, further comprising: an electrical connection line; the edge grid line and n 1 The first main grids are electrically contacted, and the electric connecting wires are electrically connected with the edge grid lines and the second main grids of the adjacent solar cells; alternatively, the edge gate line is connected with n 2 And the second main grids are electrically contacted, and the electric connecting wires are electrically connected with the edge grid lines and the first main grids of the adjacent solar cells.
The technical scheme provided by the embodiment of the application has at least the following advantages:
in the solar cell provided by the embodiment of the application, the edge grid line is electrically contacted with the first main grid, and/or the edge grid line is electrically contacted with the second main grid, the grid lines (positive electrode or negative electrode) with the same polarity in the solar cell are mutually connected in series by using one grid line, and one solar cell forms an integral electrode, so that the first main grid and each first fine grid can be guaranteed to be in a mutually conductive state, the probability of efficiency and yield reduction of the cell caused by the occurrence of a problem of one of the first main grids can be avoided, and the first fine grids in the conductive state can also be used for collecting the first fine grids positioned at the edge of the substrate to improve the collection efficiency of the cell. Likewise, the battery efficiency can be improved by improving the battery collection efficiency of the second fine grid.
In addition, the problem of poor appearance between the first main grids and the first fine grids due to different manufacturing processes can be avoided due to the fact that the first main grids and the first fine grids are all in the conducting state. The mutual communication between the first main grids and the mutual communication between the second main grids can also avoid the problem of reduced battery efficiency caused by broken grids of one of the thin grids or the main grids.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the drawings that are required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a solar cell according to an embodiment of the present disclosure;
fig. 2 is a schematic partial structure of a solar cell according to an embodiment of the present disclosure;
FIG. 3 is a schematic cross-sectional view of the structure of FIG. 2 along the line A1-A2;
FIG. 4 is a schematic cross-sectional view of the structure of FIG. 2 along the section B1-B2;
fig. 5 is a schematic structural diagram of a solar cell according to an embodiment of the present disclosure;
fig. 6 is a layout diagram of a grid line in a solar cell according to an embodiment of the present disclosure;
Fig. 7 is a schematic structural diagram of a photovoltaic module according to another embodiment of the present disclosure;
FIG. 8 is a schematic cross-sectional view of the structure of FIG. 7 along the line M1-M2;
fig. 9 is a schematic structural diagram of a solar cell in a photovoltaic module according to another embodiment of the present disclosure.
Detailed Description
As known from the background art, the yield of the solar cell and the photovoltaic module is poor.
Analysis finds that one of the reasons for the poor yield of solar cells and photovoltaic modules is: the current back contact solar cell, namely, the first electrode and the second electrode in the IBC cell are both located on the back surface of the substrate, and further include a first main gate and a second main gate, the first electrode is electrically contacted with the corresponding first main gate, the second electrode is electrically contacted with the corresponding second main gate, the first electrode intersects with the extending direction of the first main gate, and the second electrode intersects with the extending direction of the second main gate, so that electrical insulation between the first electrode and the second main gate with different polarities is involved, electrical insulation between the second electrode and the first main gate with different polarities occurs, and then electrical connection occurs between the first main gate and part of the first electrode, the first main gate is electrically insulated from the other first electrodes, and the first main gate cannot collect carriers of all the first electrodes, when one of the first main gates has a problem or a problem of poor welding between the first main gate and the welding strip, a plurality of first electrodes abutted by the first main gate cannot be collected, thereby affecting the solar cell and photovoltaic yield of the photovoltaic module. Similarly, the second main grid has the same problem, thereby influencing the yield of the solar cell and the photovoltaic module.
The embodiment of the application provides a solar cell, the solar cell includes edge grid line, electrical contact between edge grid line and the first main grid, and/or electrical contact between edge grid line and the second main grid, use a grid line to establish ties each other between the grid line of the same polarity (positive electrode or negative electrode) in the solar cell, a solar cell constitutes an holistic electrode, thereby can guarantee that first main grid and each first thin grid are the state that switches on each other, thereby can avoid because one of them first main grid goes wrong and lead to the efficiency of battery and the probability that the yield descends, and the first thin grid of state that switches on can also be collected the first thin grid that is located the base edge and improve the collection efficiency of battery. Likewise, the battery efficiency can be improved by improving the battery collection efficiency of the second fine grid.
In addition, the first main grids and the first fine grids are in a conducting state, so that the problem of poor appearance among the first main grids and the first fine grids caused by different manufacturing processes can be avoided. The mutual communication between the first main grids and the mutual communication between the second main grids can also avoid the problem of reduced battery efficiency caused by broken grids of one of the thin grids or the main grids.
Embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, as will be appreciated by those of ordinary skill in the art, in the various embodiments of the present application, numerous technical details have been set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and with various changes and modifications based on the following embodiments.
Fig. 1 is a schematic structural diagram of a solar cell according to an embodiment of the present disclosure; fig. 2 is a schematic partial structure of a solar cell according to an embodiment of the present disclosure; FIG. 3 is a schematic cross-sectional view of the structure of FIG. 2 along the line A1-A2; fig. 4 is a schematic cross-sectional view of fig. 2 along the section B1-B2.
Referring to fig. 1 and 3, in one aspect, a solar cell according to an embodiment of the present application includes: a substrate 100 and a passivation layer 102 on the substrate 100, the substrate 100 having two first boundaries 101 opposite along a first direction Y; along a first directionTo the arranged fine gate 110, the fine gate 110 penetrates the passivation layer 102 and is electrically connected with the substrate 100; the fine grid 110 includes first fine grids 111 and second fine grids 112 alternately arranged in the first direction X; a plurality of main gates 120 arranged along the second direction X, the main gates 120 being positioned on the surface of the passivation layer 102 and being in electrical contact with the fine gates 110, the main gates 120 comprising m alternately arranged along the second direction X 1 First main gate 121 and m 2 A plurality of second main gates 122, the first main gate 121 being in electrical contact with the first fine gate 111, the second main gate 122 being in electrical contact with the second fine gate 112; wherein the first main gate 121 is one of a positive electrode and a negative electrode, and the second main gate 122 is the other of the positive electrode and the negative electrode; at least one edge gate line 113 extending along the second direction X, the edge gate line 113 being adjacent to the first boundary 101, the edge gate line 113 of a partial region penetrating the passivation layer 102 and electrically connected to the substrate 100, the edge gate line 113 being connected to n 1 The first main gate 121 is electrically contacted; wherein 1 < n 1 ≤m 1 ，n 1 、m 1 Is a natural number.
In some embodiments, referring to fig. 3, the solar cell is a back contact solar cell, which refers to a solar cell in which electrodes of different polarities (positive and negative electrodes) are both located on the back side of the substrate.
Referring to fig. 3, in some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, which may be silicon or germanium, for example. The elemental semiconductor material may be in a single crystal state, a polycrystalline state, an amorphous state, or a microcrystalline state (a state having both a single crystal state and an amorphous state, referred to as a microcrystalline state), and for example, silicon may be at least one of single crystal silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.
In some embodiments, the material of the substrate 100 may also be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanium, silicon carbide, gallium arsenide, indium gallium, perovskite, cadmium telluride, copper indium selenium, and the like. The substrate 100 may also be a sapphire substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.
In some embodiments, the substrate 100 may be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type doping element, which may be any of v group elements such As phosphorus (P) element, bismuth (Bi) element, antimony (Sb) element, and arsenic (As) element. The P-type semiconductor substrate is doped with a P-type element, and the P-type doped element may be any one of group iii elements such as boron (B) element, aluminum (Al) element, gallium (Ga) element, and indium (In) element.
In some embodiments, the substrate 100 has a first surface 11 and a second surface 12 disposed opposite to each other, where the first surface 11 of the substrate 100 may be a front surface, and the second surface 12 may be a back surface, and the front surface may be a light receiving surface for receiving incident light, and the back surface may be a back surface. The backlight surface can also receive the incident light, but the efficiency of receiving the incident light is weaker than that of the light receiving surface.
It should be noted that, the incident light received by the light receiving surface is directly irradiated on the solar cell by sunlight, and the incident light received by the back surface is caused by reflection on the ground, reflection by other objects, and refraction of the film layer on the substrate.
In some embodiments, the first surface 11 has a first pile structure 13, the first pile structure 13 comprising a plurality of raised structures 105. The first surface 11 has a front surface field (front surface field, FSF) with a conductivity type of dopant ions that is the same as the conductivity type of dopant ions of the substrate 100, and the field passivation effect is used to reduce the surface minority carrier concentration, thereby reducing the surface recombination rate, and also reducing the series resistance and improving the electron transport capability.
In some embodiments, substrate 100 has alternating regions i and ii, where i is one of region P or region N, and ii is the other of region P or region N, with a spacer gap between regions P and N, where first fine gate 111 is located in region i and second fine gate 112 is located in region ii.
In some embodiments, the P region and the N region do not have a spacer gap therebetween, and an insulating film layer is disposed between the P region and the N region to insulate the P region from the N region, thereby insulating the first fine gate 111 from the second fine gate 112.
In some embodiments, the substrate 100 further has a region III at the edge of the substrate 100, the region III having the same characteristics as an adjacent region I or region II, such as the region III shown in FIG. 3 disposed adjacent to the region I with a spacer gap between the regions III and I, and the polarity of the region III being the same as the polarity of the region I, such as the region I being the region N, the region III also being the region N. In some embodiments, the polarity of region III is different from the polarity of region I, e.g., region I is region N, region III is region P, and an edge gate line on region III is in electrical contact with the second main gate.
In some embodiments, referring to fig. 3, the spacer gap is flush with the P-region and the N-region, i.e., the substrate 100 is not etched, and insulation is achieved between the P-region and the N-region by some isolating film, which may be the passivation layer 102.
In some embodiments, the spacer gap is lower than the P region and the spacer gap is lower than the N region, the spacer gap has a trench extending from the second surface toward the first surface, the trench is used to achieve automatic isolation between regions of different conductivity types, and leakage caused by formation of a PN junction by heavily doped P and N regions in IBC cells (crossed back electrode contact cells, interdigitated Back Contact) can be eliminated, which affects cell efficiency.
In some embodiments, the surface of the spacer gap may be a polished surface structure, the surface of the spacer gap may be a second textured structure, and the roughness of the first textured structure is greater than or equal to the roughness of the second textured structure.
Wherein "roughness" refers to an arithmetic average of absolute values of amounts of vertical deviations of peaks and valleys within a sampling length from an average horizontal line, which is set in the sampling length. Roughness can be measured by comparison, photocutting, interferometry, and needle punching.
In some embodiments, the solar cell includes a first dielectric layer 143 and a first doped semiconductor layer 144 on the i region and a second dielectric layer 153 and a second doped semiconductor layer 154 on the ii region; the passivation layer 102 covers the first doped semiconductor layer 144 and the second doped semiconductor layer 154, the first fine gate 111 extends through the passivation layer 102 in electrical contact with the first doped semiconductor layer 144, and the second fine gate 112 extends through the passivation layer 102 in electrical contact with the second doped semiconductor layer 154.
In some embodiments, the film layer arrangement on the iii region is the same as the film layer arrangement on the i region, i.e., the iii region has a first dielectric layer and a first doped semiconductor layer thereon, and the edge gate line electrically contacts the first doped semiconductor layer through the passivation layer. In some embodiments, the film layer arrangement on the iii region is the same as the film layer arrangement on the ii region, i.e., the iii region has a second dielectric layer and a second doped semiconductor layer thereon, and the edge gate line electrically contacts the second doped semiconductor layer through the passivation layer.
In some embodiments, the first doped semiconductor layer 144 is doped with one of an N-type doping element or a P-type doping element, and the second doped semiconductor layer 154 is doped with the other of the N-type doping element or the P-type doping element.
In some embodiments, at least one of the first dielectric layer 143 or the second dielectric layer 153 may be a tunneling dielectric layer, the material of which includes silicon oxide or silicon carbide.
In some embodiments, at least one of the first doped semiconductor layer 144 or the second doped semiconductor layer 154 may be at least one of a doped amorphous silicon layer, a doped polysilicon layer, a doped microcrystalline silicon layer, a doped silicon carbide layer, or a doped crystalline silicon layer.
In some embodiments, the solar cell may include a first intrinsic dielectric layer, a first doped amorphous silicon layer, and a first transparent conductive layer over the i region; the first intrinsic medium layer is positioned on the second surface, the first doped amorphous silicon layer is positioned on the first intrinsic medium layer, and the first transparent conductive layer is positioned on the first doped amorphous silicon layer; the second intrinsic medium layer is positioned on the II region, the second doped amorphous silicon layer is positioned on the second surface, the second doped amorphous silicon layer is positioned on the second intrinsic medium layer, and the second transparent conductive layer is positioned on the second doped amorphous silicon layer. Wherein the first doped amorphous silicon layer is doped with one of an N-type doping element or a P-type doping element, and the second doped amorphous silicon layer is doped with the other of the N-type doping element or the P-type doping element.
With continued reference to fig. 3 and 4, the solar cell further includes: a front passivation layer 103, the front passivation layer 103 covering the front surface of the substrate 100.
In some embodiments, the material of at least one of the front passivation layer 103 and the passivation layer 102 comprises: one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, or aluminum oxide.
In some embodiments, at least one of the front passivation layer 103 and the passivation layer 102 includes a stacked film layer, where the stacked film layer includes at least a first passivation layer and a second passivation layer, and a material of the first passivation layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, or aluminum oxide. The material of the second passivation layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, titanium oxide, hafnium oxide, or aluminum oxide.
In some embodiments, the material of the front passivation layer 103 is the same as the material of the passivation layer 102, and the front passivation layer 103 and the passivation layer 102 are prepared in the same manufacturing process.
In some embodiments, the first thin gate 111, the second thin gate 112, and the edge gate line 113 are all made of a burn-through paste, wherein the first thin gate 111 burns through the passivation layer 102 and is in electrical contact with the first doped semiconductor layer 144, the second thin gate 112 burns through the passivation layer 102 and is in electrical contact with the second doped semiconductor layer 154, and the edge gate line 113 burns through the passivation layer 102 and is in electrical contact with the first doped semiconductor layer 144.
For example, the method of forming the first fine gate 111 includes: a screen printing process is used to print a metal paste on the surface of a portion of the passivation layer 102. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel.
With continued reference to fig. 1, the first fine grid 111 and the second fine grid 112 extend along the second direction X, and the first direction Y and the second direction X may be perpendicular to each other, or may have an included angle smaller than 90 degrees, for example, 60 degrees, 45 degrees, 30 degrees, or the like, where the first direction Y and the second direction X are not the same direction. In order to facilitate explanation and understanding, the embodiment uses the first direction Y and the second direction X perpendicular to each other as an example, and in a specific application, the angle between the first direction Y and the second direction X may be adjusted according to the actual needs and the application scenario, which is not limited in this embodiment of the present application.
In some embodiments, the substrate includes two second boundaries, the two second boundaries being opposite along the second direction X. The reason why the chamfer is formed is that in the conventional solar cell, because the silicon single crystal process for preparing the substrate is refined and limited, the silicon single crystal rod can only be made into a circle at present, the silicon rod is sliced into the shape of a single crystal silicon wafer after coming out, namely, the silicon rod section is sliced into the shape of the single crystal silicon wafer (after the area is calculated, the illumination area can be increased to the greatest extent in one unit, the silicon rod material can be saved to the greatest extent, the cell and component production are also facilitated), the chamfer is usually arranged at the juncture of each boundary of the substrate, the stress outside the silicon wafer is reduced, and the micro-damage of the corners of the silicon wafer is avoided.
In some embodiments, the edge gate line 113 may be provided to increase the collection rate of the current generated by the substrate at the first boundary. And secondly, the edge grid line 113 is electrically contacted with the first main grid so as to realize the electrical connection between all the first fine grids 111 and the first main grid 121, thereby improving the battery collection rate and reducing the defective rate of the battery.
In some embodiments, the edge grid lines 113 can improve the collection efficiency of the solar cell by 1% -5%, and reduce the reject ratio of the cell by less than 5%, so that the photoelectric conversion efficiency of the solar cell and the cost performance of the photovoltaic module are improved.
In some embodiments, the edge gate line 113 is a whole gate line connected to the adjacent first main gate 121, and the extending direction of the edge gate line 113 is perpendicular to the extending direction of the first main gate 121 or the extending direction of the edge gate line 113 overlaps with the extending direction of the first fine gate 111, so that a part of the existing printing screen of the fine gate 110 can be modified or the edge gate line 113 can be printed secondarily, thereby reducing improvement on the prior art and improving compatibility and applicability of equipment.
In some embodiments, the edge grid line 113 is a grid line electrically connected to a portion of the first main grid, a portion of the connection grid line is located inside the cell, and the solar cell realizes the electrical connection between the first main grid and the first thin grid 111 through the edge grid line 113 and the connection grid line.
In some embodiments, the material of the edge gate line 113 is the same as the material of the fine gate 110. The slurry of the edge grid line 113 is the same as that of the fine grid 110, that is, the edge grid line 113 is formed by burning-through slurry, and the edge grid line 113 also penetrates through the passivation layer to be electrically connected with the corresponding first doped semiconductor layer, so that the edge grid line 113 not only can realize current penetration of the first main grid 121, but also can collect current adjacent to the substrate surface of the first boundary 101, thereby increasing a collection path and improving current collection efficiency.
In some embodiments, the paste of the edge gate line 113 is the same as the paste of the main gate 120, that is, the edge gate line 113 is formed by non-burning paste, and the edge gate line 113 is located on the surface of the passivation layer, so that the i region and the ii region of the substrate surface under the edge gate line 113 do not need to be typeset, so as to prevent the problem of short circuit caused by electrical contact between the edge gate line 113 and the doped region of another polarity. In addition, the edge grid line 113 can not damage the passivation layer, so that the integrity of the film layer of the passivation layer is ensured, the passivation effect of the passivation layer on the substrate is improved, the optical loss of the solar cell is reduced, and the photoelectric conversion efficiency of the solar cell is improved. In addition, as the non-burning-through paste does not damage PN junctions due to excessive glass powder, metal recombination can be effectively reduced, the open-circuit voltage of the solar cell is improved, and the conversion efficiency of the solar cell is improved.
The traditional slurry comprises a mixture of metal powder, glass powder and an organic carrier. The non-burn-through type slurry is a slurry which contains glass powder with lower content than the traditional slurry, has weak burn-through capability in the sintering process and does not need or cannot burn through the passivation layer. The burn-through type slurry refers to slurry which has strong burn-through capability and can burn through a passivation layer in the sintering process.
In some embodiments, referring to fig. 2, the first fine gate 111 includes a plurality of first sub-gate lines 1111 arranged along the second direction X, a passivation layer between two adjacent first sub-gate lines 1111 forms a first spacer 1112, the second main gate 122 is located on the first spacer 1112, and the first main gate 121 is in electrical contact with the first sub-gate lines 1111; the second fine gate 112 includes a plurality of second sub-gate lines 1121 arranged along the second direction X, the passivation layer between two adjacent second sub-gate lines 1121 forms a second spacing region 1122, and the first main gate 121 is located on the second spacing region 1122; the second main gate 122 is in electrical contact with the second sub-gate line 1121.
In some embodiments, a width W1 of the edge gate line 113 along the first direction Y is greater than or equal to a width W2 of the thin gate 110 along the first direction Y. The width W2 of the thin gate 110 along the first direction Y may be at least one of the width of the first thin gate 111 along the first direction Y or the width of the second thin gate 112 along the second direction Y. In this way, the edge gate lines 113 have a larger width to achieve the electrical connection between the first main gates 121, and the edge gate lines 113 do not have an excessive influence on the layout of the original gate lines. When the width of the edge grid line 113 is equal to the width of the thin grid 110, the edge grid line 113 and the thin grid 110 can be simultaneously manufactured without affecting the original process, so that the compatibility of the original equipment and devices is improved, and the manufacturing cost of the solar cell is reduced.
In some embodiments, having a wider edge grid line 113 may increase the collection area and the collection probability near the edge of the first boundary 101, thereby increasing the collection efficiency, if the width of the edge grid line 113 is greater than the width of the thin grid 110. The wider edge grid line 113 can also be used as the end point of the first main grid close to the first boundary, so that the higher edge grid line 113 can improve the accuracy of the first main grid lap joint on the edge grid line 113, and the first main grid 121 can also be correspondingly arranged to be shorter because the edge grid line can share the welding pressure of the first main grid, namely, the end part of the first main grid 121 close to the first boundary 101 can be flush with or lower than the side surface of the edge grid line 113 close to the first boundary 101, so that the distance between the welding point of the welding strip and the first main grid 121 and the first boundary 101 is relatively far, and the probability of breakage of the battery piece is further reduced.
In some embodiments, the width W1 of the edge gate line 113 along the first direction Y includes: 10um to 55um. The width W1 of the edge gate line 113 along the first direction may be 10um to 16um, 16um to 22um, 22um to 30um, 30um to 38um, 38um to 46um, or 46um to 55um. The width of the edge grid line 113 along the first direction is within any range, the capability of the edge grid line 113 for collecting carriers at the edge is strong, and the edge grid line 113 and the first boundary 101 have a certain distance, so that the probability of breakage of the first boundary is reduced.
In some embodiments, the spacing between the edge gate line 113 and the adjacent thin gate 110 is a first spacing S1, and the first spacing is less than or equal to a distance S2 between the adjacent first thin gate 111 and the second thin gate 112. In this way, the distance between the edge grid line 113 and the thin grid 110 is suitable, and in the typesetting without wasting the shielding area of the edge grid line 113 and the thin grid 110, the typesetting between the edge grid line 113 and the thin grid 110 can realize the minimum migration distance and the minimum migration loss of the carriers on the substrate, thereby improving the open circuit voltage of the solar cell.
It should be noted that, in the embodiment of the present application, the first pitch illustrated in fig. 2 refers to a pitch between an area where the edge gate line is located and an axis of an adjacent fine gate, and the embodiment of the present application is not limited to a specific meaning of the first pitch, for example, the first pitch may also be a distance between a side of the edge gate line near the first boundary and a side of the adjacent fine gate far from the first boundary, or a shortest distance between the edge gate line and the adjacent fine gate.
In some embodiments, the first spacing S1 ranges from 0.2mm to 0.7mm. The first distance ranges from 0.2mm to 0.35mm, from 0.35mm to 0.46mm, from 0.46mm to 0.58mm, from 0.58mm to 0.63mm, or from 0.63mm to 0.7mm.
In some embodiments, the distance S2 between the adjacent first fine grid 111 and the second fine grid 112 ranges from 0.3mm to 0.8mm. The distance S2 between the adjacent first fine grid 111 and second fine grid 112 ranges from 0.3mm to 0.35mm, from 0.35mm to 0.43mm, from 0.43mm to 0.5mm, from 0.5mm to 0.58mm, from 0.58mm to 0.66mm, from 0.66mm to 0.72mm or from 0.72mm to 0.8mm.
Referring to fig. 5, fig. 5 is another schematic structural diagram of a solar cell according to an embodiment of the present application, wherein an edge gate line 113 is electrically contacted with a first main gate 121, and the edge gate line 113 is electrically contacted with n 2 The second main gates 122 are electrically contacted; n is 1 < n 2 ≤m 2 ，n 1 、m 1 、n 2 M 2 Are natural numbers.
In some embodiments, the at least one edge gate line 113 includes: a first edge gate line 1131 and a second edge gate line 1132, the first edge gate line 1131 being located between the first boundary and the second fine gate 112, the first edge gate line 1131 being in electrical contact with the first main gate, the second edge gate line 1132 being located between the other first boundary and the first fine gate 111, the second edge gate line 1132 being in electrical contact with the second main gate. According to the embodiment of the application, the two edge grid lines 113 are arranged on the two first boundaries, so that the mutual communication between the first main grids and the mutual communication between the second main grids are realized, and the collection efficiency of the solar cell and the yield of the solar cell are improved.
In some embodiments, the first edge grid lines 1131 are electrically connected to each first main grid, the second edge grid lines 1132 are electrically connected to each second main grid, so that the collection efficiency of the solar cell can be improved by 3% -10%, and the reject ratio of the cell can be reduced by within 8%.
In some embodiments, a grid line is used to connect grid lines (positive electrode or negative electrode) with the same polarity in the solar cell in series, and the solar cell forms an integral electrode, so that a state that the first main grid and each first fine grid 111 are conducted mutually can be ensured, the probability of efficiency and yield reduction of the cell due to the problem of one of the first main grids can be avoided, and the first fine grids 111 located at the edge of the substrate can be collected to improve the collection efficiency of the cell due to the conducting state of the first fine grids 111. Likewise, the battery efficiency may be improved by improving the battery collection efficiency of the second fine grid 112.
In addition, the problem of poor appearance between the respective first main grids 121 and the first fine grids 111 due to the difference in manufacturing process can be avoided due to the on state. The mutual communication between the first main grids 121 and the mutual communication between the second main grids 122 can also avoid the problem of a decrease in battery efficiency due to the breakage of one of the thin grids 110 or the main grids 120.
In some embodiments, edge gate lines 113 and n 1 The first main gate 121 is electrically contacted; edge gate lines 113 and n 2 The second main gates 122 are electrically contacted; n is 1 < n 1 ＜m 1 ，1＜n 2 ＜m 2 . The partial connection grid lines are positioned in the battery, the connection grid lines realize the electrical connection between the remaining first main grids 121 and the electrical connection between the remaining second main grids 122, the solar battery realizes the electrical connection between the first main grids 121 and the first thin grids 111 through the edge grid lines 113 and the connection grid lines, and the solar battery realizes the electrical connection between the second main grids 122 and the second thin grids 112 through the edge grid lines 113 and the connection grid lines.
In some embodiments, fig. 6 is a layout diagram of a grid line in a solar cell according to an embodiment of the present application, and referring to fig. 6, m 1 ≥8，m 2 The number of the first main grids is 8, the number of the second main grids is 8, and the number of the main grids is 16.
In some embodiments, the number of first primary gates may be a natural number greater than 8 and the number of second primary gates may be a natural number greater than 8.
The embodiment of the application provides a solar cell, the solar cell includes an edge grid line 113, the edge grid line 113 is electrically contacted with a first main grid 121, and/or the edge grid line 113 is electrically contacted with a second main grid 122, one grid line is used to connect grid lines (positive electrode or negative electrode) with the same polarity in the solar cell in series, and one solar cell forms an integral electrode, so that the first main grid 121 and each first fine grid 111 are in a mutually conducting state, thereby avoiding the probability of decreasing the efficiency and yield of the cell due to the problem of one of the first main grids 121, and the first fine grids 111 in the conducting state can also collect the first fine grids 111 positioned at the edge of a substrate to improve the collection efficiency of the cell. Likewise, the battery efficiency may be improved by improving the battery collection efficiency of the second fine grid 112.
In addition, the problem of poor appearance between the respective first main grids 121 and the first fine grids 111 due to the difference in manufacturing process can be avoided due to the on state. The mutual communication between the first main grids 121 and the mutual communication between the second main grids 122 can also avoid the problem of a decrease in battery efficiency due to the breakage of one of the thin grids 110 or the main grids 120.
Correspondingly, another aspect of the embodiments of the present application further provides a photovoltaic module, which may include the solar cell provided in the foregoing embodiments, and the technical features of the solar cell are the same as or corresponding to those of the foregoing embodiments, and are not described in detail herein.
Fig. 7 is a schematic structural diagram of a photovoltaic module according to another embodiment of the present disclosure; FIG. 8 is a schematic cross-sectional view of the structure of FIG. 7 along the line M1-M2; fig. 9 is a schematic structural diagram of a solar cell in a photovoltaic module according to another embodiment of the present disclosure.
Referring to fig. 7 to 9, according to some embodiments of the present application, another aspect of embodiments of the present application further provides a photovoltaic module, including: a cell string formed by connecting a plurality of solar cells 20 according to any one of the above embodiments; the solar cell includes an edge grid line 113, a first main grid 121, and a second main grid 122; a connection part 209, the connection part 209 being for electrically connecting the first main grid 121 and the second main grid 122 of the adjacent two solar cells 20; a packaging adhesive film 27 for covering the surface of the battery string; and a cover plate 28 for covering the surface of the packaging adhesive film facing away from the battery strings.
Specifically, in some embodiments, the plurality of battery strings may be electrically connected by a connection member 209, and the connection member 209 is soldered to the main grid on the battery plate. For example, one end of the connection member is electrically connected to the first main gate of the first battery cell, and the other end of the connection member is electrically connected to the second main gate of the adjacent second battery cell.
In some embodiments, no space is provided between the battery cells, i.e., the battery cells overlap each other.
In some embodiments, the connection member is welded to the fine grid on the battery plate.
In some embodiments, referring to fig. 9, the solar cell has solder joints 108 thereon for effecting soldering between the connection members 209 and the main grid.
In some embodiments, referring to fig. 8, the photovoltaic module further comprises: and an insulating film 206, wherein the insulating film 206 covers part of the surface of the solar cell 20, for example, the insulating film 206 covers part of the surface of the first main grid and part of the surface of the first thin grid, so that when the connecting component is electrically connected with the second main grid, the electric insulation between the second main grid and the first main grid is realized, the surface of the welding point 108 is exposed by the insulating film 206, and the insulating film is also positioned between the connecting component 209 and the solar cell, thereby realizing the welding between the connecting component and the corresponding main grid, avoiding the condition that the connecting component is electrically contacted with the main grid with the other polarity, and further improving the yield. For example, the connection member is soldered to the first main gate, and the insulating film electrically insulates the connection member from the second main gate.
In some embodiments, the packaging adhesive film 27 includes a first packaging adhesive film and a second packaging adhesive film, wherein the first packaging adhesive film covers one of the front surface or the back surface of the solar cell, and the second packaging adhesive film covers the other of the front surface or the back surface of the solar cell, specifically, at least one of the first packaging adhesive film or the second packaging adhesive film may be an organic packaging adhesive film such as a polyvinyl butyral (Polyvinyl Butyral, abbreviated as PVB) adhesive film, an ethylene-vinyl acetate copolymer (EVA) adhesive film, a polyethylene octene co-elastomer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film.
It should be noted that, the first packaging film and the second packaging film have a parting line before the lamination process, and the concept of forming the photovoltaic module after the lamination process does not have the first packaging film and the second packaging film any more, that is, the first packaging film and the second packaging film have formed the integrated packaging film 27.
In some embodiments, the cover 28 may be a glass cover, a plastic cover, or the like having a light-transmitting function. Specifically, the surface of the cover plate 28 facing the packaging film 27 may be a concave-convex surface, so as to increase the utilization rate of incident light. The cover plate 28 includes a first cover plate and a second cover plate, the first cover plate is opposite to the first packaging adhesive film, and the second cover plate is opposite to the second packaging adhesive film; or the first cover plate is opposite to one side of the solar cell, and the second cover plate is opposite to the other side of the solar cell.
In some embodiments, further comprising: an electrical connection line; edge grid line and n 1 The first main grids are electrically contacted, and the edge grid lines are electrically connected with the second main grids of the adjacent solar cells through electrical connection wires; alternatively, the edge gate line and n 2 The second main grids are electrically contacted, and the edge grid lines are electrically connected with the first main grids of the adjacent solar cells through electrical connection wires. Therefore, the mutual communication between the two solar cells can be realized by utilizing the electric connection wire, so that the yield of the photovoltaic module is improved, and the problem of yield reduction caused by the occurrence of cold joint of one of the connection parts is effectively avoided.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the present application and that various changes in form and details may be made therein without departing from the spirit and scope of the present application. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention shall be defined by the appended claims.
Claims (13)
1. A solar cell, comprising:
a substrate and a passivation layer on the substrate, the substrate having two first boundaries opposing in a first direction;
The thin grid penetrates through the passivation layer and is electrically connected with the substrate; the fine grids comprise first fine grids and second fine grids which are alternately arranged along the first direction;
a plurality of lines arranged in the second directionA main grid arranged on the surface of the passivation layer and electrically contacted with the fine grid, wherein the main grid comprises m alternately arranged along the second direction 1 First main grid and m 2 A second main gate, the first main gate being in electrical contact with the first fine gate, the second main gate being in electrical contact with the second fine gate; the first main grid is one of an anode electrode or a cathode electrode, and the second main grid is the other of the anode electrode or the cathode electrode;
at least one edge gate line extending along the second direction, the edge gate line being adjacent to the first boundary, the edge gate line of a partial region penetrating the passivation layer and electrically connected to the substrate, the edge gate line being connected to n 1 -said first main gate electrical contacts; and/or the edge grid line and n 2 -said second main gate electrical contacts; wherein 1 < n 1 ≤m 1 ，1＜n 2 ≤m 2 ，n 1 、m 1 、n 2 M 2 Are natural numbers.
2. The solar cell of claim 1, wherein at least one edge grid line comprises: the first edge grid line is positioned between the first boundary and the second thin grid, the first edge grid line is electrically contacted with the first main grid, the second edge grid line is positioned between the other first boundary and the first thin grid, and the second edge grid line is electrically contacted with the second main grid.
3. The solar cell according to claim 1, comprising: one of the edge gate lines is in electrical contact with the first main gate or the edge gate line is in electrical contact with the second main gate.
4. The solar cell according to claim 1 or 2, wherein the first fine grid comprises a plurality of first sub-grid lines arranged along the second direction, a passivation layer between two adjacent first sub-grid lines forms a first spacer, the second main grid is located on the first spacer, and the first main grid is in electrical contact with the first sub-grid lines; the second fine grid comprises a plurality of second sub-grid lines which are arranged along the second direction, a passivation layer between two adjacent second sub-grid lines forms a second interval region, and the first main grid is positioned on the second interval region; the second main gate is in electrical contact with the second sub-gate line.
5. The solar cell of claim 1, wherein a width of the edge grid line along the first direction is greater than or equal to a width of the thin grid along the first direction.
6. The solar cell of claim 5, wherein a width of the edge grid line along the first direction comprises: 10um to 55um.
7. The solar cell of claim 1, wherein a pitch of the edge grid line to the adjacent fine grid is a first pitch that is less than or equal to a distance between the adjacent first fine grid and the second fine grid.
8. The solar cell of claim 7, wherein the first pitch ranges from 0.2mm to 0.7mm.
9. The solar cell according to claim 7, wherein a distance between the adjacent first and second fine grids ranges from 0.3mm to 0.8mm.
10. The solar cell of claim 1, wherein the edge grid lines are of the same material as the fine grid.
11. The solar cell of claim 1, wherein the edge grid line is aligned with n 1 Each of the first main grids is electrically connected withTouching; the edge grid line and n 2 -said second main gate electrical contacts; n is 1 < n 1 ＜m 1 ，1＜n 2 ＜m 2 。
12. A photovoltaic module, comprising:
a cell string formed by connecting a plurality of solar cells according to any one of claims 1 to 11; the solar cell comprises an edge grid line, a first main grid and a second main grid;
a connection member for electrically connecting the first and second main grids of two adjacent solar cells;
The packaging adhesive film is used for covering the surface of the battery string;
and the cover plate is used for covering the surface of the packaging adhesive film, which is away from the battery strings.
13. The photovoltaic module of claim 12, further comprising: an electrical connection line; the edge grid line and n 1 The first main grids are electrically contacted, and the electric connecting wires are electrically connected with the edge grid lines and the second main grids of the adjacent solar cells; alternatively, the edge gate line is connected with n 2 And the second main grids are electrically contacted, and the electric connecting wires are electrically connected with the edge grid lines and the first main grids of the adjacent solar cells.
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