CN117727685A - Method for filling trench formed in semiconductor substrate - Google Patents
Method for filling trench formed in semiconductor substrate Download PDFInfo
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- CN117727685A CN117727685A CN202311200590.8A CN202311200590A CN117727685A CN 117727685 A CN117727685 A CN 117727685A CN 202311200590 A CN202311200590 A CN 202311200590A CN 117727685 A CN117727685 A CN 117727685A
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 title claims abstract description 38
- 238000011049 filling Methods 0.000 title claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 106
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 106
- 239000010703 silicon Substances 0.000 claims abstract description 106
- 238000000151 deposition Methods 0.000 claims abstract description 101
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 52
- 229920005591 polysilicon Polymers 0.000 claims abstract description 52
- 230000008021 deposition Effects 0.000 claims description 50
- 238000011065 in-situ storage Methods 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 12
- 230000007704 transition Effects 0.000 claims 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 13
- 239000000463 material Substances 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000001953 recrystallisation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000000708 deep reactive-ion etching Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- -1 for example Inorganic materials 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
The present disclosure relates to a method of filling a trench formed in a semiconductor substrate. Embodiments provide a method of forming a semiconductor device. A first silicon layer is deposited as an amorphous layer in a trench of a semiconductor substrate. A second silicon layer is deposited on top of and in contact with the first silicon layer as a polysilicon layer. After depositing the second silicon layer, the first silicon layer comprises polysilicon having an average grain size that is different from an average grain size of the second silicon layer. A third semiconductor layer is deposited on top of and in contact with the second silicon layer to at least partially fill the trench.
Description
Cross Reference to Related Applications
The present application claims the benefit of french application No.2209435 filed at 2022, 9, 19, which is incorporated herein by reference.
Technical Field
The present disclosure relates generally to the field of semiconductor devices and methods of manufacturing the same.
Background
Various electronic devices have been provided that include vertically extending trenches in a semiconductor substrate that are partially or completely filled with polysilicon.
Such trenches are used, for example, for forming insulating walls that laterally separate different elements of an integrated circuit, for example different pixels of an image sensor or different basic memory cells of a memory circuit, or also for forming vertical electronic elements such as vertical transistors or vertical capacitors.
The difficulty is that filling the trench with polysilicon may cause strong mechanical stresses on the substrate, which may cause problems during device fabrication.
It is desirable to overcome all or part of the disadvantages of known methods of filling trenches formed in a semiconductor substrate with polysilicon.
Disclosure of Invention
Embodiments provide a method of filling a trench formed in a semiconductor substrate. This embodiment may include the steps of: a) Depositing a first silicon layer on the side wall and the bottom of the groove under the amorphous deposition condition; b) Depositing a second silicon layer on top of and in contact with the first layer under polycrystalline deposition conditions; and c) depositing a third doped silicon layer on top of and in contact with the second layer under amorphous deposition conditions to completely fill the trench. At the end of step b), the first layer is made of polysilicon with a grain size different from that of the second layer.
According to one embodiment, under the influence of the deposition conditions of the second layer, the silicon of the first layer crystallizes and changes from amorphous to polycrystalline during the deposition of the second layer.
According to an embodiment, the method comprises an intermediate annealing step between step a) and step b), during which the silicon of the first layer crystallizes and changes from amorphous to polycrystalline.
According to one embodiment, at the end of step c), the first silicon layer is in tension and the second silicon layer is in compression.
According to one embodiment, the second silicon layer is deposited in situ in the same deposition chamber as the first silicon layer without removing the substrate from the chamber between depositions.
According to one embodiment, the method comprises a step of depositing a dielectric layer at the sidewalls and bottom of the trench prior to step a).
According to one embodiment, in step a), a first silicon layer is deposited on top of and in contact with the dielectric layer.
According to one embodiment, the first silicon layer is doped in situ during its deposition.
According to one embodiment, the method comprises a step of thinning the substrate from the surface of the substrate opposite the trench between step b) and step c).
According to one embodiment, the method comprises a rapid thermal annealing step between the thinning step and step c).
Another embodiment provides an electronic device including a trench disposed in a semiconductor substrate. The first polysilicon layer covers the sidewalls and bottom of the trench and the second polysilicon layer is located on top of and in contact with the first layer. A third doped silicon layer is located on top of and in contact with the second layer. The third layer completes the complete filling of the trench. The polysilicon of the first layer has a different grain size than the polysilicon of the second layer.
According to an embodiment, the polysilicon of the first layer has an average grain size in the range of 50 to 120nm, and the polysilicon of the second layer has an average grain size in the range of 10 to 30 nm.
Drawings
The foregoing and other features and advantages will be described in detail in the remainder of the disclosure of the specific embodiments presented by way of illustration and not limitation with reference to the accompanying drawings wherein:
fig. 1A is a cross-sectional view of a semiconductor structure showing steps of an example of a method of filling a trench according to an embodiment;
fig. 1B is a cross-sectional view of a semiconductor structure showing steps of an example of a method of filling a trench according to an embodiment;
fig. 1C is a cross-sectional view of a semiconductor structure showing steps of an example of a method of filling a trench according to an embodiment;
fig. 1D is a cross-sectional view of a semiconductor structure showing steps of an example of a method of filling a trench according to an embodiment;
fig. 1E is a cross-sectional view of a semiconductor structure showing steps of an example of a method of filling a trench according to an embodiment;
fig. 1F is a cross-sectional view of a semiconductor structure showing steps of an example of a method of filling a trench according to an embodiment;
fig. 2A is a cross-sectional view of a semiconductor structure showing steps of an example of a method of filling a trench according to an embodiment; and
fig. 2B is a cross-sectional view of a semiconductor structure illustrating steps of an example of a method of filling a trench according to an embodiment.
Detailed Description
Like features are denoted by like reference numerals throughout the various figures. In particular, structural and/or functional features common in the various embodiments may have the same reference numerals.
For clarity, only the steps and elements useful for understanding the embodiments described herein are shown and described in detail. In particular, only the formation of trenches for electronic devices is described in detail. Other elements of the electronic device are not described in detail, and the described embodiments are compatible with all or most of the known embodiments of electronic devices including trenches filled with polysilicon.
Unless otherwise indicated, when referring to two elements being connected together, this means that there is no direct connection of any intermediate element other than a conductor, and when referring to two elements being connected together, this means that the two elements may be connected or they may be coupled via one or more other elements.
In the following disclosure, when referring to absolute positional qualifiers, such as the terms "front", "rear", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "upper", "lower", etc., or orientation qualifiers, such as "horizontal", "vertical", etc., reference is made to the orientation of the drawings unless otherwise indicated.
Unless otherwise indicated, the expressions "about", "substantially" and "on the order of …" mean within 10%, preferably within 5%.
Fig. 1A to 1F are partially simplified cross-sectional views showing successive steps of an example of a trench filling method according to an embodiment.
Fig. 1A shows a structure obtained at the end of the step of forming the trench 101 in the semiconductor substrate 103. The trenches may extend vertically downwards from the surface of the substrate (the upper surface in the example shown) to a depth less than the thickness of the substrate 103, for example to a depth in the range from 1 to 50 μm, or for example from 2 to 15 μm, or for example on the order of 6 μm.
The width of the trench 101 may be, for example, in the range from 0.1 μm to 2 μm, or, for example, on the order of 600 nm.
The substrate 103 may be made of, for example, silicon, for example, single crystal silicon. However, the described embodiments are not necessarily limited to this particular case and may be applied to substrates made of other semiconductor materials, including or not including silicon.
In the example shown, the upper surface of the substrate may be coated with a dielectric passivation layer 105, for example made of silicon nitride. Trench 103 may extend through layer 105.
The trench 101 may be formed, for example, by photolithography followed by etching, for example, by a plasma etching method, or by a DRIE ("deep reactive ion etching") type method, for example.
Fig. 1B shows the structure obtained on the sidewalls and bottom of the trench 101 at the end of an optional step of depositing a layer or liner 107 of dielectric material (e.g., silicon oxide). In this example, layer 107 may be used to electrically insulate the semiconductor material of the substrate from polysilicon subsequently deposited in the trench. In this example, the layer 107 may be in contact with the material of the substrate 103 on the sidewalls and bottom of the trench 101. Layer 107 may be deposited over the entire upper surface of substrate 103, for example, by a conformal deposition method. Thus, in the example shown, layer 107 may further extend over an upper surface of dielectric layer 105. The thickness of the dielectric layer 107 may be, for example, in the range of 2nm to 200 nm.
Fig. 1C shows the structure obtained at the end of the step of depositing an amorphous silicon layer 109 on the sidewalls and bottom of the trench 101. In this example, layer 109 may be deposited on top of the upper surface of dielectric layer 107 and in contact with the upper surface of dielectric layer 107. Layer 109 may be deposited on the entire upper surface of substrate 103, for example, by a conformal deposition method. The thickness of the amorphous silicon layer 109 may be, for example, in the range of 50 to 500nm, or, for example, on the order of 150 nm.
Preferably, layer 109 may be doped in-situ during its deposition. The doping may be P-type or N-type. For example, the doping may be boron or phosphorus doping. The doping level of layer 109 may be, for example, 1×10 18 Atoms/cm 3 to 1X 10 22 Atoms/cm 3 Within a range of (2).
The deposition may be performed, for example, at a temperature below 600 ℃, or for example, in the range of 400 to 580 ℃, to obtain amorphous silicon of layer 109 at the end of the deposition.
Fig. 1D shows the structure obtained at the end of the step of depositing in situ a polysilicon layer 111 on the sidewalls and on the bottom of the trench 101 after deposition of the layer 109. In this example, layer 111 may be deposited on top of and in contact with the upper surface of amorphous silicon layer 109. Layer 111 may be deposited on the entire upper surface of substrate 103, for example, by a conformal deposition method. The thickness of the polysilicon layer 111 may be, for example, in the range of 50 to 500nm, or, for example, on the order of 130 nm.
For example, layer 111 may be undoped (e.g., unintentionally doped). As a variant, layer 111 may be doped in situ during its deposition. The doping may then be P-type or N-type. For example, the doping may be boron or phosphorus doping. The doping level of layer 111 may be, for example, 1×10 18 Atoms/cm 3 to 1X 10 22 Atoms/cm 3 Within a range of (2).
The deposition may be carried out, for example, at a temperature higher than 580 ℃, or for example, between 600 and 700 ℃, to obtain a polycrystalline state of the deposited silicon.
By in situ deposition it is meant herein that layer 111 may be deposited in the same deposition chamber as used for the deposition of layer 109 in the step of fig. 1C without the need to take the structure out of the chamber between the deposition of layer 109 and the deposition of layer 111.
In this example, no intermediate anneal is provided between the deposition of layer 109 and the deposition of layer 111, so that the silicon of layer 109 may still be amorphous at the beginning of the deposition step of layer 111.
The temperature in the chamber during deposition of layer 111 may cause in situ recrystallization of amorphous silicon layer 109. Thus, during deposition of the polysilicon layer 111, the amorphous silicon layer 109 may be converted to polysilicon.
The polysilicon of layer 109 obtained by in situ recrystallization of the amorphous silicon deposited in the previous step may be tensile, i.e. it may exert a tensile force (stretching) on the material of substrate 103, which is parallel to the plane of layer 109. The polysilicon of layer 111, which is directly obtained by deposition under polycrystalline deposition conditions, may be compressed, i.e. it may exert a compressive force on the material of substrate 103 parallel to the plane of layer 111. Thus, the tensile force exerted by layer 109 may be at least partially compensated by the compressive force exerted by layer 111, which can limit or reduce deformation of substrate 103 previously associated with filling of trench 101. For example, the polysilicon layer of layer 109 may exert a tensile force in the range of 100 to 500MPa, while the polysilicon of layer 111 may exert a compressive force in the range of 100 to 500 MPa. It should be noted that these values may depend on the thermal budget applied, the dopant chemistry and doping level, and the deposition thickness. Furthermore, the influence of the deformation of the plate may vary depending on the density of the grooves of each wafer and the depth thereof.
It should be noted that in practice, at the end of the method, the polysilicon layers 109 and 111 may have different grain sizes due to their different formation conditions (amorphous deposition and recrystallization of layer 109 to polysilicon, polycrystalline deposition of layer 111). For example, layer 109 may have an average grain size that is greater than layer 111. For example, the polysilicon of layer 111 may have an average grain size ranging from 10 to 30nm, such as columnar growth. The recrystallized amorphous silicon of layer 109 may have an average grain size ranging from 50 to 120nm, for example, with a random grain distribution. These grain sizes and arrangements may fluctuate depending on thermal budget, dopant chemistry and its concentration, deposition surface, etc.
Fig. 1E shows the structure obtained at the end of the step of filling the trench 101 with the doped amorphous silicon layer 113. For example, layer 113 may be deposited over and in contact with the upper surface of polysilicon layer 111. Layer 113 may be deposited, for example, on the entire upper surface of substrate 103. The thickness of the amorphous silicon layer 113 may be selected to be high enough to complete the complete filling of the trench 101.
Preferably, layer 113 may be doped in situ during its deposition. The doping may be P-type or N-type. For example, the doping may be boron or phosphorus doping. The doping level of layer 113 may be, for example, 1×10 18 Atoms/cm 3 to 1X 10 22 Atoms/cm 3 Within a range of (2).
The deposition of layer 113 may be performed, for example, at a temperature below 600 ℃, or in the range of 400 to 580 ℃, for example, to obtain an amorphous state of silicon of layer 113 at the end of the deposition.
Fig. 1F shows the structure obtained at the end of the step of planarizing its upper surface, for example by chemical mechanical polishing. During this step, the structure may be thinned from its upper surface to remove portions of layers 113, 111, 109 and 107 coating the upper surface of substrate 103 to expose the upper surface of dielectric passivation layer 105. The thinning may be interrupted, for example, on the upper surface of the dielectric passivation layer 105.
An advantage of the method described in connection with fig. 1A to 1F may be that it enables to perform the filling of the trenches formed in the substrate while limiting the deformation of the substrate under the influence of the stress exerted by the trench filling material.
This may be particularly advantageous when the density of trenches at the substrate surface is significantly greater than 9%, for example, and especially when the trenches are deep (e.g., greater than 2 μm deep).
After the step of depositing polysilicon layer 111 and before depositing layer 113, a heat treatment, such as an RTP ("rapid thermal process") type anneal, may be advantageously performed to relax the strain of layers 109 and 111 before final filling with layer 113. The annealing may be carried out, for example, at a temperature in the range 800 ℃ to 1200 ℃, or, for example, on the order of 955 ℃. The duration of the annealing may be, for example, in the range of 2 seconds to 5 minutes.
In the example described in connection with fig. 1A-1E, the amorphous silicon layer 109 deposited in the step of fig. 1C may be converted to polysilicon during the step of depositing the polysilicon layer 111.
As a variant, an intermediate step of in-situ annealing of layer 109 may be performed prior to deposition of layer 111, resulting in the conversion of amorphous silicon of layer 109 to polysilicon. By in situ annealing, it is meant herein that annealing can be accomplished in the chamber used to perform the deposition in the step of fig. 1C without the need to remove the structure from the chamber between deposition and annealing. Annealing may be performed, for example, at a temperature above 560 ℃, or, for example, in the range of 580 ℃ to 900 ℃.
In-situ annealing of amorphous silicon layer 109 may in turn result in layer 109 being converted into a tensile polysilicon layer, i.e., exerting a tensile force (pulling) on the material of substrate 103, the tensile force being parallel to the plane of layer 109.
Polysilicon layer 111 may then be deposited in situ (in the same device) on polysilicon layer 109, the remainder of the method being the same as previously described, for example as another embodiment.
As shown in fig. 2A and 2B, as a modification, the upper surface of the intermediate structure shown in fig. 1D may be thinned between the deposition of layer 111 and the deposition of layer 113 by removing portions of layer 111, or removing portions of layer 111 and layer 109, or removing portions of layer 111, layer 109, and layer 107, as shown in fig. 2B.
The trenches formed by the above method may form, for example, insulating walls that laterally separate different elements of the integrated circuit; for example, different pixels of an image sensor or different basic memory cells of a memory circuit. As a variant, these trenches may form vertical electronic components such as vertical transistors or vertical capacitors.
Various embodiments and modifications have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined and that other variations will occur to those skilled in the art. In particular, the described embodiments are not necessarily limited to the above application examples.
Finally, based on the functional indications given above, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art.
Claims (25)
1. A method of forming a semiconductor device, the method comprising:
depositing a first silicon layer in a trench of a semiconductor substrate, the first silicon layer being deposited as an amorphous layer;
depositing a second silicon layer on top of and in contact with the first silicon layer, the second silicon layer being deposited as a polysilicon layer, wherein after depositing the second silicon layer, the first silicon layer comprises polysilicon having an average grain size that is different from an average grain size of the second silicon layer; and
a third semiconductor layer is deposited on top of and in contact with the second silicon layer to fill the trench.
2. The method of claim 1, wherein silicon of the first silicon layer crystallizes and transitions from an amorphous state to a polycrystalline state during deposition of the second silicon layer under the influence of deposition conditions of the second silicon layer.
3. The method of claim 1, further comprising: after depositing the first silicon layer and before depositing the second silicon layer, annealing the first silicon layer to crystallize the first silicon layer and to transform the first silicon layer from an amorphous state to a polycrystalline state.
4. The method of claim 1, wherein after depositing the third semiconductor layer, the first silicon layer is tensile and the second silicon layer is compressive.
5. The method of claim 1, wherein depositing the first silicon layer and depositing the second silicon layer comprises: the first silicon layer and the second silicon layer are deposited in situ in the same deposition chamber without removing the substrate from the chamber between depositing the first silicon layer and depositing the second silicon layer.
6. The method of claim 1, further comprising: a dielectric layer is deposited in the trench prior to depositing the first silicon layer.
7. The method of claim 6, wherein depositing the first silicon layer comprises: the first silicon layer is deposited on top of and in contact with the dielectric layer.
8. The method of claim 1, wherein the first silicon layer is doped in-situ while depositing the first silicon layer.
9. The method of claim 1, further comprising: after depositing the second silicon layer and before depositing the third semiconductor layer, the intermediate structure is thinned by removing a portion of an upper surface of the intermediate structure formed after depositing the second silicon layer.
10. The method of claim 9, further comprising: a rapid thermal anneal is performed after thinning the intermediate structure and before depositing the third semiconductor layer.
11. The method of claim 1, wherein the third semiconductor layer comprises a third doped silicon layer, and wherein depositing the third semiconductor layer comprises: the third doped silicon layer is deposited under amorphous deposition conditions.
12. The method of claim 1, wherein the first silicon layer comprises polysilicon having an average grain size that is greater than a grain size of the second silicon layer.
13. The method of claim 12, wherein an average grain size of the first silicon layer is in a range of 50 to 120nm and an average grain size of the second silicon layer is in a range of 10 to 30 nm.
14. A semiconductor device, comprising:
a semiconductor substrate having a trench disposed therein;
a dielectric layer contacting sidewalls and bottom of the trench;
a first polysilicon layer over and in contact with the dielectric layer;
a second polysilicon layer over and in contact with the first polysilicon layer, wherein an average grain size of the second polysilicon layer is different from an average grain size of the second polysilicon layer; and
a third doped silicon layer over and in contact with the second polysilicon layer, the third doped silicon layer completely filling the trench.
15. The device of claim 14, wherein an average grain size of the first polysilicon layer is in a range of 50 to 120nm and an average grain size of the second polysilicon layer is in a range of 10 to 30 nm.
16. The device of claim 14, wherein the first polysilicon layer is tensile and the second polysilicon layer is compressive.
17. A method of forming a semiconductor device, the method comprising:
depositing a dielectric layer on sidewalls and bottom of the trench of the semiconductor substrate;
depositing a first silicon layer on the dielectric layer, the first silicon layer being deposited as an amorphous layer under amorphous deposition conditions;
depositing a second silicon layer in contact with the first silicon layer, the second silicon layer being deposited as a polysilicon layer under polysilicon deposition conditions, wherein upon deposition of the second silicon layer, the silicon of the first silicon layer crystallizes and transitions from amorphous to polycrystalline such that the first silicon layer comprises polysilicon having an average grain size that is different from an average grain size of the second silicon layer; and
a third semiconductor layer is deposited in contact with the second silicon layer to fill the trench, the third semiconductor layer being deposited under amorphous deposition conditions.
18. The method of claim 17, wherein after depositing the third semiconductor layer, the first silicon layer is tensile and the second silicon layer is compressive.
19. The method of claim 17, wherein depositing the first silicon layer and depositing the second silicon layer comprises: the first silicon layer is deposited and then the second silicon layer is deposited in the same deposition chamber without removing the substrate from the chamber between depositing the first silicon layer and depositing the second silicon layer.
20. The method of claim 17, further comprising: after depositing the second silicon layer and before depositing the third semiconductor layer, the intermediate structure is thinned by removing a portion of an upper surface of the intermediate structure formed after depositing the second silicon layer.
21. The method of claim 17, wherein an average grain size of the first silicon layer is in a range of 50 to 120nm and an average grain size of the second silicon layer is in a range of 10 to 30 nm.
22. A method of forming a semiconductor device, the method comprising:
depositing a dielectric layer on the side wall and the bottom of the trench of the semiconductor substrate;
depositing a first silicon layer over the dielectric layer, the first silicon layer being deposited as an amorphous layer under amorphous deposition conditions;
annealing the first silicon layer to crystallize and convert the first silicon layer from an amorphous state to a polycrystalline state after depositing the first silicon layer;
depositing a second silicon layer in contact with the first silicon layer after annealing the first silicon layer, the second silicon layer being deposited as a polysilicon layer under polysilicon deposition conditions, wherein the second silicon layer comprises polysilicon having an average grain size that is different from an average grain size of the first silicon layer; and
a third semiconductor layer is deposited in contact with the second silicon layer to at least partially fill the trench, the third semiconductor layer being deposited under amorphous deposition conditions.
23. The method of claim 22, wherein after depositing the third semiconductor layer, the first silicon layer is tensile and the second silicon layer is compressive.
24. The method of claim 22, further comprising: after depositing the second silicon layer and before depositing the third semiconductor layer, the intermediate structure is thinned by removing a portion of an upper surface of the intermediate structure formed after depositing the second silicon layer.
25. The method of claim 22, wherein an average grain size of the first silicon layer is in a range of 50 to 120nm and an average grain size of the second silicon layer is in a range of 10 to 30 nm.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR2209435 | 2022-09-19 | ||
| US18/466,542 | 2023-09-13 | ||
| US18/466,542 US20240096620A1 (en) | 2022-09-19 | 2023-09-13 | Method of filling a trench formed in a semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117727685A true CN117727685A (en) | 2024-03-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311200590.8A Pending CN117727685A (en) | 2022-09-19 | 2023-09-18 | Method for filling trench formed in semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117727685A (en) |
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- 2023-09-18 CN CN202311200590.8A patent/CN117727685A/en active Pending
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