CN117724018A

CN117724018A - Circuit and electronic device for magnetic field detection

Info

Publication number: CN117724018A
Application number: CN202311618397.6A
Authority: CN
Inventors: 王敏; 朱永成; 黄金煌
Original assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Current assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority date: 2023-11-29
Filing date: 2023-11-29
Publication date: 2024-03-19

Abstract

The application relates to field intensity detection field discloses a circuit for magnetic field detection, include: a carrier amplifying circuit configured to receive a carrier signal of the antenna end, and to amplify the carrier signal to output an ac amplified carrier signal; an envelope detection circuit, connected to the carrier amplifying circuit, configured to convert the ac amplified carrier signal into a dc amplified carrier signal; and the quantization circuit is connected with the envelope detection circuit and is configured to compare and quantize the direct current amplified carrier signal with a preset signal value so as to detect a magnetic field. The circuit can more accurately detect the tiny magnetic field change condition, thereby improving the sensitivity of magnetic field detection. The application also discloses electronic equipment.

Description

Circuit and electronic device for magnetic field detection

Technical Field

The present application relates to the field of field strength detection, for example to a circuit and an electronic device for magnetic field detection.

Background

Currently, some electronic devices need to first enter a listening mode in the process of establishing communication, detect the existence of an external magnetic field, and wake the electronic device to start working once the existence of the magnetic field is detected.

In order to detect the presence or absence of an external magnetic field, the related art discloses a magnetic field detection method including: and acquiring the voltage amplitude of the antenna end, and judging whether the external field intensity exists by judging whether the carrier amplitude of the antenna end exceeds a fixed reference amplitude.

In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art: the related art requires that the antenna carrier amplitude exceeds a fixed reference amplitude to operate, and thus is not applicable in a scenario of detecting a low field strength small carrier amplitude due to low sensitivity.

It should be noted that the information disclosed in the foregoing background section is only for enhancing understanding of the background of the present application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.

The embodiment of the disclosure provides a circuit and electronic equipment for magnetic field detection, so as to improve the sensitivity of the magnetic field detection circuit.

In some embodiments, a circuit for magnetic field detection includes: a carrier amplifying circuit configured to receive a carrier signal of the antenna end, and to amplify the carrier signal to output an ac amplified carrier signal; an envelope detection circuit, connected to the carrier amplifying circuit, configured to convert the ac amplified carrier signal into a dc amplified carrier signal; and the quantization circuit is connected with the envelope detection circuit and is configured to compare and quantize the direct current amplified carrier signal with a preset signal value so as to detect a magnetic field.

Optionally, the carrier amplifying circuit includes: the in-phase input end of the operational amplification unit is connected with the common mode voltage, the output end of the operational amplification unit is connected with the envelope detection circuit, and the operational amplification unit is configured to amplify the carrier signal according to the common mode voltage; and the gain adjusting sub-circuit is connected with the antenna end at a first end and the inverting input end and the output end of the operational amplifying unit at a second end respectively and is configured to adjust the amplification gain multiple of the operational amplifying unit.

Optionally, the gain adjustment subcircuit includes: the first direct current isolation unit is connected with the antenna end and is configured to filter a carrier signal so as to eliminate direct current interference; and the negative feedback unit is connected with the first direct current isolation unit at a first end, is connected with the inverting input end and the output end of the operational amplification unit at a second end respectively, and is configured to adjust the amplification gain of the filtered carrier signal.

Optionally, the negative feedback unit includes: the first end of the first resistor is connected with the first DC isolation unit, the second end of the first resistor is connected with the inverting input end of the operational amplification unit and is configured to return the alternating current amplified carrier signal output by the output end of the operational amplification unit to the inverting input end of the operational amplification unit; and the first end of the second resistor is connected with the inverting input end of the operational amplifier unit, the second end of the second resistor is connected with the output end of the operational amplifier, and the second resistor is configured to adjust the amplification gain multiple of the carrier amplifying circuit by adjusting the resistance value of the second resistor.

Optionally, the envelope detection circuit includes: the second direct current isolation unit is connected with the output end of the carrier amplifying circuit and is configured to filter the alternating current amplified carrier signal so as to eliminate direct current interference; and the first end of the rectifier circuit is connected with the second DC isolation unit, the second end of the rectifier circuit is connected with the quantization circuit, and the rectifier circuit is configured to convert the filtered AC amplified carrier signal into a DC amplified carrier signal for output.

Optionally, the commutator circuit comprises: the grid electrode of the transistor is respectively connected with the second DC isolation unit and the common mode voltage and is grounded in situ; the first end of the filtering unit is connected with the source electrode of the transistor, the second end of the filtering unit is connected with the drain electrode of the transistor and is configured to filter high-frequency and low-frequency clutters of signals output by the transistor so as to output direct-current amplified carrier signals; and a current source connected to the drain of the transistor and configured to supply a current to the transistor.

Optionally, the quantization circuit includes: and the comparison unit is provided with a first input end connected with the output end of the envelope detection circuit, a second input end connected with a preset signal and configured to compare the direct current amplified carrier signal output by the envelope detection circuit with the preset signal value of the second input end and to output the quantized comparison result so as to determine the magnetic field detection result.

Optionally, the circuit for magnetic field detection further comprises: and the output end of the timing circuit is connected with the carrier amplifying circuit and is configured to generate a periodic pulse signal so as to enable the carrier amplifying circuit to be turned on or turned off.

Optionally, the circuit for magnetic field detection further comprises: and the signal selection circuit is respectively connected with the antenna end, the output end of the carrier amplifying circuit and the output end of the timing circuit, and the output end of the signal selection circuit is connected with the output end of the envelope detection circuit and is configured to select and output the carrier signal of the antenna end or the amplified carrier signal output by the carrier amplifying circuit according to the periodic pulse signal generated by the timing circuit.

In some embodiments, an electronic device includes: an electronic device body; the circuit for detecting a magnetic field as described above is mounted on the electronic device body.

The circuit and the electronic device for magnetic field detection provided by the embodiment of the disclosure can realize the following technical effects:

the carrier signal of the antenna end is amplified and converted into a direct current amplified carrier signal, and then the direct current amplified carrier signal is compared and quantified with a preset signal value, so that the intensity of the carrier signal is increased, and the existence of a magnetic field can be accurately detected in a scene with lower field intensity or smaller carrier amplitude. Thus, the tiny magnetic field change condition can be detected more accurately, and the sensitivity of magnetic field detection is improved.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:

FIG. 1 is a circuit for magnetic field detection provided by an embodiment of the present disclosure;

fig. 2 is a schematic diagram of a carrier amplifying circuit according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of an envelope detection circuit provided by an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of another circuit for magnetic field detection provided by an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of another circuit for magnetic field detection provided by an embodiment of the present disclosure;

fig. 6 is a schematic diagram of an electronic device provided by an embodiment of the present disclosure.

Reference numerals:

1. a circuit for magnetic field detection; 100. an electronic device; 200. an electronic device body;

10. a carrier amplifying circuit; 101. an operational amplification unit; 102. a gain adjustment sub-circuit; 1021. a first DC blocking unit; 1022. a negative feedback unit; 1221. a first resistor; 1222. a second resistor;

20. an envelope detection circuit; 201. a second DC blocking unit; 202. a rectifier circuit; 2021. a transistor; 2022. a filtering unit; 2023. a current source; 2024. a third resistor;

30. a quantization circuit; 301. a comparison unit;

40. a timing circuit;

50. a signal selection circuit;

60. an antenna end;

70. a common mode voltage terminal;

80. a power supply voltage terminal;

90. and a reference signal terminal.

Detailed Description

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.

The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

The term "plurality" means two or more, unless otherwise indicated.

In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are a "proportional" relationship.

The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.

It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

In the embodiment of the disclosure, a circuit for magnetic field detection is applied to an electronic device with an NFC function. Among them, NFC (Near Field Communication ) is a short-range wireless communication technology with an operating frequency of 13.56MHz. The electronic equipment with the NFC function can perform non-contact point-to-point data transmission, conveniently and safely complete information exchange and access of contents and services, and is widely applied to the fields of access control, public transportation, mobile phone payment and the like.

As shown in connection with fig. 1, an embodiment of the present disclosure provides a circuit 1 for magnetic field detection. The circuit 1 for magnetic field detection includes a carrier amplifying circuit 10, an envelope detecting circuit 20, and a quantizing circuit 30. The carrier amplifying circuit 10 is configured to receive the carrier signal of the antenna terminal 60, and to amplify the carrier signal to output an ac amplified carrier signal. The envelope detection circuit 20 is connected to the carrier amplification circuit 10 and is configured to convert an ac amplified carrier signal into a dc amplified carrier signal. The quantization circuit 30 is connected to the envelope detection circuit 20 and is configured to compare and quantize the dc amplified carrier signal with a preset signal value for magnetic field detection.

Wherein, the frequency corresponding to the carrier signal is 13.56MHz. The carrier signal includes a carrier voltage.

Illustratively, the envelope detection circuit 20 converts the ac amplified carrier signal to a dc amplified carrier signal with a conversion gain of 1. Wherein, conversion gain means: the envelope detection circuit 20 converts the ac amplified carrier signal into a dc amplified carrier signal, and outputs a ratio between the dc signal amplitude and the ac signal amplitude. For example, the amplitude of the input ac signal is X, the amplitude of the output dc signal is Y, and the conversion gain is Y/X. A conversion gain of 1 is understood to mean that the amplitude of the output dc signal is equal to the amplitude of the input ac signal. That is, the envelope detection circuit 20 converts the input ac signal into a dc signal without causing loss or change.

In the disclosed embodiment, the intensity of the carrier signal is increased by amplifying and converting the carrier signal of the antenna end 60 into a dc amplified carrier signal and comparing and quantifying the dc amplified carrier signal with a preset signal value, so that the presence of the magnetic field can be detected more accurately in a scene with a lower field strength or a smaller carrier amplitude. Thus, the tiny magnetic field change condition can be detected more accurately, and the sensitivity of magnetic field detection is improved.

Alternatively, as shown in fig. 2, the carrier amplifying circuit 10 includes an operational amplifying unit 101 and a gain adjusting sub-circuit 102. The operational amplification unit 101 has an in-phase input terminal connected to the common mode voltage and an output terminal connected to the envelope detection circuit 20 and is configured to amplify the carrier signal in accordance with the common mode voltage. The gain adjustment sub-circuit 102 has a first end connected to the antenna end 60 and a second end connected to the inverting input and output ends of the operational amplification unit 101, respectively, and is configured to adjust the amplification gain of the operational amplification unit 101.

Wherein the common mode voltage is provided by common mode voltage terminal 70.

In the disclosed embodiment, the carrier amplifying circuit 10 includes the operational amplifying unit 101 and the gain adjusting sub-circuit 102, is capable of effectively amplifying a carrier signal, and can control the amplification factor by adjusting the gain adjusting sub-circuit 102, thereby realizing flexible signal processing. In addition, since the non-inverting input end of the operational amplification unit 101 is connected with the common-mode voltage, the amplified alternating current amplified carrier signal can be ensured to keep stable amplitude and phase, and subsequent signal processing and communication transmission are facilitated.

Optionally, as shown in fig. 2, the gain adjustment sub-circuit 102 includes a first dc blocking unit 1021 and a negative feedback unit 1022. The first dc blocking unit 1021 is connected to the antenna terminal 60 and is configured to filter the carrier signal to eliminate dc interference. The negative feedback unit 1022 has a first end connected to the first dc blocking unit 1021, and a second end connected to the inverting input and output of the operational amplifier 101, respectively, and is configured to adjust the amplification gain of the filtered carrier signal.

The first dc blocking unit 1021 may be a first capacitor, for example. A first end of the first capacitor is connected to the antenna end 60, and a second end of the first capacitor is connected to a first end of the negative feedback unit 1022.

In the disclosed embodiment, the performance of the carrier amplifying circuit 10 is further optimized. The gain adjustment sub-circuit 102 includes a first dc blocking unit 1021 and a negative feedback unit 1022, and can effectively implement amplification and anti-interference processing of a carrier signal. Specifically, the first dc blocking unit 1021 is connected to the antenna terminal 60, and improves the purity and stability of the carrier signal. The negative feedback unit 1022 can feedback and adjust the output signal of the operational amplification unit 101, thereby realizing adjustment of the amplification gain of the operational amplification unit 101.

Alternatively, as shown in fig. 2, the negative feedback unit 1022 includes a first resistor 1221 and a second resistor 1222. The first resistor 1221 has a first end connected to the first dc blocking unit 1021, and a second end connected to the inverting input terminal of the operational amplification unit 101, and is configured to return the ac amplified carrier signal output from the output terminal of the operational amplification unit 101 to the inverting input terminal of the operational amplification unit 101. The second resistor 1222 has a first end connected to the inverting input terminal of the operational amplifier unit 101, and a second end connected to the output terminal of the operational amplifier, and is configured to adjust the amplification gain of the carrier amplifying circuit 10 by adjusting the resistance value of the second resistor 1222.

In the disclosed embodiment, a more accurate and flexible carrier amplifying circuit 10 is provided. By the negative feedback unit 1022 composed of the first resistor 1221 and the second resistor 1222, more accurate signal feedback and gain adjustment can be realized, and by adjusting the resistance value of the second resistor 1222 to adjust the amplification gain multiple of the carrier amplifying circuit 10, more flexible gain adjustment capability is provided, and more stable and efficient carrier signal amplification and processing can be realized.

Illustratively, with respect to the structure of the carrier amplifying circuit 10, the amplifying gain of the carrier amplifying circuit 10 is:

where AV is the amplification gain of the carrier amplifying circuit 10, R ₂ Resistance value of the second resistor 1222, R ₁ The resistance of the first resistor 1221, S is complex frequency, C ₁ Vac0 is the carrier voltage of the antenna end 60, V _CM Is the common mode voltage of Vac 0.

The output voltage of the carrier amplifying circuit 10 is:

here, vamp is an output voltage of the carrier amplifying circuit 10, and the output voltage of the carrier amplifying circuit 10 is a voltage obtained by amplifying the carrier voltage by the carrier amplifying circuit 10.

From the above calculation formula, C can be set ₁ The value of (i.e., the capacitance of the first capacitor) such that 1/SC at 13.56MHz carrier ₁ Far less than R ₁ (i.e., the resistance value of the first resistor 1221) such that the carrier amplitude of the ac amplified carrier signal amplified by the carrier amplifying circuit 10 is approximately equal to R ₂ /R ₁ Adjusting the amplification gain of the carrier amplifying circuit 10 is achieved by adjusting the resistance value of the second resistor 1222Multiple. The amplification gain of the carrier amplifying circuit 10 can be configured according to actual requirements. Carrier amplitude refers to the amplitude variation of a 13.56MHz carrier in NFC communications.

Alternatively, as shown in fig. 3, the envelope detection circuit 20 includes a second dc blocking unit 201 and a rectifier circuit 202. The second dc blocking unit 201 is connected to the output terminal of the carrier amplifying circuit 10 and is configured to filter the ac amplified carrier signal to eliminate dc interference. The rectifier sub-circuit 202 has a first end connected to the second dc blocking unit 201, and a second end connected to the quantization circuit 30, and is configured to convert the filtered ac amplified carrier signal into a dc amplified carrier signal for output.

The second dc blocking unit 201 may be a second capacitor. A first end of the second capacitor is connected to the output terminal of the carrier amplifying circuit 10, and a second end of the second capacitor is connected to the first end of the rectifier circuit 202.

In the disclosed embodiment, the ac amplified carrier signal is further processed by an envelope detection circuit 20. The envelope detection circuit 20 includes a second dc blocking unit 201 and a rectifier circuit 202, and can filter the ac amplified carrier signal to eliminate dc interference, and convert the filtered signal into a dc amplified carrier signal for output. In this way, more stable and efficient signal processing and transmission can be achieved.

Optionally, as shown in fig. 3, the rectifier sub-circuit 202 includes a transistor 2021, a filter unit 2022, and a current source 2023. The gate of the transistor 2021 is connected to the second dc blocking unit 201 and the common mode voltage, respectively, and is grounded in place. The filtering unit 2022 has a first end connected to the source of the transistor 2021, and a second end connected to the drain of the transistor 2021, and is configured to filter out high-frequency noise and low-frequency noise of the signal output by the transistor 2021, so as to output a dc amplified carrier signal. A current source 2023 is connected to the drain of the transistor 2021 and configured to supply current to the transistor 2021.

Illustratively, the transistor 2021 is a PMOS transistor, i.e., a P-type metal-oxide-semiconductor (PMOS) transistor.

The filtering unit 2022 may be exemplarily set to a third capacitance. The first terminal of the third capacitor is connected to the source of the transistor 2021, and the second terminal is connected to the drain of the transistor 2021.

Illustratively, a first terminal of the current source 2023 is connected to the drain of the transistor 2021 and a second terminal is connected to a supply voltage configured to provide current to the transistor 2021. Wherein the supply voltage is provided by a supply voltage terminal 80.

In the disclosed embodiment, by providing the transistor 2021, the ac amplified carrier signal processed by the second dc blocking unit 201 can be received, and the rectification action of the ac amplified carrier signal is achieved by the control of the gate. By providing the filtering unit 2022, clutter and noise in the signal can be effectively removed, the purity and stability of the signal can be improved, and a high-quality input signal can be provided for subsequent signal processing. Providing the appropriate current through the current source 2023 may enable the transistor 2021 to function properly while improving the efficiency and performance of the rectifier circuit 202. In this way, the envelope detection circuit 20 can perform more accurate rectification and filtering processing after receiving the ac carrier amplified signal, and convert the ac carrier amplified signal into a dc carrier amplified signal for output.

Optionally, as shown in fig. 3, the rectifier circuit 202 further includes a third resistor 2024. The first terminal of the third resistor 2024 is connected to the common mode voltage, and the second terminal is connected to the second dc blocking unit 201 and the gate of the transistor 2021, respectively. The third resistor 2024 is configured to provide a dc bias voltage to the transistor 2021.

Where R3C2 is much greater than 1/(2pi f), f=13.56 MHz.

Alternatively, as shown in fig. 4, the quantization circuit 30 includes a comparison unit 301. The first input terminal of the comparing unit 301 is connected to the output terminal of the envelope detection circuit 20, and the second input terminal is connected to a preset signal, and is configured to compare the dc amplified carrier signal output by the envelope detection circuit 20 with the preset signal value of the second input terminal, and to quantize and output the comparison result to determine the magnetic field detection result.

The comparison unit 301 may be a comparator, for example. The number of the comparators may be 1 or more. Specifically, the comparator is a voltage comparator (i.e., ADC comparator) configured to compare the dc amplified carrier voltage output by the envelope detection circuit 20 with a preset voltage value at the second input terminal to determine the magnetic field detection result. Wherein the preset signal is provided by the reference signal terminal 90. The reference signal terminal 90 may be a reference voltage terminal.

In the disclosed embodiment, the comparing unit 301 can accurately compare the magnitude of the dc amplified carrier signal with a preset signal value. The comparison result can be conveniently processed and analyzed by quantifying the comparison result and then outputting the current field strength indication information. In this way, the accuracy and sensitivity of the magnetic field detection result can be ensured, and the magnetic field strength in the scene of low field strength small carrier amplitude can be determined by the magnetic field detection result.

Optionally, as shown in fig. 5, the circuit 1 for magnetic field detection further comprises a timing circuit 40. An output of the timing circuit 40 is connected to the carrier amplifying circuit 10 and is configured to generate a periodic pulse signal to turn the carrier amplifying circuit 10 on or off.

Wherein the periodic pulse signal includes a low level signal and a high level signal. Specifically, in the case where the timing circuit 40 generates a high-level signal, the carrier amplifying circuit 10 is turned on. In the case where the timing circuit 40 generates a low level signal, the carrier amplifying circuit 10 is turned off.

Illustratively, the period duration of the periodic pulse signal generated by the timing circuit 40 may be set to 1ms (millisecond), wherein the high level signal may be set to 100us (microsecond). Can be specifically set according to the actual application requirements.

In the disclosed embodiment, the on and off of the carrier amplifying circuit 10 is controlled by generating a periodic pulse signal, and the periodic pulse signal can be output to control the on-off state of the carrier amplifying circuit 10. In this way, it is not necessary to turn on the carrier amplifying circuit 10 at all times, and the power consumption of the circuit 1 for magnetic field detection can be reduced.

Optionally, as shown in fig. 5, the circuit 1 for magnetic field detection further comprises a signal selection circuit 50. The input terminal of the signal selection circuit 50 is connected to the antenna terminal 60, the output terminal of the carrier amplification circuit 10, and the output terminal of the timing circuit 40, respectively, and the output terminal is connected to the output terminal of the envelope detection circuit 20, and is configured to select the carrier signal of the output antenna terminal 60 or the amplified carrier signal output by the carrier amplification circuit 10 according to the periodic pulse signal generated by the timing circuit 40.

Illustratively, the signal selection circuit 50 may be a MUX selection circuit.

Specifically, in the case where the timing circuit 40 generates a high-level signal, the signal selection circuit 50 selects the ac amplified carrier signal output from the carrier amplification circuit 10, and outputs the ac amplified carrier signal to the envelope detection circuit 20. In the case where the timing circuit 40 generates a low-level signal, the signal selection circuit 50 selects the carrier signal of the antenna terminal 60 and outputs the carrier signal of the antenna terminal 60 to the envelope detection circuit 20.

It can be appreciated that the circuit 1 for magnetic field detection as shown in fig. 1 to 4 has an overall power consumption of itotal=iamp+ienvdet+icomp. Where Iamp is the power consumption of the carrier amplifying circuit 10, iamp is the main power consumption contribution, ienvdet is the power consumption of the envelope detecting circuit 20, and Icomp is the power consumption of the quantizing circuit 30. As in the circuit 1 for magnetic field detection shown in fig. 5, the overall power consumption is itotal=iamp (ton/t) +ienvdet+icomp. Where ton is the period of time for the timing circuit 40 to output the high level signal, t is the period of time for the timing circuit 40 to output the periodic pulse signal, and t is greater than ton, and the ratio of ton to t can be set according to the actual application requirement.

In the disclosed embodiment, according to the above algorithm of the overall power consumption of the two circuits 1 for magnetic field detection, it can be derived that by providing the timing circuit 40 and the signal selection circuit 50, the overall power consumption of the circuits 1 for magnetic field detection can be reduced. the smaller ton, the larger t and the lower the power consumption. In practical application requirements, the detection sensitivity of the circuit to field intensity can be balanced and the power consumption of the circuit can be reduced by setting the proportion of ton and t.

As shown in fig. 6, an embodiment of the present disclosure provides an electronic device 100. The electronic device 100 comprises an electronic device body 200 and the circuit 1 for magnetic field detection as described above. The circuit 1 for magnetic field detection is mounted to the electronic apparatus body 200.

The electronic device 100 is an electronic device having NFC functionality.

In the disclosed embodiment, the electronic device 100 is capable of sensitively detecting the field strength condition of a magnetic field in a scenario of low field strength and small carrier amplitude, while reducing power consumption.

The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. Moreover, the terminology used in the present application is for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, when used in this application, the terms "comprises," "comprising," and/or "includes," and variations thereof, mean that the stated features, integers, steps, operations, elements, and/or components are present, but that the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of other like elements in a process, method or apparatus comprising such elements. In this context, each embodiment may be described with emphasis on the differences from the other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method sections disclosed in the embodiments, the description of the method sections may be referred to for relevance.

Those of skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. The skilled artisan may use different methods for each particular application to achieve the described functionality, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to devices, apparatuses, etc.) may be practiced in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units may be merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to implement the present embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than that disclosed in the description, and sometimes no specific order exists between different operations or steps. For example, two consecutive operations or steps may actually be performed substantially in parallel, they may sometimes be performed in reverse order, which may be dependent on the functions involved. Each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Claims

1. A circuit for magnetic field detection, comprising:

a carrier amplifying circuit configured to receive a carrier signal of the antenna end, and to amplify the carrier signal to output an ac amplified carrier signal;

an envelope detection circuit, connected to the carrier amplifying circuit, configured to convert the ac amplified carrier signal into a dc amplified carrier signal;

and the quantization circuit is connected with the envelope detection circuit and is configured to compare and quantize the direct current amplified carrier signal with a preset signal value so as to detect a magnetic field.

2. The circuit of claim 1, wherein the carrier amplifying circuit comprises:

the in-phase input end of the operational amplification unit is connected with the common mode voltage, the output end of the operational amplification unit is connected with the envelope detection circuit, and the operational amplification unit is configured to amplify the carrier signal according to the common mode voltage;

and the gain adjusting sub-circuit is connected with the antenna end at a first end and the inverting input end and the output end of the operational amplifying unit at a second end respectively and is configured to adjust the amplification gain multiple of the operational amplifying unit.

3. The circuit of claim 2, wherein the gain adjustment sub-circuit comprises:

the first direct current isolation unit is connected with the antenna end and is configured to filter a carrier signal so as to eliminate direct current interference;

and the negative feedback unit is connected with the first direct current isolation unit at a first end, is connected with the inverting input end and the output end of the operational amplification unit at a second end respectively, and is configured to adjust the amplification gain of the filtered carrier signal.

4. A circuit according to claim 3, wherein the negative feedback unit comprises:

the first end of the first resistor is connected with the first DC isolation unit, the second end of the first resistor is connected with the inverting input end of the operational amplification unit and is configured to return the alternating current amplified carrier signal output by the output end of the operational amplification unit to the inverting input end of the operational amplification unit;

and the first end of the second resistor is connected with the inverting input end of the operational amplifier unit, the second end of the second resistor is connected with the output end of the operational amplifier, and the second resistor is configured to adjust the amplification gain multiple of the carrier amplifying circuit by adjusting the resistance value of the second resistor.

5. The circuit of claim 1, wherein the envelope detection circuit comprises:

the second direct current isolation unit is connected with the output end of the carrier amplifying circuit and is configured to filter the alternating current amplified carrier signal so as to eliminate direct current interference;

and the first end of the rectifier circuit is connected with the second DC isolation unit, the second end of the rectifier circuit is connected with the quantization circuit, and the rectifier circuit is configured to convert the filtered AC amplified carrier signal into a DC amplified carrier signal for output.

6. The circuit of claim 5, wherein the rectifier circuit comprises:

the grid electrode of the transistor is respectively connected with the second DC isolation unit and the common mode voltage and is grounded in situ;

the first end of the filtering unit is connected with the source electrode of the transistor, the second end of the filtering unit is connected with the drain electrode of the transistor and is configured to filter high-frequency and low-frequency clutters of signals output by the transistor so as to output direct-current amplified carrier signals;

and a current source connected to the drain of the transistor and configured to supply a current to the transistor.

7. The circuit of claim 1, wherein the quantization circuit comprises:

and the comparison unit is provided with a first input end connected with the output end of the envelope detection circuit, a second input end connected with a preset signal and configured to compare the direct current amplified carrier signal output by the envelope detection circuit with the preset signal value of the second input end and to output the quantized comparison result so as to determine the magnetic field detection result.

8. The circuit of any one of claims 1 to 7, further comprising:

and the output end of the timing circuit is connected with the carrier amplifying circuit and is configured to generate a periodic pulse signal so as to enable the carrier amplifying circuit to be turned on or turned off.

9. The circuit of claim 8, further comprising:

and the signal selection circuit is respectively connected with the antenna end, the output end of the carrier amplifying circuit and the output end of the timing circuit, and the output end of the signal selection circuit is connected with the output end of the envelope detection circuit and is configured to select and output the carrier signal of the antenna end or the amplified carrier signal output by the carrier amplifying circuit according to the periodic pulse signal generated by the timing circuit.

10. An electronic device, comprising:

an electronic device body;

the circuit for magnetic field detection according to any one of claims 1 to 9, mounted to an electronic device body.