CN117716510A

CN117716510A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Info

Publication number: CN117716510A
Application number: CN202280047641.5A
Authority: CN
Inventors: 大隅悠史; 奥田肇
Original assignee: Rohm Co Ltd
Current assignee: Rohm Co Ltd
Priority date: 2021-07-21
Filing date: 2022-06-08
Publication date: 2024-03-15

Abstract

The semiconductor device includes: a chip having a main surface; a diode region provided on the main surface; a plurality of trench structures formed on the main surface at intervals in the diode region, each of the trench structures including an upper electrode and a lower electrode, the upper electrode and the lower electrode being buried in the trench in the up-down direction via an insulator; and a diode having a pn junction portion formed in a surface layer portion of the main surface in a region between the plurality of trench structures.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Technical Field

The present application corresponds to Japanese patent application Nos. 2021-121046 filed on 7 months 21 in 2021 and 2021-121047 filed on 21 months 2021 to Japanese patent application, the disclosures of which are incorporated herein by reference in their entirety. The present disclosure relates to a semiconductor device.

Background

Fig. 6 of patent document 1 discloses a semiconductor device having a semiconductor layer, 2 trench field plate structures, and a rectifying element. The trench field plate structure comprises a field electrode buried in the trench. The rectifying element includes an n-type semiconductor region and a p-type semiconductor region formed in the semiconductor layer in a region between two trench field plate structures.

Prior art literature

Patent literature

Patent document 1: U.S. patent application publication No. 2015/0207407 specification

Disclosure of Invention

Problems to be solved by the invention

One embodiment provides a new semiconductor device having a diode with high versatility.

Means for solving the problems

One embodiment provides a semiconductor device including: a chip having a main surface; a diode region provided on the main surface; a plurality of trench structures formed on the main surface at intervals in the diode region, each of the trench structures including an upper electrode and a lower electrode, the upper electrode and the lower electrode being buried in the trench in the up-down direction via an insulator; and a diode having a pn junction portion formed in a surface layer portion of the main surface in a region between the plurality of trench structures.

One embodiment provides a semiconductor device including: a chip having a main surface; a circuit region provided on the main surface; a protection region provided on the main surface; an electrical circuit formed in the circuit region; a plurality of trench structures formed on the main surface at intervals in the protection region, each of the trench structures including an upper electrode and a lower electrode, the upper electrode and the lower electrode being buried in the trench in the up-down direction via an insulator; and an electrostatic breakdown protection diode having a pn junction portion formed in a surface layer portion of the main surface in a region between the plurality of trench structures, and electrically connected to the electric circuit.

One embodiment provides a semiconductor device including: a chip having a main surface; a plurality of temperature measurement areas provided on the main surface at intervals; a plurality of trench structures formed on the main surface at intervals in the temperature measurement regions, each trench structure having an electrode structure including an upper electrode and a lower electrode, the upper electrode and the lower electrode being buried in the trench in the up-down direction via an insulator; and a plurality of temperature sensing diodes each having a pn junction portion formed in a surface layer portion of the main surface in a region between the plurality of trench structures in the corresponding temperature measuring region, and detecting a temperature of the corresponding temperature measuring region.

One embodiment provides a semiconductor device including: a chip having a main surface; a temperature measurement region provided on the main surface; a control region provided on the main surface; a plurality of trench structures formed on the main surface at intervals in the temperature measurement region, each of the trench structures including an upper electrode and a lower electrode, the upper electrode and the lower electrode being embedded in the trench in an up-down direction via an insulator; a temperature sensing diode having a pn junction formed in a surface layer portion of the main surface in a region between the plurality of trench structures, and generating a temperature measurement signal for detecting a temperature of the temperature measurement region; and a control circuit configured to generate an electrical signal based on the temperature measurement signal from the temperature sensing diode.

One embodiment provides a semiconductor device including: a chip having a main surface; a temperature measurement region provided on the main surface; a protection region provided in a region different from the temperature measurement region in the main surface; a plurality of first trench structures formed on the main surface at intervals in the temperature measurement region, each of the first trench structures including a first upper electrode and a first lower electrode, the first upper electrode and the first lower electrode being embedded in the first trench in the up-down direction via a first insulator; a temperature sensing diode having a first pn junction portion formed in a surface layer portion of the main surface in a region between the plurality of first trench structures; a plurality of second trench structures formed on the main surface at intervals in the protection region, each of the second trench structures including a second upper electrode and a second lower electrode, the second upper electrode and the second lower electrode being buried in the second trench in the up-down direction via a second insulator; and an electrostatic breakdown protection diode having a second pn junction portion formed in a surface layer portion of the main surface in a region between the plurality of second trench structures.

One embodiment provides a semiconductor device including: a chip having a main surface; a current detection region provided on the main surface; a diode region provided on the main surface; a current monitoring device formed in the current detection region so as to generate a monitoring current; a plurality of trench structures formed at intervals in the diode region and each having an electrode structure including an upper electrode and a lower electrode, the upper electrode and the lower electrode being buried in the trench in the up-down direction via an insulator; and diodes each having a pn junction portion formed in a surface layer portion of the main surface in a region between the plurality of trench structures formed in the diode region at intervals.

One embodiment provides a semiconductor control device including: a chip having a main surface; a temperature measurement region provided on the main surface; a control region provided on the main surface; a plurality of trench structures formed on the main surface at intervals in the temperature measurement region, each of the trench structures including an upper electrode and a lower electrode, the upper electrode and the lower electrode being embedded in the trench in an up-down direction via an insulator; a temperature sensing diode having a pn junction formed in a surface layer portion of the main surface in a region between the plurality of trench structures, and generating an internal temperature measurement signal for detecting a temperature of the temperature measurement region; and a control circuit configured to generate an electrical signal from the internal temperature measurement signal from the temperature sensing diode.

An embodiment provides a semiconductor module including a semiconductor device and a semiconductor control device electrically connected to the semiconductor device, the semiconductor device including: a first chip; the first temperature measuring area is arranged on the first chip; a plurality of first trench structures formed at intervals in the first temperature measurement region and each having an electrode structure including a first upper electrode and a first lower electrode, the first upper electrode and the first lower electrode being buried in the first trench in the up-down direction via a first insulator; and first temperature sensing diodes each having a first pn junction portion formed in a surface layer portion of the first chip in regions between the plurality of first trench structures and generating a first temperature measurement signal indicating a temperature of the first temperature measurement region, the semiconductor control device comprising: a second chip; the second temperature measuring area is arranged on the second chip; a control region disposed on the second chip; a plurality of second trench structures formed on the second chip at intervals in the second temperature measurement region, each of the second trench structures including a second upper electrode and a second lower electrode, the second upper electrode and the second lower electrode being buried in the second trench in the up-down direction via a second insulator; a second temperature sensing diode having a second pn junction formed at a surface layer portion of the second chip in a region between the plurality of second trench structures, and generating a second temperature measurement signal indicating a temperature of the second temperature measurement region; and a control circuit formed in the control region and generating an electrical signal for controlling the semiconductor device according to the first temperature measurement signal and the second temperature measurement signal.

The above and other objects, features and effects will become apparent from the embodiments described with reference to the accompanying drawings.

Drawings

Fig. 1 is a schematic plan view of a semiconductor device of a first embodiment.

Fig. 2 is a schematic cross-sectional view of the semiconductor device shown in fig. 1.

Fig. 3 is a schematic circuit block diagram showing an electrical structure of the semiconductor device shown in fig. 1.

Fig. 4 is an equivalent circuit diagram of the main transistor and the monitor transistor shown in fig. 3.

Fig. 5 is another equivalent circuit diagram of the main transistor and monitor transistor shown in fig. 4.

Fig. 6A is a circuit diagram illustrating an example of the operation of the main transistor.

Fig. 6B is a circuit diagram illustrating an example of the operation of the main transistor.

Fig. 6C is a circuit diagram illustrating an example of the operation of the main transistor.

Fig. 7 is a circuit block diagram showing a specific electrical configuration example of the semiconductor device shown in fig. 1 (=a configuration example in which a main transistor of the 2 system and a monitor transistor of the 2 system are applied to the semiconductor device of the first embodiment).

Fig. 8 is an enlarged view of the region VIII shown in fig. 1, and is a plan view showing an example of layout of the output region 7.

Fig. 9 is an enlarged view of the area IX shown in fig. 8.

Fig. 10 is an enlarged view of the region X shown in fig. 8.

Fig. 11 is a cross-sectional view taken along line XI-XI shown in fig. 9.

Fig. 12 is a cross-sectional view taken along line XII-XII shown in fig. 9.

Fig. 13 is a sectional view taken along line XIII-XIII shown in fig. 9.

Fig. 14 is a cross-sectional view taken along line XIV-XIV shown in fig. 9.

Fig. 15 is a cross-sectional perspective view showing an example of the first channel structure.

Fig. 16 is a cross-sectional perspective view showing an example of the second channel structure.

Fig. 17 is a cross-sectional perspective view showing a third channel structure example.

Fig. 18 is a cross-sectional perspective view showing a fourth channel structure example.

Fig. 19 is an enlarged view of the region XIX shown in fig. 8.

FIG. 20 is a cross-sectional view taken along line XX-XX shown in FIG. 19.

Fig. 21 is a cross-sectional view taken along line XXI-XXI shown in fig. 19.

Fig. 22 is a cross-sectional view taken along line XXII-XXII shown in fig. 19.

Fig. 23 is a cross-sectional view taken along line XXIII-XXIII shown in fig. 19.

FIG. 24 is a cross-sectional perspective view showing the output region and the first temperature measuring region.

FIG. 25 is an enlarged plan view partially showing another embodiment of the first temperature measuring region.

Fig. 26 is a graph showing the temperature characteristic of the first temperature sensing diode shown in fig. 19.

Fig. 27 is an enlarged view of the region XXVII shown in fig. 1.

Fig. 28 is a graph showing breakdown characteristics of the ESD diode shown in fig. 27.

Fig. 29 is a graph showing the relationship between the breakdown current of the ESD diode shown in fig. 27 and the planar area of the ESD diode.

Fig. 30A is a cross-sectional perspective view showing an example of the operation of the main transistor.

Fig. 30B is a cross-sectional perspective view showing an example of the operation of the main transistor.

Fig. 30C is a cross-sectional perspective view showing an example of the operation of the main transistor.

Fig. 31 is a timing chart showing a control example of the main transistor.

Fig. 32 is a schematic plan view showing a semiconductor device according to the second embodiment.

Fig. 33 is a schematic cross-sectional view of the semiconductor device shown in fig. 32.

Fig. 34 is a schematic plan view showing a semiconductor device according to the third embodiment.

Fig. 35 is a schematic cross-sectional view of the semiconductor device shown in fig. 34.

Fig. 36 is a schematic plan view showing a semiconductor module according to the fourth embodiment.

Detailed Description

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The drawings are schematic and are not necessarily to scale, nor are they necessarily to scale. In addition, the same reference numerals are given to the corresponding structures between the drawings, and the repetitive description thereof will be omitted or simplified. For the construction in which the description is omitted or simplified, the description that was made before the description is omitted or simplified is applied.

Fig. 1 is a schematic plan view of a semiconductor device 1A of the first embodiment. Fig. 2 is a schematic cross-sectional view of the semiconductor device 1A shown in fig. 1. Fig. 3 is a schematic circuit block diagram showing an electrical structure of the semiconductor device 1A shown in fig. 1. Fig. 4 is an equivalent circuit diagram of the main transistor 11 and the monitor transistor 14 shown in fig. 3. Fig. 5 is another equivalent circuit diagram of the main transistor 11 and the monitor transistor 14 shown in fig. 4. Fig. 3 shows an example in which the inductive load L is connected to the source terminal 37.

Referring to fig. 1, in this embodiment (this embodiment), a semiconductor device 1A includes a chip 2 (semiconductor chip) formed in a rectangular parallelepiped shape. The chip 2 may be constituted by a chip 2 containing Si single crystal or SiC single crystal. In this embodiment, the chip 2 is constituted by a chip 2 containing Si single crystal.

The chip 2 has: a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view (hereinafter, simply referred to as "plan view") viewed from the normal direction Z thereof.

The first main surface 3 is a circuit surface on which an electric circuit is formed. The second main surface 4 is a mounting surface, and may be a grinding surface having grinding marks. The first to fourth side surfaces 5A to 5D include: a first side 5A, a second side 5B, a third side 5C, and a fourth side 5D. The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3, and face (face away) in a second direction Y intersecting (specifically, orthogonal to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face each other in the first direction X.

The semiconductor device 1A includes a circuit region 6 provided on the first main surface 3. The circuit region 6 is a region having an electric circuit, and includes a plurality of device regions divided according to the types of functional devices constituting a part of the electric circuit. In this embodiment, the circuit region 6 includes: an output zone 7, at least one current detection zone 8, at least one temperature measurement zone 9 and a control zone 10.

In the present embodiment, the semiconductor device 1A includes a plurality of current detection regions 8 and a plurality of temperature measurement regions 9. The output region 7, the current detection region 8, the temperature measurement region 9, and the control region 10 may also be referred to as "first device region", "second device region", "third device region", and "fourth device region", respectively.

The output region 7 is a region having a circuit device configured to generate an output signal to be output to the outside. In the present embodiment, the output region 7 is divided into regions on the first main surface 3 on the first side surface 5A side. The output region 7 may be divided into a quadrangular shape in plan view, or may be divided into a polygonal shape other than the quadrangular shape. The position, size, and planar shape of the output region 7 are arbitrary and are not limited to a specific one.

The plurality of current detection regions 8 are regions having circuit devices configured to generate an output monitor signal that monitors the output signal. The plurality of current detection regions 8 are preferably adjacent to the output region 7. In this embodiment, the plurality of current detection regions 8 each have a planar area smaller than that of the output region 7, and are disposed inside the output region 7. Specifically, the current detection region 8 is formed as a part of the utilization output region 7.

The plurality of current detection regions 8 are each preferably arranged adjacent to the output region 7 in at least two directions in a plan view. The plurality of current detection regions 8 may also each be adjacent to the output region 7 in 4 directions in plan view. The position, size, and planar shape of the current detection region 8 are arbitrary, and are not limited to a specific embodiment.

The control region 10 is a region having various circuit devices configured to generate control signals for controlling the output region 7. In this embodiment, the control region 10 is divided into a region on the second side surface 5B side with respect to the output region 7, and is opposed to the output region 7 in the second direction Y. The control region 10 may be divided into a quadrangular shape in plan view, or may be divided into polygonal shapes other than the quadrangular shape. The position, size, and planar shape of the control region 10 are arbitrary and are not limited to a specific manner.

The control zone 10 preferably has a planar area below the planar area of the output zone 7. The control region 10 is preferably formed at an area ratio of 0.1 to 1 with respect to the output region 7. The area ratio is the ratio of the planar area of the control zone 10 to the planar area of the output zone 7. The area ratio is preferably less than 1. Of course, a control zone 10 having a planar area exceeding the planar area of the output zone 7 may also be employed.

The plurality of temperature measuring areas 9 are areas having circuit devices configured to detect the temperature of the chip 2. The plurality of temperature measurement regions 9 are provided on the first main surface 3 at intervals so as to detect the temperature of the chip 2 in different regions. In this embodiment, the plurality of temperature measuring areas 9 includes a first temperature measuring area 9A and a second temperature measuring area 9B. The first temperature measuring region 9A is disposed adjacent to the output region 7, and detects the temperature of the output region 7. The second temperature measuring region 9B is disposed adjacent to the control region 10 and detects the temperature of the control region 10.

In this embodiment, the first temperature measuring region 9A has a plane area smaller than that of the output region 7, and is divided inside the output region 7. That is, the first temperature measuring region 9A is surrounded by the output region 7 in a plan view. The term "surrounded" as referred to herein includes, in addition to the way in which the first temperature measurement region 9A is surrounded by the output region 7 over the entire circumference, the way in which the first temperature measurement region 9A is adjacent to the output region 7 in at least two directions.

For example, the first temperature measuring region 9A may be sandwiched between the output regions 7 from one side and the other side in the first direction X, or may be sandwiched between the output regions 7 from one side and the other side in the second direction Y. The first temperature measurement region 9A may be adjacent to the output region 7 in the first direction X and the second direction Y. In this case, the first temperature measuring region 9A may be adjacent to the output region 7 in two directions or three directions. In this embodiment, the first temperature measuring region 9A is adjacent to the output region 7 in 4 directions in a plan view.

In this embodiment, the temperature measuring region 9 is arranged together with the current detecting region 8 in one output region 7. The first temperature measurement region 9A faces the current detection region 8 in one or both of the first direction X and the second direction Y (in this embodiment, the first direction X). The position, size, and planar shape of the first temperature measurement region 9A are arbitrary, and are not limited to a specific embodiment. The first temperature measuring region 9A preferably has a planar area smaller than the planar area of the control region 10.

The second temperature measuring region 9B is preferably adjacent to the control region 10 in at least 2 directions in a plan view. In this embodiment, the second temperature measurement region 9B has a planar area smaller than that of the control region 10, and is divided inside the control region 10. That is, in the present embodiment, the second temperature measuring region 9B is adjacent to the control region 10 in 4 directions in a plan view.

The position, size, and planar shape of the second temperature measurement region 9B are arbitrary, and are not limited to a specific one. The second temperature measuring region 9B preferably has a planar area smaller than the planar area of the output region 7. The second temperature measuring region 9B preferably has a planar area smaller than the planar area of the control region 10. The second temperature measuring region 9B preferably has a planar area substantially equal to that of the first temperature measuring region 9A.

When the output area 7 generates the output signal and the control area 10 generates the control signal, the output area 7 has a first temperature TE1, and the control area 10 has a second temperature TE2 (TE 1 not equal to TE 2) different from the first temperature TE 1. Specifically, the second temperature TE2 is smaller than the first temperature TE1 (TE 1 > TE 2). The first temperature measuring region 9A generates a first temperature measuring signal ST1 for detecting the first temperature TE1, and the second temperature measuring region 9B generates a second temperature measuring signal ST2 for detecting the second temperature TE 2.

Referring to fig. 2 to 5, the semiconductor device 1A includes an n-system (n-system) insulated gate type main transistor 11 formed in the output region 7. "n" is 2 or more (n.gtoreq.2). The main transistor 11 may also be referred to as a "gate split transistor" (gate divided transistor). The main transistor 11 includes: n (n-number) first gates FG, one first drain FD, and one first source FS. The first gate FG, the first drain FD, and the first source FS may also be referred to as "main gate", "main drain", and "main source", respectively.

The main transistor 11 is configured to input n gate signals G (gate voltages) which are the same or different to n first gates FG at an arbitrary timing. Each gate signal G includes: an on signal for controlling a part of the main transistor 11 to an on state, and an off signal for controlling a part of the main transistor 11 to an off state.

The main transistor 11 generates a single output current IO (output signal) in response to n gate signals G. That is, the main transistor 11 is constituted by a multiple-input single-output switching device. Specifically, the output current IO is a drain/source current flowing between the first drain FD and the first source FS. The output current IO is output out of the chip 2.

Referring to fig. 4, the main transistor 11 includes n system transistors 12. The n system transistors 12 are integrated in a single output region 7 and are controlled to be in an on state and an off state electrically independent of each other. Specifically, the n system transistors 12 are connected in parallel to each other so as to receive n gate signals G, respectively, and constitute 1 system parallel circuit (=main transistor 11). That is, the main transistor 11 of the n-system is configured as: the system transistor 12 in the on state and the system transistor 12 in the off state coexist at any time.

The n system transistors 12 each include: a second gate SG, a second drain SD and a second source SS. The second gate SG, the second drain SD, and the second source SS may also be referred to as a "system gate", "system drain", and "system source", respectively. The n second gates SG are connected to the n first gates FG in a one-to-one correspondence, respectively. The n second drains SD are connected to 1 first drain FD, respectively. The n second sources SS are connected to 1 first source FS, respectively.

That is, the n second gates SG, the n second drains SD, and the n second sources SS of the n system transistors 12 constitute the n first gates FG, one first drain FD, and one first source FS of the main transistor 11, respectively. The n first gates FG are substantially composed of n second gates SG.

The n system transistors 12 generate the system currents IS in response to the corresponding gate signals G, respectively. Specifically, the n system currents IS are drain/source currents flowing between the second drains SD and the second sources SS of the n system transistors 12. The n system currents IS may be different from each other or equal to each other. n system currents IS are added between the first drain FD and the first source FS. Thereby, a single output current IO composed of the added value of the n system currents IS generated.

Referring to fig. 5, the n system transistors 12 each include a single or a plurality of unit transistors 13 that are systemized (grouped) as individual control targets. In this embodiment, the plurality of unit transistors 13 are each formed of a trench gate type. Specifically, the n system transistors 12 each have a unit parallel circuit composed of a single or a plurality of unit transistors 13.

The case where the system transistor 12 is constituted by a single unit transistor 13 is also included in the "unit parallel circuit" mentioned here. The number of unit transistors 13 included in each of the system transistors 12 is arbitrary, but it is preferable that at least one of the system transistors 12 includes a plurality of unit transistors 13. The n system transistors 12 may be constituted by the same number or different numbers of unit transistors 13.

Each unit transistor 13 includes: third gate TG, third drain TD, and third source TS. The third gate TG, the third drain TD, and the third source TS may also be referred to as "cell source", "cell drain", and "cell source", respectively.

In each of the system transistors 12, the third gate TG is electrically connected to the second gate SG, the third drain TD is electrically connected to the second drain SD, and the third source TS is electrically connected to the second source SS. That is, the third gate TG, the third drain TD, and the third source TS of the single or multiple unit transistors 13 that are systemized constitute the second gate SG, the second drain SD, and the second source SS of each of the system transistors 12, respectively.

The plurality of unit transistors 13 may have substantially equal gate threshold voltages or may have different gate threshold voltages. The plurality of unit transistors 13 may have substantially equal channel areas per unit area, or may have different channel areas.

That is, the plurality of unit transistors 13 may have substantially equal on-resistance characteristics or may have different on-resistance characteristics. The electrical characteristics of the respective system transistors 12 are finely adjusted by adjusting the number of unit transistors 13, gate threshold voltages, channel areas, and the like.

Referring to fig. 2 to 5, the semiconductor device 1A includes an insulated gate type monitor transistor 14 formed in an m-system (m-system) of the current detection region 8. "m" is 1 or more (m.gtoreq.1). In the present embodiment, the monitor transistor 14 is formed in the output region 7 (preferably, in the central portion) at a distance from the peripheral edge of the output region 7 so as to be adjacent to the plurality of system transistors 12. The monitor transistor 14 is preferably adjacent to the plurality of system transistors 12 in at least two directions in a top view. That is, the monitor transistor 14 is preferably integrated with a plurality of system transistors 12 in a single output region 7.

The monitor transistor 14 may also be configured to be connected in parallel with the at least one system transistor 12 to monitor the at least one system current IS. The monitor transistor 14 IS preferably constituted by a monitor transistor 14 of m system (m.gtoreq.2), and the monitor transistor 14 of m system IS connected in parallel to the plurality of system transistors 12 to monitor the plurality of system currents IS.

In the present embodiment, the monitor transistor 14 IS composed of n-system (m=n) monitor transistors 14, and the n-system monitor transistors 14 are connected in parallel to the n-system transistors 12 so as to monitor the n-system currents IS. Hereinafter, the configuration of the monitor transistor 14 will be described by replacing "m systems" or "m (m-number)" with "n systems" or "n" as necessary.

In this embodiment, the monitor transistor 14 includes: n first monitor gates FMG, 1 first monitor drain FMD, and 1 first monitor source FMS. The first monitor gate FMG, the first monitor drain FMD, and the first monitor source FMS may also be referred to as "main monitor gate", "main monitor drain", and "main monitor source", respectively.

The n first monitor gates FMG are each configured to be individually inputted with n monitor gate signals MG. The first monitor drain FMD is electrically connected to the first drain FD. The first monitor source FMS is electrically separated from the first source FS.

N monitor gate signals MG (monitor gate voltages) identical or different are input to n first monitor gates FMG at any time. Each monitor gate signal MG includes an on signal that controls a part of the monitor transistor 14 to an on state and an off signal that controls a part of the monitor transistor 14 to an off state.

In this embodiment, the monitor transistor 14 generates a single output monitor current IOM (output monitor signal) that monitors n system currents IS (output currents IO) in response to n monitor gate signals MG. That is, in the present embodiment, the monitor transistor 14 is constituted by a multiple-input single-output switching device. Specifically, the output monitor current IOM is a drain/source current flowing between the first monitor drain FMD and the first monitor source FMS.

In this embodiment, n first monitor gates FMG are electrically connected to corresponding n first gates FG in a one-to-one correspondence. Therefore, the n first monitor gates FMG are configured to be individually inputted with the monitor gate signals MG composed of the gate signals G. That is, the monitor transistor 14 is turned on and off at the same time as the n system transistors 12, and generates an output monitor current IOM that increases and decreases in conjunction with the increase and decrease of the output current IO.

The output monitor current IOM is output from the current path of the output current IO to the outside of the output region 7 via an electrically independent current path. The output monitor current IOM is equal to or less than the output current IO (IOM is less than or equal to IO). The output monitor current IOM is preferably smaller than the output current IO (IOM < IO). The current ratio IOM/IO of the output monitor current IOM to the output current IO is arbitrary. The current ratio IOM/IO may be 1/10000 or more and 1 or less (preferably less than 1).

Referring to fig. 4, the monitor transistor 14 includes m (n in this embodiment) system monitor transistors 15. The number of systems of the monitor transistors 14 is adjusted by the number of system monitor transistors 15. That IS, in the case where the monitor transistor 14 of the m system (m Σ1) monitors the at least one system current IS, the at least one system monitor transistor 15 IS electrically connected (specifically, connected in parallel) with the at least one system transistor 12.

In the case where the monitor transistor 14 of m system (m.gtoreq.2) monitors the plurality of system currents IS, the plurality of system monitor transistors 15 are electrically connected to the plurality of system transistors 12. In this embodiment, n system monitor transistors 15 are electrically connected to n system transistors 12, and monitor n system currents IS.

The n system monitor transistors 15 are integrated in a single output region 7 and are configured to be controlled to be in an on state and an off state electrically independent of each other. Specifically, the n system monitor transistors 15 are connected in parallel to each other so as to be individually inputted with n monitor gate signals MG, constituting one system monitor parallel circuit (=monitor transistor 14). That is, the system monitor transistor 15 in which the monitor transistor 14 is in an on state and the system monitor transistor 15 in an off state coexist at any time.

The n system monitor transistors 15 each include: a second monitor gate SMG, a second monitor drain SMD, and a second monitor source SMS. The second monitor gate SMG, the second monitor drain SMD, and the second monitor source SMS may also be referred to as a "system monitor gate", "system monitor drain", and "system monitor source", respectively.

The n second monitor gates SMG are connected to the n first monitor gates FMG, respectively, in a one-to-one correspondence. The n second monitor drains SMD are connected to one first monitor drain FMD, respectively. n second monitoring source SMS are connected to one first monitoring source FMS, respectively.

The n second monitor gates SMG, the n second monitor drains SMD, and the n second monitor sources SMS of the n system monitor transistors 15 constitute n first monitor gates FMG, 1 first monitor drain FMD, and 1 first monitor source FMS of the monitor transistor 14, respectively. The n first monitor gates FMG are substantially composed of n second monitor gates SMG.

The same or different n monitor gate signals MG are input to n second monitor gates SMG at any time. The n system monitor transistors 15 generate system monitor currents ISM (system monitor signals) for monitoring the system currents IS of the corresponding system transistors 12 in response to the corresponding monitor gate signals MG, respectively.

Specifically, the system monitor current ISM is a drain/source current flowing between the second monitor drain SMD and the second monitor source SMS of the system monitor transistor 15. n system monitor currents ISM are added between the first monitor drain FMD and the first monitor source FMS. Thereby, a single output monitor current IOM constituted by the added value of the n system monitor currents ISM is generated.

In the present embodiment, the n system monitor transistors 15 are each configured to be electrically connected to the corresponding system transistor 12 in a one-to-one correspondence, and to be controlled in association with the corresponding system transistor 12. Specifically, the n system monitor transistors 15 are connected in parallel to the corresponding system transistors 12 so as to output the system monitor current ISM from the current path of the system current IS to the electrically independent current path.

The n second monitor gates SMG are electrically connected to the corresponding first gates FG in a one-to-one correspondence, respectively. The second monitor drain SMD is electrically connected to the first drain FD. The second monitor source SMS is electrically separated from the first source FS. That is, in this embodiment, the monitor gate signals MG composed of the gate signals G are input to the n second monitor gates SMG, respectively.

Thus, the n system monitor transistors 15 are turned on and off at the same time as the corresponding system transistors 12, and generate the system monitor current ISM which increases and decreases in conjunction with the increase and decrease of the corresponding system current IS. The system monitor current ISM IS taken out from the second monitor drain SMD and the second monitor source SMS electrically independent of the system current IS. Each system monitoring current ISM IS below the corresponding system current IS (ISM IS less than or equal to IS).

Each system monitor current ISM IS preferably smaller than the corresponding system current IS (ISM < IS). The current ratio ISM/IS of the system monitor current ISM relative to the system current IS arbitrary. The current ratio ISM/IS may be 1/10000 or more and 1 or less (preferably less than 1).

Referring to fig. 5, the n system monitor transistors 15 each include a single or a plurality of unit monitor transistors 16 that are systemized (packetized) as individual control objects. In this embodiment, the plurality of unit monitor transistors 16 are each formed of a trench gate type. Specifically, the n system monitor transistors 15 each have a unit monitor parallel circuit constituted by a single or a plurality of unit monitor transistors 16.

The case where the system monitor transistor 15 is constituted by a single unit monitor transistor 16 is also included in the "unit monitor parallel circuit" mentioned here. The number of unit monitor transistors 16 included in each system monitor transistor 15 is arbitrary. The n system monitor transistors 15 may be constituted by the same number or different numbers of unit monitor transistors 16. The number of unit monitor transistors 16 included in each system monitor transistor 15 is preferably smaller than the number of unit transistors 13 included in the corresponding system transistor 12. In this case, the system monitor current ISM equal to or lower than the system current IS can be easily generated.

Each unit monitor transistor 16 includes: third monitor gate TMG, third monitor drain TMD, and third monitor source TMS. The third monitor gate TMG, the third monitor drain TMD, and the third monitor source TMS may also be referred to as "cell monitor gate", "cell monitor drain", and "cell monitor source", respectively.

In each system monitor transistor 15, a third monitor gate TMG is electrically connected to the second monitor gate SMG, a third monitor drain TMD is electrically connected to the second monitor drain SMD, and a third monitor source TMS is electrically connected to the second monitor source SMS.

That is, the third monitor gate TMG, the third monitor drain TMD, and the third monitor source TMS of the unit monitor transistor 16, which are systemized, constitute the second monitor gate SMG, the second monitor drain SMD, and the second monitor source SMS of each system monitor transistor 15, respectively.

The plurality of unit monitor transistors 16 may have substantially equal gate threshold voltages or may have different gate threshold voltages. The plurality of unit monitor transistors 16 may have substantially equal channel areas per unit area or may have different channel areas. That is, the plurality of unit monitor transistors 16 may have substantially equal on-resistance characteristics or may have different on-resistance characteristics.

The gate threshold voltage, channel area, on-resistance characteristics, and the like of the unit monitor transistor 16 included in each system monitor transistor 15 may be substantially equal to or different from the gate threshold voltage, channel area, on-resistance characteristics, and the like of the unit transistor 13 included in the corresponding system transistor 12.

The channel area of the unit monitor transistor 16 included in each system monitor transistor 15 is preferably smaller than the channel area of the unit transistor 13 included in the corresponding system transistor 12. The electrical characteristics of each system monitor transistor 15 are finely adjusted by adjusting the number of unit monitor transistors 16, gate threshold voltage, channel area, and the like.

Referring to fig. 1 and 3, the semiconductor device 1A includes a plurality of temperature sensing diodes 17 (diodes) formed in a plurality of temperature measuring regions 9. The plurality of temperature sensing diodes 17 includes a first temperature sensing diode 17A formed in the first temperature measuring region 9A and a second temperature sensing diode 17B formed in the second temperature measuring region 9B. In this embodiment, the first temperature sensing diode 17A is formed in the output region 7, and the second temperature sensing diode 17B is formed in the control region 10. That is, the main transistor 11, the monitor transistor 14, and the temperature sensing diode 17 are integrated in the output region 7.

The first temperature sensing diode 17A includes an anode and a cathode. An anode potential is applied to the anode of the first temperature sensing diode 17A, and a cathode potential is applied to the cathode of the first temperature sensing diode 17A. The voltage between the anode potential and the cathode potential may be equal to or higher than the forward voltage of the first temperature sensing diode 17A (for example, equal to or higher than 5V). The anode potential may be any high potential (e.g., power supply potential VB). The cathode potential may be any low potential lower than the anode potential (for example, a potential lower than the power supply potential VB by about 5V).

A first temperature measurement signal ST1 for detecting the first temperature TE1 of the output region 7 is generated in the first temperature sensing diode 17A and the first temperature measurement region 9A. The first temperature sensing diode 17A has a first forward voltage Vf1, and the first forward voltage Vf1 has a temperature characteristic that varies according to the first temperature TE1 of the output region 7. Specifically, the first forward voltage Vf1 has a negative temperature characteristic that the first forward voltage Vf1 linearly decreases with an increase in the first temperature TE1. The first temperature measurement signal ST1 varies according to the first temperature TE1 of the output region 7, and indirectly detects the first temperature TE1.

The second temperature sensing diode 17B includes an anode and a cathode. An anode potential is applied to the anode of the second temperature sensing diode 17B, and a cathode potential is applied to the cathode of the second temperature sensing diode 17B. The voltage between the anode potential and the cathode potential may be equal to or higher than the forward threshold voltage of the second temperature sensing diode 17B (for example, equal to or higher than 5V). The anode potential may be any high potential (e.g., power supply potential VB). The cathode potential may be any low potential lower than the anode potential (for example, a potential lower than the power supply potential VB by about 5V).

The second temperature sensing diode 17B generates a second temperature measurement signal ST2 for detecting the second temperature TE2 of the control region 10 in the second temperature measurement region 9B. The second temperature sensing diode 17B has a second forward voltage Vf2, and the second forward voltage Vf2 has a temperature characteristic that varies according to the second temperature TE2 of the control region 10. Specifically, the second forward voltage Vf2 has a negative temperature characteristic that the second forward voltage Vf2 linearly decreases with an increase in the second temperature TE2. The second temperature measurement signal ST2 varies according to the second temperature TE2 of the control region 10, and indirectly detects the second temperature TE2.

The second temperature sensing diode 17B preferably has substantially the same structure as the first temperature sensing diode 17A and has substantially the same electrical characteristics as the first temperature sensing diode 17A. When the main transistor 11 generates the output current IO, the second temperature TE2 is smaller than the first temperature TE1 (T1 > T2). Therefore, when the output current IO is generated, the second forward voltage Vf2 of the second temperature sensing diode 17B exceeds the first forward voltage Vf1 of the first temperature sensing diode 17A (Vf 1 < Vf 2).

The semiconductor device 1A includes a control circuit 18 formed in the control region 10. The control circuit 18 may also be referred to as a "control IC (Control Integrated Circuit)". The control circuit 18 constitutes IPD (Intelligent Power Device) together with the main transistor 11. The IPD may also be referred to as "IPM (Intelligent Power Module)". The control circuit 18 includes: a plurality of functional circuits that realize various functions in response to an electrical signal input from the outside.

The multi-functional circuit includes: a gate drive circuit 19, an active clamp circuit 20, an overcurrent protection circuit 21, and an overheat protection circuit 22. The overcurrent protection circuit 21 may also be referred to as a "OCP (Over Current Protection) circuit" and the overheat protection circuit 22 may also be referred to as a "TSD (Thermal Shutdown) circuit". Although not shown, the control circuit 18 may include a plurality of types of abnormality detection circuits for detecting an abnormality (for example, overvoltage) of the main transistor 11, the monitor transistor 14, and the like.

The gate driving circuit 19 is electrically connected to the first gate FG of the main transistor 11 and the first monitor gate FMG of the monitor transistor 14, and controls the main transistor 11 and the monitor transistor 14 in response to an electric signal from the outside. Specifically, the gate driving circuit 19 is electrically connected to n first gates FG of the main transistor 11 (second gates SG of the n system transistors 12), and individually controls the n system transistors 12.

The gate driving circuit 19 is also configured to be electrically connected to n first monitor gates FMG (n second monitor gates SMG) of the monitor transistors 14, and individually control the n system monitor transistors 15. In this embodiment, n first monitor gates FMG (n second monitor gates SMG) of the monitor transistor 14 are electrically connected to the corresponding first gates FG. Accordingly, the gate driving circuit 19 individually controls the n first monitor gates FMG in such a manner as to be interlocked with the n first gates FG.

The active clamp circuit 20 is electrically connected to the main transistor 11 and the gate drive circuit 19. The active clamp circuit 20 is configured to: when the counter electromotive force is input to the main transistor 11 due to the energy stored in the inductive load L, the output voltage VO is limited (clamped), thereby protecting the main transistor 11 from the counter electromotive force. That is, the active clamp circuit 20 is configured to: when the counter electromotive force is inputted, the main transistor 11 is caused to perform an active clamp operation, thereby limiting the output voltage VO until the counter electromotive force is consumed.

Specifically, the active clamp circuit 20 is electrically connected to the first gate FG and the first drain FD of a part (but not all) of the main transistor 11. The active clamp circuit 20 controls a part of the system transistors 12 to be in an on state and controls the other system transistors 12 to be in an off state during the active clamp operation. That is, the active clamp circuit 20 increases the on-resistance of the main transistor 11 during the active clamp operation, and protects the main transistor 11 from the counter electromotive force.

The active clamp circuit 20 is also electrically connected to the monitor transistor 14 and the gate drive circuit 19. The active clamp circuit 20 is configured to: when the counter electromotive force is input to the monitor transistor 14 due to the energy stored in the inductive load L, the output voltage VO is limited (clamped), thereby protecting the monitor transistor 14 from the counter electromotive force. That is, the active clamp circuit 20 causes the monitor transistor 14 to perform an active clamp operation when the back electromotive force is inputted, thereby limiting the output voltage VO until the back electromotive force is consumed.

Specifically, the active clamp circuit 20 is electrically connected to the first monitor gate FMG and the first monitor drain FMD of a part (but not all) of the monitor transistor 14. The active clamp circuit 20 controls a part of the system monitor transistors 15 to be in an on state and controls the other system monitor transistors 15 to be in an off state during the active clamp operation.

Specifically, the active clamp circuit 20 performs on/off control of the n-system monitor transistor 14 in conjunction with on/off of the n-system main transistor 11 during the active clamp operation. More specifically, the active clamp circuit 20 controls the system monitor transistor 15 corresponding to the system transistor 12 in the on state to be in the on state and controls the system monitor transistor 15 corresponding to the system transistor 12 in the off state to be in the off state during the active clamp operation.

That is, the active clamp circuit 20 increases the on-resistance of the monitor transistor 14 during the active clamp operation, and protects the monitor transistor 14 from the counter electromotive force. The active clamp circuit 20 may be configured to: when the first source FS of the main transistor 11 is equal to or lower than a predetermined voltage (for example, a predetermined negative voltage), the on/off control is performed on the n system transistors 12, and the on/off control is performed on the n system monitor transistors 15.

The overcurrent protection circuit 21 is electrically connected to the monitor transistor 14 and the gate drive circuit 19. The overcurrent protection circuit 21 is electrically connected to the first monitor source FMS of the monitor transistor 14, and obtains a part or all (in this embodiment, all) of the output monitor current IOM. The overcurrent protection circuit 21 is configured to control the gate signal G generated by the gate drive circuit 19 in accordance with the output monitor current IOM, and to limit the output current IO to a predetermined value or less (for example, 0A), thereby protecting the main transistor 11 from the overcurrent.

The overcurrent protection circuit 21 may be configured to acquire at least one of the plurality of system monitor currents ISM. The current input to the overcurrent protection circuit 21 in the output monitor current IOM (system monitor currents ISM) is regulated by the shunt and non-shunt of the output monitor current IOM (system monitor currents ISM) according to the circuit configuration of the control circuit 18. The overcurrent protection circuit 21 indirectly monitors the output current IO through the output monitor current IOM.

The overcurrent protection circuit 21 may be configured to: when the output monitor current IOM exceeds a predetermined threshold value, an overcurrent detection signal SOD is generated, and the overcurrent detection signal SOD is output to the gate drive circuit 19. The overcurrent detection signal SOD is a signal for limiting a part or all of the n gate signals G generated in the gate drive circuit 19 to a predetermined value or less (for example, off).

The gate driving circuit 19 limits a part or all of the n gate signals G in response to the overcurrent detection signal SOD, and suppresses an overcurrent flowing through the main transistor 11. When the output monitor current IOM is equal to or lower than the predetermined threshold value, the overcurrent protection circuit 21 shifts the gate drive circuit 19 (the main transistor 11) to normal control.

The above-described configuration (operation) of the overcurrent protection circuit 21 is merely an example. The overcurrent protection circuit 21 may have various current-voltage characteristics and various operation modes. The overcurrent protection circuit 21 may have a circuit configuration including at least one of the following characteristics: constant current droop characteristics, feedback current limit characteristics, and constant power control voltage droop characteristics. The overcurrent protection circuit 21 may have a circuit configuration including an operation mode of an automatic recovery type or a latch type (a closing type that does not automatically recover).

The overheat protection circuit 22 is electrically connected to the gate drive circuit 19 and the at least one temperature sensing diode 17. In this embodiment, the overheat protection circuit 22 is electrically connected to both the first and second temperature sensing diodes 17A and 17B, and receives a part or all of the first temperature measurement signal ST1 (hereinafter, simply referred to as "first temperature measurement signal ST 1") from the first temperature sensing diode 17A and receives a part or all of the second temperature measurement signal ST2 (hereinafter, simply referred to as "second temperature measurement signal ST 2") from the second temperature sensing diode 17B.

Specifically, the overheat protection circuit 22 is configured to control the gate signal G generated by the gate driving circuit 19 based on the first temperature measurement signal ST1 and the second temperature measurement signal ST2, and to limit the output current IO to a predetermined value or less (for example, 0A), thereby protecting the main transistor 11 from overheat.

As an example, the overheat protection circuit 22 may include: a low potential applying unit 23, a first current source 24, a second current source 25, a differential circuit 26, and a logic circuit 27. The low potential applying section 23 applies a low potential smaller than the power supply potential VB to other circuits. The low potential applying section 23 may be a circuit device such as a constant voltage regulator or a zener diode, or may be any low potential wiring.

The first current source 24 is electrically connected to the first temperature sensing diode 17A and the low potential applying section 23, and flows a constant current to the low potential applying section 23. The first current source 24 forms a first node N1 with the first temperature sensing diode 17A. The second current source 25 is electrically connected to the second temperature sensing diode 17B and the low potential applying section 23, and supplies a constant current to the low potential applying section 23. The second current source 25 may be configured to generate a constant current substantially equal to the first current source 24. The second current source 25 forms a second node N2 with the second temperature sensing diode 17B.

The differential circuit 26 is electrically connected to the first node N1 and the second node N2. The differential circuit 26 may also include a comparator having a non-inverting input (-) and an inverting input (+). The comparator may have a noise-reducing hysteresis characteristic between the non-inverting input (-) and the inverting input (+) terminal. The first node N1 may be electrically connected to the non-inverting input (-) of the comparator and the second node N2 may be electrically connected to the inverting input (+) of the comparator.

The differential circuit 26 is configured to output a differential signal Δvf (Δvf=vf2-vf1, vf2 > Vf 1) indicating a differential value between the first temperature measurement signal ST1 (first forward voltage Vf 1) and the second temperature measurement signal ST2 (second forward voltage Vf 2). The differential signal avf indirectly represents the temperature difference Δtj between the first temperature TE1 of the output zone 7 and the second temperature TE2 of the control zone 10 (Δtj=t1-TE 2: TE2 < TE 1).

The logic circuit 27 is electrically connected to the differential circuit 26 and the gate drive circuit 19. The logic circuit 27 is configured to: for example, when the differential signal Δvf exceeds a predetermined threshold VT (VT < Δvf), the overheat detection signal SOH is generated and output to the gate drive circuit 19. The overheat detection signal SOH is a signal for limiting a part or all of the n gate signals G generated in the gate drive circuit 19 to off.

The gate drive circuit 19 controls a part or all of the main transistor 11 to be in an off state in response to the overheat detection signal SOH, and suppresses the temperature rise of the output region 7. In addition, the gate drive circuit 19 controls a part or all of the monitor transistor 14 to be in an off state in response to the overheat detection signal SOH, and suppresses a temperature rise in the current detection region 8 (output region 7). The logic circuit 27, for example, when the differential signal Δvf is equal to or smaller than the threshold VT (VT > Δvf), shifts the gate driving circuit 19 to normal control.

Of course, the overheat protection circuit 22 may be configured to input only the first temperature measurement signal ST1 from the first temperature sensing diode 17A, and to control the gate signal G based on only the first temperature measurement signal ST 1. In this case, the overheat protection circuit 22 may be configured to: when the first temperature measurement signal ST1 exceeds the threshold VT (ST 1 > VT), a part or all of the main transistor 11 is controlled to be in an off state, and when the first temperature measurement signal ST1 is equal to or lower than the threshold VT (ST 1 < VT), the main transistor 11 is controlled to be in an on state.

Referring to fig. 2, the semiconductor device 1A includes an interlayer insulating layer 30 covering the first main surface 3. The interlayer insulating layer 30 covers the output region 7, the current detection region 8, the temperature measurement region 9, and the control region 10. In this embodiment, the interlayer insulating layer 30 is formed of a multilayer wiring structure having a laminated structure in which a plurality of insulating layers and a plurality of wiring layers are alternately laminated.

Each insulating layer may contain at least one of a silicon oxide film and a silicon nitride film. Each wiring layer may include at least one of a pure Al layer (an Al layer having a purity of 99% or more), a Cu layer (a Cu layer having a purity of 99% or more), an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

Referring to fig. 2 to 5, the semiconductor device 1A includes n main gate lines 31 as an example of control lines arranged above the first main surface 3 (an open above). The n main gate wirings 31 are composed of n wiring layers selectively routed into the interlayer insulating layer 30. The n main gate wirings 31 are electrically connected in a one-to-one correspondence with the n first gates FG of the main transistor 11 in a mutually electrically independent state in the output region 7.

The n main gate wirings 31 are electrically connected to the control circuit 18 (gate driving circuit 19) in the control region 10, respectively. The n main gate wirings 31 individually transfer n gate signals G generated by the control circuit 18 (gate drive circuit 19) to n first gates FG of the main transistor 11.

The n main gate wirings 31 are electrically connected to the third gates TG of 1 or more unit transistors 13, respectively, wherein the 1 or more unit transistors 13 are to be controlled individually from an aggregate composed of a plurality of unit transistors 13. The n main gate wirings 31 may include: 1 or more main gate wirings 31 electrically connected to one unit transistor 13 to be systemized as an individual control object. In addition, the n main gate wirings 31 may include: one or a plurality of main gate wirings 31 connected in parallel to a plurality of unit transistors 13 to be systemized as individual control targets.

The semiconductor device 1A includes n monitor gate wirings 32 as an example of monitor control wirings arranged above the first main surface 3. The n monitor gate wirings 32 are composed of n wiring layers selectively routed into the interlayer insulating layer 30. The n monitor gate wirings 32 are electrically connected in a one-to-one correspondence with the n first monitor gates FMG of the monitor transistors 14 in the output region 7 in a mutually electrically independent state.

The n monitor gate wirings 32 are electrically connected to the control circuit 18 (gate driving circuit 19) in the control region 10, respectively. The n monitor gate wirings 32 individually transfer the n monitor gate signals MG generated by the control circuit 18 (gate drive circuit 19) to the n first monitor gates FMG of the monitor transistors 14.

The n monitor gate wirings 32 are electrically connected to the third monitor gates TMG of 1 or more unit monitor transistors 16, respectively, wherein the 1 or more unit monitor transistors 16 are to be systemized as individual control targets from an aggregate composed of a plurality of unit monitor transistors 16. The n monitor gate wirings 32 may include: and 1 or more monitor gate wirings 32 electrically connected to 1 unit monitor transistors 16 to be systemized as individual control targets.

The n monitor gate wirings 32 may include: 1 or more monitor gate wirings 32 connected in parallel to a plurality of unit monitor transistors 16 to be systemized as individual control targets. In the present embodiment, the n monitor gate wirings 32 are electrically connected to the corresponding main gate wirings 31 in a one-to-one correspondence. The n monitor gate wirings 32 may be integrally formed with the corresponding main gate wirings 31, respectively.

The n monitor gate wirings 32 are electrically connected to the control circuit 18 (gate driving circuit 19) via the corresponding main gate wirings 31, respectively. The n monitor gate wirings 32 individually transfer n gate signals G (n monitor gate signals MG) generated by the control circuit 18 (gate drive circuit 19) to n first monitor gates FMG of the monitor transistors 14.

The semiconductor device 1A includes 1 or more main source wirings 33 disposed in the interlayer insulating layer 30. The 1 or more main source wirings 33 are constituted by wiring layers formed in the interlayer insulating layer 30. 1 or more main source wirings 33 are selectively routed into the interlayer insulating layer 30 and electrically connected to the first source FS of the main transistor 11.

The semiconductor device 1A includes 1 or more monitor source wirings 34 disposed in the interlayer insulating layer 30. The 1 or more monitor source wirings 34 include wiring layers formed within the interlayer insulating layer 30. 1 or more monitor source wirings 34 are selectively routed into the interlayer insulating layer 30 and electrically connected to the first monitor source FMS of the monitor transistor 14 and the overcurrent protection circuit 21.

Referring to fig. 1 and 2, the semiconductor device 1A includes a plurality of terminal electrodes 35. The number, arrangement, and planar shape of the plurality of terminal electrodes 35 are adjusted according to the specifications of the main transistor 11 and the control circuit 18, and are not limited to those shown in fig. 1. In this embodiment, the plurality of terminal electrodes 35 includes: a drain terminal 36 (power supply terminal), a source terminal 37 (output terminal), an input terminal 38, an enable terminal 39, a sense terminal 40, and a ground terminal 41.

The drain terminal 36 directly covers the second main surface 4 of the chip 2 and is electrically connected to the second main surface 4. The drain terminal 36 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The drain terminal 36 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are laminated in any manner. The drain terminal 36 is electrically connected to the first drain FD of the main transistor 11, the first monitor drain FMD of the monitor transistor 14, and the control circuit 18, and transmits the power supply potential VB.

The terminal electrode 35 other than the drain terminal 36 is disposed on the interlayer insulating layer 30. The source terminal 37 is disposed on the first main surface 3 above the output region 7 (above). The source terminal 37 has a planar area smaller than that of the drain terminal 36. The source terminal 37 is electrically connected to the first source FS of the main transistor 11 and the control circuit 18. The source terminal 37 transmits the output current IO generated by the main transistor 11 to the outside.

The terminal electrodes 38 to 41 other than the source terminal 37 are disposed on the first main surface 3 on regions (specifically, the control regions 10) other than the output regions 7, respectively. The terminal electrodes 38 to 41 other than the source terminal 37 each have a planar area smaller than the planar area of the source terminal 37. The input terminal 38 transmits an input voltage for driving the control circuit 18.

The enable terminal 39 delivers an electrical signal for enabling or disabling a portion or all of the functions of the control circuit 18. The sense terminal 40 transmits an electric signal for detecting an abnormality of the main transistor 11, the monitor transistor 14, the control circuit 18, and the like to the outside. The ground terminal 41 transmits the ground voltage GND to the control circuit 18 via a ground wiring (not shown) led into the interlayer insulating layer 30.

The terminal electrodes 37 to 40 other than the drain terminal 36 may include at least one of a pure Al layer, a pure Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer. The semiconductor device 1A may include a plurality of plating layers that cover the outer surfaces of the terminal electrodes 37 to 40 other than the drain terminal 36. Each plating layer may contain at least one of a Ni layer, a Pd layer, and an Au layer.

The semiconductor device 1A includes at least one (in this embodiment, a plurality of) protection regions 42 provided on the first main surface 3. The guard region 42 forms part of the circuit region 6. The guard region 42 may also be referred to as a "fifth device region". The plurality of protection regions 42 are regions each having a circuit device configured to protect an electric circuit from static electricity. The plurality of protection regions 42 are provided on the first main surface 3 at intervals, and are covered with the interlayer insulating layer 30.

Fig. 1 shows an example in which the plurality of protection areas 42 includes a plurality (3) of first protection areas 42A and a plurality (4) of second protection areas 42B, as an example. The main purpose of the plurality of first protection regions 42A is to protect the output region 7 (main transistor 11) from static electricity. The main purpose of the plurality of second protection areas 42B is to protect the control area 10 (control circuit 18) from static electricity.

In this embodiment, the plurality of first protection regions 42A are provided inside the first main surface 3 (preferably, in the region near the output region 7) in a plan view. The plurality of second protection regions 42B are provided at the peripheral edge portion of the first main surface 3 in plan view. The plurality of second protection regions 42B are preferably arranged at positions close to the terminal electrodes 36 to 40, respectively, in plan view.

The plurality of second protection regions 42B may be arranged, for example, at intervals in the first direction X or the second direction Y from the plurality of terminal electrodes 35, and may face at least one terminal electrode 35 in the first direction X or the second direction Y. The plurality of second protection regions 42B may also overlap at least 1 terminal electrode 35 (e.g., terminal electrodes 37 to 40) in plan view. In fig. 1, an example is shown in which the plurality of second protection regions 42B are arranged close to the terminal electrode 35 other than the source terminal 37.

Each protection zone 42 preferably has a planar area smaller than the planar area of the output zone 7. Each guard region 42 preferably has a planar area that is smaller than the planar area of the control region 10. The protective regions 42 preferably have a planar surface area in plan view that exceeds the planar surface area of the temperature measuring regions 9. The number, position, size, planar shape, etc. of the protection areas 42 are arbitrarily adjusted according to the number, position, size, planar shape, etc. of the protection objects.

Referring to fig. 1 and 3, the semiconductor device 1A includes a plurality of ESD diodes 43 (diodes) formed in a plurality of protection regions 42. ESD is an abbreviation for "Electro Static Discharge". The ESD diode 43 may also be referred to as an "electrostatic destruction protection diode". The plurality of ESD diodes 43 includes a plurality of first ESD diodes 43A formed in the plurality of first protection regions 42A and a plurality of second ESD diodes 43B formed in the plurality of second protection regions 42B.

The plurality of first ESD diodes 43A are interposed between the plurality of main gate wirings 31 and any application terminal of the low potential so that the forward current flows toward the plurality of main gate wirings 31, respectively, and protect the main transistor 11 and the monitor transistor 14 from static electricity. The plurality of first ESD diodes 43A includes an anode and a cathode, respectively. Anodes of the plurality of first ESD diodes 43A are electrically connected to an arbitrary application terminal of a low potential (for example, the source terminal 37 or the ground terminal 41). Cathodes of the plurality of first ESD diodes 43A are electrically connected to the plurality of main gate wirings 31, respectively.

The plurality of second ESD diodes 43B are interposed between the plurality of terminal electrodes 35 and any application end of the low potential so that the forward current flows toward the plurality of terminal electrodes 35, and protect the control circuit 18 from static electricity. The at least one second ESD diode 43B is interposed between the active clamp 20 and an arbitrary application terminal of the low potential so that a forward current flows toward the active clamp 20.

The plurality of second ESD diodes 43B includes an anode and a cathode, respectively. Anodes of the plurality of second ESD diodes 43B are electrically connected to an arbitrary application terminal of a low potential (e.g., the source terminal 37 or the ground terminal 41). The cathodes of the second ESD diodes 43B are electrically connected to the corresponding terminal electrode 35 and the active clamp circuit 20, respectively.

Fig. 6A to 6C are circuit diagrams for explaining an example of the operation of the main transistor 11 and the monitor transistor 14, respectively, corresponding to fig. 4. Referring to fig. 6A, gate signals G (i.e., off signals) smaller than the gate threshold voltage are all input to the n main gate wirings 31. Such control is applied, for example, to the turning-off operation of the main transistor 11. Thereby, all the system transistors 12 are turned off.

Thereby, the main transistor 11 is turned off. On the other hand, in the monitor transistor 14, the n system monitor transistors 15 are turned off in conjunction with the n system transistors 12. Thereby, the monitor transistor 14 is in an off state in association with the main transistor 11.

Referring to fig. 6B, gate signals G (i.e., on signals) equal to or higher than the gate threshold voltage are all input to the n main gate wirings 31. Such control is applied, for example, during normal operation of the main transistor 11. Thus, the n system transistors 12 are turned on, and as a result, the main transistor 11 is turned on. The main transistor 11 generates an output current IO containing n system currents IS generated by n system transistors 12. At this time, the channel utilization of the main transistor 11 is relatively increased, and the on-resistance is relatively decreased.

On the other hand, in the monitor transistor 14, the n system monitor transistors 15 are turned on in conjunction with the n system transistors 12. Thereby, the monitor transistor 14 is connected to the main transistor 11 and is turned on. The monitor transistor 14 generates an output monitor current IOM that monitors the output current IO. The output monitor current IOM contains n system monitor currents ISM generated by n system monitor transistors 15. At this time, the channel utilization of the monitor transistor 14 is relatively increased, and the on-resistance is relatively decreased.

Referring to fig. 6C, a gate signal G (i.e., an on signal) equal to or higher than a gate threshold voltage is input to x (1+.x < n) main gate wirings 31, and a gate signal G (i.e., an off signal) lower than the gate threshold voltage is input to (n-x) main gate wirings 31. Such control is applied to the active clamp operation of the main transistor 11. Thus, the x system transistors 12 are turned on, and the (n-x) system transistors 12 are turned off, so that the main transistor 11 is turned on in a state where a part of the current paths are on and a part of the current paths are off.

The main transistor 11 generates an output current IO containing x system currents IS generated by x system transistors 12. In other words, the main transistor 11 generates an output current IO including x system currents IS exceeding 0A and (n-x) system currents IS composed of 0A. At this time, the channel utilization of the main transistor 11 is relatively reduced, and the on-resistance is relatively increased.

On the other hand, in the monitor transistor 14, the x system monitor transistors 15 are turned on in conjunction with the x system transistors 12, and the (n-x) system monitor transistors 15 are turned off in conjunction with the (n-x) system transistors 12. Thus, the monitor transistor 14 is in a conductive state in a state where a part of the current path is conductive and a part of the current path is non-conductive so as to be coupled to the main transistor 11.

The monitor transistor 14 includes x system monitor currents ISM generated by x system monitor transistors 15, and generates an output monitor current IOM that monitors the output current IO. In other words, the monitor transistor 14 generates the output monitor current IOM including x system monitor currents ISM exceeding 0A, and (n-x) system monitor currents ISM composed of 0A. At this time, the channel utilization of the monitor transistor 14 is relatively reduced, and the on-resistance is relatively increased.

In fig. 6A to 6C, a part or all (in this embodiment, all) of the output monitor current IOM generated by the monitor transistor 14 is input to the overcurrent protection circuit 21 (see fig. 3). The overcurrent protection circuit 21 generates an overcurrent detection signal SOD when the output monitor current IOM exceeds a predetermined threshold value, and outputs the overcurrent detection signal SOD to the gate drive circuit 19.

The gate driving circuit 19 limits a part or all of the n gate signals G in response to the overcurrent detection signal SOD, and limits a part or all of the n system currents IS generated by the n system transistors 12. Thereby, the overcurrent state of the main transistor 11 is eliminated. When the output monitor current IOM is equal to or less than the predetermined threshold value, the overcurrent protection circuit 21 stops generating the overcurrent detection signal SOD, and the gate drive circuit 19 (main transistor 11) is shifted to the normal control.

On the other hand, in fig. 6A to 6C, the first temperature measurement signal ST1 generated by the first temperature sensing diode 17A and the second temperature measurement signal ST2 generated by the second temperature sensing diode 17B are input to the overheat protection circuit 22 (refer to fig. 3). The overcurrent protection circuit 21 generates a differential signal Δvf from the first temperature measurement signal ST1 and the second temperature measurement signal ST 2. When the differential signal Δvf exceeds the threshold VT, the overcurrent protection circuit 21 generates the overheat detection signal SOH, and outputs the overheat detection signal SOH to the gate drive circuit 19.

The gate drive circuit 19 limits a part or all of the n gate signals G in response to the overheat detection signal SOH, and limits a part or all of the n system currents IS generated by the n system transistors 12. Thereby, a part or all of the main transistor 11 is controlled to be in an off state, while a part or all of the monitor transistor 14 is controlled to be in an off state. Thereby, the overheated state of the output area 7 is eliminated. When the differential signal Δvf is equal to or smaller than the threshold VT, the overcurrent protection circuit 21 stops generating the overheat detection signal SOH, and the gate drive circuit 19 shifts to normal control.

In this way, in the semiconductor device 1A, the on-resistance (channel utilization) of the n-system main transistor 11 is configured to be changed by individual control of the n-system transistors 12. Specifically, the main transistor 11 is controlled such that the on-resistance in the active clamp operation is different from the on-resistance in the normal operation by individual control of the n system transistors 12. More specifically, the main transistor 11 is controlled such that the on-resistance in the active clamp operation exceeds the on-resistance in the normal operation by individual control of the n system transistors 12.

On the other hand, the monitor transistor 14 is configured such that the on-resistance (channel utilization) is changed by individual control of m (m=n in this embodiment) system monitor transistors 15. Specifically, the monitor transistor 14 is configured to change on-resistance in association with the main transistor 11.

Specifically, the monitor transistor 14 is controlled so that the on-resistance in the active clamp operation in association with the main transistor 11 is different from the on-resistance in the normal operation. More specifically, the monitor transistor 14 is controlled so that the on-resistance in the active clamp operation in association with the main transistor 11 exceeds the on-resistance in the normal operation.

On the other hand, the overcurrent protection circuit 21 controls the on/off of the main transistor 11 based on the output from the monitor transistor 14, protecting the main transistor 11 from an overcurrent. The overheat protection circuit 22 controls the on/off of the main transistor 11 and the on/off of the monitor transistor 14 based on the outputs from the plurality of temperature sensing diodes 17, and protects the main transistor 11 and the monitor transistor 14 from overheat. The plurality of ESD diodes 43 protect the main transistor 11 and the control circuit 18 from static electricity.

Fig. 7 is a circuit block diagram showing a specific electrical configuration example of the semiconductor device 1A shown in fig. 1 (=a configuration example in which the main transistor 11 of the 2-system and the monitor transistor 14 of the 2-system are applied to the semiconductor device 1A). Fig. 7 is a circuit diagram showing a main portion of the control circuit 18. Fig. 7 shows an example in which the inductive load L is connected to the source terminal 37.

The semiconductor device 1A includes: a 2-system (n=2) main transistor 11, a 2-system (m=n=2) monitor transistor 14, 2 (n=2) main gate wirings 31, 2 (m=n=2) monitor gate wirings 32, a gate driving circuit 19, an active clamp circuit 20, and an overcurrent protection circuit 21.

The 2-system main transistor 11 includes a first-system transistor 12A and a second-system transistor 12B. The 2 second gates SG constitute 2 first gates FG. The 2 second drains SD are electrically connected to the drain terminals 36, respectively. The 2 second sources SS are electrically connected to the source terminals 37, respectively.

The first system transistor 12A generates a first system current IS1 and the second system transistor 12B generates a second system current IS2. The main transistor 11 of the 2-system generates an output current IO comprising a first system current IS1 and a second system current IS2. As can be seen from the above description, the second system current IS2 may be different from the first system current IS1 or equal to the first system current IS 1. Hereinafter, the first system current IS1 and the second system current IS2 simply represent the system current IS without distinction.

The main transistor 11 of the system is controlled in a first operation mode, a second operation mode and a third operation mode. In the first operation mode, the first to second system transistors 12A to 12B are simultaneously controlled to be in an off state. In the second operation mode, the first to second system transistors 12A to 12B are simultaneously controlled to be in an on state. In the third operation mode, only one of the first to second system transistors 12A to 12B is controlled to be in an on state. In this mode, in the third operation mode, the first system transistor 12A is controlled to be in an on state, and the second system transistor 12B is controlled to be in an off state.

The 2-system monitor transistor 14 includes a first system monitor transistor 15A and a second system monitor transistor 15B. The 2 second monitor gates SMG constitute 2 first monitor gates FMG. The 2 second monitor drain SMDs are electrically connected to the drain terminals 36, respectively. The 2 second monitor sources SMS are electrically separated from the source terminal 37 (the second sources SS of the first to second system transistors 12A to 12B).

The first system monitor transistor 15A generates a first system monitor current ISM1, and the second system monitor transistor 15B generates a second system monitor current ISM2. The monitor transistor 14 of the 2-system generates an output monitor current IOM including a first system monitor current ISM1 and a second system monitor current ISM2. As can be seen from the above description, the second system monitor current ISM2 may be different from the first system monitor current ISM1 or may be equal to the first system monitor current ISM 1. Hereinafter, the first system monitor current ISM1 and the second system monitor current ISM2 represent the system monitor current ISM without distinction.

The monitor transistor 14 of the system is controlled 2 in a first operation mode, a second operation mode and a third operation mode. In the first operation mode, the first to second system monitoring transistors 15A to 15B are simultaneously controlled to be in an off state. In the second operation mode, the first to second system monitor transistors 15A to 15B are simultaneously controlled to be in the on state. In the third operation mode, only one of the first to second system monitor transistors 15A to 15B is controlled to be in an on state.

In the present mode, in the third operation mode, the first system monitor transistor 15A is controlled to be in an on state, and the second system monitor transistor 15B is controlled to be in an off state. In the present embodiment, the first to third operation modes of the monitor transistor 14 are performed in conjunction with the first to third operation modes of the main transistor 11.

The 2 main gate wirings 31 include a first main gate wiring 31A and a second main gate wiring 31B. The first main gate wiring 31A is electrically connected to the second gate SG of the first system transistor 12A. The second main gate wiring 31B is electrically connected to the second gate SG of the second system transistor 12B.

The 2 monitor gate wirings 32 include a first monitor gate wiring 32A and a second monitor gate wiring 32B. The first monitor gate wiring 32A is electrically connected to the first main gate wiring 31A and the second monitor gate SMG of the first system monitor transistor 15A. The second monitor gate wiring 32B is electrically connected to the second main gate wiring 31B and the second monitor gate SMG of the second system monitor transistor 15B.

In the following description, "a state of being electrically connected to the first main gate wiring 31A" includes "a state of being electrically connected to the second gate SG of the first system transistor 12A" and "a state of being electrically connected to the second monitor gate SMG of the first system monitor transistor 15A". In addition, "a state of being electrically connected to the second main gate wiring 31B" includes "a state of being electrically connected to the second gate SG of the second system transistor 12B" and "a state of being electrically connected to the second monitor gate SMG of the second system monitor transistor 15B".

The gate driving circuit 19 is electrically connected to the first to second main gate wirings 31A to 31B. The gate driving circuit 19 generates first to second gate signals G1 to G2 in response to the enable signal EN, and outputs the first to second gate signals G1 to G2 to the first to second main gate wirings 31A to 31B, respectively. The first to second monitor gate signals MG1 to MG2 input to the first to second system monitor transistors 15A to 15B are constituted by the first to second gate signals G1 to G2, respectively.

Specifically, in the enable state in which the enable signal EN is at the high level (en=h), the gate drive circuit 19 generates the first and second gate signals G1 to G2 for controlling both the first and second system transistors 12A to 12B and both the first and second system monitor transistors 15A to 15B to be in the on state. In the disabled state in which the enable signal EN is low (en=l), the gate drive circuit 19 generates first and second gate signals G1 to G2 that control both the first and second system transistors 12A to 12B and both the first and second system monitor transistors 15A to 15B to be in the off state.

In this embodiment, the gate driving circuit 19 includes: a first current source 51, a second current source 52, a third current source 53, a fourth current source 54, a controller 55, and an n-channel driving MISFET56. Although not specifically illustrated, a first current source 51, a second current source 52, a third current source 53, a fourth current source 54, a controller 55, and a driving MISFET56 are formed in the control region 10, respectively.

The first current source 51 generates a first source current IH1. The first current source 51 is electrically connected to the application terminal of the boost voltage VG (=charge pump output) and the first main gate wiring 31A. The second current source 52 generates a second source current IH2. The second current source 52 is electrically connected to the application terminal of the boost voltage VG and the second main gate wiring 31B.

The third current source 53 generates the first sink current IL1. The third current source 53 is electrically connected to the first main gate wiring 31A and the source terminal 37. The fourth current source 54 generates a second sink current IL2. The fourth current source 54 is electrically connected to the second main gate wiring 31B and the source terminal 37.

The controller 55 is electrically connected to the first to fourth current sources 51 to 54. The controller 55 controls the first to second current sources 51 to 52 to be on-state and controls the third to fourth current sources 53 to 54 to be off-state in the enable state (en=h). Thus, the first source current IH1 is output to the first main gate wiring 31A, and the second source current IH2 is output to the second main gate wiring 31B.

In the disabled state (en=l), the controller 55 controls the first to second current sources 51 to 52 to be in the off state, and controls the third to fourth current sources 53 to 54 to be in the on state. Thereby, a first sink current IL1 is drawn from the first main gate wiring 31A, and a second sink current IL2 is drawn from the second main gate wiring 31B.

The driving MISFET56 is electrically connected to the second main gate wiring 31B and the source terminal 37. The driving MISFET56 includes: drain, source, gate and back gate. The drain of the driving MISFET56 is electrically connected to the second main gate wiring 31B. The source of the driving MISFET56 is electrically connected to the source terminal 37. The back gate of the driving MISFET56 is electrically connected to the source terminal 37.

The active clamp circuit 20 is connected between the drain and gate of the first system transistor 12A. In addition, an active clamp circuit 20 is connected between the drain and the gate of the first system monitor transistor 15A. The active clamp circuit 20 is configured to control both the first system transistor 12A and the first system monitor transistor 15A to an on state and to control both the second system transistor 12B and the second system monitor transistor 15B to an off state in cooperation with the gate drive circuit 19 when the first source FS (source terminal 37) of the main transistor 11 is negative voltage.

Specifically, the active clamp circuit 20 has an internal node voltage Vx electrically connected to the gate drive circuit 19. The active clamp circuit 20 controls the gate drive circuit 19 via the internal node voltage Vx, and generates first to second gate signals G1 to G2 for controlling both the first system transistor 12A and the first system monitor transistor 15A to be in an on state and for controlling both the second system transistor 12B and the second system monitor transistor 15B to be in an off state.

More specifically, the active clamp circuit 20 generates first to second gate signals G1 to G2 for controlling both the first system transistor 12A and the first system monitor transistor 15A to be in an on state and for controlling both the second system transistor 12B and the second system monitor transistor 15B to be in an off state by controlling the gate drive circuit 19 via the internal node voltage Vx after the transition from the enable state (en=h) to the disable state (en=l) before the transition of the main transistor 11 to the active clamp operation.

The main transistor 11 is shifted to a state before the active clamp operation, specifically, before the output voltage VO is clamped. Both the second-system transistor 12B and the second-system monitor transistor 15B are controlled to be in an off state by fixing the second gate signal G2 to the output voltage VO. That is, the gate/source of the second system transistor 12B is shorted, and the second system monitors the gate/source of the transistor 15B for the short.

The active clamp circuit 20 limits the drain/source voltage (=vbb-VOUT) of the main transistor 11 to a clamp voltage Vclp or less. In this embodiment, the second system transistor 12B and the second system monitor transistor 15B do not contribute to the active clamp operation. Therefore, the active clamp circuit 20 is not connected to the second system transistor 12B and the second system monitor transistor 15B.

In this embodiment, the active clamp circuit 20 includes: a zener diode column 57, a diode column 58, and an n-channel clamp MISFET59. Although a specific illustration is omitted, a zener diode column 57, a diode column 58, and a clamp MISFET59 are formed in the control region 10, respectively.

The zener diode column 57 is constituted by a series circuit including a plurality of (e.g., 8) zener diodes connected in series in the forward direction. The number of zener diodes is arbitrary and may be 1. The zener diode column 57 includes a cathode and an anode. The cathode of the zener diode string 57 is electrically connected to the drain terminal 36 and the second drains SD of the first to second system transistors 12A to 12B.

The diode string 58 is constituted by a series circuit including a plurality of (e.g., 3) pn junction diodes connected in series in the forward direction. The number of pn junction diodes is arbitrary and may be 1. The diode string 58 includes a cathode and an anode. The anode of the diode string 58 is connected with the anode of the zener diode string 57 in reverse bias.

The clamp MISFET59 includes: drain, source, gate and back gate. The drain of the clamp MISFET59 is electrically connected to the drain terminal 36 and the second drains SD of the first to second system transistors 12A to 12B. The source of the clamp MISFET59 is electrically connected to the first main gate wiring 31A. The gate of the clamp MISFET59 is electrically connected to the cathode of the diode column 58. The back gate of the clamp MISFET59 is electrically connected to the source terminal 37.

The internal node voltage Vx of the active clamp circuit 20 is electrically connected to the gate of the driving MISFET 56. The active clamp circuit 20 controls the driving MISFET56 to be in an on state or an off state according to the internal node voltage Vx. The internal node voltage Vx may be the voltage within the active clamp 20. The internal node voltage Vx may be the gate voltage of the clamp MISFET59 or the cathode voltage of one of the pn junction diodes of the diode string 58.

In this embodiment, the semiconductor device 1A includes a first protection circuit 61, a second protection circuit 62, and a third protection circuit 63 as an example of an electrostatic breakdown protection circuit that protects various circuits from static electricity.

The first protection circuit 61 protects the first system transistor 12A from static electricity. The first protection circuit 61 is electrically connected to the first main gate wiring 31A and the source terminal 37. In this embodiment, the first protection circuit 61 is constituted by a first diode pair including the first ESD diode 43A and the first pn junction diode 64 connected in reverse bias.

The cathode of the first ESD diode 43A is electrically connected to the first main gate wiring 31A. The first pn-junction diode 64 comprises a cathode and an anode. The anode of the first pn junction diode 64 is reverse biased connected to the anode of the first ESD diode 43A. The cathode of the first pn junction diode 64 is electrically connected to the source terminal 37.

The second protection circuit 62 protects the second system transistor 12B from static electricity. The second protection circuit 62 is electrically connected to the second main gate wiring 31B and the source terminal 37. In this embodiment, the second protection circuit 62 is constituted by a second diode pair including the first ESD diode 43A and the second pn junction diode 65 connected in reverse bias.

The cathode of the first ESD diode 43A is electrically connected to the second main gate wiring 31B. The second pn junction diode 65 comprises a cathode and an anode. The anode of the second pn junction diode 65 is reverse biased connected to the anode of the first ESD diode 43A. The cathode of the second pn junction diode 65 is electrically connected to the source terminal 37.

The third protection circuit 63 protects the active clamp circuit 20 from static electricity. The third protection circuit 63 is electrically connected to the active clamp circuit 20 and the source terminal 37. The third protection circuit 63 is constituted by a parallel circuit including a depletion type n-channel type protection MISFET66 and a first ESD diode 43A. The protection MISFET66 includes: drain, source, gate and back gate.

The drain of the protection MISFET66 is electrically connected to the gate of the clamp MISFET 59. The source, gate and back gate of the protection MISFET66 are electrically connected to the source terminal 37. The cathode of the second ESD diode 43B is electrically connected to the drain of the protection MISFET66 (the gate of the clamp MISFET 59). The anode of the first ESD diode 43A is electrically connected to the source terminal 37.

Fig. 8 is an enlarged view of the region VIII shown in fig. 1, and is a plan view showing an example of the layout of the output region 7 shown in fig. 7. Fig. 9 is an enlarged view of the area IX shown in fig. 8. Fig. 10 is an enlarged view of the region X shown in fig. 8. Fig. 11 is a cross-sectional view taken along line XI-XI shown in fig. 9. Fig. 12 is a cross-sectional view taken along line XII-XII shown in fig. 9. Fig. 13 is a sectional view taken along line XIII-XIII shown in fig. 9. Fig. 14 is a cross-sectional view taken along line XIV-XIV shown in fig. 9.

Referring to fig. 8 to 14, the semiconductor device 1A includes an n-type first semiconductor region 71 formed in a surface layer portion of the second main surface 4 of the chip 2. The first semiconductor region 71 forms the first drain FD of the main transistor 11 and the first monitor drain FMD of the monitor transistor 14. The first semiconductor region 71 may also be referred to as a "drain region". The first semiconductor region 71 is formed over the entire surface layer portion of the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.

The n-type impurity concentration of the first semiconductor region 71 may be 1×10 ¹⁸ cm ^-3 Above and 1×10 ²¹ cm ^-3 The following is given. The thickness of the first semiconductor region 71 may be 10 μm or more and 450 μm or less. The thickness of the first semiconductor region 71 is preferably 50 μm or more and 150 μm or less. In this embodiment, the first semiconductor region 71 is formed of an n-type semiconductor substrate (Si substrate).

The semiconductor device 1A includes an n-type second semiconductor region 72 formed in a surface layer portion of the first main surface 3 of the chip 2. The second semiconductor region 72 forms the first drain FD of the main transistor 11 and the first monitor drain FMD of the monitor transistor 14 together with the first semiconductor region 71. The second semiconductor region 72 may also be referred to as a "drift region". The second semiconductor region 72 is formed over the entire surface layer portion of the first main surface 3 so as to be electrically connected to the first semiconductor region 71, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.

The second semiconductor region 72 has a lower n-type impurity concentration than the first semiconductor region 71. The n-type impurity concentration of the second semiconductor region 72 may be 1×10 ¹⁵ cm ^-3 Above and 1×10 ¹⁸ cm ^-3 The following is given. The second semiconductor region 72 has a thickness smaller than that of the first semiconductor region 71. The thickness of the second semiconductor region 72 may be 1 μm or more and 25 μm or less. The thickness of the second semiconductor region 72 is preferably 5 μm or more and 15 μm or less. In this embodiment, the second semiconductor region 72 is formed of an n-type epitaxial layer (Si epitaxial layer).

The semiconductor device 1A includes a first trench isolation structure 73 (trench separation structure) as an example of a region isolation structure that partitions the output region 7 in the first main surface 3. The first trench isolation construction 73 may also be referred to as a "DTI (deep trench isolation) construction". The first trench isolation structure 73 is formed in a ring shape surrounding a partial region of the first main surface 3 in a plan view, and defines an output region 7 having a predetermined shape.

In this embodiment, the first trench isolation structure 73 is formed in a four-sided ring shape having 4 sides parallel to the first to fourth side surfaces 5A to 5D in plan view, and divides the output region 7 in a four-sided shape. The planar shape of the first groove separation structure 73 is arbitrary, and may be formed in a polygonal ring shape. The output region 7 may also be divided into polygonal shapes according to the planar shape of the first trench isolation structure 73.

The first trench isolation feature 73 has an isolation width WI and an isolation depth DI. The separation width WI is a width in a direction orthogonal to the direction in which the first trench separation structure 73 extends in a plan view. The separation width WI may be 0.5 μm or more and 2.5 μm or less. The separation width WI is preferably 1.2 μm or more and 2 μm or less. The separation depth DI may be 1 μm or more and 10 μm or less. The separation depth DI is preferably 2 μm or more and 6 μm or less.

The aspect ratio DI/WI of the first trench isolation structure 73 may also exceed 1 and be 5 or less. Aspect ratio DI/WI is the ratio of separation depth DI relative to separation width WI. The aspect ratio DI/WI is preferably 2 or more. The bottom wall of the first trench isolation structure 73 is preferably spaced apart from the bottom of the second semiconductor region 72 by a spacing of 1 μm or more and 5 μm or less.

The first groove separation structure 73 has corners connecting a portion extending in the first direction X and a portion extending in the second direction Y in an arc shape (curved shape). In this embodiment, the quadrangle of the first trench isolation structure 73 is formed in an arc shape. That is, the output region 7 is divided into four-sided shapes having four corners extending in an arc shape. The corners of the first groove separation structure 73 preferably have a certain separation width WI along the circular arc direction.

The first trench isolation structure 73 has a single-electrode structure including a first isolation trench 74, a first isolation insulating film 75 (first isolation insulator), a first isolation electrode 76, and a first isolation cap insulating film 77. The first separation groove 74 is dug from the first main face 3 toward the second main face 4. The first separation trench 74 is formed on the first main surface 3 side with a space from the bottom of the second semiconductor region 72. The first separation groove 74 may also be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall.

The first separation insulating film 75 is formed on the wall surface of the first separation trench 74. Specifically, the first separation insulating film 75 is formed in a film shape on the wall surface of the first separation groove 74, and the groove space is partitioned in the first separation groove 74. The first separation insulating film 75 may also include a silicon oxide film. The first separation insulating film 75 preferably includes a silicon oxide film composed of an oxide of the chip 2.

The first separation insulating film 75 has a separation thickness TI. The separation thickness TI is a thickness along the normal direction of the wall surface of the first separation groove 74. The separation thickness TI may be 0.1 μm or more and 1 μm or less. The separation thickness TI is preferably 0.15 μm or more and 0.65 μm or less. In the first separation insulating film 75, a thickness of a portion covering the bottom wall of the first separation trench 74 may be smaller than a thickness of a portion covering the side wall of the first separation trench 74.

The first separation electrode 76 is embedded in the first separation trench 74 as a single body (integrated member) via the first separation insulating film 75. In this embodiment, the first separation electrode 76 may also include conductive polysilicon. A source potential (reference potential serving as a reference for circuit operation) may be applied to the first separation electrode 76. The first separation electrode 76 has an electrode surface exposed from the first separation groove 74. The electrode surface of the first separation electrode 76 may be curved toward the bottom wall of the first separation groove 74.

The first separation cap insulating film 77 covers the electrode surface of the first separation electrode 76 in a film shape in the first separation trench 74. The first separation cap insulating film 77 is connected to the first separation insulating film 75. The first separation cap insulating film 77 may also include a silicon oxide film. The first separation cap insulating film 77 preferably includes a silicon oxide film composed of an oxide of the first separation electrode 76. That is, it is preferable that the first separation cap insulating film 77 contains an oxide of polycrystalline silicon, and the first separation insulating film 75 contains an oxide of single crystal silicon.

The semiconductor device 1A includes a p-type first body region 80 formed in the surface layer portion of the first main surface 3 in the output region 7. The p-type impurity concentration of the first body region 80 may be 1×10 ¹⁶ cm ^-3 Above and 1×10 ¹⁸ cm ^-3 The following is given. The first body region 80 is formed in the entire surface layer portion of the first main surface 3 in the output region 7, and is in contact with the side wall of the first trench isolation structure 73. The first body region 80 is formed in a region on the first main surface 3 side with respect to the bottom wall of the first trench isolation structure 73. The first body region 80 is preferably intermediate with respect to the first trench isolation feature 73The portion is formed in the region on the first main surface 3 side.

The semiconductor device 1A includes a main transistor 11 formed on the first main surface 3 in the output region 7. The main transistor 11 is formed on the first main surface 3 at a distance from the first trench isolation structure 73 in a plan view. The main transistor 11 comprises a plurality of unit transistors 13 integrated in the first main face 3 of the output region 7.

The number of unit transistors 13 is arbitrary. Fig. 10 shows an example in which 60 unit transistors 13 are formed. The number of unit transistors 13 is preferably an even number. The plurality of unit transistors 13 are arranged in a row in the first direction X in a plan view, and each are formed in a stripe shape extending in the second direction Y. The plurality of unit transistors 13 are formed in a stripe shape extending in the second direction Y in a plan view.

Specifically, the plurality of unit transistors 13 are each constituted by a unit cell 81. Each unit cell 81 includes 1 trench structure 82 and a channel cell 83 controlled by the trench structure 82. Trench structure 82 may also be referred to as a "gate structure" or a "trench gate structure".

Each trench structure 82 constitutes a third gate TG of each unit transistor 13. The channel unit 83 is a region in which opening and closing of a current path is controlled by the trench structure 82. In this embodiment, the unit cell 81 includes a pair of channel cells 83 formed on both sides of one trench structure 82.

The plurality of groove structures 82 are arranged at intervals in the first direction X in a plan view, and each are formed in a band shape extending in the second direction Y. That is, the plurality of groove structures 82 are formed in a stripe shape extending in the second direction Y in a plan view. The plurality of groove structures 82 have a first end 82a on one side and a second end 82b on the other side in the longitudinal direction (second direction Y), respectively.

Each trench structure 82 has a trench width W and a trench depth D. The trench width W is a width in a direction (first direction X) orthogonal to the direction in which the trench structure 82 extends. The trench width W is preferably smaller than the separation width WI (W < WI) of the first trench separation formation 73. The trench width W may be 0.5 μm or more and 2 μm or less. The trench width W is preferably 0.5 μm or more and 1.5 μm or less. Of course, the groove width W may be substantially equal to the separation width WI (w≡wi).

The trench depth D is preferably less than the separation depth DI (D < DI) of the first trench separation formation 73. The trench depth D may be 1 μm or more and 10 μm or less. The trench depth D is preferably 2 μm or more and 6 μm or less. Of course, the trench depth D may also be approximately equal to the separation depth DI (D≡DI).

The aspect ratio D/W of the trench structure 82 may also exceed 1 and be less than 5. The aspect ratio D/W is the ratio of the trench depth D to the trench width W. The aspect ratio D/W is particularly preferably 2 or more. The bottom wall of the trench structure 82 is preferably spaced apart from the bottom of the second semiconductor region 72 by a spacing of 1 μm or more and 5 μm or less.

The plurality of trench formations 82 are arranged to be spaced apart by a trench spacing IT in the first direction X. The trench interval IT is preferably set to a value at which the depletion layer expanding from the plurality of trench structures 82 is integrated below the bottom walls of the plurality of trench structures 82. The trench spacing IT may be more than 0.25 times the trench width W and less than 1.5 times the trench width W. The trench spacing IT is preferably equal to or less than the trench width W (IT.ltoreq.W). The trench spacing IT may be 0.5 μm or more and 2 μm or less.

The structure of 1 trench structure 82 will be described below. The trench structure 82 has a multi-electrode structure including a trench 84, an upper insulating film 85, a lower insulating film 86, an upper electrode 87, a lower electrode 88, and an intermediate insulating film 89. Trench 84 may also be referred to as a "gate trench". The trench structure 82 includes an electrode (gate electrode) buried in the trench 84 with an insulator (gate insulator) interposed therebetween. The insulator is composed of an upper insulating film 85, a lower insulating film 86, and an intermediate insulating film 89. The electrode is constituted by an upper electrode 87 and a lower electrode 88.

The groove 84 is excavated from the first main face 3 toward the second main face 4. The trench 84 penetrates the first body region 80 and is formed on the first main surface 3 side at a distance from the bottom of the second semiconductor region 72. The groove 84 may also be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The bottom wall corners of the groove 84 are preferably formed in a curved shape. The entire bottom wall of the groove 84 may be curved toward the second main surface 4.

The upper insulating film 85 covers the upper wall surface of the trench 84. Specifically, the upper insulating film 85 covers the upper wall surface of the region on the opening side of the trench 84 with respect to the bottom of the first body region 80. The upper insulating film 85 crosses the boundary of the second semiconductor region 72 and the first body region 80. The upper insulating film 85 has a portion covering the first body region 80 and a portion covering the second semiconductor region 72.

The coverage area of the upper insulating film 85 with respect to the first body region 80 is larger than the coverage area of the upper insulating film 85 with respect to the second semiconductor region 72. The upper insulating film 85 may include a silicon oxide film. The upper insulating film 85 preferably includes a silicon oxide film composed of an oxide of the chip 2. The upper insulating film 85 is formed as a gate insulating film.

The upper insulating film 85 has a first thickness T1. The first thickness T1 is a thickness along the normal direction of the wall surface of the groove 84. The first thickness T1 is smaller than the separation thickness TI of the first separation insulating film 75 (T1 < TI). The first thickness T1 may be 0.01 μm or more and 0.05 μm or less. The first thickness T1 is preferably 0.02 μm or more and 0.04 μm or less.

The lower insulating film 86 covers the lower wall surface of the trench 84. Specifically, the lower insulating film 86 covers the lower wall surface of the bottom wall side region of the trench 84 with respect to the bottom of the first body region 80. The lower insulating film 86 divides the groove space in the bottom wall side region of the trench 84. The lower insulating film 86 is in contact with the second semiconductor region 72. The lower insulating film 86 may also include a silicon oxide film. The lower insulating film 86 preferably includes a silicon oxide film composed of an oxide of the chip 2.

The lower insulating film 86 has a second thickness T2. The second thickness T2 is a thickness along the normal direction of the wall surface of the groove 84. The second thickness T2 exceeds the first thickness T1 of the upper insulating film 85 (T1 < T2). The second thickness T2 may be substantially equal to the separation thickness TI of the first separation insulating film 75 (t2≡ti). The second thickness T2 may be 0.1 μm or more and 1 μm or less. The second thickness T2 is preferably 0.15 μm or more and 0.65 μm or less. In the lower insulating film 86, the thickness of the portion covering the bottom wall of the trench 84 may also be smaller than the thickness of the portion covering the side wall of the trench 84.

The upper electrode 87 is buried in the trench 84 at an upper side (opening side) through the upper insulating film 85. The upper electrode 87 is buried in a stripe shape extending in the second direction Y in a plan view. The upper electrode 87 faces the first body region 80 and the second semiconductor region 72 through the upper insulating film 85. The area of the upper electrode 87 facing the first body region 80 is larger than the area of the upper electrode 87 facing the second semiconductor region 72. The upper electrode 87 may also comprise conductive polysilicon. The upper electrode 87 is formed as a gate electrode. The upper electrode 87 is inputted with a gate signal G.

The upper electrode 87 has an electrode surface exposed from the trench 84. The electrode surface of the upper electrode 87 may be curved toward the bottom wall of the trench 84. The electrode surface of the upper electrode 87 is preferably located closer to the bottom wall side of the trench 84 than the depth position of the electrode surface of the first split electrode 76 in the depth direction of the trench 84.

The lower electrode 88 is buried in the trench 84 at a lower side (bottom wall side) via the lower insulating film 86. The lower electrode 88 is buried in a stripe shape extending in the second direction Y in a plan view. The lower electrode 88 may also have a thickness (length) exceeding the thickness (length) of the upper electrode 87 in the depth direction of the trench 84.

The lower electrode 88 faces the second semiconductor region 72 through the lower insulating film 86. The lower electrode 88 has an upper end portion protruding from the lower insulating film 86 toward the first main surface 3. The upper end portion of the lower electrode 88 engages with the bottom portion of the upper electrode 87, and faces the upper insulating film 85 across the bottom portion of the upper electrode 87 in the lateral direction along the first main surface 3.

The lower electrode 88 may also comprise conductive polysilicon. In this embodiment, the lower electrode 88 is formed as a gate electrode. The lower electrode 88 and the upper electrode 87 are fixed at the same potential. That is, the same gate signal G is applied to the lower electrode 88 simultaneously with the upper electrode 87. This can suppress a voltage drop between the upper electrode 87 and the lower electrode 88, and thus can suppress electric field concentration between the upper electrode 87 and the lower electrode 88. In addition, by increasing the carrier density in the vicinity of the trench 84, the on-resistance of the chip 2 (particularly, the second semiconductor region 72) can be reduced.

An intermediate insulating film 89 is interposed between the upper electrode 87 and the lower electrode 88 to electrically insulate the upper electrode 87 and the lower electrode 88. Specifically, the intermediate insulating film 89 covers the lower electrode 88 exposed from the lower insulating film 86 in a region between the upper electrode 87 and the lower electrode 88. The intermediate insulating film 89 is connected to the upper insulating film 85 and the lower insulating film 86. The intermediate insulating film 89 may include a silicon oxide film. The intermediate insulating film 89 preferably includes a silicon oxide film made of an oxide of the lower electrode 88.

The intermediate insulating film 89 has an intermediate thickness TM in the normal direction Z. The intermediate thickness TM is smaller than the second thickness T2 (TM < T2) of the lower insulating film 86. The intermediate thickness TM may be 0.01 μm or more and 0.05 μm or less. The intermediate thickness TM is preferably 0.02 μm or more and 0.04 μm or less.

The pair of channel units 83 are formed in a band shape extending in the second direction Y on both sides of each of the channel structures 82, respectively. The pair of channel units 83 has a length in the second direction Y that is smaller than the length of the trench configuration 82. The entire regions of the pair of channel units 83 face the upper electrode 87 through the upper insulating film 85. The pair of channel units 83 has the following channel widths, respectively: the channel width is equivalent to a value obtained by multiplying the channel interval IT by 1/2.

The pair of channel cells 83 includes at least one n-type source region 90 formed in the surface layer portion of the first body region 80. The number of source regions 90 included in the pair of channel cells 83 is arbitrary. In this embodiment, the pair of channel units 83 includes a plurality of source regions 90, respectively. All the source regions 90 included in each unit cell 81 form the third source TS of each unit transistor 13.

The n-type impurity concentration of the source region 90 exceeds the n-type impurity concentration of the second semiconductor region 72. The n-type impurity concentration of the source region 90 may be 1×10 ¹⁸ cm ^-3 Above and 1×10 ²¹ cm ^-3 The following is given. The plurality of source regions 90 are formed in the region on the first main surface 3 side from the bottom of the first body region 80 with a gap therebetween, and face the upper electrode 87 with the upper insulating film 85 interposed therebetween. The plurality of source regions 90 are arranged to be spaced apart in the second direction Y in each channel unit 83. That is, the plurality of source regions 90 are arranged to be spaced apart along the trench configuration 82 on both sides of the corresponding trench configuration 82.

The pair of channel units 83 includes: at least one p-type contact region 91 formed in a region different from the source region 90 is formed in the surface layer portion of the first body region 80. The number of contact regions 91 included in the pair of channel units 83 is arbitrary. In this embodiment, the pair of channel units 83 includes a plurality of contact regions 91, respectively. Contact region 91The p-type impurity concentration of the first body region 80. The p-type impurity concentration of the contact region 91 may be 1×10 ¹⁸ cm ^-3 Above and 1×10 ²¹ cm ^-3 The following is given.

The plurality of contact regions 91 are formed in the region on the first main surface 3 side from the bottom of the first body region 80 with a gap therebetween, and face the upper electrode 87 with the upper insulating film 85 interposed therebetween. The plurality of contact regions 91 are formed to alternate with the plurality of source regions 90 in the second direction Y with 1 source region 90 interposed therebetween. That is, the plurality of contact regions 91 are arranged to be spaced apart along the trench configuration 82 on both sides of the corresponding trench configuration 82.

The pair of channel units 83 includes: a plurality of channel regions 92 are formed within the first body region 80 between the plurality of source regions 90 and the second semiconductor region 72. The on/off of the plurality of channel regions 92 in the pair of channel cells 83 is controlled by the 1-trench configuration 82. The plurality of channel regions 92 included in the pair of channel units 83 form one channel of the unit transistor 13. Thus, one unit cell 81 functions as one unit transistor 13.

The 2 unit cells 81 disposed on both sides in the first direction X in the output region 7 preferably do not include the source region 90 in the channel cell 83 on the first trench isolation structure 73 side. According to such a structure, leakage current between the trench structure 82 and the first trench isolation structure 73 can be suppressed. In this embodiment, the 2 unit cells 81 near both sides of the first trench isolation structure 73 preferably include only the contact region 91 (hereinafter, referred to as "outermost contact region 91") in the channel cell 83 on the first trench isolation structure 73 side.

The outermost contact region 91 is formed on the side of the trench structure 82 at a spacing from the first trench isolation structure 73, and is connected to the side wall of the corresponding trench structure 82. The outermost contact regions 91 may also be formed as strips extending along the sidewalls of the corresponding trench configuration 82. The unit cell 81 adjacent to the temperature measurement region 9 within the output region 7 preferably does not include the source region 90 in the channel cell 83 on the temperature measurement region 9 side. In this case, the unit cell 81 preferably includes only the contact region 91 in the channel cell 83 on the temperature measurement region 9 side.

The main transistor 11 includes n (n=2 in this embodiment) system transistors 12 integrated in the output region 7. The 2 system transistors 12 include a first system transistor 12A and a second system transistor 12B. The first system transistor 12A includes a plurality (30 in this embodiment) of first unit transistors 13A that are selectively systemized as individual control targets from among the plurality of unit transistors 13.

The second system transistor 12B includes: a plurality (30 in this embodiment) of second unit transistors 13B that are selectively systemized as individual control objects from among the plurality of unit transistors 13 other than the first unit transistor 13A. The number of the second unit transistors 13B may be different from the number of the first unit transistors 13A. The number of the second unit transistors 13B is preferably equal to the number of the first unit transistors 13A.

Hereinafter, "unit cell 81", "trench structure 82", "channel cell 83", "trench 84", "upper insulating film 85", "lower insulating film 86", "upper electrode 87", "lower electrode 88", "intermediate insulating film 89", "source region 90", "contact region 91", and "channel region 92" of the first unit transistor 13A are referred to as "first unit cell 81A", "first trench structure 82A", "first channel cell 83A", "first trench 84A", "first upper insulating film 85A", "first lower insulating film 86A", "first upper electrode 87A", "first lower electrode 88A", "first intermediate insulating film 89A", "first source region 90A", "first contact region 91A", and "first channel region 92A", respectively. The first gate signal G1 is input to the first upper electrode 87A and the first lower electrode 88A.

Hereinafter, "unit cell 81", "trench structure 82", "channel cell 83", "trench 84", "upper insulating film 85", "lower insulating film 86", "upper electrode 87", "lower electrode 88", "intermediate insulating film 89", "source region 90", "contact region 91", and "channel region 92" of the second unit transistor 13B are referred to as "second unit cell 81B", "second trench structure 82B", "second channel cell 83B", "second trench 84B", "second upper insulating film 85B", "second lower insulating film 86B", "second upper electrode 87B", "second lower electrode 88B", "second intermediate insulating film 89B", "second source region 90B", "second contact region 91B", and "second channel region 92B", respectively. A second gate signal G2 electrically independent of the first gate signal G1 is input to the second upper electrode 87B and the second lower electrode 88B.

The first system transistor 12A comprises at least one first recombination unit 101. The number of the first complex cells 101 is arbitrary and is adjusted according to the size of the output region 7 (the total number of the unit transistors 13). In this embodiment, the first system transistor 12A includes a plurality (15 in this embodiment) of first complex cells 101.

The plurality of first composite cells 101 are each composed of α (α≡2) first unit transistors 13A (first unit cells 81A) arranged adjacent to the first main surface 3 in plan view. The plurality of first complex units 101 are arranged to be spaced apart in the first direction X in a plan view.

The second system transistor 12B includes at least one second recombination unit 102. The number of the second complex cells 102 is arbitrary and is adjusted according to the size of the output region 7 (the total number of the unit transistors 13). The number of the second complex units 102 may be different from the number of the first complex units 101. The number of second complex units 102 is preferably equal to the number of first complex units 101.

In this embodiment, the second system transistor 12B includes a plurality (15 in this embodiment) of second complex cells 102. The plurality of second composite cells 102 are each composed of β (β+.2) second unit transistors 13B (second unit cells 81B) arranged adjacent to the first main surface 3 in plan view.

The plurality of second complex units 102 are disposed adjacent to the plurality of first complex units 101, respectively, in a plan view. Specifically, the plurality of second complex units 102 are arranged in the area between the plurality of first complex units 101 that are close to each other in plan view. More specifically, the plurality of second complex units 102 are arranged so as to alternate with the plurality of first complex units 101 along the first direction X in a plan view with 1 first complex unit 101 interposed therebetween.

The number of first unit transistors 13A included in one first complex cell 101 may be 1 (α=1), and the number of second unit transistors 13B included in one second complex cell 102 may be 1 (β=1). That is, the plurality of second unit transistors 13B may be arranged alternately with the plurality of first unit transistors 13A so as to sandwich one unit transistor 13 in a plan view.

However, in this case, the number of the first unit transistors 13A and the second unit transistors 13B facing each other increases. As a result, the risk of short-circuiting between the first unit transistor 13A and the second unit transistor 13B in proximity increases due to process errors or the like. The term "short circuit" as used herein refers to a short circuit between the first trench structure 82A (third gate TG) of the first unit transistor 13A and the second trench structure 82B (third gate TG) of the second unit transistor 13B (see also the circuit diagram of fig. 7).

For example, when one first unit transistor 13A is short-circuited to one second unit transistor 13B in the vicinity, all the first unit transistors 13A are short-circuited to all the second unit transistors 13B. That is, the first system transistor 12A and the second system transistor 12B function as one system transistor 12, and as a result, the first system transistor 12A and the second system transistor 12B do not constitute the main transistor 11 of the 2 system (see also the circuit diagram of fig. 7).

Therefore, the number of the first unit transistors 13A included in 1 first complex cell 101 is preferably 2 or more (α Σ2), and the number of the second unit transistors 13B included in 1 second complex cell 102 is preferably 2 or more (β Σ2). According to this structure, the number of the first unit transistors 13A and the second unit transistors 13B facing each other can be reduced. As a result, the risk of short-circuiting between the first unit transistor 13A and the second unit transistor 13B in proximity can be reduced.

The first unit transistor 13A (specifically, the first channel region 92A) is a heat source in the output region 7. Therefore, the number of the first unit transistors 13A determines the heat generation amount of one first complex cell 101, and the arrangement of the plurality of first complex cells 101 determines the heat generation portion in the output region 7. That is, if the number of the first unit transistors 13A constituting one first complex cell 101 is increased, the amount of heat generated in one first complex cell 101 increases. When the plurality of first complex units 101 are arranged adjacently, the heat generating portion of the output region 7 is localized.

Therefore, the number of the first unit transistors 13A is preferably 4 or less (α.ltoreq.4). According to this configuration, a local temperature rise in one first complex unit 101 can be suppressed. In view of the short-circuit risk and the heat generation amount, the number of the first unit transistors 13A is particularly preferably 2 (α=2). The plurality of first complex units 101 are preferably arranged at equal intervals in the output area 7. According to this structure, the heat generating portions caused by the plurality of first complex units 101 can be removed from the output region 7, and a local temperature rise in the output region 7 can be suppressed.

In each of the first composite units 101, the plurality of first channel regions 92A (first source regions 90A) arranged on the one first trench structure 82A side preferably face regions between the plurality of first channel regions 92A (first source regions 90A) arranged on the other first trench structure 82A side in the first direction X. According to this structure, the heat generation start points in the respective first complex units 101 can be eliminated. This can suppress a local temperature rise in each first complex cell 101.

At this time, in each of the first unit cells 81A, the plurality of first channel regions 92A formed in one of the first channel cells 83A are preferably opposed to the plurality of first channel regions 92A formed in the other first channel cell 83A through the corresponding first trench structure 82A.

In each of the first composite units 101, the plurality of first channel regions 92A formed in the region between the pair of first trench structures 82A are preferably arranged so as to be offset from each other in the second direction Y in a plan view. Of course, in each of the first unit cells 81A, the plurality of first channel regions 92A formed in one of the first channel cells 83A may be opposed to the region formed between the plurality of first channel regions 92A in the other first channel cell 83A with the corresponding first trench structure 82A interposed therebetween.

In each of the first unit cells 81A, the plurality of first contact regions 91A formed in one of the first channel cells 83A may be opposed to the plurality of first contact regions 91A formed in the other first channel cell 83A through the corresponding first trench structure 82A. In each of the first complex units 101, the plurality of first contact regions 91A arranged on the one first trench structure 82A side may be opposed to the region between the plurality of first contact regions 91A arranged on the other first trench structure 82A side in the first direction X.

In each of the first composite units 101, the plurality of first contact regions 91A formed in the region between the pair of first trench structures 82A may be arranged so as to be offset from each other in the second direction Y in a plan view. In addition, the plurality of first contact regions 91A may be opposed to the plurality of first source regions 90A in the first direction X in a plan view.

The second unit transistor 13B becomes a heat source in the output region 7. Therefore, the number of the second unit transistors 13B determines the heat generation amount of one second complex cell 102, and the arrangement of the plurality of second complex cells 102 determines the heat generation portion in the output region 7. That is, if the number of the second unit transistors 13B constituting one second complex cell 102 is increased, the amount of heat generated in one second complex cell 102 increases. When the plurality of second complex units 102 are disposed adjacent to each other, the heat generating portion of the output region 7 is localized.

Therefore, the number of the second unit transistors 13B is preferably 4 or less (β.ltoreq.4). According to this configuration, a local temperature rise in one second complex unit 102 can be suppressed. At this time, the number of the second unit transistors 13B is preferably equal to the number of the first unit transistors 13A. According to this configuration, it is possible to suppress the deviation of the heat generation range by the first complex unit 101 and the heat generation range by the second complex unit 102. In view of the short-circuit risk and the heat generation amount, the number of the second unit transistors 13B is particularly preferably 2 (β=2).

The plurality of second complex units 102 are preferably arranged at equal intervals in the output area 7. According to this structure, the heat generating portions caused by the plurality of second complex units 102 can be removed from the output region 7, and a local temperature rise in the output region 7 can be suppressed. At this time, it is preferable that the at least one second complex unit 102 is disposed close to the at least one first complex unit 101.

According to this structure, in the first complex cell 101 and the second complex cell 102 which are close to each other, a state in which one cell is in an on state and the other cell is in an off state can be formed. This can suppress local temperature increases caused by the first complex unit 101 and the second complex unit 102.

At this time, at least one second complex cell 102 is preferably arranged in a region between 2 adjacent first complex cells 101. In this case, it is particularly preferable that the plurality of second complex units 102 are alternately arranged with the plurality of first complex units 101 so as to sandwich one first complex unit 101.

According to these configurations, the 2 first complex units 101 in proximity can be separated by the amount of the second complex unit 102. This makes it possible to appropriately eliminate heat generation sites caused by the plurality of first complex units 101 and the plurality of second complex units 102, and to appropriately suppress local temperature increases in the output region 7.

In each of the second complex units 102, the plurality of second channel regions 92B (second source regions 90B) arranged on the one second trench structure 82B side are preferably opposed to regions between the plurality of second channel regions 92B (second source regions 90B) arranged on the other second trench structure 82B side in the first direction X. According to this structure, the heat generation start points in the respective second complex units 102 can be eliminated. This can suppress a local temperature rise in each of the second complex units 102.

At this time, in each of the second unit cells 81B, the plurality of second channel regions 92B formed in one of the second channel cells 83B are preferably opposed to the plurality of second channel regions 92B formed in the other second channel cell 83B through the corresponding second trench structure 82B. In each of the second composite units 102, the plurality of second channel regions 92B formed in the region between the pair of second trench structures 82B are preferably arranged so as to be offset from each other in the second direction Y in a plan view.

The plurality of second channel regions 92B are preferably arranged offset from the plurality of first channel regions 92A in the second direction Y in the inter-trench regions of the first trench structures 82A and the second trench structures 82B. That is, the plurality of second channel regions 92B are preferably opposed to the regions between the plurality of first contact regions 91A in the first direction X in the inter-trench region. According to these configurations, the heat generation starting point in the inter-trench region can be eliminated. This can suppress a local temperature rise in the inter-trench region.

In each of the second unit cells 81B, the plurality of second contact regions 91B formed in one of the second channel cells 83B may be opposed to the plurality of second contact regions 91B formed in the other of the second channel cells 83B through the corresponding second trench structures 82B. In each of the second complex units 102, the plurality of second contact regions 91B arranged on the one second trench structure 82B side may be opposed to the regions between the plurality of second contact regions 91B arranged on the other second trench structure 82B side in the first direction X.

Of course, in each of the second unit cells 81B, the plurality of second channel regions 92B formed in one of the second channel cells 83B may be opposed to the regions formed between the plurality of second channel regions 92B in the other second channel cell 83B with the corresponding second trench structure 82B interposed therebetween.

In each of the second complex units 102, the plurality of second contact regions 91B formed in the region between the pair of second trench structures 82B may be arranged to be offset from each other in the second direction Y in a plan view. The plurality of second contact regions 91B may be opposite to the plurality of second source regions 90B in the first direction X in a plan view.

The main transistor 11 of the n-system has a total channel ratio RT. The total channel ratio RT is the ratio of the total planar area of all channel regions 92 to the planar area of all channel cells 83. The planar area of each channel region 92 is defined by the planar area of each source region 90. The total channel ratio RT is adjusted in a range of more than 0% and less than 100%. The total channel ratio RT is preferably adjusted in a range of 25% to 75%.

The total channel ratio RT is divided into n system channel ratios RS by n system transistors 12. The total channel ratio RT of the main transistor 11 of the 2-system is formed by the sum of the first-system channel ratio RSA of the first-system transistor 12A and the second-system channel ratio RSB of the second-system transistor 12B (rt=rsa+rsb).

The first system channel ratio RSA is the ratio of the total planar area of all first channel regions 92A to the total planar area of all channel cells 83. The second system channel ratio RSB is the ratio of the total planar area of all second channel regions 92B to the total planar area of all channel cells 83.

The planar area of each first channel region 92A is defined by the planar area of each first source region 90A, and the planar area of each second channel region 92B is defined by the planar area of each second source region 90B. The first system channel ratio RSA is adjusted by the arrangement pattern of the first source region 90A and the first contact region 91A. The second system channel ratio RSB is adjusted by the arrangement pattern of the second source region 90B and the second contact region 91B.

The first system channel ratio RSA is divided into a plurality of first channel ratios RCA by a plurality of first complex units 101. The first channel ratio RCA is a ratio of the total planar area of the plurality of first channel regions 92A in each first composite unit 101 to the total planar area of all the channel units 83.

The first system channel ratio RSA is formed by the addition of a plurality of first channel ratios RCA. The plurality of first complex cells 101 preferably have first channel ratios RCA equal to each other. In each of the first unit transistors 13A, a plurality of first channel regions 92A may be formed at first areas different from each other or equal to each other per unit area.

The second system channel ratio RSB is divided into a plurality of second channel ratios RCB by a plurality of second complex units 102. The second channel ratio RCB is a ratio of the total planar area of the plurality of second channel regions 92B in each second composite unit 102 to the total planar area of all the channel units 83. The plurality of second complex units 102 are constituted by the added values of the plurality of second channel ratios RCB.

The plurality of second complex cells 102 preferably have second channel ratios RCB equal to each other. In each of the second unit transistors 13B, a plurality of second channel regions 92B may be formed at second areas different from each other or equal to each other per unit area. The second area may be equal to or different from the first area of the plurality of first channel regions 92A per unit area.

The second system channel ratio RSB may be approximately equal to the first system channel ratio RSA (rsa≡rsb). The second system channel ratio RSB may also exceed the first system channel ratio RSA (RSA < RSB). The second system channel ratio RSB may also be less than the first system channel ratio RSA (RSB < RSA). In the following, a structural example of the channel is shown in fig. 15 to 18.

Fig. 15 to 18 are cross-sectional perspective views showing first to fourth channel structure examples. In the example of fig. 15, the total channel ratio RT is 50%, the first system channel ratio RSA is 25%, and the second system channel ratio RSB is 25%. In the example of fig. 16, the total channel ratio RT is 50%, the first system channel ratio RSA is 12.5%, and the second system channel ratio RSB is 37.5%.

In the example of fig. 17, the total channel ratio RT is 33%, the first system channel ratio RSA is 8.3%, and the second system channel ratio RSB is 24.7%. In the example of fig. 18, the total channel ratio RT is 25%, the first system channel ratio RSA is 6.3%, and the second system channel ratio RSB is 18.7%.

Referring again to fig. 8 to 14, the main transistor 11 includes a plurality of pairs (15 pairs in this embodiment, 30 total) of first trench connection structures 111 formed on the first main surface 3 in the output region 7. The plurality of pairs of first groove connection structures 111 include first groove connection structures 111 on one side (first side surface 5A side) and first groove connection structures 111 on the other side (second side surface 5B side) which face each other with the corresponding 1 first complex cell 101 interposed therebetween in the second direction Y.

The first groove connecting structure 111 on one side connects the first end portions 82A of the plurality (a pair in this embodiment) of first groove structures 82A in an arch shape to each other in a plan view. The other first groove connecting structure 111 connects the second ends 82b of the plurality (a pair in this embodiment) of first groove structures 82A in an arch shape in plan view. The pair of first groove connection structures 111 and the plurality of (in this embodiment, a pair of) first groove structures 82A constituting 1 first complex unit 101 constitute 1 annular groove structure.

The first groove connecting structure 111 on the other side has the same structure as the first groove connecting structure 111 on the one side except that it is connected to the second end 82b of the first groove structure 82A. Hereinafter, the structure of one first groove connecting structure 111 will be described, and the description of the structure of the other first groove connecting structure 111 will be omitted.

The first groove connection structure 111 on one side has a first portion 111a extending in the first direction X and a plurality of (a pair of in this embodiment) second portions 111b extending in the second direction Y. The first portion 111a is opposite the plurality of first ends 82a in plan view. The plurality of second portions 111b extend from the first portion 111a toward the plurality of first end portions 82a, and are connected to the plurality of first end portions 82 a.

The first groove connection structure 111 on one side has a connection width WC and a connection depth DC. The connection width WC is a width in a direction orthogonal to a direction in which the first groove connection structure 111 extends. The connection width WC is preferably approximately equal to the groove width W of the groove formation 82 (wc≡w). The connection depth DC is preferably approximately equal to the trench depth D of the trench configuration 82 (DC≡D).

The aspect ratio DC/WC of the first trench connection feature 111 is preferably approximately equal to the aspect ratio D/W of the trench feature 82 (DC/WC≡D/W). The bottom wall of the first trench connection structure 111 is preferably spaced apart from the bottom of the second semiconductor region 72 by a spacing of 1 μm or more and 5 μm or less.

The first trench connection structure 111 on one side has a single-electrode structure including a first connection trench 112, a first connection insulating film 113, a first connection electrode 114, and a first cap insulating film 115. The first connecting grooves 112 extend in an arch shape so as to communicate with the first end portions 82a of the plurality of first grooves 84A in plan view, and dig from the first main surface 3 toward the second main surface 4. The first connection groove 112 divides the first portion 111a and the second portion 111b of the first groove connection structure 111. The first connection trenches 112 are formed on the first main surface 3 side with a space from the bottom of the second semiconductor region 72.

The first connection groove 112 may be formed in a tapered shape in which an opening width narrows from the opening toward the bottom wall. The bottom wall corner of the first connecting groove 112 is preferably formed in a curved shape. The entire bottom wall of the first connecting groove 112 may be formed in a curved shape toward the second main surface 4. The side walls and the bottom wall of the first connecting groove 112 are smoothly connected with the side walls and the bottom wall of the first groove 84A.

The first connection insulating film 113 is formed on the wall surface of the first connection groove 112. Specifically, the first connection insulating film 113 is formed in a film shape on the wall surface of the first connection groove 112, and a groove space is partitioned in the first connection groove 112. The first connection insulating film 113 extends in the first direction X in the first portion 111a of the first connection groove 112. The first connection insulating film 113 extends in the second direction Y in the second portion 111b of the first connection groove 112.

The first connection insulating film 113 is connected to the first upper insulating film 85A and the first lower insulating film 86A at the communication portions between the first connection trench 112 and the first trench 84A. The first connection insulating film 113 may include a silicon oxide film. The first connection insulating film 113 preferably includes a silicon oxide film composed of an oxide of the chip 2.

The first connection insulating film 113 has a third thickness T3. The third thickness T3 is a thickness along the normal direction of the wall surface of the first connection groove 112. The third thickness T3 exceeds the first thickness T1 of the first upper insulating film 85A (T1 < T3). The third thickness T3 may be substantially equal to the second thickness T2 of the lower insulating film 86 (t2≡t3). The third thickness T3 may be substantially equal to the separation thickness TI of the first separation insulating film 75 (t3≡ti).

The third thickness T3 may be 0.1 μm or more and 1 μm or less. The third thickness T3 is preferably 0.15 μm or more and 0.65 μm or less. In the first connection insulating film 113, a thickness of a portion covering the bottom wall of the first connection groove 112 may be smaller than a thickness of a portion covering the side wall of the first connection groove 112.

The first connection electrode 114 is buried as a single body in the first connection groove 112 via the first connection insulating film 113. In this embodiment, the first connection electrode 114 may include conductive polysilicon. The first connection electrode 114 extends in the first direction X in the first portion 111a of the first connection groove 112. The first connection electrode 114 extends in the second direction Y in the second portion 111b of the first connection groove 112. The first connection electrode 114 is connected to the first lower electrode 88A at the communication portion of the first connection groove 112 and the first groove 84A.

The first connection electrode 114 is electrically insulated from the first upper electrode 87A via the first intermediate insulating film 89A. That is, the first connection electrode 114 is constituted by a lead portion led out from the first trench 84A to the first connection trench 112 through the first connection insulating film 113 and the first intermediate insulating film 89A in the first lower electrode 88A. The first gate signal G1 is transferred to the first lower electrode 88A via the first connection electrode 114. That is, the same first gate signal G1 is applied to the first connection electrode 114 at the same time as the first upper electrode 87A.

The first connection electrode 114 has an electrode surface exposed from the first connection groove 112. The electrode surface of the first connection electrode 114 may be curved toward the bottom wall of the first connection groove 112. The electrode surface of the first connection electrode 114 is preferably located (protrudes) in the depth direction of the first connection groove 112 toward the first main surface 3 than the depth position of the electrode surface of the upper electrode 87 of the groove structure 82.

The first cap insulating film 115 covers the electrode surface of the first connection electrode 114 in a film shape within the first connection groove 112. The first cap insulating film 115 suppresses the first connection electrode 114 from shorting with other electrodes. The first cap insulating film 115 is connected to the first connection insulating film 113.

The first cap insulating film 115 may include a silicon oxide film. The first cap insulating film 115 preferably includes a silicon oxide film composed of an oxide of the first connection electrode 114. That is, the first cap insulating film 115 preferably includes an oxide of polysilicon, and the first connection insulating film 113 preferably includes an oxide of single crystal silicon.

The main transistor 11 includes a plurality of pairs (15 pairs in this embodiment, 30 total) of second trench connection structures 121 formed on the first main surface 3 in the output region 7. The plurality of pairs of second groove connection structures 121 include the second groove connection structure 121 on one side (the first side surface 5A side) and the second groove connection structure 121 on the other side (the second side surface 5B side) which face each other with the corresponding 1 second complex units 102 interposed therebetween in the second direction Y.

The first ends 82a of the plurality (in this embodiment, a pair) of second groove structures 82B are connected to each other in an arch shape in a plan view by one second groove connection structure 121. The second groove connecting structure 121 on the other side connects the second ends 82B of the plurality (a pair in this embodiment) of second groove structures 82B in an arch shape to each other in a plan view. The pair of second groove connection structures 121 and the plurality of (in this embodiment, a pair of) second groove structures 82B constituting 1 second complex unit 102 constitute 1 annular groove structure.

The second groove connecting structure 121 on the other side has the same structure as the second groove connecting structure 121 on the one side except that it is connected to the second end 82B of the second groove structure 82B. Hereinafter, the structure of one second groove connecting structure 121 will be described, and the description of the structure of the other second groove connecting structure 121 will be omitted.

The second groove connection structure 121 on one side has a first portion 121a extending in the first direction X and a plurality of (a pair of in this embodiment) second portions 121b extending in the second direction Y. The first portion 121a is opposite to the plurality of first end portions 82a in plan view. The plurality of second portions 121b extend from the first portions 121a toward the plurality of first end portions 82a, and are connected to the plurality of first end portions 82 a. The second groove connection structure 121 on one side has a connection width WC and a connection depth DC as in the first groove connection structures 111.

The second trench connection structure 121 on one side has a single-electrode structure including a second connection trench 122, a second connection insulating film 123, a second connection electrode 124, and a second cap insulating film 125. The second connecting grooves 122 extend in an arch shape so as to communicate with the first end portions 82a of the pair of second grooves 84B in plan view, and are dug from the first main surface 3 toward the second main surface 4. The second connection groove 122 divides the first portion 121a and the second portion 121b of the second groove connection structure 121. The second connection trenches 122 are formed on the first main surface 3 side at intervals from the bottom of the second semiconductor region 72.

The second connecting groove 122 includes a side wall and a bottom wall. The second connecting groove 122 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The bottom wall corner of the second connecting groove 122 is preferably formed in a curved shape. The entire bottom wall of the second connecting groove 122 may be formed in a curved shape toward the second main surface 4. The side walls and the bottom wall of the second connecting groove 122 are smoothly connected with the side walls and the bottom wall of the second groove 84B.

The second connection insulating film 123 is formed on the wall surface of the second connection trench 122. Specifically, the second connection insulating film 123 is formed in a film shape on the wall surface of the second connection groove 122, and a groove space is partitioned in the second connection groove 122. The second connection insulating film 123 extends in the first direction X in the first portion 121a of the second connection trench 122.

The second connection insulating film 123 extends in the second direction Y in the second portion 121b of the second connection trench 122. The second connection insulating film 123 may include a silicon oxide film. The second connection insulating film 123 preferably includes a silicon oxide film composed of an oxide of the chip 2. The second connection insulating film 123 has a third thickness T3, like the first connection insulating film 113.

The second connection electrode 124 is buried as a single body in the second connection trench 122 via the second connection insulating film 123. In this embodiment, the second connection electrode 124 may include conductive polysilicon. The second connection electrode 124 extends in the first direction X in the first portion 121a of the second connection trench 122. The second connection electrode 124 extends in the second direction Y in the second portion 121b of the second connection trench 122. The second connection electrode 124 is connected to the second lower electrode 88B at the communication portion of the second connection groove 122 and the second groove 84B.

The second connection electrode 124 is electrically insulated from the second upper electrode 87B via the second intermediate insulating film 89B. That is, the second connection electrode 124 is constituted by a lead portion led out from the second trench 84B to the second connection trench 122 through the second connection insulating film 123 and the second intermediate insulating film 89B in the second lower electrode 88B. The second gate signal G2 is transferred to the second lower electrode 88B via the second connection electrode 124. That is, the same second gate signal G2 is applied to the second connection electrode 124 at the same time as the second upper electrode 87B.

The second connection electrode 124 has an electrode surface exposed from the second connection groove 122. The electrode surface of the second connection electrode 124 may be curved toward the bottom wall of the second connection trench 122. The electrode surface of the second connection electrode 124 is preferably located (protrudes) in the depth direction of the second connection groove 122 toward the first main surface 3 than the depth position of the electrode surface of the upper electrode 87 of the groove structure 82.

The second cap insulating film 125 covers the electrode surface of the second connection electrode 124 in a film shape in the second connection groove 122. The second cap insulating film 125 suppresses the second connection electrode 124 from shorting with other electrodes. The second cap insulating film 125 is connected to the second connection insulating film 123.

The second cap insulating film 125 may include a silicon oxide film. The second cap insulating film 125 preferably includes a silicon oxide film composed of an oxide of the second connection electrode 124. That is, the second cap insulating film 125 preferably contains an oxide of polysilicon, and the second connection insulating film 123 preferably contains an oxide of single crystal silicon.

Referring to fig. 8, the semiconductor device 1A further includes the above-described first temperature measurement region 9A partitioned inside the output region 7. A specific structure of the first temperature measuring region 9A will be described below. Fig. 19 is an enlarged view of the region XIX shown in fig. 8. FIG. 20 is a cross-sectional view taken along line XX-XX shown in FIG. 19. Fig. 21 is a cross-sectional view taken along line XXI-XXI shown in fig. 19. Fig. 22 is a cross-sectional view taken along line XXII-XXII shown in fig. 19. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII shown in fig. 19. Fig. 24 is a cross-sectional perspective view showing the output region 7 and the first temperature measurement region 9A.

Referring to fig. 19 to 24, semiconductor device 1A includes a diode separation structure 131, which is an example of a region separation structure that partitions first temperature measurement region 9A in first main surface 3. Diode separation structure 131 may also be referred to as a "DTI structure". In this embodiment, the diode separation structure 131 has a double-trench separation structure including a second trench separation structure 132 and a third trench separation structure 133. Of course, the diode separating structure 131 may have a single-trench separating structure constituted only by the second trench separating structure 132, or may have a multi-trench separating structure including three or more trench separating structures.

The second trench isolation structure 132 is formed in a ring shape surrounding a part of the inside of the first main surface 3 in the output region 7 in a plan view, and defines a first temperature measurement region 9A of a predetermined shape. In the present embodiment, the second trench isolation structure 132 is formed in a four-sided ring shape having four sides parallel to the first to fourth side surfaces 5A to 5D in plan view, and divides the first temperature measurement region 9A in the four-sided shape. The planar shape of the second groove separation structure 132 is arbitrary, and may be formed in a polygonal ring shape. The first temperature measuring region 9A may also be divided into polygonal shapes according to the planar shape of the second trench isolation structure 132.

The second trench isolation structure 132 has a separation width WI and a separation depth DI (aspect ratio DI/WI) as the first trench isolation structure 73. The bottom wall of the second trench isolation structure 132 is preferably spaced apart from the bottom of the second semiconductor region 72 by a spacing of 1 μm or more and 5 μm or less.

The second groove separation structure 132 has corners connecting a portion extending in the first direction X and a portion extending in the second direction Y in an arc shape (curved shape). In the present embodiment, the quadrangle of the second trench isolation structure 132 is formed in an arc shape. That is, the first temperature measurement region 9A is divided into four-sided shapes having four corners extending in an arc shape. The corners of the second groove separation structure 132 preferably have a certain separation width WI along the circular arc direction.

The second trench isolation structure 132 has a single electrode structure including a second isolation trench 134, a second isolation insulating film 135 (second isolation insulator), a second isolation electrode 136, and a second isolation cap insulating film 137. The second separation groove 134 is dug from the first main surface 3 toward the second main surface 4. The second separation trench 134 is formed on the first main surface 3 side with a space from the bottom of the second semiconductor region 72. The second separation groove 134 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall.

The second separation insulating film 135 is formed on the wall surface of the second separation trench 134. Specifically, the second separation insulating film 135 is formed in a film shape on the wall surface of the second separation trench 134, and the groove space is partitioned in the second separation trench 134. The second separation insulating film 135 may include a silicon oxide film. The second separation insulating film 135 preferably includes a silicon oxide film composed of an oxide of the chip 2. The second separation insulating film 135 has a separation thickness TI as the first separation insulating film 75.

The second separation electrode 136 is embedded in the second separation trench 134 as a single body (integrated member) via the second separation insulating film 135. In this embodiment, the second separation electrode 136 may include conductive polysilicon. An anodic potential is applied to the second separation electrode 136. Of course, the source potential may be applied to the second separation electrode 136 as in the first separation electrode 76. The second separation electrode 136 has an electrode surface exposed from the second separation trench 134. The electrode surface of the second separation electrode 136 may be curved to be depressed toward the bottom wall of the second separation trench 134.

The second separation cap insulating film 137 covers the electrode surface of the second separation electrode 136 in a film shape in the second separation trench 134. The second separation cap insulating film 137 is connected to the second separation insulating film 135. The second separation cap insulating film 137 may include a silicon oxide film. The second separation cap insulating film 137 preferably includes a silicon oxide film composed of an oxide of the second separation electrode 136.

The third groove separation structure 133 is formed in a ring shape surrounding the second groove separation structure 132 at a distance from the second groove separation structure 132 in a plan view. That is, the third groove separation structure 133 divides the mesa portion 138 extending annularly in a plan view between the second groove separation structure 132. The third groove separation structure 133 is formed in a four-sided ring shape having four sides parallel to the second groove separation structure 132 in a plan view. The third groove separation structure 133 may have any planar shape, and may be formed in a polygonal ring shape.

The third trench isolation structure 133 is formed to be spaced apart from the second trench isolation structure 132 by the first isolation trench interval IST. The first separation trench spacing IST preferably exceeds the trench spacing IT of the plurality of trench formations 82. The first separation trench interval IST may be 0.5 μm or more and 4 μm or less. The third trench isolation structure 133 has a separation width WI and a separation depth DI (aspect ratio DI/WI) as the first trench isolation structure 73.

The bottom wall of the third trench isolation structure 133 is preferably spaced from the bottom of the third region by a space of 1 μm or more and 5 μm or less. The third groove separation structure 133 has corners connecting a portion extending in the first direction X and a portion extending in the second direction Y in an arc shape (curved shape). In this embodiment, the quadrangle of the third groove separation structure 133 is formed in an arc shape. The corners of the third groove separation structure 133 preferably have a certain separation width WI along the circular arc direction.

The third trench isolation structure 133 has a single-electrode structure including a third isolation trench 144, a third isolation insulating film 145 (third isolation insulator), a third isolation electrode 146, and a third isolation cap insulating film 147. The third separation trench 144, the third separation insulating film 145, the third separation electrode 146, and the third separation cap insulating film 147 are formed in substantially the same manner as the second separation trench 134, the second separation insulating film 135, the second separation electrode 136, and the second separation cap insulating film 137. A specific description of the third separation trench 144, the third separation insulating film 145, the third separation electrode 146, and the third separation cap insulating film 147, to which the second trench separation structure 132 is applied, is thus omitted.

The semiconductor device 1A includes a second body region 150 (body region) formed in the surface layer portion of the first main surface 3 in the first temperature measurement region 9A. The second body region 150 may have a p-type impurity concentration of 1 x 10 ¹⁶ cm ^-3 Above and 1×10 ¹⁸ cm ^-3 The following is given. The p-type impurity concentration of the second body region 150 is preferably approximately equal to the p-type impurity concentration of the first body region 80. The second body region 150 preferably has a thickness (depth) that is approximately equal to the first body region 80. According to this configuration, the second body region 150 can be formed simultaneously with the first body region 80.

The second body region 150 is formed in the entire surface layer portion of the first main surface 3 in the first temperature measurement region 9A. The second body region 150 is not formed in the mesa portion 138. The second body region 150 meets the inner peripheral wall of the second groove separating structure 132, but does not meet the outer peripheral wall of the second groove separating structure 132 and the inner peripheral wall of the third groove separating structure 133. The first body region 80 is not formed in the mesa portion 138 at the surface layer portion of the first main surface 3.

The first body region 80 meets the outer peripheral wall of the third groove separation structure 133, but does not meet the outer peripheral wall of the second groove separation structure 132 and the inner peripheral wall of the third groove separation structure 133. Of course, the second body region 150 (first body region 80) may be formed in the surface layer portion of the first main surface 3 in the mesa portion 138.

The semiconductor device 1A includes a plurality of diode trench structures 151 (trench structures) formed on the first main surface 3 in the first temperature measurement region 9A. The diode trench structure 151 is electrically independent of the trench structure 82 of the main transistor 11. The number of the plurality of diode trench structures 151 may be 2 or more, and may be adjusted according to the size of the first temperature measurement region 9A. In this embodiment, the semiconductor device 1A includes 2 diode trench structures 151.

The plurality of diode trench structures 151 are arranged at intervals in the first direction X in a plan view, and are each formed in a strip shape extending in the second direction Y. That is, the plurality of diode trench structures 151 are formed in a stripe shape extending in the second direction Y in a plan view. The plurality of diode trench structures 151 have a first end 151a on one side and a second end 151b on the other side in the longitudinal direction (second direction Y), respectively.

Each diode trench structure 151 has a trench width W and a trench depth D (aspect ratio D/W) as in each trench structure 82. The bottom wall of each diode trench structure 151 is preferably spaced apart from the bottom of the second semiconductor region 72 by a distance of 1 μm or more and 5 μm or less. The plurality of diode trench structures 151 are arranged with a trench interval IT in the first direction X, like the plurality of trench structures 82.

The structure of one diode trench structure 151 will be described below. The diode trench structure 151 has a multi-electrode structure including a third trench 154, a third upper insulating film 155, a third lower insulating film 156, a third upper electrode 157, a third lower electrode 158, and a third intermediate insulating film 159. The third trench 154 may also be referred to as a "diode trench".

The diode trench structure 151 includes an embedded electrode embedded in the third trench 154 with an embedded insulator interposed therebetween. The buried insulator is composed of a third upper insulating film 155, a third lower insulating film 156, and a third intermediate insulating film 159. The buried electrode is composed of a third upper electrode 157 and a third lower electrode 158.

The third groove 154 is dug from the first main face 3 toward the second main face 4. The third trench 154 penetrates the second body region 150 and is formed on the first main surface 3 side at a distance from the bottom of the second semiconductor region 72. The third groove 154 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The bottom wall corner of the third groove 154 is preferably formed in a curved shape. The entire bottom wall of the third groove 154 may be formed in a curved shape toward the second main surface 4.

The third upper insulating film 155 covers the upper wall surface of the third trench 154. Specifically, the third upper insulating film 155 covers the upper wall surface of the region located on the opening side of the third trench 154 with respect to the bottom of the second body region 150. The third upper insulating film 155 crosses the boundaries of the second semiconductor region 72 and the second body region 150. The third upper insulating film 155 has a portion covering the second body region 150 and a portion covering the second semiconductor region 72.

The coverage area of the third upper insulating film 155 with respect to the second body region 150 is larger than the coverage area of the third upper insulating film 155 with respect to the second semiconductor region 72. The third upper insulating film 155 may include a silicon oxide film. The third upper insulating film 155 preferably includes a silicon oxide film composed of an oxide of the chip 2. The third upper insulating film 155 has a first thickness T1, like the first upper insulating film 85A.

The third lower insulating film 156 covers the lower wall surface of the third trench 154. Specifically, the third lower insulating film 156 covers the lower wall surface of the region located on the bottom wall side of the third trench 154 with respect to the bottom of the second body region 150. The third lower insulating film 156 divides the groove space in the bottom wall side region of the third trench 154.

The third lower insulating film 156 is connected to the second semiconductor region 72. The third lower insulating film 156 may include a silicon oxide film. The third lower insulating film 156 preferably includes a silicon oxide film composed of an oxide of the chip 2. The third lower insulating film 156 has the second thickness T2 as the first lower insulating film 86A.

The third upper electrode 157 is buried in the third trench 154 at an upper side (opening side) thereof via the third upper insulating film 155. The third upper electrode 157 is buried in a band shape extending in the second direction Y in a plan view. The third upper electrode 157 is opposed to the second body region 150 and the second semiconductor region 72 through the third upper insulating film 155.

The opposing area of the third upper electrode 157 with respect to the second body region 150 is larger than the opposing area of the third upper electrode 157 with respect to the second semiconductor region 72. The third upper electrode 157 may include conductive polysilicon. The third upper electrode 157 is formed as a low potential electrode. It is preferable to apply a potential other than the gate potential (gate signal G) to the third upper electrode 157. An anode potential may be applied to the third upper electrode 157.

The third upper electrode 157 has an electrode surface exposed from the third trench 154. The electrode surface of the third upper electrode 157 may be curved to be depressed toward the bottom wall of the third trench 154. The electrode surface of the third upper electrode 157 is preferably located closer to the bottom wall side of the third trench 154 than the depth position of the electrode surface of the second split electrode 136 (the first split electrode 76) in the depth direction of the third trench 154.

The third lower electrode 158 is buried in the third trench 154 at a lower side (bottom wall side) thereof via the third lower insulating film 156. The third lower electrode 158 is buried in a band shape extending in the second direction Y in a plan view. The third lower electrode 158 may have a thickness (length) exceeding that of the third upper electrode 157 in the depth direction of the third trench 154.

The third lower electrode 158 is opposed to the second semiconductor region 72 via the third lower insulating film 156. The third lower electrode 158 has an upper end portion protruding from the third lower insulating film 156 toward the first main surface 3 side. The upper end portion of the third lower electrode 158 engages with the bottom portion of the third upper electrode 157, and faces the third upper insulating film 155 along the lateral direction of the first main surface 3 with the bottom portion of the third upper electrode 157 interposed therebetween.

The third lower electrode 158 may comprise conductive polysilicon. The third lower electrode 158 is preferably applied with a potential other than the gate potential (gate signal G). The third lower electrode 158 is preferably fixed at the same potential as the third upper electrode 157. That is, an anode potential may be applied to the third lower electrode 158. This suppresses a voltage drop between the third upper electrode 157 and the third lower electrode 158, and therefore, an electric field concentration between the third upper electrode 157 and the third lower electrode 158 can be suppressed.

The third intermediate insulating film 159 is interposed between the third upper electrode 157 and the third lower electrode 158, and electrically insulates the third upper electrode 157 and the third lower electrode 158. Specifically, the third intermediate insulating film 159 covers the third lower electrode 158 exposed from the third lower insulating film 156 in the region between the third upper electrode 157 and the third lower electrode 158.

The third intermediate insulating film 159 is connected to the third upper insulating film 155 and the third lower insulating film 156. The third interlayer insulating film 159 may include a silicon oxide film. The third intermediate insulating film 159 preferably includes a silicon oxide film made of an oxide of the third lower electrode 158. The third intermediate insulating film 159 has an intermediate thickness TM in the normal direction Z, like the first intermediate insulating film 89A.

The semiconductor device 1A includes a first temperature sensing diode 17A formed in the first temperature measuring region 9A. The first temperature-sensitive diode 17A has a pn junction portion formed in the surface layer portion of the first main surface 3 in the region between the plurality of diode trench structures 151. Specifically, the pn junction is formed in the surface layer of the second body region 150. In this embodiment, the pn junction is not formed in the region between the diode separation structure 131 and the diode trench structure 151.

Specifically, the first temperature sensing diode 17A includes a p-type anode region 161 (first polarity region) and an n-type cathode region 162 (second polarity region) formed in the surface layer portion of the second body region 150, respectively. The cathode region 162 is formed in the surface layer portion of the second body region 150 so as to form a pn junction with the anode region 161.

More specifically, the first temperature sensing diode 17A includes a plurality of anode regions 161 and a plurality of cathode regions 162. The plurality of cathode regions 162 are alternately arranged with the plurality of anode regions 161 along the second direction Y with one anode region 161 interposed therebetween.

The plurality of anode regions 161 and the plurality of cathode regions 162 meet the plurality of diode trench structures 151. Regarding the plurality of diode trench structures 151, the plurality of anode regions 161 and the plurality of cathode regions 162 are opposed to the third upper electrode 157 via the third upper insulating film 155.

An anode potential is applied to the plurality of anode regions 161, and a cathode potential is applied to the plurality of cathode regions 162. That is, the plurality of anode regions 161 are fixed at the same potential as one or both (in this embodiment, both) of the third upper electrode 157 and the third lower electrode 158.

Each anode region 161 has a concentration gradient in which the p-type impurity concentration increases and decreases along the second direction Y. Specifically, each anode region 161 includes a high concentration region 161a, a first low concentration region 161b, and a second low concentration region 161c formed along the second direction Y. The high concentration region 161a is a region having a higher p-type impurity concentration than the second body region 150. The first low concentration region 161b and the second low concentration region 161c are each a region having a lower p-type impurity concentration than the high concentration region 161 a.

The high concentration region 161a is formed on the first main surface 3 side from the bottom of the second body region 150 at a distance therefrom, and faces the second semiconductor region 72 through a part of the second body region 150. The high concentration region 161a preferably has a p-type impurity concentration substantially equal to that of the contact region 91 of the output region 7.

The high concentration region 161a preferably has a thickness (depth) substantially equal to that of the contact region 91. According to this configuration, the high concentration region 161a can be formed simultaneously with the contact region 91. The high concentration region 161a has a first region width WR1 in the second direction Y. The first region width WR1 is preferably substantially equal to the length of the contact region 91.

The first low concentration region 161b is located on one side of the second direction Y with respect to the high concentration region 161 a. The second low concentration region 161c is located at the other side of the second direction Y with respect to the high concentration region 161 a. In this embodiment, the first low concentration region 161b and the second low concentration region 161c are formed by using a part of the second body region 150.

Thus, the first and second low concentration regions 161b and 161c each have a p-type impurity concentration of the second body region 150. The first low density region 161b and the second low density region 161c each have a second region width WR2 (wr1+notewr2) different from the first region width WR1 in the second direction Y. The second zone width WR2 is preferably smaller than the first zone width WR1 (WR 1 > WR 2).

The cathode regions 162 are formed on the first main surface 3 side from the bottom of the second body region 150 at intervals, and face the second semiconductor region 72 through a part of the second body region 150. Each of the cathode regions 162 preferably has an n-type impurity concentration substantially equal to that of the source region 90 of the output region 7. Each of the cathode regions 162 preferably has a thickness (depth) substantially equal to that of the source region 90. According to this configuration, the cathode region 162 may be formed simultaneously with the source region 90.

Each cathode region 162 has a third region width WR3 (wr2+notewr3) different from the second region width WR2 in the second direction Y. The second region width WR2 preferably has a length that is less than the length of the source region 90. The third zone width WR3 preferably exceeds the second zone width WR2 (WR 2 < WR 3). The third region width WR3 may be equal to or greater than the first region width WR1 (WR 1. Ltoreq. WR 3), or may be smaller than the first region width WR1 (WR 1 > WR 3).

The semiconductor device 1A includes a p-type diode contact region 171 formed in a region between the diode isolation structure 131 (the second trench isolation structure 132) and the diode trench structure 151 at a surface layer portion of the second body region 150. The diode contact region 171 has a higher p-type impurity concentration than the second body region 150. The diode contact region 171 preferably has a p-type impurity concentration substantially equal to that of the high concentration region 161a (the contact region 91 of the output region 7).

The diode contact region 171 is formed to be spaced apart from the second trench isolation structure 132 and to meet the diode trench structure 151. The diode contact region 171 faces the third upper electrode 157 via the third upper insulating film 155. The diode contact region 171 is formed on the first main surface 3 side from the bottom of the second body region 150 at a distance therefrom, and faces the second semiconductor region 72 through a part of the second body region 150. The diode contact region 171 is formed in a band shape extending along the sidewall of the corresponding diode trench structure 151 in a plan view.

The semiconductor device 1A includes a pair of diode trench connection structures 181 formed on the first main surface 3 in the first temperature measurement region 9A. The pair of diode groove connection structures 181 includes the diode groove connection structure 181 on one side (the first side surface 5A side) and the diode groove connection structure 181 on the other side (the second side surface 5B side) which face each other across the plurality of diode groove structures 151 in the second direction Y.

The diode trench connection structure 181 on one side connects the first ends 151a of the pair of diode trench structures 151 to each other in an arch shape in a plan view. The other diode trench connection structure 181 connects the second ends 151b of the pair of diode trench structures 151 to each other in an arch shape in a plan view. The pair of diode trench connection structures 181 and the plurality of diode trench structures 151 form one annular trench structure.

The diode trench connection structure 181 on the other side has the same structure as the diode trench connection structure 181 on the one side except that it is connected to the second end 151b of the diode trench structure 151. Hereinafter, the structure of the diode trench connection structure 181 on one side will be described, and the description of the structure of the diode trench connection structure 181 on the other side will be omitted.

The diode trench connection structure 181 of one side has a first portion 182a extending in the first direction X and a plurality of second portions 182b extending in the second direction Y. The first portion 182a is opposite the plurality of first ends 151a in plan view. The plurality of second portions 182b extend from the first portion 182a toward the plurality of first ends 151a and are connected to the plurality of first ends 151 a.

The diode trench connection structure 181 on one side has a connection width WC and a connection depth DC as in the first trench connection structure 111 (the second trench connection structure 121). The bottom wall of the diode trench connection structure 181 is preferably spaced apart from the bottom of the second semiconductor region 72 by a spacing of 1 μm or more and 5 μm or less.

The diode trench connection structure 181 on one side has a single-electrode structure including a third connection trench 182, a third connection insulating film 183, a third connection electrode 184, and a third cap insulating film 185. The third connecting grooves 182 extend in an arch shape so as to communicate with the first end portions 151a of the plurality of third grooves 154 in a plan view, and dig from the first main surface 3 toward the second main surface 4. The third connection trench 182 divides the first portion 182a and the second portion 182b of the diode trench connection structure 181. The third connection trenches 182 are formed on the first main surface 3 side with a space from the bottom of the second semiconductor region 72.

The third connecting groove 182 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The bottom wall corner of the third connecting groove 182 is preferably formed in a curved shape. The entire bottom wall of the third connecting groove 182 may be formed in a curved shape toward the second main surface 4. The side walls and the bottom wall of the third connecting groove 182 are smoothly connected with the side walls and the bottom wall of the third groove 154.

The third connection insulating film 183 is formed on the wall surface of the third connection trench 182. Specifically, the third connection insulating film 183 is formed in a film shape on the wall surface of the third connection groove 182, and a groove space is partitioned in the third connection groove 182. The third connection insulating film 183 extends in the first direction X in the first portion 182a of the third connection trench 182. The third connection insulating film 183 extends in the second direction Y in the second portion 182b of the third connection trench 182.

The third connection insulating film 183 is connected to the third upper insulating film 155 and the third lower insulating film 156 at the communication portions of the third connection trench 182 and the third trench 154. The third connection insulating film 183 may include a silicon oxide film. The third connection insulating film 183 preferably includes a silicon oxide film made of an oxide of the chip 2. The third connection insulating film 183 has a third thickness T3, like the first connection insulating film 113 and the like.

The third connection electrode 184 is embedded in the third connection trench 182 as a single body via the third connection insulating film 183. In this embodiment, the third connection electrode 184 may include conductive polysilicon. The third connection electrode 184 extends in the first direction X in the first portion 182a of the third connection trench 182. The third connection electrode 184 extends in the second direction Y in the second portion 182b of the third connection trench 182. The third connection electrode 184 is connected to the third lower electrode 158 at the communication portion of the third connection groove 182 and the third groove 154.

The third connection electrode 184 is electrically insulated from the third upper electrode 157 via the third interlayer insulating film 159. That is, the third connection electrode 184 is formed of a lead portion led out from the third trench 154 to the third connection trench 182 through the third connection insulating film 183 and the third intermediate insulating film 159 in the third lower electrode 158.

The third connection electrode 184 has an electrode surface exposed from the third connection groove 182. The electrode surface of the third connection electrode 184 may be curved toward the bottom wall of the third connection groove 182. The electrode surface of the third connection electrode 184 is preferably located (protrudes) further toward the first main surface 3 than the depth of the electrode surface of the third upper electrode 157 in the depth direction of the third connection groove 182.

The third cap insulating film 185 covers the electrode surface of the third connection electrode 184 in a film shape in the third connection groove 182. The third cap insulating film 185 suppresses short-circuiting of the third connection electrode 184 with other electrodes. The third cap insulating film 185 is connected to the third connection insulating film 183.

The third cap insulating film 185 may include a silicon oxide film. The third cap insulating film 185 preferably includes a silicon oxide film composed of an oxide of the third connection electrode 184. That is, the third cap insulating film 185 preferably includes an oxide of polysilicon, and the third connection insulating film 183 includes an oxide of single crystal silicon.

Thus, the semiconductor device 1A includes in the first temperature measurement region 9A: the diode separating structure 131, the plurality of diode trench structures 151, the second body region 150, the second temperature sensing diode 17B, the diode contact region 171, and the diode trench connecting structure 181.

The first temperature sensing diode 17A has a negative temperature characteristic in which the first forward voltage Vf1 linearly decreases with an increase in the first temperature TE1 of the output region 7. Thereby, the first temperature sensing diode 17A generates the first temperature measurement signal ST1 that varies according to the first temperature TE1 of the output region 7, and indirectly monitors the first temperature TE1 of the output region 7.

Referring again to fig. 1, the semiconductor device 1A further includes the above-described second temperature measurement region 9B partitioned inside the control region 10. The construction of the second temperature measuring region 9B side is the same as that of the first temperature measuring region 9A side. That is, the semiconductor device 1A includes, in the second temperature measurement region 9B: the diode separating structure 131, the plurality of diode trench structures 151, the second body region 150, the second temperature sensing diode 17B, the diode contact region 171, and the diode trench connecting structure 181. The diode separating structure 131 may have a single-trench separating structure constituted only by the second trench separating structure 132, or may have a multi-trench separating structure including a plurality of trench separating structures.

That is, the second temperature sensing diode 17B has substantially the same structure as the first temperature sensing diode 17A, and has substantially the same electrical characteristics as the first temperature sensing diode 17A. The second temperature sensing diode 17B has a negative temperature characteristic in which the second forward voltage Vf2 linearly decreases with an increase in the second temperature TE2 of the control region 10. Thereby, the second temperature sensing diode 17B generates the second temperature measurement signal ST2 that varies according to the second temperature TE2 of the control area 10, and indirectly monitors the second temperature TE2 of the control area 10.

Fig. 25 is an enlarged plan view partially showing another embodiment of the first temperature measuring region 9A. Fig. 19 shows an example of the structure of the first temperature measurement region 9A including 2 diode trench structures 151. However, as shown in fig. 25, the first temperature measurement region 9A including 3 or more diode trench structures 151 may be employed. In fig. 25, an example in which 4 diode trench structures 151 are formed is shown, but the number of diode trench structures 151 may be arbitrary or 5 or more.

The first temperature sensing diode 17A has a plurality of pn junction portions formed on the surface layer portion of the first main surface 3 in regions between the pair of diode trench structures 151 that are close to each other. That is, the first temperature-sensitive diode 17A includes a plurality of anode regions 161 and a plurality of cathode regions 162 respectively formed in regions between the pair of diode trench structures 151 that are close to each other. The layout of the first temperature measuring region 9A (first temperature sensing diode 17A) is adjusted by such a configuration. Of course, the layout of the second temperature measuring region 9B (second temperature sensing diode 17B) is also adjusted by such a configuration.

Fig. 26 is a graph showing the temperature characteristic of the first temperature sensing diode 17A shown in fig. 19. In fig. 26, the vertical axis represents the first forward voltage Vf1[ mV ] of the first temperature-sensing diode 17A, and the horizontal axis represents the first temperature TE1[ °c ] of the output region 7. Fig. 26 shows temperature characteristics of the first forward voltage Vf1 by a plurality of drawing points.

Referring to fig. 26, the first temperature sensing diode 17A has a negative temperature characteristic in which the first forward voltage Vf1 linearly decreases with an increase in the first temperature TE1 of the output region 7. Thereby, the first temperature sensing diode 17A generates the first temperature measurement signal ST1 that varies according to the first temperature TE1 of the output region 7, and indirectly monitors the first temperature TE1 of the output region 7.

When the main transistor 11 generates the output current IO, the second temperature TE2 is smaller than the first temperature TE1 (T1 > T2). Therefore, at the time of generation of the output current IO, the forward voltage Vf2 of the second temperature sensing diode 17B exceeds the forward voltage Vf1 of the first temperature sensing diode 17A (Vf 1 < Vf 2).

The differential signal Δvf generated by the differential circuit 26 represents a differential value (Δvf=vf2-vf1) of the first temperature measurement signal ST1 (first forward voltage Vf 1) and the second temperature measurement signal ST2 (second forward voltage Vf 2). Fig. 26 shows an example of the differential signal Δvf when the first temperature TE1 is 75 ℃ and the second temperature TE2 is 25 ℃. As for other description of the structure of the second temperature measuring region 9B side, description of the structure of the first temperature measuring region 9A side is omitted.

Referring again to fig. 1, the semiconductor device 1A further includes the plurality of protection regions 42 (the plurality of first protection regions 42A and the plurality of second protection regions 42B) divided into arbitrary regions inside the first main surface 3. The configuration of the plurality of first guard areas 42A is arbitrary. The plurality of second protection regions 42B are disposed at positions close to the plurality of terminal electrodes 35, respectively. The structure of the guard region 42 will be described below. Fig. 27 is an enlarged view of the region XXVII shown in fig. 1. Fig. 27 is an enlarged plan view showing the structure of the second guard region 42B side.

The plurality of protection regions 42 are respectively constructed in the same manner as the first temperature measuring region 9A. That is, the semiconductor device 1A includes, in each protection region 42: the diode separating structure 131, the plurality of diode trench structures 151, the second body region 150, the second temperature sensing diode 17B, the diode contact region 171, and the diode trench connecting structure 181. The diode separating structure 131 may have a single-trench separating structure constituted only by the second trench separating structure 132, or may have a multi-trench separating structure including a plurality of trench separating structures.

The planar area of each protection region 42 is preferably smaller than the planar area of the terminal electrode 35 (terminal electrodes 38 to 41) other than the source terminal 37. The planar area of each protection zone 42 preferably exceeds the planar area of each temperature measurement zone 9. The number of the plurality of diode trench structures 151 in each protection region 42 preferably exceeds the number of the plurality of diode trench structures 151 in each temperature measurement region 9.

The total planar area of the anode region 161 in each protection zone 42 preferably exceeds the total planar area of the anode region 161 in each temperature measurement zone 9. The total planar area of the cathode region 162 in each protection region 42 preferably exceeds the total planar area of the cathode region 162 in each temperature measurement region 9.

By increasing the planar area of each protection region 42, the current handling capability when a relatively large reverse bias voltage VR is applied to each ESD diode 43 can be improved. The other explanation of the structure of each protection region 42 is omitted as to the explanation of the structure of the applicable first temperature measuring region 9A.

Fig. 28 is a graph showing breakdown characteristics of the ESD diode 43 shown in fig. 27. In fig. 28, the vertical axis represents reverse current IR [ a ], the lower horizontal axis represents reverse bias voltage VR [ V ], and the upper horizontal axis represents leakage current IL [ a ]. In fig. 28, the breakdown characteristics of the ESD diode 43 are represented by a plurality of drawing points formed by black circles, and the leakage current characteristics of the ESD diode 43 are represented by a plurality of drawing points formed by X marks. Referring to fig. 28, it was confirmed that the ESD diode 43 has good breakdown characteristics and operates appropriately against static electricity.

Fig. 29 is a graph showing a relationship between the breakdown current IB of the ESD diode 43 shown in fig. 27 and the planar area of the ESD diode 43. In fig. 29, the vertical axis represents the breakdown current IB [ a ] of the ESD diode 43 ]The horizontal axis represents the total planar area [ μm ] of the cathode region 162 ² ]. The breakdown current IB is the reverse current IR when the ESD diode 43 is broken.

Fig. 29 is a graph obtained by a known TLP (Transmission Line Pulse) assay. In the TLP measurement method, a reverse bias voltage VR is applied to the ESD diode 43 in a pulse shape to an extent that the ESD diode 43 is broken, and a breakdown current IB is obtained. The total planar area of the cathode region 162 is adjusted by adjusting the planar area of the protection region 42, the number of the plurality of diode trench structures 151, and the like.

In the protection region 42, the total planar area of the anode region 161 increases in cooperation with the increase of the total planar area of the cathode region 162. Referring to fig. 29, the breakdown current IB of the ESD diode 43 is increased by increasing the planar area of the protection region 42 (the total planar area of the cathode region 162).

As is clear from the evaluation results of fig. 28 and 29, the ESD diode 43 has the same structure as the temperature sensing diode 17, has a structure different from that of the zener diode, and has the same breakdown characteristics as the zener diode, and functions as an ESD protection device. In other words, it is known that the temperature sensing diode 17 has the same structure as the ESD diode 43 and has a forward voltage characteristic that linearly changes with respect to a temperature change, and functions as a temperature sensing device.

As an example, each protection region 42 preferably has a planar area exceeding the planar area of each temperature measurement region 9 in plan view. That is, the ESD diode 43 preferably has a planar area exceeding the planar area of the temperature sensing diode 17. Thus, the ESD diode 43 has a basic configuration common to the temperature sensing diode 17, and also functions as an ESD protection device.

At this time, the total planar area of the cathode region 162 of the ESD diode 43 preferably exceeds the total planar area of the cathode region 162 of the temperature sensing diode 17. In addition, the total planar area of the anode region 161 of the ESD diode 43 preferably exceeds the total planar area of the anode region 161 of the temperature sensing diode 17.

Referring again to fig. 11 to 14, fig. 21 to 25, and the like, the semiconductor device 1A includes a first field insulating film 191 partially covering the first main surface 3 in the output region 7. The first field insulating film 191 may include a silicon oxide film. The first field insulating film 191 preferably includes a silicon oxide film composed of an oxide of the chip 2.

The first field insulating film 191 is formed on the first trench isolation structure 73 side with a space from the main transistor 11 in a plan view, and covers the periphery of the first trench isolation structure 73. The first field insulating film 191 directly covers the first body region 80 at the peripheral edge portion of the output region 7, exposing the outermost contact region 91.

The first field insulating film 191 is formed in a band shape extending along the inner edge (inner peripheral wall) of the first trench isolation structure 73 in a plan view. In this embodiment, the first field insulating film 191 is formed in a ring shape extending along the inner peripheral wall of the first trench isolation structure 73 in a plan view, and surrounds the inside of the output region 7 over the entire circumference.

The first field insulating film 191 has sides extending in one direction (first direction X) and sides extending in a crossing direction (second direction Y) crossing the one direction in a plan view. The first field insulating film 191 is connected to the first separation insulating film 75 on the inner edge (inner peripheral wall) side of the first trench separation structure 73. The output region 7 is divided by the first trench isolation structure 73 within the chip 2, and is divided by the first field insulating film 191 over the chip 2.

The first field insulating film 191 has a first insulating sidewall 191a that divides the output region 7 above the chip 2. The first insulating sidewall 191a is formed throughout the entire circumference of the first field insulating film 191. The first insulating sidewall 191a has a side extending in one direction (first direction X) and a side extending in a crossing direction (second direction Y) crossing the one direction. The first insulating sidewall 191a is located over the first body region 80. The first insulating sidewall 191a is inclined obliquely downward at an acute angle with respect to the first main surface 3.

Specifically, the first insulating sidewall 191a has an upper end portion located on the main surface side of the first field insulating film 191 and a lower end portion located on the first main surface 3 side, and is inclined obliquely downward from the upper end portion toward the lower end portion. The first insulating side wall 191a forms an inclination angle (20 degree. Ltoreq.θ. Ltoreq.40°) of 20 degrees or more and 40 degrees or less with the first main surface 3. The inclination angle is as follows: when a straight line connecting the upper end portion and the lower end portion of the first insulating sidewall 191a is set in the cross-sectional view, the straight line forms an angle (absolute value) with respect to the first main surface 3 inside the first field insulating film 191. The inclination angle is preferably less than 40 ° (θ < 40 °).

The inclination angle is particularly preferably converged to 30 ° ± the range of 6 DEG (theta is more than or equal to 24 DEG and less than or equal to 36 DEG). The inclination angle typically converges in a range of 28 ° or more and 36 ° or less (28 °. Ltoreq.θ. Ltoreq.36°). The first insulating sidewall 191a may be inclined in a curved shape depressed toward the first main surface 3 in a region between the upper end portion and the lower end portion. At this time, the inclination angle is also the following angle in the sectional view: when a straight line connecting the upper end portion and the lower end portion of the first insulating sidewall 191a is set, the angle (absolute value) of the straight line with respect to the first main surface 3 is set.

According to the first insulating sidewall 191a having a relatively slow inclination angle, it is possible to suppress electrode residues that are generated at the time of forming the trench structure 82 or the like from remaining in a state of adhering to the first insulating sidewall 191 a. This reduces the risk of short-circuiting between the plurality of unit transistors 13 due to electrode residues. Digging the electrode surface of the first upper electrode 87A and the electrode surface of the second upper electrode 87B deeper than the electrode surface of the first separation electrode 76 or the like is effective in reducing the risk of short-circuiting of the first upper electrode 87A and the second upper electrode 87B due to electrode residues.

The first field insulating film 191 has a thickness exceeding the first thickness T1 of the upper insulating film 85. The thickness of the first field insulating film 191 is a thickness along the normal direction Z of a portion other than the first insulating sidewall 191 a. The thickness of the first field insulating film 191 preferably exceeds the intermediate thickness TM of the intermediate insulating film 89.

The thickness of the first field insulating film 191 may be substantially equal to the second thickness T2 of the lower insulating film 86. The thickness of the first field insulating film 191 may be substantially equal to the separation thickness TI of the first separation insulating film 75. The thickness of the first field insulating film 191 may be 0.1 μm or more and 1 μm or less. The thickness of the first field insulating film 191 is preferably 0.15 μm or more and 0.65 μm or less.

Referring again to fig. 21 to 25, the semiconductor device 1A includes a second field insulating film 192 that partially covers the first main surface 3 in the temperature measuring region 9. The second field insulating film 192 may include a silicon oxide film. The second field insulating film 192 preferably includes a silicon oxide film composed of an oxide of the chip 2. The second field insulating film 192 is formed on the diode separation structure 131 side with a gap from the main transistor 11 and the temperature sensitive diode 17 in a plan view, and covers the periphery of the diode separation structure 131.

Specifically, the second field insulating film 192 includes: a first cover 193, a second cover 194, and a third cover 195. The first cover 193 is formed along the inner edge (inner peripheral wall) of the second trench isolation structure 132 at the peripheral edge of the temperature measurement region 9. The second cover 194 covers the mesa 138 between the second trench isolation structure 132 and the third trench isolation structure 133 above the first main surface 3. The third cover 195 is formed along the outer edge (outer peripheral wall) of the third groove separation structure 133 inside the output region 7.

The first cover 193 directly covers the second body region 150 at the peripheral edge of the temperature measurement region 9, exposing the diode contact region 171. The first cover 193 is formed in a band shape extending along an inner edge (inner peripheral wall) of the second groove separation structure 132 in a plan view.

In this embodiment, the first cover 193 is formed in a ring shape extending along the inner edge (inner peripheral wall) of the second trench isolation structure 132 in a plan view, and surrounds the inside of the temperature measurement region 9 over the entire circumference. The first cover 193 is connected to the second separation insulating film 135 on the inner edge (inner peripheral wall) side of the second trench separation structure 132. The first cover 193 has a side extending in one direction (first direction X) and a side extending in a crossing direction (second direction Y) crossing the one direction in a plan view.

The second cover 194 directly covers the second semiconductor region 72 at the mesa 138. The second field insulating film 192 is formed in a band shape extending along the outer edge (outer peripheral wall) of the second trench isolation structure 132 and the inner edge (inner peripheral wall) of the third trench isolation structure 133 in a plan view.

In the present embodiment, the second cover portion 194 is formed in a ring shape extending along the mesa portion 138 in a plan view, and surrounds the second trench isolation structure 132 over the entire circumference. The second cover 194 is connected to the second separation insulating film 135 on the outer edge (outer peripheral wall) side of the second trench separation structure 132, and is connected to the third separation insulating film 145 on the inner edge (inner peripheral wall) side of the third trench separation structure 133.

The third covering portion 195 directly covers the first body region 80 inside the output region 7, exposing the contact region 91. The third cover 195 is formed in a band shape extending along the outer edge (outer peripheral wall) of the third groove separation structure 133 in a plan view.

In this embodiment, the third cover 195 is formed in a ring shape extending along the outer edge (outer peripheral wall) of the third groove separation structure 133 in plan view, and surrounds the third groove separation structure 133 over the entire circumference. The third cover 195 is connected to the third separation insulating film 145 on the outer edge (outer peripheral wall) side of the third trench separation structure 133. The third cover 195 has a side extending in one direction (first direction X) and a side extending in a crossing direction (second direction Y) crossing the one direction in a plan view.

The temperature measuring region 9 is divided by the diode separating structure 131 in the chip 2, and is divided by the second field insulating film 192 above the chip 2. The output region 7 is internally divided by a first field insulating film 191 and a second field insulating film 192 on the chip 2.

The second field insulating film 192 has a second insulating sidewall 192a that divides the temperature measuring region 9 and the output region 7 above the chip 2. The second insulating sidewall 192a is formed throughout the entire circumference of the second field insulating film 192. The second insulating sidewall 192a has a side extending in one direction (first direction X) and a side extending in a crossing direction (second direction Y) crossing the one direction.

The second insulating sidewall 192a on the temperature measuring region 9 side is located above the second body region 150, and the second insulating sidewall 192a on the output region 7 side is located above the first body region 80. The second insulating sidewall 192a is inclined obliquely downward at an acute angle with respect to the first main surface 3. Specifically, the second insulating sidewall 192a has an upper end portion located on the main surface side of the second field insulating film 192 and a lower end portion located on the first main surface 3 side, and is inclined obliquely downward from the upper end portion toward the lower end portion.

The second insulating side wall 192a forms an inclination angle (20 ° - θ -40 °) of 20 ° or more and 40 ° or less with the first main surface 3, like the first insulating side wall 191 a. The inclination angle is particularly preferably converged at 30 ° ± the range of 6 DEG (theta is more than or equal to 24 DEG and less than or equal to 36 DEG). The inclination angle typically converges in a range of 28 ° or more and 36 ° or less (28 °. Ltoreq.θ. Ltoreq.36°).

The second insulating sidewall 192a may be inclined in a curved shape depressed toward the first main surface 3 in a region between the upper end portion and the lower end portion. At this time, the inclination angle is also the following angle: when a straight line connecting the upper end portion and the lower end portion of the second insulating sidewall 192a is set in the cross-sectional view, the straight line forms an angle (absolute value) with respect to the first main surface 3.

According to the second insulating sidewall 192a having a relatively slow inclination angle, it is possible to suppress electrode residues generated at the time of forming the trench structure 82, the diode trench structure 151, and the like from remaining in a state of adhering to the second insulating sidewall 192 a. This reduces the risk of short-circuiting between the temperature sensing diode 17 and the unit transistor 13 due to electrode residues. Digging the electrode surface of the third upper electrode 157 deeper than the electrode surfaces of the first split electrode 76, the second split electrode 136, and the like is effective in reducing the risk of short-circuiting of the first upper electrode 87A, the second upper electrode 87B, and the third upper electrode 157 due to electrode residues.

The second field insulating film 192 preferably has a thickness substantially equal to that of the first field insulating film 191. Although a specific illustration is omitted, the second field insulating film 192 may cover the second temperature measuring region 9B side region and the protection region 42 side region in the same manner as the first temperature measuring region 9A.

The semiconductor device 1A includes a main surface insulating film 196 that selectively covers the first main surface 3 in the output region 7. The main surface insulating film 196 may include a silicon oxide film. The main surface insulating film 196 preferably includes a silicon oxide film made of an oxide of the chip 2. The main surface insulating film 196 covers the region outside the first field insulating film 191 and the second field insulating film 192 in the output region 7. The main surface insulating film 196 is connected to the upper insulating film 85, the first connection insulating film 113, the second connection insulating film 123, the third upper insulating film 155, the first field insulating film 191 (first insulating sidewall 191 a), and the second field insulating film 192 (second insulating sidewall 192 a).

The main surface insulating film 196 has a thickness smaller than that of the first field insulating film 191 (the second field insulating film 192). The thickness of the main surface insulating film 196 is preferably one fifth or less of the thickness of the first field insulating film 191 (the second field insulating film 192). The thickness of the main surface insulating film 196 may be substantially equal to the first thickness T1 of the upper insulating film 85. The thickness of the main surface insulating film 196 may be 0.01 μm or more and 0.05 μm or less. The thickness of the main surface insulating film 196 is preferably 0.02 μm or more and 0.04 μm or less.

The semiconductor device 1A includes the interlayer insulating layer 30 covering the first main surface 3. The semiconductor device 1A includes a plurality of via electrodes 201 to 209 buried in the interlayer insulating layer 30. The plurality of via electrodes 201 to 209 include: a plurality of first via electrodes 201, a plurality of second via electrodes 202, a plurality of third via electrodes 203, a plurality of fourth via electrodes 204, a plurality of fifth via electrodes 205, a plurality of sixth via electrodes 206, a plurality of seventh via electrodes 207, a plurality of eighth via electrodes 208, and a plurality of ninth via electrodes 209. The plurality of via electrodes 201 to 209 may be formed of tungsten via electrodes. In some of the drawings, a plurality of via electrodes 201 to 209 are represented by X marks or lines in a simplified manner.

The plurality of first via electrodes 201 are each constituted by a source via electrode for the first split electrode 76. The plurality of first via electrodes 201 are buried in portions of the interlayer insulating layer 30 covering the first trench isolation structures 73. The plurality of first via electrodes 201 are buried along the first separation electrode 76 at intervals, and are electrically connected to the first separation electrode 76, respectively. The arrangement and shape of the plurality of first via electrodes 201 are arbitrary. One or more first via electrodes 201 extending in a band shape or a ring shape in a top view may be formed over the first separation electrode 76.

The plurality of second via electrodes 202 are each constituted by a gate via electrode for the plurality of upper electrodes 87. The plurality of second via electrodes 202 are buried in portions of the interlayer insulating layer 30 covering the plurality of trench structures 82, respectively. In this embodiment, the plurality of second via electrodes 202 are electrically connected to both ends of the plurality of upper electrodes 87, respectively. The arrangement and shape of the plurality of second via electrodes 202 are arbitrary. 1 or more second via electrodes 202 extending in a stripe shape along the upper electrodes 87 in a plan view may also be formed on each upper electrode 87.

The plurality of third via electrodes 203 are each constituted by a source via electrode for the plurality of channel cells 83. The plurality of third via electrodes 203 are buried in portions of the interlayer insulating layer 30 covering the plurality of channel units 83. The plurality of third via electrodes 203 are electrically connected to the plurality of source regions 90 and the plurality of contact regions 91 (outermost contact regions 91), respectively. The arrangement and shape of the plurality of third through-hole electrodes 203 are arbitrary. One or more third via electrodes 203 extending in a stripe shape in a top view may be formed over each channel unit 83.

The fourth via electrodes 204 are formed of gate via electrodes for the first to second connection electrodes 114 and 124. The fourth via electrodes 204 are buried in portions of the interlayer insulating layer 30 covering the first to second connection electrodes 114 and 124. Each fourth through-hole electrode 204 is electrically connected to the plurality of first to second connection electrodes 114 and 124. The arrangement and shape of the plurality of fourth via electrodes 204 are arbitrary. 1 or more fourth through-hole electrodes 204 extending in a stripe shape along the respective first to second connection electrodes 114, 124 in a plan view may be formed on the respective first to second connection electrodes 114, 124.

The plurality of fifth via electrodes 205 are each constituted by a source via electrode for the monitor transistor 14. The fifth via electrode 205 is buried in the following portion: a portion of the plurality of first channel units 83A serving as the first channel units 83A of the first system monitor transistor 15A is covered in the interlayer insulating layer 30.

The number of first channel units 83A for the first system monitor transistor 15A is set smaller than the number of first channel units 83A for the first system transistor 12A. In this embodiment, the first channel unit 83A located in one first complex unit 101 serves as the first channel unit 83A of the first system monitor transistor 15A.

In addition, the fifth via electrode 205 is buried in the following portion: covering the portion of the second channel unit 83B that serves as the second system monitor transistor 15B in the second channel unit 83B. The number of second channel units 83B for the second system monitor transistor 15B is set smaller than the number of second channel units 83B for the second system transistor 12B. The fifth via electrode 205 is electrically connected to the plurality of source regions 90 and the plurality of contact regions 91. The fifth via electrode 205 is arbitrarily arranged and shaped. The plurality of fifth via electrodes 205 may be arranged at intervals along the channel unit 83 in a plan view.

The plurality of sixth via electrodes 206 are each constituted by an anode via electrode for the diode separating structure 131 (the second trench separating structure 132 and the third trench separating structure 133). The plurality of sixth via electrodes 206 are buried in portions of the interlayer insulating layer 30 covering the diode separation structure 131. The sixth via electrodes 206 are buried along the diode separation structure 131 at intervals, and are electrically connected to the second separation electrode 136 and the third separation electrode 146, respectively.

The arrangement and shape of the plurality of sixth via electrodes 206 are arbitrary. One or more sixth via electrodes 206 extending in a band shape or a ring shape in a top view may be formed over the second separation electrode 136. In addition, 1 or more sixth via electrodes 206 extending in a circular shape, a polygonal shape, a band shape, or a ring shape in a plan view may be formed over the third separation electrode 146.

The seventh via electrodes 207 are each constituted by anode via electrodes for the anode regions 161. The seventh via electrodes 207 are buried in portions of the interlayer insulating layer 30 covering the anode regions 161. The seventh via electrodes 207 are buried along the anode regions 161 at intervals, and are electrically connected to the anode regions 161, respectively. The arrangement and shape of the seventh via electrodes 207 are arbitrary. It may be formed in a band shape, a circular shape or a polygonal shape in a plan view.

The eighth via electrodes 208 are each constituted by a cathode via electrode for the cathode region 162. The eighth via electrodes 208 are buried in portions of the interlayer insulating layer 30 covering the cathode regions 162. The eighth via electrodes 208 are buried along the cathode regions 162 at intervals, and are electrically connected to the cathode regions 162, respectively. The arrangement and shape of the plurality of eighth via electrodes 208 are arbitrary. It may be formed in a band shape, a circular shape or a polygonal shape in a plan view.

The ninth via electrodes 209 are each constituted by an anode via electrode for the diode trench structure 151 and the diode trench connection structure 181. The ninth via electrodes 209 are buried in portions of the interlayer insulating layer 30 covering the diode trench structure 151 and the diode trench connection structure 181. The ninth via electrodes 209 are electrically connected to the third upper electrodes 157 and the third connection electrodes 184, respectively. The arrangement and shape of the plurality of ninth via electrodes 209 are arbitrary. It may be formed in a band shape, a circular shape or a polygonal shape in a plan view.

The semiconductor device 1A includes 1 or more of the main source wirings 33 disposed in the interlayer insulating layer 30. The 1 or more main source wirings 33 are selectively routed into the interlayer insulating layer 30, electrically connected to the first separation electrode 76 via the plurality of first via electrodes 201, and electrically connected to the plurality of source regions 90 and the plurality of contact regions 91 via the plurality of third via electrodes 203.

In addition, 1 or more main source wirings 33 are electrically connected to the second split electrode 136 and the third split electrode 146 of the diode split structure 131 via the plurality of sixth via electrodes 206. One or more main source wirings 33 are electrically connected to the source terminal 37 described above.

The semiconductor device 1A includes 1 or more of the monitor source wirings 34 disposed in the interlayer insulating layer 30. The 1 or more monitor source wirings 34 are constituted by wiring layers formed in the interlayer insulating layer 30. The 1 or more monitor source wirings 34 are selectively routed into the interlayer insulating layer 30, electrically connected to the first channel cell 83A of the first system monitor transistor 15A via the fifth via electrode 205, and electrically connected to the second channel cell 83B of the second system monitor transistor 15B via the fifth via electrode 205. 1 or more monitor source wirings 34 are electrically connected to the above-described overcurrent protection circuit 21.

The semiconductor device 1A includes n of the above-described main gate wirings 31 formed in the interlayer insulating layer 30. n main gate wirings 31 are selectively routed into the interlayer insulating layer 30. The n main gate wirings 31 are electrically connected to each of 1 or more trench structures 82 (unit transistors 13) to be systematic as individual control targets in the output region 7, and are electrically connected to the control circuit 18 (gate drive circuit 19) described above in the control region 10.

In this embodiment, the n main gate wirings 31 include a first main gate wiring 31A and a second main gate wiring 31B. The first main gate wiring 31A is electrically connected to the first upper electrode 87A, the first lower electrode 88A, and the first connection electrode 114 via the corresponding second via electrode 202 and the corresponding fourth via electrode 204, and applies the first gate signal G1. The second main gate wiring 31B is electrically connected to the second upper electrode 87B, the second lower electrode 88B, and the second connection electrode 124 via the corresponding second via electrode 202 and the corresponding fourth via electrode 204, and applies a second gate signal G2.

The semiconductor device 1A includes the above-described n monitor gate wirings 32 formed in the interlayer insulating layer 30. n monitor gate wires 32 are selectively routed into the interlayer insulating layer 30. In this embodiment, the n monitor gate lines 32 include a first monitor gate line 32A and a second monitor gate line 32B.

The first monitor gate wiring 32A is electrically connected to the first upper electrode 87A, the first lower electrode 88A, and the first connection electrode 114 via the corresponding second via electrode 202 and the corresponding fifth via electrode 205. In this embodiment, the first monitor gate wiring 32A is integrally formed with the first main gate wiring 31A. The second monitor gate wiring 32B is electrically connected to the second upper electrode 87B and the second lower electrode 88B via the corresponding second via electrode 202 and the corresponding fifth via electrode 205. In this embodiment, the second monitor gate wiring 32B is integrally formed with the second main gate wiring 31B.

The semiconductor device 1A includes the plurality of anode wirings 211 formed in the interlayer insulating layer 30. The plurality of anode wirings 211 are constituted by a plurality of wiring layers selectively routed into the interlayer insulating layer 30. The plurality of anode wires 211 are electrically connected to the second separation electrode 136, the third separation electrode 146, and the plurality of anode regions 161 via the plurality of sixth via electrodes 206, the plurality of seventh via electrodes 207, and the plurality of ninth via electrodes 209.

The anode wiring 211 of the plurality of temperature measuring regions 9 is electrically connected to an arbitrary application terminal of a high potential (for example, a power supply potential VB). The anode wiring 211 of the plurality of protection regions 42 is electrically connected to the application terminal of the source potential or the application terminal of the ground potential corresponding to the ESD protection object. Of course, when a source potential is applied to the anode region 161, the anode wiring 211 may be connected to the main source wiring 33 of the outer periphery.

The semiconductor device 1A includes the above-described plurality of cathode wirings 212 formed in the interlayer insulating layer 30. The plurality of cathode wirings 212 are constituted by a plurality of wiring layers selectively routed into the interlayer insulating layer 30. The plurality of cathode wirings 212 are electrically connected to the plurality of cathode regions 162 via the plurality of eighth via electrodes 208. The cathode wirings 212 of the plurality of temperature measuring regions 9 are electrically connected to an arbitrary application terminal of a low potential (for example, a potential lower than the power supply potential VB by about 5V). The cathode wiring 212 of the plurality of protection regions 42 is electrically connected to the active clamp circuit 20 and any terminal electrode 35.

Control examples of the main transistor 11 of the 2-system will be described below with reference to fig. 30A to 30C and fig. 31. Fig. 30A to 30C are cross-sectional perspective views showing an example of the operation of the main transistor 11. Fig. 31 is a timing chart showing a control example of the main transistor 11. Fig. 30A to 30C show a configuration example in which the total channel ratio RT is 50%, the first system channel ratio RSA is 25%, and the second system channel ratio RSB is 25%. In fig. 30A to 30C, the channel (source region 90) in the off state is indicated by filled hatching.

In fig. 31, an enable signal EN, an output voltage VO (solid line), a first gate signal G1 (one-dot chain line), a second gate signal G2 (broken line), and an output current IO are shown in order from the upper side of the paper. Hereinafter, the gate/source voltage of the first system transistor 12A is set to "Vgs1", the gate/source voltage of the clamp MISFET59 is set to "Vgs2", the gate/source voltage of the drive MISFET56 is set to "Vgs3", the breakdown voltage of the zener diode column 57 is set to "VZ", and the forward voltage drop of the diode column 58 is set to "VF".

Referring to fig. 31, the enable signal EN maintains a low level until time t 1. In the enable signal EN, the low level is a logic level when the main transistor 11 is turned off, and the high level is a logic level when the main transistor 11 is turned on.

At this time, the first to second gate signals G1 to G2 are maintained at a low level (≡vout), and therefore the first to second system transistors 12A to 12B are controlled to be in an off state (see fig. 30A). This state corresponds to the first operation mode of the main transistor 11. On the other hand, the first to second gate signals G1 to G2 are maintained at low levels, and therefore, the first to second system monitor transistors 15A to 15B are controlled to be in an off state together with the first to second system transistors 12A to 12B.

At time t1, the enable signal EN is controlled from a low level to a high level. When the enable signal EN goes high, the first to second gate signals G1 to G2 rise from low level (VOUT) to high level (VG), and both the first to second system transistors 12A to 12B are simultaneously controlled to be in an on state (see fig. 30B).

Thus, the main transistor 11 is in a normal operation (first operation) state. This state corresponds to the second operation mode of the main transistor 11. When the first to second system transistors 12A to 12B are in the on state, the output current IO starts to flow. The output voltage VO rises to around the power supply voltage VB. The main transistor 11 is driven at the total channel ratio RT (=50%) in the normal operation.

On the other hand, when the first to second gate signals G1 to G2 rise from the low level to the high level, both the first to second system monitor transistors 15A to 15B are controlled to be in the on state in association with the first to second system monitor transistors 12A to 12B. Thereby, the monitor transistor 14 is in a normal operation state. When the first to second system monitor transistors 15A to 15B are in the on state, an output monitor current IOM for monitoring the output current IO is generated and output to the overcurrent protection circuit 21.

At time t2, the enable signal EN is controlled from the high level to the low level. When the enable signal EN is at a low level, the first to second gate signals G1 to G2 drop from a high level to a low level. At this time, the main transistor 11 continues to flow the output current IO until all the energy stored in the inductive load L is discharged during the on period. As a result, the output voltage VO drops sharply to a negative voltage lower than the ground voltage GND.

Thereby, the main transistor 11 shifts to the active clamp operation (second operation). When the first to second gate signals G1 to G2 drop from the high level to the low level, the monitor transistor 14 is shifted to the active clamp operation in association with the main transistor 11.

At time t3, when the output voltage VO drops to the channel switching voltage VB-a lower than the power supply voltage VB by a prescribed value a (=vz+vf+vgs 3), the internal node voltage Vx becomes higher than the gate/source voltage Vgs 3. Thus, the MISFET56 is driven to an on state, and the gate/source of the second system transistor 12B is shorted (g2=vout). As a result, the second system transistor 12B is controlled to be in an off state. At this time, the second system monitor transistor 15B is controlled to be in an off state in conjunction with the second system transistor 12B.

On the other hand, at time t4, when the output voltage VO decreases to the lower limit voltage VB-b lower than the power supply voltage VB by the predetermined value b (=vz+vf+vgs 1+vgs 2), the first system transistor 12A is controlled to be in the on state by the active clamp circuit 20. The lower limit voltage VB-b is smaller than the channel switching voltage VB-a (VB-b < VB-a). At this time, the first system monitor transistor 15A is controlled to be in an on state in conjunction with the first system transistor 12A.

Therefore, the second system transistor 12B is completely stopped by driving the MISFET56 before the operation of the active clamp circuit 20. Thus, the main transistor 11 is driven by the first system transistor 12A in a state where the second system transistor 12B is stopped during the active clamp operation (see fig. 30C). This state corresponds to the third operation mode of the main transistor 11.

The main transistor 11 is driven at the first system channel ratio RSA (=25%) during the active clamp operation. That is, the main transistor 11 is controlled such that the channel utilization ratio in the active clamp operation exceeds zero and is smaller than the channel utilization ratio in the normal operation. In other words, the main transistor 11 is controlled to have an on-resistance higher in the active clamp operation than in the normal operation.

Likewise, the second system monitor transistor 15B is completely stopped in conjunction with the second system transistor 12B before the operation of the active clamp circuit 20. Thus, in the active clamp operation, the monitor transistor 14 is driven by the first system monitor transistor 15A in a state where the second system monitor transistor 15B is stopped.

That is, the monitor transistor 14 is controlled such that the channel utilization ratio in the active clamp operation exceeds zero and is smaller than the channel utilization ratio in the normal operation. In other words, the monitor transistor 14 is controlled to have an on-resistance higher than that in the normal operation.

The output current IO is discharged via the first system transistor 12A. Thus, the output voltage VO is limited to be equal to or higher than the lower limit voltage VB-b. That is, the active clamp circuit 20 limits the output voltage VO with reference to the power supply voltage VB, and limits the drain/source voltage Vds (=vb-VOUT) of the main transistor 11 to the clamp voltage Vclp (=b) or less. The active clamp operation is continued until time t5 when the energy stored in the inductive load L is released and the output current IO does not flow.

Thus, according to this control example, the semiconductor device 1A having the on-resistance variable main transistor 11 whose on-resistance can be changed according to the operation state can be provided. That is, according to the semiconductor device 1A, a current can be supplied by the first to second system transistors 12A to 12B in the normal operation (in the first operation).

This can reduce the on-resistance. On the other hand, during the active clamp operation (during the second operation), a current can be supplied to the first system transistor 12A while the second system transistor 12B is stopped. This suppresses a rapid temperature rise caused by the back electromotive force of the inductive load L, and consumes (absorbs) the back electromotive force by the first system transistor 12A.

In other words, according to the semiconductor device 1A, the channel utilization ratio of the main transistor 11 is relatively increased during the normal operation, and the channel utilization ratio of the main transistor 11 is relatively decreased during the active clamp operation. This can reduce the on-resistance. Further, since a rapid temperature rise due to the back electromotive force of the inductive load L during the active clamp operation can be suppressed, the active clamp tolerance Eac can be improved. In this way, according to the semiconductor device 1A, both excellent on-resistance and excellent active clamp resistance Eac can be achieved.

In fig. 30A to 30C, a part or all (in this embodiment, all) of the output monitor current IOM generated by the monitor transistor 14 is input to the overcurrent protection circuit 21 (see also fig. 7). The overcurrent protection circuit 21 generates an overcurrent detection signal SOD when the output monitor current IOM exceeds a predetermined threshold value, and outputs the overcurrent detection signal SOD to the gate drive circuit 19.

The gate drive circuit 19 limits a part or all of the n gate signals G in response to the overcurrent detection signal SOD, and limits one or both of the first to second system currents IS1 to IS2 generated by the first to second system transistors 12A to 12B. Thereby, the overcurrent state of the main transistor 11 is eliminated. When the output monitor current IOM is equal to or less than the predetermined threshold value, the overcurrent protection circuit 21 stops generating the overcurrent detection signal SOD, and the gate drive circuit 19 (main transistor 11) shifts to normal control.

In fig. 30A to 30C, a first temperature measurement signal ST1 generated by the first temperature sensing diode 17A and a second temperature measurement signal ST2 generated by the second temperature sensing diode 17B are input to the overheat protection circuit 22 (see also fig. 7). The overcurrent protection circuit 21 generates a differential signal Δvf from the first temperature measurement signal ST1 and the second temperature measurement signal ST 2. When the differential signal Δvf exceeds the threshold VT, the overcurrent protection circuit 21 generates the overheat detection signal SOH, and outputs the overheat detection signal SOH to the gate drive circuit 19.

The gate drive circuit 19 limits a part or all of the n gate signals G in response to the overheat detection signal SOH, and limits one or both of the first to second system currents IS1 to IS2 generated by the first to second system transistors 12A to 12B. Thereby, a part or all of the main transistor 11 is controlled to be in an off state, while a part or all of the monitor transistor 14 is controlled to be in an off state. Thereby, the overheated state of the output area 7 is eliminated. When the differential signal Δvf becomes equal to or smaller than the threshold VT, the overcurrent protection circuit 21 stops generating the overheat detection signal SOH, and causes the gate drive circuit 19 to shift to the normal control.

As described above, according to the present embodiment, a new semiconductor device 1A having a diode with high versatility can be provided. Specifically, the semiconductor device 1A according to the first embodiment includes: the chip 2, a diode region (temperature measuring region 9 and/or protection region 42), a plurality of diode trench structures 151 (trench structures), and diodes (temperature sensing diode 17 and/or ESD diode 43). The chip 2 has a first main face 3. The diode region is provided on the first main surface 3.

A plurality of diode trench structures 151 are formed on the first main surface 3 at intervals in the diode region. The plurality of diode trench structures 151 each have an electrode structure including a third upper electrode 157 (upper electrode) and a third lower electrode 158 (lower electrode), wherein the third upper electrode 157 (upper electrode) and the third lower electrode 158 (lower electrode) are buried in the trench 84 in the up-down direction via an insulator. The diode has a pn junction portion formed in the surface layer portion of the first main surface 3 in a region between the plurality of diode trench structures 151.

The diode can have a forward voltage characteristic that varies linearly with respect to temperature variation. In addition, the diode has a different structure from the zener diode, and may have the same breakdown voltage characteristics as the zener diode. This enables the use of a diode as the temperature sensing diode 17 or the ESD diode 43. Accordingly, a new semiconductor device 1A having a diode with high versatility can be provided.

The semiconductor device 1A according to the second embodiment includes: chip 2, circuit region 6, protection region 42, electrical circuit, a plurality of diode trench structures 151 (trench structures) and ESD diode 43 (electrostatic breakdown protection diode). The chip 2 has a first main face 3. The circuit region 6 is provided on the first main surface 3. The protection region 42 is provided on the first main surface 3. An electrical circuit is formed in the circuit region 6. A plurality of diode trench structures 151 are formed at intervals on the first main surface 3 in the protection region 42.

The plurality of diode trench structures 151 each have an electrode structure including a third upper electrode 157 (upper electrode) and a third lower electrode 158 (lower electrode), wherein the third upper electrode 157 (upper electrode) and the third lower electrode 158 (lower electrode) are buried in the trench 84 in the up-down direction via an insulator. The ESD diode 43 has a pn junction portion formed in a surface layer portion of the first main surface 3 in a region between the plurality of diode trench structures 151. The ESD diode 43 is electrically connected to the electrical circuit to protect the electrical circuit from static electricity. According to this configuration, a diode formed in the protection region 42 is used as the ESD diode 43.

The semiconductor device 1A according to the third embodiment includes: chip 2, a plurality of temperature measurement areas 9, a plurality of diode trench structures 151 (trench structures), and a plurality of temperature sensing diodes 17. The chip 2 has a first main face 3. The plurality of temperature measurement regions 9 are provided on the first main surface 3 at intervals. A plurality of diode trench structures 151 are formed on the first main surface 3 at intervals in each temperature measurement region 9.

The plurality of diode trench structures 151 each have an electrode structure including a third upper electrode 157 (upper electrode) and a third lower electrode 158 (lower electrode), wherein the third upper electrode 157 (upper electrode) and the third lower electrode 158 (lower electrode) are buried in the trench 84 in the up-down direction via an insulator. Each of the temperature sensing diodes 17 has a pn junction portion formed in the surface layer portion of the first main surface 3 in a region between the plurality of diode trench structures 151 in each of the temperature measurement regions 9. Each temperature sensing diode 17 detects the temperature of each temperature measuring region 9. According to this configuration, a plurality of diodes formed in the plurality of temperature measuring regions 9 are used as the plurality of temperature sensing diodes 17.

The semiconductor device 1A according to the fourth embodiment includes: chip 2, temperature measuring region 9, control region 10, a plurality of diode trench structures 151 (trench structures), temperature sensing diode 17, and control circuit 18. The chip 2 has a first main face 3. The temperature measuring region 9 is provided on the first main surface 3. The control zone 10 is arranged on the first main face 3. A plurality of diode trench structures 151 are formed on the first main surface 3 at intervals in the temperature measuring region 9.

The plurality of diode trench structures 151 each have an electrode structure including a third upper electrode 157 (upper electrode) and a third lower electrode 158 (lower electrode), wherein the third upper electrode 157 (upper electrode) and the third lower electrode 158 (lower electrode) are buried in the trench 84 in the up-down direction via an insulator. The temperature sensing diode 17 has a pn junction portion formed in the surface layer portion of the first main surface 3 in a region between the plurality of diode trench structures 151, and generates a temperature measurement signal for detecting the temperature of the temperature measurement region 9. The control circuit 18 is formed in the control area 10 and is configured to generate an electrical signal based on a temperature measurement signal from the temperature sensing diode 17. According to this configuration, a diode formed in the temperature measuring region 9 is used as the temperature sensing diode 17.

The semiconductor device 1A according to the fifth embodiment includes: the chip 2, the temperature measurement region 9, the protection region 42, the plurality of diode trench structures 151 (first trench structures) on the temperature measurement region 9 side, the plurality of diode trench structures 151 (second trench structures) on the protection region 42 side, the temperature sensing diode 17, and the ESD diode 43 (electrostatic breakdown protection diode). The chip 2 has a first main face 3. The temperature measuring region 9 is provided on the first main surface 3. The protection region 42 is provided in a region different from the temperature measurement region 9 in the first main surface 3.

A plurality of diode trench structures 151 on the temperature measurement region 9 side are formed on the first main surface 3 at intervals in the temperature measurement region 9. The plurality of diode trench structures 151 on the temperature measurement region 9 side have an electrode structure including a third upper electrode 157 (upper electrode) and a third lower electrode 158 (lower electrode), respectively, wherein the third upper electrode 157 (upper electrode) and the third lower electrode 158 (lower electrode) are buried in the trench 84 in the up-down direction via an insulator.

A plurality of diode trench structures 151 on the protection region 42 side are formed on the first main surface 3 at intervals in the protection region 42. The plurality of diode trench structures 151 on the protection region 42 side have an electrode structure including a third upper electrode 157 (upper electrode) and a third lower electrode 158 (lower electrode), respectively, wherein the third upper electrode 157 (upper electrode) and the third lower electrode 158 (lower electrode) are buried in the trench 84 in the up-down direction via an insulator.

The temperature sensing diode 17 has a pn junction (first pn junction) formed in the surface layer of the first main surface 3 in the region between the plurality of diode trench structures 151 on the temperature measurement region 9 side. The ESD diode 43 has a pn junction (second pn junction) formed in the surface layer of the first main surface 3 in the region between the plurality of diode trench structures 151 on the protection region 42 side. According to this configuration, the diode formed in the temperature measuring region 9 is used as the temperature sensing diode 17, and the diode formed in the protection region 42 is used as the ESD diode 43.

The semiconductor device 1A according to the sixth embodiment of the present invention includes, in addition to any one of the first to fifth embodiments, an output region 7 (device region) and a main transistor 11 (functional device) formed in the output region 7. In this case, the diode region (temperature measuring region 9 and/or protection region 42) may also be disposed adjacent to the output region 7.

When the diode region is constituted by the temperature measurement region 9, the temperature sensing diode 17 is formed in the temperature measurement region 9. The temperature sensitive diode 17 is preferably configured to detect the temperature of the output area 7. When the diode region is constituted by the protection region 42, a protection diode is formed in the protection region 42. The protection diode is preferably configured to protect the main transistor 11 from static electricity.

In these cases, the main transistor 11 preferably includes a trench structure 82 (trench gate structure). The trench structure 82 preferably has an electrode structure including an upper electrode 87 (upper gate electrode) and a lower electrode 88 (lower gate electrode), wherein the upper electrode 87 (upper gate electrode) and the lower electrode 88 (lower gate electrode) are buried in the trench 84 (gate trench) in the up-down direction via a gate insulator (upper insulating film 85 and lower insulating film 86). At this time, part or all of the manufacturing process of the diode may be incorporated into the manufacturing process of the main transistor 11.

Fig. 32 is a schematic plan view showing a semiconductor device 1B according to the second embodiment. Fig. 33 is a schematic cross-sectional view of the semiconductor device 1B shown in fig. 32. Fig. 32 and 33 show a case where the main transistor 11 of the 2-system is used as an example of the main transistor 11 of the n-system, but the present invention is not limited thereto.

In the semiconductor device 1A of the first embodiment described above, the output region 7 (main transistor 11), the current detection region 8 (monitor transistor 14), the temperature measurement region 9 (temperature sensing diode 17), the control region 10 (control circuit 18), and the protection region 42 (ESD diode 43) are provided in one chip 2. In contrast, the semiconductor device 1B of the second embodiment does not include the control region 10 (control circuit 18), but includes: an output region 7 (main transistor 11), a current detection region 8 (monitor transistor 14), a temperature measurement region 9 (temperature sensing diode 17), a control region 10 (control circuit 18), and a protection region 42 (ESD diode 43).

The semiconductor device 1B includes: the chip 2, the output region 7 (main transistor 11), the current detection region 8 (monitor transistor 14), the at least one first temperature measurement region 9A (first temperature sensing diode 17A), the at least one first protection region 42A (first ESD diode 43A), the first trench isolation structure 73, the diode isolation structure 131, the first field insulating film 191, the second field insulating film 192, the main surface insulating film 196, the interlayer insulating layer 30, the plurality of via electrodes 201 to 209, n (2 in this embodiment) main gate wirings 31, the at least one main source wiring 33, the at least one monitor source wiring 34, the at least one anode wiring 211, the at least one cathode wiring 212, and the ground wiring 220. The ground wiring 220 is constituted by a wiring layer selectively routed into the interlayer insulating layer 30.

In the present embodiment, the semiconductor device 1B includes one first temperature measurement region 9A (first temperature sensing diode 17A) and a plurality of first protection regions 42A (first ESD diodes 43A). The output region 7 (main transistor 11), the current detection region 8 (monitor transistor 14), the first temperature measurement region 9A (first temperature sensing diode 17A), the first protection region 42A (first ESD diode 43A), and the like are formed separately in the same manner as in the case of the first embodiment.

The semiconductor device 1B includes a plurality of first terminal electrodes 221. In this embodiment, the plurality of first terminal electrodes 221 includes: the drain terminal 36, the source terminal 37, n (2 in this embodiment) first gate terminals 222, a first monitor source terminal 223 for the monitor transistor 14, a first anode terminal 224 for the temperature sensing diode 17, a first cathode terminal 225 for the temperature sensing diode 17, and a first ground terminal 226.

As in the case of the first embodiment, the drain terminal 36 covers the second main surface 4 of the chip 2. The source terminal 37, the first gate terminal 222, the first monitor source terminal 223, the first anode terminal 224, the first cathode terminal 225, and the first ground terminal 226 are configured to be externally connected by a conductive connection member such as a wire (e.g., a bonding wire). The source terminal 37 covers the output region 7 above the first main surface 3 as in the case of the first embodiment.

The n first gate terminals 222 are arranged in a region outside the source terminal 37 in plan view. In the present embodiment, the n first gate terminals 222 are arranged in a region outside the output region 7 in a plan view. The n first gate terminals 222 are electrically connected to the n main gate wirings 31 so as to transmit the n gate signals G from the outside to the n main gate wirings 31 individually.

The first monitor source terminal 223 is disposed in a region outside the source terminal 37 in a plan view. In this embodiment, the first monitor source terminal 223 is disposed in a region outside the output region 7 in a plan view. The first monitor source terminal 223 is electrically connected to the first monitor source FMS of the monitor transistor 14 via the monitor source wiring 34.

The first anode terminal 224 is arranged in a region outside the source terminal 37 in plan view. In this embodiment, the first anode terminal 224 is arranged in a region outside the output region 7 in a plan view. The first anode terminal 224 is electrically connected to the anode region 161 of the temperature sensing diode 17 via the anode wiring 211. The first cathode terminal 225 is disposed in a region outside the source terminal 37 on the first main surface 3 (specifically, on the interlayer insulating layer 30).

In this embodiment, the first cathode terminal 225 is arranged in a region outside the output region 7 in a plan view. The first cathode terminal 225 is electrically connected to the cathode region 162 of the temperature-sensitive diode 17 via the cathode wiring 212. The first ground terminal 226 is arranged in a region outside the source terminal 37 in plan view. In this embodiment, the first ground terminal 226 is arranged in a region outside the output region 7 in a plan view. The first anode terminal 224 is electrically connected to the ground wiring 220. The presence or absence of the first ground terminal 226 and the ground wiring 220 may be arbitrary or may be eliminated.

The plurality of first protection regions 42A may be arranged, for example, at intervals in the first direction X or the second direction Y from the first terminal electrode 221 other than the drain terminal 36 in a plan view, and may face at least one first terminal electrode 221 in the first direction X or the second direction Y. The plurality of first protection regions 42A may also overlap at least 1 first terminal electrode 221 in a plan view.

The plurality of first ESD diodes 43A protect the main transistor 11, the monitor transistor 14, the temperature sensing diode 17, and the like from static electricity that may be generated when wires (e.g., bonding wires) are connected to the plurality of first terminal electrodes 221. The first terminal electrodes 221 connected to the first ESD diodes 43A are arbitrary, and it is not necessarily required that the plurality of first ESD diodes 43A are electrically connected to all the first terminal electrodes 221 except the drain terminal 36. That is, the first ESD diode 43A may be electrically connected to the first terminal electrode 221, which requires protection against static electricity, among the plurality of first terminal electrodes 221.

In this embodiment, the plurality of first ESD diodes 43A are interposed between the plurality of first terminal electrodes 221 and any application terminal of the low potential so that the forward current flows toward the plurality of first terminal electrodes 221 other than the drain terminal 36 and the source terminal 37. The anodes of the first ESD diodes 43A may be electrically connected to the source terminal 37 or to the first ground terminal 226.

As described above, according to the present embodiment, a new semiconductor device 1B having a diode with high versatility can be provided. That is, the semiconductor device 1B includes: the chip 2, a diode region (temperature measuring region 9 and/or protection region 42), a plurality of diode trench structures 151 (trench structures), and diodes (temperature sensing diode 17 and/or ESD diode 43). The chip 2 has a first main face 3. The diode region is provided on the first main surface 3.

The diode may have a forward voltage characteristic that varies linearly with respect to temperature variation. In addition, the diode has a different structure from the zener diode, and may have the same breakdown voltage characteristics as the zener diode. Thus, a diode can be used as the temperature sensing diode 17 or the ESD diode 43. Accordingly, a new semiconductor device 1B having a diode with high versatility can be provided. According to the semiconductor device 1B, since the control region 10 (control circuit 18) is not required, the wiring pattern can be simplified and the manufacturing man-hour can be reduced.

Fig. 34 is a schematic plan view showing a semiconductor device 1C according to the third embodiment. Fig. 35 is a schematic cross-sectional view of the semiconductor device 1C shown in fig. 34. Fig. 34 and 35 show a method of generating the gate signals G1 to G2 of the 2-system, but the method is not limited thereto.

With the semiconductor device 1A of the first embodiment, the output region 7 (main transistor 11), the current detection region 8 (monitor transistor 14), the temperature measurement region 9 (temperature sensing diode 17), the control region 10 (control circuit 18), and the protection region 42 (ESD diode 43) are provided on one chip 2.

In contrast, the semiconductor device 1C of the third embodiment does not include the output region 7 (main transistor 11) and the current detection region 8 (monitor transistor 14), but includes: temperature measuring region 9 (temperature sensing diode 17), control region 10 (control circuit 18) and protection region 42 (ESD diode 43). The semiconductor device 1C is, for example, a semiconductor control device externally connected to the semiconductor device 1B of the second embodiment, and externally controlling the semiconductor device 1B.

The semiconductor device 1C includes: the chip 2, the control region 10 (control circuit 18), at least 1 second temperature measurement region 9B (second temperature sensing diode 17B), at least 1 second protection region 42B (second ESD diode 43B), the first trench isolation structure 73, the diode isolation structure 131, the first field insulating film 191, the second field insulating film 192, the main surface insulating film 196, the interlayer insulating layer 30, the plurality of via electrodes 206 to 208, n (2 in this embodiment) main gate wirings 31, at least 1 monitor source wiring 34, at least 1 anode wiring 211, at least 1 cathode wiring 212, and the ground wiring 227. The ground wiring 227 is constituted by a wiring layer selectively routed into the interlayer insulating layer 30.

In the present embodiment, the semiconductor device 1C includes one second temperature measurement region 9B (second temperature sensing diode 17B) and a plurality of second protection regions 42B (second ESD diodes 43B). The output region 7 (main transistor 11), the current detection region 8 (monitor transistor 14), the second temperature measurement region 9B (second temperature sensing diode 17B), the second protection region 42B (second ESD diode 43B), and the like are formed, respectively, in the same manner as in the case of the first embodiment.

The semiconductor device 1C includes a plurality of second terminal electrodes 228 disposed on the first main surface 3 (specifically, on the interlayer insulating layer 30). The plurality of second terminal electrodes 228 further includes: a drain terminal 36, an input terminal 38, an enable terminal 39, a sense terminal 40, a ground terminal 41, n (2 in this embodiment) second gate terminals 229, a second monitor source terminal 230, a second anode terminal 231, a second cathode terminal 232, and a second ground terminal 233.

As in the case of the first embodiment, the drain terminal 36 covers the second main surface 4 of the chip 2. The input terminal 38, the enable terminal 39, the sense terminal 40, the ground terminal 41, the second gate terminal 229, the second monitor source terminal 230, the second anode terminal 231, the second cathode terminal 232, and the second ground terminal 233 are configured to be externally connected by conductive connection members such as wires (e.g., bonding wires).

The input terminal 38, the enable terminal 39, the sense terminal 40, and the ground terminal 41 are arranged in a row on one end side of the chip 2 with respect to the control region 10 (control circuit 18) in a plan view. That is, in the semiconductor device 1C, the plurality of second terminal electrodes 228 for the control circuit 18 are arranged in a row on one end side of the chip 2 in a plan view.

The second gate terminal 229, the second monitor source terminal 230, the second anode terminal 231, the second cathode terminal 232, and the second ground terminal 233 (hereinafter, simply referred to as "terminal electrodes 228 to 232") are arranged in a row on the other end side of the chip 2 with respect to the control region 10 (control circuit 18) in a plan view.

The terminal electrodes 228 to 232 are provided in correspondence with the terminal electrodes 222 to 226, respectively, so as to be electrically connected to the terminal electrodes 222 to 226 of the semiconductor device 1B, respectively. That is, in the semiconductor device 1C, the plurality of second terminal electrodes 228 for the semiconductor device 1B are arranged in a row on the other end side of the chip 2 so as to face the plurality of second terminal electrodes 228 for the control circuit 18 across the control circuit 18 in a plan view.

The n second gate terminals 229 are electrically connected to the n main gate wirings 31, respectively, and transmit the n gate signals G generated by the control circuit 18 to the n main gate wirings 31, respectively. The second monitor source terminal 230 is electrically connected to the control circuit 18 (the overcurrent protection circuit 21) via the monitor source wiring 34.

The second anode terminal 231 is electrically connected to an arbitrary application end of the high potential (for example, the power supply potential VB) via the anode wiring 211. The second cathode terminal 232 is electrically connected to the overheat protection circuit 22 via the cathode wiring 212. The second ground terminal 233 is electrically connected to the ground wiring 227 (ground terminal 41). The presence or absence of the second ground terminal 233 and the ground wiring 227 may be arbitrary or may be eliminated.

The plurality of second protection regions 42B may be arranged, for example, at intervals in the first direction X or the second direction Y from the plurality of second terminal electrodes 228 other than the drain terminal 36 in plan view, and opposed to at least the second terminal electrodes 228 in the first direction X or the second direction Y. The plurality of second protection regions 42B may overlap at least 1 second terminal electrode 228 other than the drain terminal 36 in a plan view.

The plurality of second ESD diodes 43B protect the control circuit 18, the second temperature sensing diode 17B, and the like from static electricity that may be generated when wires (e.g., bonding wires) are connected to the plurality of second terminal electrodes 228. The second terminal electrode 228 to which the second ESD diode 43B is connected is arbitrary, and it is not necessarily required that the plurality of second ESD diodes 43B are electrically connected to all the second terminal electrodes 228 except the drain terminal 36. That is, the second ESD diode 43B may be electrically connected to the second terminal electrode 228 of the plurality of second terminal electrodes 228, which requires protection against static electricity.

In this embodiment, the plurality of second ESD diodes 43B are interposed between the plurality of second terminal electrodes 228 and any application terminal of the low potential so that the forward current flows toward the drain terminal 36, the ground terminal 41, and the plurality of second terminal electrodes 228 other than the second ground terminal 233.

In addition, at least one second ESD diode 43B is interposed between the active clamp 20 and an arbitrary application terminal of the low potential so that a forward current flows toward the active clamp 20 side. Anodes of the plurality of second ESD diodes 43B may be electrically connected to the ground terminal 41 (second ground terminal 233).

As described above, according to the present embodiment, a new semiconductor device 1C having a diode with high versatility can be provided. That is, the semiconductor device 1C includes: the chip 2, a diode region (temperature measuring region 9 and/or protection region 42), a plurality of diode trench structures 151 (trench structures), and diodes (temperature sensing diode 17 and/or ESD diode 43). The chip 2 has a first main face 3. The diode region is provided on the first main surface 3.

The diode can have a forward voltage characteristic that varies linearly with respect to temperature variation. In addition, the diode has a different structure from the zener diode, and may have the same breakdown voltage characteristics as the zener diode. This enables the use of a diode as the temperature sensing diode 17 or the ESD diode 43.

Accordingly, a new semiconductor device 1C having a diode with high versatility can be provided. According to the semiconductor device 1C, since the output region 7 (the main transistor 11 and the monitor transistor 14) is not required, the wiring pattern can be simplified and the manufacturing man-hour can be reduced.

Fig. 36 is a schematic plan view showing a semiconductor module 1D according to the fourth embodiment. Referring to fig. 36, the semiconductor module 1D includes: the semiconductor device 1B of the second embodiment, the semiconductor device 1C of the third embodiment, and the plurality of conductive connection members 240. That is, the semiconductor module 1D has a structure in which the semiconductor device 1A of the first embodiment is separated into the semiconductor device 1B and the semiconductor device 1C. Hereinafter, the semiconductor device 1B side may be referred to as an "output side", and the semiconductor device 1C side may be referred to as a "control side".

In this embodiment, the plurality of conductive connection members 240 are each constituted by a wire (bonding wire). The plurality of conductive connection parts 240 may include at least one of copper wires, aluminum wires, and gold wires. Of course, the conductive connection member 240 may be a member other than a wire (e.g., a metal plate, a metal clip, etc.). The plurality of conductive connection members 240 electrically connect the plurality of first terminal electrodes 221 of the semiconductor device 1B with the corresponding second terminal electrodes 228 of the semiconductor device 1C in a one-to-one correspondence relationship, respectively.

The semiconductor device 1C generates n gate signals G and outputs the n gate signals G to the n main gate wirings 31 on the control side. n gate signals G are input to n first gate terminals 222 of the semiconductor device 1B via n conductive connection parts 240. Thus, n gate signals G are input to the first gate FG of the main transistor 11 via the main gate wiring 31 on the output side, and the main transistor 11 is controlled to be turned on and off in a predetermined switching pattern. At the same time, the monitor transistor 14 is turned on and off in association with the main transistor 11.

The output current IO generated by the main transistor 11 is output to the source terminal 37 via the main source wiring 33 on the output side, and reaches the first monitor source terminal 223 via the monitor source wiring 34 on the output side. The output monitor current IOM is output to the second monitor source terminal 230 of the control side via the conductive connection part 240. Thereby, the output monitor current IOM is input to the overcurrent protection circuit 21 of the control circuit 18 via the monitor source wiring 34.

The overcurrent protection circuit 21 generates an overcurrent detection signal SOD when the output monitor current IOM exceeds a predetermined threshold value, and outputs the overcurrent detection signal SOD to the gate drive circuit 19. The gate drive circuit 19 generates n gate signals G for controlling the n system transistors 12 in response to the overcurrent detection signal SOD as in the case of the first embodiment. Thereby, the overcurrent state of the output area 7 is eliminated.

On the other hand, the first temperature sensing diode 17A of the semiconductor device 1B generates a first temperature measurement signal ST1 for detecting the first temperature TE1 of the semiconductor device 1B (specifically, the output region 7). The first temperature measurement signal ST1 generated by the first temperature sensing diode 17A is output to the first cathode terminal 225 via the cathode wiring 212 on the output side, and reaches the second cathode terminal 232 of the semiconductor device 1C via the conductive connection member 240. Thus, the first temperature measurement signal ST1 is input to the overheat protection circuit 22 of the control circuit 18 via the cathode wiring 212 on the control side.

On the other hand, the second temperature sensing diode 17B of the semiconductor device 1C generates a second temperature measurement signal ST2 for detecting the second temperature TE2 of the semiconductor device 1C (specifically, the control region 10). The second temperature measurement signal ST2 generated by the second temperature sensing diode 17B is input to the overheat protection circuit 22 of the control circuit 18 via the cathode wiring 212 on the control side. The overheat protection circuit 22 generates a differential signal Δvf from the first temperature measurement signal ST1 and the second temperature measurement signal ST2.

When the differential signal Δvf exceeds the threshold VT, the overcurrent protection circuit 21 generates the overheat detection signal SOH, and outputs the overheat detection signal SOH to the gate drive circuit 19. The gate drive circuit 19 generates n gate signals G for controlling the n system transistors 12 in response to the overheat detection signal SOH as in the case of the first embodiment. Thereby, the overheated state of the output area 7 is eliminated.

As described above, according to the present embodiment, a new semiconductor module 1D having a diode with high versatility can be provided.

The invention can also be implemented in other ways. In the above embodiments, the specific configurations of the main transistor 11 of the 2-system and the monitor transistor 14 of the 2-system are shown. When the n-system main transistors 11 are used, the n-system transistors 12 each include at least one unit cell 81.

In addition, when the m-system (n-system) monitor transistors 14 are employed, the m (n-system) monitor transistors 15 each include at least one unit cell 81. The electrical connection modes of the n system transistors 12 and the m (n) system monitor transistors 15 are adjusted by the plurality of via electrodes 201 to 209, the plurality of main source wirings 33, the plurality of monitor source wirings 34, the plurality of main gate wirings 31, and the like.

In the above embodiments, an example is shown in which the system monitor current ISM of the plurality of system monitor transistors 15 is taken out from the first monitor drain FMD and the first monitor source FMS as the output monitor current IOM. However, the second monitor source SMS of the at least one system monitor transistor 15 may be electrically separated from the first monitor source FMS to form a current path electrically independent from the first monitor source FMS.

That is, in the monitor transistor 14, a configuration may be adopted in which at least 1 system monitor current ISM is taken out separately from the output monitor current IOM. In addition, in the monitor transistor 14, the plurality of system monitor currents ISM may be extracted separately from the output monitor current IOM via a plurality of current paths or the same current path.

For example, when the main transistor 11 of the 3-system including the first to third system transistors 12 is used, the output monitor current IOM may be constituted by the system monitor currents ISM of the first to second system transistors 12, and the system monitor current ISM of the third system transistor 12 may be taken out from a current path different from the output monitor current IOM.

At this time, the control circuit 18 including the current detection circuit for the third system transistor 12 may be used, and a system monitor current ISM different from the output monitor current IOM may be input to the current detection circuit. The control circuit 18 may be configured to control the main transistor 11 based on the system monitor current ISM input to the current detection circuit, or may be configured to control a functional circuit (for example, a state detection circuit such as the overcurrent protection circuit 21 or the overheat protection circuit 22) other than the main transistor 11.

In the above embodiments, an example in which the plurality of system monitor transistors 15 are connected to the corresponding system transistors 12 in a one-to-one correspondence is shown. However, a plurality of first monitor gates FMG may be connected to one first gate FG.

That IS, the monitor transistor 14 may include a plurality of system monitor transistors 15 that generate a plurality of system monitor currents ISM that monitor 1 system current IS. At least 1 or all of the plurality of system monitor currents ISM monitoring 1 system current IS may form part of the output monitor current IOM. At least 1 or all of the plurality of system monitor currents ISM monitoring the 1 system current IS may also constitute a system monitor current ISM different from the output monitor current IOM.

In the above embodiments, an example in which the monitor transistor 14 includes the system monitor transistor 15 electrically connected to the system transistor 12 has been described. However, the monitor transistor 14 may also include at least one system monitor transistor 15 electrically independent of the system transistor 12.

That is, at least one first monitor gate FMG of the monitor transistor 14 may be controlled by at least one monitor gate signal MG electrically independent of the gate signal G. At this time, the monitor transistor 14 may be configured to generate an output monitor current IOM obtained by adding the amount of at least one system monitor current ISM that is electrically independent to the other system monitor currents ISM.

In the above embodiments, an example in which the main transistor 11 and the monitor transistor 14 are connected to one gate driver circuit 19 is shown. However, a structure may be adopted in which the first gate driver circuit 19 is connected to the main transistor 11 and the second gate driver circuit 19 is connected to the monitor transistor 14. At this time, the monitor transistor 14 may be controlled to be in linkage with the main transistor 11, or may be controlled not to be in linkage.

In the above embodiments, an example in which the main transistor 11 and the monitor transistor 14 are connected to one active clamp circuit 20 is shown. However, a configuration may be adopted in which the first active clamp circuit 20 is connected to the main transistor 11, and the second active clamp circuit 20 is connected to the monitor transistor 14.

In the above embodiments, the first lower electrode 88A and the first upper electrode 87A are fixed at the same potential. However, a potential different from that of the first upper electrode 87A may be applied to the first lower electrode 88A. At this time, the first lower electrode 88A may be formed as a source electrode, and a source potential is applied to the first lower electrode 88A. According to this structure, parasitic capacitance between the chip 2 and the first lower electrode 88A can be reduced. This can increase the switching speed of the first unit transistor 13A (main transistor 11).

In the above embodiments, the second lower electrode 88B and the second upper electrode 87B are fixed at the same potential. However, a potential different from that of the second upper electrode 87B may be applied to the second lower electrode 88B. At this time, the second lower electrode 88B may be formed as a source electrode, and a source potential is applied to the second lower electrode 88B. According to this structure, parasitic capacitance between the chip 2 and the second lower electrode 88B can be reduced. This can increase the switching speed of the second unit transistor 13B (main transistor 11).

In the above embodiments, the third lower electrode 158 and the third upper electrode 157 are fixed at the same potential. However, the third upper electrode 157 and the third lower electrode 158 may be fixed to an anode potential, a cathode potential, a ground potential, a floating potential, or other potentials (e.g., source potential) as needed. The floating potential refers to a state not electrically connected to other components (i.e., an electrically floating state). Of course, the third upper electrode 157 and the third lower electrode 158 may be fixed at different potentials.

In each of the above embodiments, when the first upper electrode 87A and the first lower electrode 88A are fixed at the same potential, the first intermediate insulating film 89A may be removed from the first trench structure 82A. At this time, the first lower electrode 88A may be formed integrally with the first upper electrode 87A.

In each of the above embodiments, when the second upper electrode 87B and the second lower electrode 88B are fixed at the same potential, the second intermediate insulating film 89B may be removed from the second trench structure 82B. At this time, the second lower electrode 88B may be formed integrally with the second upper electrode 87B.

In each of the above embodiments, when the third upper electrode 157 and the third lower electrode 158 are fixed at the same potential, the third intermediate insulating film 159 may be removed from the diode trench structure 151. In this case, the third lower electrode 158 may be integrally formed with the third upper electrode 157.

In the above embodiments, the description has been given of an example in which the circuit region 6 includes the output region 7, the current detection region 8, the temperature measurement region 9, the control region 10, and the protection region 42. However, the temperature measuring region 9 and the protection region 42 may also be regarded as regions separated from the circuit region 6. That is, the temperature measuring region 9 may be regarded as a region provided so as to detect the temperature of any portion of the circuit region 6, and the protection region 42 may be regarded as a region provided so as to protect any portion of the circuit region 6.

In the above embodiments, the examples were shown in which the first conductivity type was p-type and the second conductivity type was n-type, but the first conductivity type may be n-type and the second conductivity type may be p-type. The specific structure in this case is obtained by replacing the n-type region with the p-type region and replacing the p-type region with the n-type region in the above description and the drawings. In the above embodiments, the first direction X and the second direction Y are determined by the direction in which the first to fourth side surfaces 5A to 5D of the chip 2 extend, but the first direction X and the second direction Y may be any directions as long as they maintain a relationship of intersecting each other (specifically, orthogonal to each other).

Hereinafter, examples of features extracted from the present specification and drawings are shown. In the following, a new semiconductor device, a semiconductor control device, and a semiconductor module having a diode with high versatility can be provided. Hereinafter, the letter numerals in parentheses denote the corresponding components and the like in the above-described embodiments, but are not meant to limit the scope of each item (Clause) to the embodiments.

In the following items, "semiconductor device", "semiconductor control device", and "semiconductor module" may be replaced with "electric circuit" or "semiconductor circuit". At this time, a new "electric circuit" or "semiconductor circuit" can be provided, which has a diode having high versatility.

[A1] A semiconductor device (1A, 1B, 1C) includes: a chip (2) having a main surface (3); diode regions (9, 42) provided on the main surface (3); a plurality of trench structures (151) which are formed on the main surface (3) at intervals in the diode regions (9, 42) and each have an electrode structure including an upper electrode (157) and a lower electrode (158), wherein the upper electrode (157) and the lower electrode (158) are buried in the trench (154) in the up-down direction via insulators (155, 156); and diodes (17, 43) having pn junction portions formed in the surface layer portion of the main surface (3) in regions between the plurality of trench structures (151).

[A2] The semiconductor device (1A, 1B, 1C) according to A1, wherein the semiconductor device (1A, 1B, 1C) further comprises: a body region (150) of a first conductivity type (p-type) formed in a surface layer portion of the main surface (3) in the diode region (9, 42), a plurality of trench structures (151) formed in the main surface (3) so as to penetrate the body region (150), the diode (17, 43) including: a first polarity region (161) of a first conductivity type (p-type) formed in the body region (150); a second polarity region (162) of a second conductivity type (n-type) formed in the body region (150) so as to form the pn junction with the first polarity region (161).

[A3] The semiconductor device (1A, 1B, 1C) according to A2, wherein the first polarity region (161) includes: a high concentration region (161 a) having a higher impurity concentration than the body region (150); -a low concentration region (161 b, 161 c) having a lower impurity concentration than the high concentration region (161 a), the second polarity region (162) forming the pn junction with the low concentration region (161 b, 161 c) of the first polarity region (161).

[A4] The semiconductor device (1A, 1B, 1C) according to A3, wherein the low concentration region (161B, 161C) is constituted by a portion of the body region (150).

[A5] The semiconductor device (1A, 1B, 1C) according to any one of A2 to A4, wherein the upper electrode (157) of the plurality of trench structures (151) is buried in the main surface (3) side with respect to the bottom of the body region (150), and the lower electrode (158) of the plurality of trench structures (151) is buried in the bottom wall side of the trench (154) with respect to the bottom of the body region (150).

[A6] The semiconductor device (1A, 1B, 1C) according to any one of A2 to A5, wherein the first polarity region (161) and one or both of the upper electrodes (157) and the lower electrodes (158) of the plurality of trench structures (151) are fixed at the same potential.

[A7] The semiconductor device (1A, 1B, 1C) according to any one of A1 to A6, wherein the insulator (155, 156) includes: an upper insulating film (155) that covers the upper wall surface of the trench (154) with a first thickness (T1); and a lower insulating film (156) covering a lower wall surface of the trench (154) with a second thickness (T2) exceeding the first thickness (T1), wherein the upper electrode (157) is buried in the upper wall surface side of the trench (154) through the upper insulating film (155), and wherein the lower electrode (158) is buried in the lower wall surface side of the trench (154) through the lower insulating film (156).

[A8] The semiconductor device (1A, 1B, 1C) according to any one of A1 to A7, wherein the semiconductor device (1A, 1B, 1C) further comprises: and a separation structure (131, 132, 133) formed on the main surface (3) so as to electrically separate the diode region (9, 42) from the other region.

[A9] The semiconductor device (1A, 1B, 1C) according to A8, wherein the separation structure (131, 132, 133) includes: and separation electrodes (136, 146) embedded in the separation grooves (134, 144) through separation insulators (135, 145).

[A10] The semiconductor device (1A, 1B, 1C) according to any one of A1 to A9, wherein the diode region (9, 42) is a temperature measurement region (9), and the diode (17, 43) is a temperature sensing diode (17).

[A11] The semiconductor device (1A, 1B, 1C) according to a10, wherein the temperature sensitive diode (17) has a temperature characteristic in which a forward voltage linearly changes with respect to a temperature change.

[A12] The semiconductor device (1A, 1B, 1C) according to a10 or a11, wherein the semiconductor device (1A, 1B, 1C) further comprises: a device region (7) provided on the main surface (3); and a functional device (11) formed in the device region (7), the temperature measuring region (9) being disposed adjacent to the device region (7) in a plan view, the temperature sensing diode (17) detecting a temperature of the device region (7).

[A13] The semiconductor device (1A, 1B, 1C) according to a12, wherein the temperature measuring region (9) is arranged in a region surrounded by the device region (7) in a plan view.

[A14] The semiconductor device (1A, 1B, 1C) according to a12 or a13, wherein the functional device (11) includes a trench gate structure (82) having an electrode structure including an upper gate electrode (87) and a lower gate electrode (88) buried in a vertical direction within the gate trench (84) via gate insulators (85, 86).

[A15] The semiconductor device (1A, 1B, 1C) according to any one of a12 to a14, wherein the functional device (11) includes: and a plurality of gate-divided transistors (11) which are each formed on the main surface (3) so as to be individually controllable, and which selectively control the plurality of gate-divided transistors (12) to generate a single output signal (IO).

[A16] The semiconductor device (1A, 1B, 1C) according to any one of A1 to A9, wherein the semiconductor device (1A, 1B, 1C) further comprises: a device region (7) provided on the main surface (3); and a functional device (11) formed in the device region (7), wherein the diode region (9, 42) is a protection region (42), and the diode (17, 43) is an electrostatic breakdown protection diode (43).

[A17] The semiconductor device (1A, 1B, 1C) according to a16, wherein the semiconductor device (1A, 1B, 1C) further comprises: and terminal electrodes (35, 221, 228) disposed on the main surface (3) so as to be electrically connected to the functional device (11), wherein the electrostatic breakdown protection diode (43) is electrically connected to the terminal electrodes (35, 221, 228).

[A18] A semiconductor device (1A, 1B, 1C) includes: a chip (2) having a main surface (3); a temperature measurement region (9) provided on the main surface (3); a protection region (42) provided in a region of the main surface (3) different from the temperature measurement region (9); a plurality of first trench structures (151) formed on the main surface (3) at intervals in the temperature measurement region (9) and each having an electrode structure including a first upper electrode (157) and a first lower electrode (158), wherein the first upper electrode (157) and the first lower electrode (158) are buried in the first trench (154) in the up-down direction via first insulators (155, 156); a temperature-sensitive diode (17) having a first pn junction portion formed in a surface layer portion of the main surface (3) in a region between the plurality of first trench structures (151); a plurality of second trench structures (151) formed on the main surface (3) at intervals in the protection region (42) and each having an electrode structure including a second upper electrode (157) and a second lower electrode (158), wherein the second upper electrode (157) and the second lower electrode (158) are buried in the second trench (154) in the up-down direction via second insulators (155, 156); and an electrostatic breakdown protection diode (43) having a second pn junction portion formed in a surface layer portion of the main surface (3) in a region between the plurality of second trench structures (151).

[A19] The semiconductor device (1A, 1B, 1C) according to any one of A1 to a18, wherein the semiconductor device (1A, 1B, 1C) further comprises: a control region (10) provided on the main surface (3); and a control circuit (18) formed in the control region (10).

[A20] A semiconductor module (1D), comprising: a semiconductor device (1B) according to any one of A1 to a 18; and a control device (1C) configured to be electrically connected to the semiconductor device (1B) and to control the semiconductor device (1B).

[B1] A semiconductor device (1A, 1B, 1C) includes: a chip (2) having a main surface (3); a circuit region (6) provided on the main surface (3); a protection region (42) provided on the main surface (3); an electrical circuit (11, 18) formed in the circuit region (6); a plurality of trench structures (151) which are formed on the main surface (3) at intervals in the protection region (42) and each have an electrode structure including an upper electrode (157) and a lower electrode (158), wherein the upper electrode (157) and the lower electrode (158) are buried in the trench (154) in the up-down direction via insulators (155, 156); and an electrostatic breakdown protection diode (43) which has a pn junction formed in a surface layer portion of the main surface (3) in a region between the plurality of trench structures (151), and which is electrically connected to the electrical circuits (11, 18).

[B2] The semiconductor device (1A, 1B, 1C) according to B1, wherein the semiconductor device (1A, 1B, 1C) further comprises: and terminal electrodes (35, 221, 228) disposed on the main surface (3) so as to be electrically connected to the electric circuits (11, 18), wherein the electrostatic breakdown protection diode (43) is electrically connected to the terminal electrodes (35, 221, 228).

[B3] The semiconductor device (1A, 1B, 1C) according to B2, wherein the electrostatic breakdown protection diode (43) is arranged at a position close to the terminal electrode (35, 221, 228) in a plan view.

[B4] The semiconductor device (1A, 1B, 1C) according to B2 or B3, wherein the electrostatic breakdown protection diode (43) is arranged adjacent to the terminal electrode (35, 221, 228) in a plan view or overlapping with the terminal electrode (35, 221, 228) in a plan view.

[B5] The semiconductor device (1A, 1B, 1C) according to any one of B2 to B4, wherein the electrostatic breakdown protection diode (43) has: an anode electrically connected to a reference potential or a ground potential; and a cathode electrically connected to the terminal electrode (35, 221, 228).

[B6] The semiconductor device (1A, 1B, 1C) according to any one of B2 to B5, wherein the electrostatic breakdown protection diode (43) has an area smaller than an area of the terminal electrode (35, 221, 228) in a plan view.

[B7] The semiconductor device (1A, 1B, 1C) according to any one of B2 to B6, wherein the semiconductor device (1A, 1B, 1C) includes a plurality of the terminal electrodes (35, 221, 228), and the plurality of the electrostatic breakdown protection diodes (43) are electrically connected to the plurality of the terminal electrodes (35, 221, 228), respectively.

[B8] The semiconductor device (1A, 1B, 1C) according to any one of B1 to B7, wherein the semiconductor device (1A, 1B, 1C) further comprises: a body region (150) of a first conductivity type (p-type) formed in a surface layer portion of the main surface (3) in the protection region (42), the plurality of trench structures (151) being formed in the main surface (3) so as to penetrate the body region (150), the electrostatic breakdown protection diode (43) including: a first polarity region (161) of a first conductivity type (p-type) formed in the body region (150); and a second polarity region (162) of a second conductivity type (n-type) formed in the body region (150) so as to form the pn junction with the first polarity region (161).

[B9] The semiconductor device (1A, 1B, 1C) according to B8, wherein the first polarity region (161) includes: a high concentration region (161 a) having a higher impurity concentration than the body region (150); and low concentration regions (161 b, 161 c) having an impurity concentration lower than that of the high concentration region (161 a), the second polarity region (162) forming the pn junction with the low concentration regions (161 b, 161 c) of the first polarity region (161).

[B10] The semiconductor device (1A, 1B, 1C) according to B9, wherein the low concentration region (161B, 161C) is constituted by a portion of the body region (150).

[B11] The semiconductor device (1A, 1B, 1C) according to B9 or B10, wherein the high concentration region (161A) is formed on the main surface (3) side at a distance from the bottom of the body region (150), and the second polarity region (162) is formed on the main surface (3) side at a distance from the bottom of the body region (150).

[B12] The semiconductor device (1A, 1B, 1C) according to any one of B8 to B11, wherein the upper electrode (157) of the plurality of trench structures (151) is buried in the main surface (3) side with respect to the bottom of the body region (150), and the lower electrode (158) of the plurality of trench structures (151) is buried in the bottom wall side of the trench (154) with respect to the bottom of the body region (150).

[B13] The semiconductor device (1A, 1B, 1C) according to any one of B8 to B12, wherein the first polarity region (161) and one or both of the lower electrode (158) and the upper electrode (157) of the plurality of trench structures (151) are fixed at the same potential.

[B14] The semiconductor device (1A, 1B, 1C) according to any one of B1 to B13, wherein the insulator (155, 156) includes: an upper insulating film (155) that covers the upper wall surface of the trench (154) with a first thickness (T1); and a lower insulating film (156) covering a lower wall surface of the trench (154) with a second thickness (T2) exceeding the first thickness (T1), wherein the lower electrode (158) is buried on the lower wall surface side of the trench (154) through the lower insulating film (156), and the upper electrode (157) is buried on the upper wall surface side of the trench (154) through the upper insulating film (155).

[B15] The semiconductor device (1A, 1B, 1C) according to any one of B1 to B14, wherein the semiconductor device (1A, 1B, 1C) further comprises: and a separation structure (131, 132, 133) formed on the main surface (3) so as to electrically separate the protection region (42) from other regions.

[B16] The semiconductor device (1A, 1B, 1C) according to B15, wherein the separation structure (131, 132, 133) includes: and separation electrodes (136, 146) embedded in the separation grooves (134, 144) through separation insulators (135, 145).

[B17] The semiconductor device (1A, 1B, 1C) according to any one of B1 to B16, wherein the semiconductor device (1A, 1B, 1C) further comprises: a transistor region (7, 8) included in the circuit region (6); and transistors (11, 14) which are formed on the main surface (3) in the transistor regions (7, 8) and which have a trench gate structure (82) having an electrode structure including an upper gate electrode (87) and a lower gate electrode (88) buried in the vertical direction in the gate trench (84) through gate insulators (85, 86).

[B18] The semiconductor device (1A, 1B, 1C) according to B17, wherein the transistors (11, 14) are gate-divided transistors (11, 14), the gate-divided transistors (11, 14) including a plurality of system transistors (12, 15) formed on the main surface (3) so as to be individually controllable, the gate-divided transistors (11, 14) generating a single output signal (IO, IOM) by selectively controlling the plurality of system transistors (12, 15).

[B19] The semiconductor device (1A, 1B, 1C) according to B17 or B18, wherein the semiconductor device (1A, 1B, 1C) further comprises: -a control zone (10) comprised in said circuit zone (6); and a control circuit (18) which is formed in the control region (10) so as to be electrically connected to the transistors (11, 14), and which is configured to generate a control signal (G, MG) for controlling the transistors (11, 14).

[B20] A semiconductor module (1D), comprising: the semiconductor device (1A, 1B, 1C) according to any one of B1 to B18; and a control device (1A, 1B, 1C) electrically connected to the semiconductor device (1A, 1B, 1C) and including a control circuit (18), the control circuit (18) being configured to generate a control signal (G, MG) for controlling the electrical circuit (11, 18).

[C1] A semiconductor device (1A, 1B, 1C) includes: a chip (2) having a main surface (3); a plurality of temperature measurement areas (9) provided on the main surface (3) at intervals; a plurality of trench structures (151) formed on the main surface (3) at intervals in each of the temperature measurement regions (9), each of the trench structures including an upper electrode (157) and a lower electrode (158), wherein the upper electrode (157) and the lower electrode (158) are buried in the trench (154) in the up-down direction via insulators (155, 156); and a plurality of temperature sensing diodes (17) each having a pn junction formed in a surface layer portion of the main surface (3) in a region between the plurality of trench structures (151) in the corresponding temperature measuring region (9), and detecting the temperature of the corresponding temperature measuring region (9).

[C2] The semiconductor device (1A, 1B, 1C) according to C1, wherein the plurality of temperature sensing diodes (17) each have a temperature characteristic in which a forward voltage linearly changes with respect to a temperature change.

[C3] The semiconductor device (1A, 1B, 1C) according to C2, wherein the plurality of temperature-sensitive diodes (17) each have a temperature characteristic in which a forward voltage linearly decreases with an increase in temperature.

[C4] The semiconductor device (1A, 1B, 1C) according to any one of C1 to C3, wherein the semiconductor device (1A, 1B, 1C) further comprises: a plurality of body regions (150) of the first conductivity type (p-type) formed on the surface layer portion of the main surface (3) in the plurality of temperature measurement regions (9), respectively, a plurality of trench structures (151) formed on the main surface (3) in each of the temperature measurement regions (9) so as to penetrate each of the body regions (150), respectively, and a plurality of temperature sensing diodes (17) formed in the corresponding temperature measurement regions (9), respectively, each comprising: a first polarity region (161) of a first conductivity type (p-type) formed in each of the body regions (150), and a second polarity region (162) of a second conductivity type (n-type) formed in each of the body regions (150) so as to form the pn junction with the first polarity region (161).

[C5] The semiconductor device (1A, 1B, 1C) according to C4, wherein the first polarity region (161) comprises: a high concentration region (161 a) having a higher impurity concentration than the body region (150); and low concentration regions (161 b, 161 c) having an impurity concentration lower than that of the high concentration region (161 a), the second polarity region (162) forming the pn junction with the low concentration regions (161 b, 161 c) of the first polarity region (161).

[C6] The semiconductor device (1A, 1B, 1C) according to C5, wherein the low concentration region (161B, 161C) is constituted by a portion of the body region (150).

[C7] The semiconductor device (1A, 1B, 1C) according to any one of C1 to C6, wherein the semiconductor device (1A, 1B, 1C) further comprises: a device region (7, 8) provided on the main surface (3); a control region (10) provided on the main surface (3); transistors (11, 14) formed in the device regions (7, 8); and a control circuit (18) which is formed in the control region (10) so as to be electrically connected to the plurality of temperature sensing diodes (17) and the transistors (11, 14), and which controls the transistors (11, 14) in accordance with electric signals (ST 1, ST 2) from the plurality of temperature sensing diodes (17).

[C8] The semiconductor device (1A, 1B, 1C) according to C7, wherein the control circuit (18) is configured to limit the operation of the transistors (11, 14) when the difference value of the electrical signals (ST 1, ST 2) from the plurality of temperature sensing diodes (17) exceeds a threshold value.

[C9] The semiconductor device (1A, 1B, 1C) according to C7 or C8, wherein the plurality of temperature measuring regions (9) comprises: a first temperature measurement region (9A) which is disposed at a position closer to the device region (7) than the control region (10); and a second temperature measurement region (9B) which is disposed closer to the control region (10) than the device region (7).

[C10] The semiconductor device (1A, 1B, 1C) according to C9, wherein the first temperature measuring region (9A) is adjacent to the device region (7) and the second temperature measuring region (9B) is adjacent to the control region (10).

[C11] The semiconductor device (1A, 1B, 1C) according to C9 or C10, wherein the first temperature measuring region (9A) is arranged inside the device region (7) in a plan view, and the second temperature measuring region (9B) is arranged inside the control region (10) in a plan view.

[C12] The semiconductor device (1A, 1B, 1C) according to any one of claims C7 to C11, wherein the transistor (11, 14) includes a trench gate structure (82), the trench gate structure (82) having an electrode structure including an upper gate electrode (87) and a lower gate electrode (88), wherein the upper gate electrode (87) and the lower gate electrode (88) are buried in a vertical direction within the gate trench (84) via gate insulators (85, 86).

[C13] The semiconductor device (1A, 1B, 1C) according to any one of C7 to C12, wherein the transistor (11, 14) includes: and gate-divided transistors (11, 14) each including a plurality of system transistors (12, 15) formed on the main surface (3) so as to be individually controllable, wherein the gate-divided transistors (11, 14) selectively control the plurality of system transistors (12, 15) to generate a single output signal (IO, IOM).

[C14] The semiconductor device (1A, 1B, 1C) according to C13, wherein the gate-divided transistors (11, 14) are configured such that on-resistance changes by individual control of the plurality of system transistors (12, 15).

[C15] A semiconductor control device (1C), comprising: a chip (2) having a main surface (3); a temperature measurement region (9) provided on the main surface (3); a control region (10) provided on the main surface (3); a plurality of trench structures (151) which are formed on the main surface (3) at intervals in the temperature measurement region (9) and each have an electrode structure including an upper electrode (157) and a lower electrode (158), wherein the upper electrode (157) and the lower electrode (158) are buried in the trench (154) in the up-down direction via insulators (155, 156); a temperature sensing diode (17) which has a pn junction formed in a surface layer portion of the main surface (3) in a region between a plurality of trench structures (151) and generates an internal temperature measurement signal (ST 2) for detecting the temperature of the temperature measurement region (9); and a control circuit (18) configured to generate an electrical signal from the internal temperature measurement signal (ST 2) from the temperature sensing diode (17).

[C16] The semiconductor control device (1C) according to C15, wherein the temperature sensitive diode (17) has a temperature characteristic in which a forward voltage linearly changes with respect to a temperature change.

[C17] The semiconductor control device (1C) according to C15 or C16, the temperature sensitive diode (17) has a temperature characteristic in which a forward voltage linearly decreases with an increase in temperature.

[C18] The semiconductor control device (1C) according to any one of C15 to C17, wherein the semiconductor control device (1C) further comprises: a body region (150) of a first conductivity type (p-type) formed in a surface layer portion of the main surface (3) in the temperature measurement region (9), the plurality of trench structures (151) being formed in the main surface (3) so as to penetrate the body region (150), the temperature sensing diodes (17) each including: a first polarity region (161) of a first conductivity type (p-type) formed in the body region (150), and a second polarity region (162) of a second conductivity type (n-type) formed in the body region (150) so as to form the pn junction with the first polarity region (161).

[C19] The semiconductor control device (1C) according to C18, wherein the first polarity region (161) comprises: a high concentration region (161 a) having a higher impurity concentration than the body region (150); and low concentration regions (161 b, 161 c) having an impurity concentration lower than that of the high concentration region (161 a), the second polarity region (162) forming the pn junction with the low concentration regions (161 b, 161 c) of the first polarity region (161).

[C20] The semiconductor control device (1C) according to C19, wherein the low concentration region (161 b, 161C) is constituted by a portion of the body region (150).

[C21] The semiconductor control device (1C) according to any one of C15 to C20, wherein the control circuit (18) is configured to input an external temperature measurement signal (ST 1) indicating the temperature of the semiconductor device (1A, 1B, 1C) from the semiconductor device (1A, 1B, 1C) by being externally connected to the semiconductor device (1A, 1B, 1C) as a control target, and the control circuit (18) is configured to generate the electrical signal from the internal temperature measurement signal (ST 2) and the external temperature measurement signal (ST 1).

[D1] A semiconductor module (1D) comprising a semiconductor device (1B) and a semiconductor control device (1C) electrically connected to the semiconductor device (1C), the semiconductor device (1B) comprising: a first chip (2); a first temperature measurement region (9A) provided on the first chip (2); a plurality of first trench structures (151) which are formed at intervals in the first temperature measurement region (9A) and each have an electrode structure including a first upper electrode (157) and a first lower electrode (158), wherein the first upper electrode (157) and the first lower electrode (158) are buried in the first trench (154) in the up-down direction via insulators (155, 156); and first temperature sensing diodes (17A) each having a first pn junction formed in a surface layer portion of the first chip (2) in regions between the plurality of first trench structures (151) and generating a first temperature measurement signal (ST 1) indicating a temperature of the first temperature measurement region (9A), wherein the semiconductor control device (1C) includes: a second chip (2); a second temperature measurement region (9B) provided on the second chip (2); a control region (10) provided on the second chip (2); a plurality of second trench structures (151) formed on the second chip (2) at intervals in the second temperature measurement region (9B) and each having an electrode structure including a second upper electrode (157) and a second lower electrode (158), wherein the second upper electrode (157) and the second lower electrode (158) are buried in the second trench (154) in the up-down direction via insulators (155, 156); a second temperature sensing diode (17B) having a second pn junction portion formed in a surface layer portion of the second chip (2) in a region between the plurality of second trench structures (151), and generating a second temperature measurement signal (ST 2) indicating a temperature of the second temperature measurement region (9B); and a control circuit (18) which is formed in the control region (10) and generates an electrical signal for controlling the semiconductor device (1B) in accordance with the first temperature measurement signal (ST 1) and the second temperature measurement signal (ST 2).

[D2] The semiconductor module (1D) according to D1, wherein the first temperature-sensitive diode (17A) has a temperature characteristic in which a forward voltage linearly changes with respect to a temperature change, and the second temperature-sensitive diode (17B) has a temperature characteristic in which a forward voltage linearly changes with respect to a temperature change.

[D3] The semiconductor module (1D) according to D1 or D2, wherein the first temperature-sensitive diode (17A) has a temperature characteristic in which a forward voltage linearly decreases with an increase in temperature, and the second temperature-sensitive diode (17B) has a temperature characteristic in which a forward voltage linearly decreases with an increase in temperature.

[D4] The semiconductor module (1D) according to any one of claims D1 to D3, wherein the control circuit (18) is configured to limit the operation of the semiconductor device (1B) when the difference value between the first temperature measurement signal (ST 1) and the second temperature measurement signal (ST 2) exceeds a threshold value.

[D5] The semiconductor module (1D) according to any one of D1 to D4, wherein the semiconductor module (1D) further comprises: a device region (7) provided on the first chip (2); and a functional device (11, 12) formed in the device region (7), the control circuit generating the electrical signal that controls the functional device (11, 12).

[D6] The semiconductor module (1D) according to any one of claims D1 to D5, wherein the functional device (11, 12) is a transistor (11, 14) including a trench gate structure (82), the trench gate structure (82) having an electrode structure including an upper gate electrode (87) and a lower gate electrode (88), wherein the upper gate electrode (87) and the lower gate electrode (88) are buried in a vertical direction within the gate trench (84) via a gate insulator (85, 86).

[D7] The semiconductor module (1D) according to D6, wherein the transistor (11, 14) comprises: and gate-dividing transistors (11, 14) which include a plurality of system transistors (12, 15) formed on the first chip (2) so as to be individually controllable, and which selectively control the plurality of system transistors (12, 15) to generate a single output signal (IO, IOM).

[D8] The semiconductor module (1D) according to D7, wherein the gate-dividing transistors (11, 14) are configured such that on-resistances are changed by individual control of the plurality of system transistors (12, 15).

[E1] A semiconductor device (1A, 1B, 1C) includes: a chip (2) having a main surface (3); a current detection region (8) provided on the main surface (3); diode regions (9, 42) provided on the main surface (3); a current monitoring device (14) formed in the current detection region (8) so as to generate a monitoring current (IOM); a plurality of trench structures (151) which are formed in the diode regions (9, 42) at intervals and each have an electrode structure including an upper electrode (157) and a lower electrode (158), wherein the upper electrode (157) and the lower electrode (158) are buried in the trench (154) in the up-down direction via insulators (155, 156); and diodes (17, 43) each having a pn junction portion formed in a surface layer portion of the main surface (3) in a region between the plurality of trench structures (151) formed in the diode regions (9, 42) at intervals.

[E2] The semiconductor device (1A, 1B, 1C) according to E1, wherein the current monitoring means (14) is a plurality of monitoring trench structures (82) formed in the current detection region (8), and includes an upper monitoring electrode (87) and a lower monitoring electrode (88) buried in the up-down direction within the monitoring trench (84) via monitoring insulators (85, 86).

[E3] The semiconductor device (1A, 1B, 1C) according to E1 or E2, wherein the diode region (9, 42) is a temperature measuring region (9), and the diode (17, 43) is a temperature sensing diode (17) generating a temperature measuring signal representing a temperature of the temperature measuring region (9).

[E4] The semiconductor device (1A, 1B, 1C) according to E1 or E2, wherein the diode region (9, 42) is a protection region (42), and the diode (17, 43) is an electrostatic breakdown protection diode (43).

[E5] The semiconductor device (1A, 1B, 1C) according to any one of E1 to E4, wherein the semiconductor device (1A, 1B, 1C) further comprises: a control region (10) provided on the main surface (3); and a control circuit (18) formed in the control region (10) so as to be electrically connected to the current monitoring device (14) and the diodes (17, 43).

The embodiments have been described in detail, but these are only specific examples used for the purpose of clarifying the technical content, and the present invention should not be construed as being limited to these specific examples, but the scope of the present invention is defined by the appended claims.

Symbol description

1A semiconductor device

1B semiconductor device

1C semiconductor device (semiconductor control device)

1D semiconductor module

2. Chip

3. A first main surface

6. Circuit area

7. Output area

8. Current detection area

9 temperature measuring area (diode area)

9A first temperature measuring region

9B second temperature measuring region

10. Control area

11 grid split transistor (functional device)

14 current monitoring device (functional device)

15. System transistor

17. Temperature sensing diode

17A first temperature sensing diode

17B second temperature sensing diode

18. Control circuit

35. Terminal electrode

42. Protection area (diode area)

43. Electrostatic damage protection diode

82. First trench structure

84. First groove

85. Upper insulating film

86. Lower insulating film

87. Upper electrode

88. Lower electrode

131. Diode separating structure

132. Second trench separation structure

133. Third groove separating structure

134. Second separation groove

135. Second separation insulator

136. Second separation electrode

144. Third separation groove

145. Third separation insulator

146. Third separation electrode

150. Second body area

151. Diode trench structure

154. Third groove

155. Third upper insulating film

156. Third lower insulating film

157. Third upper electrode

158. Third lower electrode

161. Anode region (first polar region)

161a high concentration region

161b low concentration region

161c low concentration region

162. Cathode region (second polar region)

221. Terminal electrode

228. Terminal electrode

G gate control signal

MG monitors gate control signals

IO output current (output signal)

IOM output monitor current (output signal)

ST1 first temperature measurement signal

ST2 second temperature measurement signal

T1 first thickness

T2 second thickness.

Claims

1. A semiconductor device, comprising:

a chip having a main surface;

a diode region provided on the main surface;

a plurality of trench structures formed on the main surface at intervals in the diode region, each of the trench structures including an upper electrode and a lower electrode, the upper electrode and the lower electrode being buried in the trench in the up-down direction via an insulator; and

and a diode having a pn junction portion formed in a surface layer portion of the main surface in a region between the plurality of trench structures.

2. The semiconductor device according to claim 1, wherein,

the semiconductor device further includes: a body region of a first conductivity type formed in a surface layer portion of the main surface in the diode region,

a plurality of the trench structures are formed in the main surface so as to penetrate the body region,

the diode includes: a first polarity region of a first conductivity type formed in the body region; a second polarity region of a second conductivity type formed in the body region so as to form the pn junction with the first polarity region.

3. The semiconductor device according to claim 2, wherein,

the first polarity region comprises: a high concentration region having a higher impurity concentration than the body region; a low concentration region having a lower impurity concentration than the high concentration region,

the second polarity region forms the pn junction with the low concentration region of the first polarity region.

4. The semiconductor device according to claim 3, wherein,

the low concentration region is constituted by a portion of the body region.

5. The semiconductor device according to any one of claims 2 to 4, wherein,

the upper electrodes of the trench structures are buried in the main surface side with respect to the bottom of the body region,

the bottom electrode of the trench structure is buried in a bottom wall side of the trench with respect to a bottom of the body region.

6. The semiconductor device according to any one of claims 2 to 5, wherein,

the first polarity region is fixed at the same potential as one or both of the upper electrodes and the lower electrodes of the plurality of trench structures.

7. The semiconductor device according to any one of claims 1 to 6, wherein,

the insulator comprises: an upper insulating film covering an upper wall surface of the trench with a first thickness; a lower insulating film covering a lower wall surface of the trench with a second thickness exceeding the first thickness,

The upper electrode is buried on the upper wall surface side of the trench via the upper insulating film,

the lower electrode is buried in the lower wall surface side of the trench with the lower insulating film interposed therebetween.

8. The semiconductor device according to any one of claims 1 to 7, wherein,

the semiconductor device further includes: and a separation structure formed on the main surface so as to electrically separate the diode region from the other region.

9. The semiconductor device according to claim 8, wherein,

the separation structure comprises: and a separation electrode buried in the separation trench via a separation insulator.

10. The semiconductor device according to any one of claims 1 to 9, wherein,

the diode region is a temperature measuring region,

the diode is a temperature sensitive diode.

11. The semiconductor device according to claim 10, wherein,

the temperature sensitive diode has a temperature characteristic in which a forward voltage linearly changes with respect to a temperature change.

12. The semiconductor device according to claim 10 or 11, wherein,

the semiconductor device further includes:

a device region provided on the main surface; and

a functional device formed in the device region,

the temperature sensing region is disposed adjacent to the device region in a top view,

The temperature sensing diode detects the temperature of the device region.

13. The semiconductor device according to claim 12, wherein,

the temperature measuring region is arranged in a region surrounded by the device region in a top view.

14. The semiconductor device according to claim 12 or 13, wherein,

the functional device includes a trench gate structure having an electrode structure including an upper gate electrode and a lower gate electrode buried in a gate trench in an up-down direction via a gate insulator.

15. The semiconductor device according to any one of claims 12 to 14, wherein,

the functional device comprises: and a plurality of gate-divided transistors of a plurality of systems, each including a plurality of system transistors formed on the main surface so as to be individually controllable, and generating a single output signal by selectively controlling the plurality of system transistors.

16. The semiconductor device according to any one of claims 1 to 9, wherein,

the semiconductor device further includes:

a device region provided on the main surface; and

a functional device formed in the device region,

the diode region is a protection region,

the diode is an electrostatic breakdown protection diode.

17. The semiconductor device of claim 16, wherein,

the semiconductor device further includes: a terminal electrode disposed on the main surface so as to be electrically connected to the functional device,

the electrostatic breakdown protection diode is electrically connected to the terminal electrode.

18. A semiconductor device, comprising:

a chip having a main surface;

a temperature measurement region provided on the main surface;

a protection region provided in a region different from the temperature measurement region in the main surface;

a plurality of first trench structures formed on the main surface at intervals in the temperature measurement region, each of the first trench structures including a first upper electrode and a first lower electrode, the first upper electrode and the first lower electrode being embedded in the first trench in the up-down direction via a first insulator;

a temperature sensing diode having a first pn junction portion formed in a surface layer portion of the main surface in a region between the plurality of first trench structures;

a plurality of second trench structures formed on the main surface at intervals in the protection region, each of the second trench structures including a second upper electrode and a second lower electrode, the second upper electrode and the second lower electrode being buried in the second trench in the up-down direction via a second insulator; and

And a second pn junction portion formed in a surface layer portion of the main surface in a region between the plurality of second trench structures.

19. The semiconductor device according to any one of claims 1 to 18, wherein,

the semiconductor device further includes:

a control region provided on the main surface; and

and the control circuit is formed in the control area.

20. A semiconductor module, comprising:

the semiconductor device according to any one of claims 1 to 18; and

and a control device electrically connected to the semiconductor device and controlling the semiconductor device.