CN117715408A - Manufacturing method of semiconductor structure and semiconductor structure - Google Patents
Manufacturing method of semiconductor structure and semiconductor structure Download PDFInfo
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- CN117715408A CN117715408A CN202211091178.2A CN202211091178A CN117715408A CN 117715408 A CN117715408 A CN 117715408A CN 202211091178 A CN202211091178 A CN 202211091178A CN 117715408 A CN117715408 A CN 117715408A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 239000003990 capacitor Substances 0.000 claims abstract description 140
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 238000005530 etching Methods 0.000 claims abstract description 46
- 239000007772 electrode material Substances 0.000 claims description 88
- 230000008093 supporting effect Effects 0.000 claims description 60
- 238000000034 method Methods 0.000 claims description 52
- 239000000463 material Substances 0.000 claims description 50
- 229920002120 photoresistant polymer Polymers 0.000 claims description 28
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 239000002178 crystalline material Substances 0.000 claims description 15
- 239000010410 layer Substances 0.000 description 533
- 230000008569 process Effects 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910003697 SiBN Inorganic materials 0.000 description 2
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000012811 non-conductive material Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The embodiment of the disclosure discloses a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; forming a laminated structure on the substrate; etching the laminated structure to form a capacitor hole; forming a first lower electrode layer and a second lower electrode layer in the capacitor hole, wherein the first lower electrode layer covers the inner surface of the capacitor hole and forms a cavity in the capacitor hole, and the second lower electrode layer fills the cavity; wherein the stress in the second lower electrode layer is less than the stress in the first lower electrode layer.
Description
Technical Field
The disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure and the semiconductor structure.
Background
Dynamic Random Access Memory (DRAM) is a semiconductor structure commonly used in electronic devices that includes a plurality of memory cells, each memory cell including a transistor and a capacitor. As DRAM feature sizes continue to shrink, the capacitance of the capacitor is typically increased by increasing the height of the capacitor pillar to increase the storage density. When the feature size is reduced below a certain value, the formation of the capacitor column with high aspect ratio can face the problems of instability and the like of the capacitor column caused by the increase of film stress and the like, so that how to form a stable and reliable columnar capacitor structure becomes a technical problem to be solved urgently at present.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a semiconductor structure for solving the technical problems in the background art.
According to a first aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor structure, including:
providing a substrate;
forming a laminated structure on the substrate;
etching the laminated structure to form a capacitor hole;
forming a first lower electrode layer and a second lower electrode layer in the capacitor hole, wherein the first lower electrode layer covers the inner surface of the capacitor hole and forms a cavity in the capacitor hole, and the second lower electrode layer fills the cavity; wherein,
the stress in the second lower electrode layer is less than the stress in the first lower electrode layer.
In some embodiments, the material of the second bottom electrode layer comprises a crystalline material comprising silicon.
In some embodiments, the crystalline material comprising silicon has a grain size of less than 1nm.
In some embodiments, the first lower electrode layer and the second lower electrode layer are collectively defined as a lower electrode, the lower electrode having a diameter of no greater than 40nm.
In some embodiments, the thickness of the first lower electrode layer along the radial direction of the capacitor hole is 10-15nm, and the thickness of the second lower electrode layer along the radial direction of the capacitor hole is 15-30nm.
In some embodiments, forming a stack structure on the substrate, and etching the stack structure to form the capacitor hole, comprises:
forming the laminated structure on the substrate, wherein the laminated structure at least comprises a first supporting layer, a first sacrificial layer, a second supporting layer, a second sacrificial layer and a third supporting layer;
and etching the laminated structure along the direction perpendicular to the substrate to expose the substrate and form the capacitor hole.
In some embodiments, forming a first lower electrode layer and a second lower electrode layer within the capacitive aperture, the first lower electrode layer covering an inner surface of the capacitive aperture and forming a cavity within the capacitive aperture, the second lower electrode layer filling the cavity, comprising:
forming a first lower electrode material layer, wherein the first lower electrode material layer covers the inner surface of the capacitor hole and the upper surface of the laminated structure, and a cavity is formed in the capacitor hole;
forming a second lower electrode material layer filling the cavity and covering the top of the first lower electrode material layer;
and etching the second lower electrode material layer and the top of the first lower electrode material layer to expose the third supporting layer, wherein the rest of the first lower electrode material layer and the second lower electrode material layer are respectively defined as the first lower electrode layer and the second lower electrode layer.
In some embodiments: after etching the top of the second bottom electrode layer and the first bottom electrode layer and exposing the third support layer, the method further includes:
forming a mask layer and a patterned photoresist layer on the mask layer over the first lower electrode layer, the second lower electrode layer and the third support layer; the mask layer comprises a first mask layer, a second mask layer and a third mask layer, wherein the material of the first mask layer is the same as that of the third support layer.
In some embodiments, after forming the mask layer and the patterned photoresist layer on the mask layer, the method further comprises:
etching the mask layer based on the patterned photoresist layer, transferring the photoresist layer pattern to the first mask layer, and forming a first opening, wherein part of the area of at least one first lower electrode layer and part of the third supporting layer are exposed by the first opening;
etching the third supporting layer by taking the first mask layer as a mask to form a second opening, wherein the second opening exposes the second sacrificial layer;
removing the second sacrificial layer to expose the second supporting layer;
Etching the second supporting layer to form a third opening, wherein the third opening exposes the first sacrificial layer;
and removing the first sacrificial layer to expose the first supporting layer, wherein the rest of the first supporting layer, the second supporting layer and the third supporting layer are defined as supporting structures.
In some embodiments, forming a first lower electrode layer and a second lower electrode layer within the capacitive aperture, the first lower electrode layer covering an inner surface of the capacitive aperture and forming a cavity within the capacitive aperture, the second lower electrode layer filling the cavity, comprising:
forming a first lower electrode material layer, wherein the first lower electrode material layer covers the inner surface of the capacitor hole and the upper surface of the laminated structure, and a cavity is formed in the capacitor hole;
removing the top of the first lower electrode material layer to expose the third supporting layer, wherein the rest of the first lower electrode material layer is defined as a first lower electrode layer, and the first lower electrode layer forms a cavity in the capacitor hole;
and forming a second lower electrode material layer, wherein the second lower electrode material layer fills the cavity and covers the tops of the first lower electrode layer and the third support layer.
In some embodiments, after forming the second bottom electrode material layer, the method further comprises:
forming a mask layer and a patterned photoresist layer on the mask layer over the second lower electrode material layer; the mask layer comprises a second mask layer and a third mask layer, and the top of the second lower electrode material layer is used as a part of the mask layer.
In some embodiments, after forming the mask layer and the patterned photoresist layer on the mask layer, the method further comprises:
etching the top of the third mask layer, the second mask layer and the second lower electrode material layer based on the patterned photoresist layer, transferring a photoresist layer pattern to the second lower electrode material layer, and forming a first opening exposing a partial region of at least one of the first lower electrode layers and a partial of the third support layer;
etching the third support layer by taking the patterned second lower electrode material layer as a mask to form a second opening, wherein the second opening exposes the second sacrificial layer;
removing the second sacrificial layer to expose the second supporting layer;
etching the second support layer to form a third opening, and removing the second lower electrode material layer covering the third support layer and the top of the first lower electrode layer, wherein the third opening exposes the first sacrificial layer, and the rest of the second lower electrode material layer is defined as the second lower electrode layer;
And removing the first sacrificial layer to expose the first supporting layer, wherein the rest of the first supporting layer, the second supporting layer and the third supporting layer are defined as supporting structures.
In some embodiments, forming the second lower electrode material layer includes:
the second lower electrode material layer is formed at a temperature ranging from 470 to 530 ℃.
In some embodiments, after removing the first sacrificial layer and exposing the first support layer, the method further comprises:
forming a dielectric layer on the exposed surfaces of the first and second lower electrode layers and the first and third support layers;
an upper electrode is formed on a surface of the dielectric layer. According to a second aspect of embodiments of the present disclosure, there is provided a semiconductor structure comprising:
a substrate;
a support structure above the substrate, the support structure including a capacitive aperture therethrough;
the lower electrode is positioned in the capacitor hole, wherein the lower electrode comprises a first lower electrode layer and a second lower electrode layer, the first lower electrode layer covers the bottom and the side wall of the capacitor hole and forms a cavity, and the second lower electrode layer is filled in the cavity; wherein the stress in the second lower electrode layer is less than the stress in the first lower electrode layer.
In some embodiments, the material of the second bottom electrode layer comprises a crystalline material comprising silicon.
In some embodiments, the crystalline material comprising silicon has a grain size of less than 1nm.
In some embodiments, the diameter of the lower electrode is no greater than 40nm.
In some embodiments, the thickness of the first lower electrode layer along the radial direction of the capacitor hole is 10-15nm, and the thickness of the second lower electrode layer along the radial direction of the capacitor hole is 15-30nm.
In some embodiments, the semiconductor structure further comprises:
a dielectric layer covering the lower electrode and the support structure, and an upper electrode covering the dielectric layer.
The embodiment of the disclosure provides a manufacturing method of a semiconductor structure, which comprises the following steps: providing a substrate; forming a laminated structure on the substrate; etching the laminated structure to form a capacitor hole; forming a first lower electrode layer and a second lower electrode layer in the capacitor hole, wherein the first lower electrode layer covers the inner surface of the capacitor hole and forms a cavity in the capacitor hole, and the second lower electrode layer fills the cavity; wherein the stress in the second lower electrode layer is less than the stress in the first lower electrode layer. The method comprises the steps of forming a capacitor hole in a laminated structure on a substrate, forming a first lower electrode layer and a second lower electrode layer in the capacitor hole, wherein the first lower electrode layer covers the inner surface of the capacitor hole and forms a cavity in the capacitor hole, the second lower electrode layer fills the cavity, and the first lower electrode layer and the second lower electrode layer jointly form a lower electrode. The second lower electrode layer fills the cavity of the first lower electrode layer, and the stress in the second lower electrode layer is smaller than that in the first lower electrode layer, so that the condition that the capacitor column is easy to incline due to overlarge stress of a single first lower electrode can be improved. And then can improve when the etching opening skew that leads to because of the electric capacity post slope, the supporting layer that causes can't normally open to can't fully get rid of the bottom oxide layer, make can't reserve abundant space for the upper electrode, thereby lead to the problem of whole electric capacity inefficacy.
Additional aspects and advantages of the disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the disclosure.
Drawings
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present disclosure;
FIGS. 2a to 2q are schematic views of a semiconductor structure provided in an embodiment of the present disclosure during a manufacturing process;
fig. 3 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the disclosure.
Reference numerals:
10-substrate; 101-a substrate; 102-a conductive contact layer; 11-a laminated structure; 111-a first support layer; 112-a first sacrificial layer; 113-a second support layer; 114-a second sacrificial layer; 115-a third support layer; 12-capacitance holes; 121-a cavity; 14-a first lower electrode layer; 141-a first lower electrode material layer; 15-a second lower electrode layer; 151-a second lower electrode material layer; 16-a lower electrode; 17-mask layer; 171-a first mask layer; 172-a second mask layer; 173-a third mask layer; 18-patterning the photoresist layer; 191-a first opening; 19-a second opening; 20-a third opening; 30-a support structure; 32-a dielectric layer; 33-upper electrode.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.
Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
As Dynamic Random Access Memory (DRAM) feature sizes continue to shrink, the capacitance of the capacitor is typically increased by increasing the height of the capacitor pillar to increase the storage density. When the feature size is reduced below a certain value, the capacitor column structure with high depth-to-width ratio is formed to face the problems that the capacitor column is inclined and the like caused by the increase of film stress and the like in the structure, and further the capacitor structure cannot be normally opened in the subsequent manufacturing process, so that the lower oxide layer cannot be sufficiently removed, the space reserved for the upper electrode of the capacitor is insufficient, and the capacitor is invalid.
Based on this, the disclosure provides a method for manufacturing a semiconductor structure, referring specifically to fig. 1, as shown in the drawings, the method includes:
step 101: providing a substrate;
step 102: forming a laminated structure on the substrate; etching the laminated structure to form a capacitor hole;
step 103: forming a first lower electrode layer and a second lower electrode layer in the capacitor hole, wherein the first lower electrode layer covers the inner surface of the capacitor hole and forms a cavity in the capacitor hole, and the second lower electrode layer fills the cavity; wherein the stress in the second lower electrode layer is less than the stress in the first lower electrode layer.
The method for manufacturing the semiconductor structure provided in the present disclosure is further described in detail below with reference to specific embodiments.
First, step 101 is performed, see fig. 2a, to provide a substrate 10.
In actual operation, the base 10 includes, for example, but is not limited to, a simple semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The substrate may be doped or undoped, or contain both doped and undoped regions therein. The substrate may also include one or more dopants (n - Or p - ) A region; if the substrate comprises a plurality of doped regions, these regions may have the same or different conductivity and/or doping concentration. These doped regions are referred to as "wells" and may be used to define individual device regions. Referring to fig. 2a, in a specific embodiment, the base 10 comprises a doped or undoped silicon substrate 101, a conductive contact layer 102 is included over the substrate 101, and the conductive material may comprise a metallic material, such as metallic tungsten (W).
Next, step 102 is performed, referring to fig. 2a and 2b, forming a laminated structure 11 on the substrate 10; the stacked structure 11 is etched to form a capacitor hole 12.
Specifically, forming the stacked structure 11 on the substrate 10 and etching the stacked structure 11 to form the capacitor hole 12 include: forming the laminated structure 11 on the substrate 10, wherein the laminated structure 11 includes at least a first supporting layer 111, a first sacrificial layer 112, a second supporting layer 113, a second sacrificial layer 114, and a third supporting layer 115 (as shown in fig. 2 a); the stacked structure 11 is etched in a direction perpendicular to the substrate 10, exposing the substrate 10, and forming the capacitor hole 12 (as shown in fig. 2 b).
The laminated structure comprises two sacrificial layers and three supporting layers, and can better support the formed capacitor structure under the condition of ensuring the height of the formed capacitor structure.
In practice, the first support layer 111, the first sacrificial layer 112, the second support layer 113, the second sacrificial layer 114, and the third support layer 115 may be formed using one or more of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD) processes; the formation of the capacitor holes 12 by etching the stack 11 may be performed by an anisotropic etching process, such as a plasma etching process. The materials for sequentially depositing the first support layer 111, the second support layer 113, and the third support layer 115 on the substrate 10 include, but are not limited to, nitrides, and in a specific embodiment, the materials for the second support layer 113 and the third support layer 115 may be insulating materials containing C, such as SiCN, which has good hardness and can support the capacitor structure formed later. The materials of the first supporting layer 111 and the first sacrificial layer 112 may be insulating materials containing B, for example, the material of the first supporting layer 111 may be SiBN, the material of the first sacrificial layer 112 may be borophosphosilicate glass (BPSG), and the materials doped with boron elements are adopted for the first sacrificial layer 112 and the first supporting layer 111, so that the hardness of the materials is reduced, the etching process is more easily completed, and the morphology of the capacitor hole 12 can be ensured.
It is understood that the types and the number of the layers included in the stacked structure 11 may vary according to the height of the capacitor structure, and are not particularly limited herein.
Finally, step 103 is performed to form a first lower electrode layer 14 and a second lower electrode layer 15 in the capacitor hole 12, wherein the first lower electrode layer 14 covers the inner surface of the capacitor hole 12 and forms a cavity 121 in the capacitor hole 12, and the second lower electrode layer 15 fills the cavity 121; wherein the stress in the second lower electrode layer 15 is smaller than the stress in the first lower electrode layer 14.
The second lower electrode layer fills the cavity of the first lower electrode layer, and the stress in the second lower electrode layer is smaller than that in the first lower electrode layer, so that the first lower electrode layer can be stably and well supported, the stability of the capacitor column in the process is enhanced, and inclination is not easy to occur. And then can improve when the etching opening skew that leads to because of the electric capacity post slope, the supporting layer that causes can't normally open to can't fully get rid of the bottom oxide layer, make can't reserve abundant space for the upper electrode, thereby lead to the problem of whole electric capacity inefficacy.
Here, the material of the second lower electrode layer 15 may include a conductive or nonconductive material, preferably a material having good filling property and small film stress, for example, including but not limited to a crystalline material containing silicon.
In some specific embodiments, the material of the second lower electrode layer 15 may include a doped or undoped silicon-containing crystalline material.
In practical operation, the materials of the second bottom electrode layer 15 include, but are not limited to, polysilicon, silicon germanium, etc., which have excellent filling properties, can be fully filled in the cavity of the first bottom electrode layer 14, and the formed film has relatively small stress, thus having good supporting effect on the first bottom electrode layer 14 and avoiding the problems of inclination, offset, etc. of the capacitor column.
In some embodiments, the crystalline material comprising silicon has a grain size of less than 1nm.
Preferably, the crystalline material comprising silicon has a grain size of less than 0.1nm. The smaller the grain size of the material is, the better the filling performance is, and the material is easier to fill in the cavity of the first lower electrode layer with the size of tens of nanometers; in addition, the smaller the grain size of the material, the smaller the formed lattice stress, and the smaller the stress of the finally formed second lower electrode layer, the better the supporting effect on the first lower electrode layer.
In some embodiments, the second lower electrode layer 15 may include a single layer of material; in some other embodiments, the second lower electrode layer 15 may include multiple layers of material, for example, the second lower electrode layer includes, in order, a 1 st sub-layer … … nth sub-layer along a radial direction of the capacitor hole from the center toward the periphery, where N is a positive integer greater than or equal to 2. In some more specific embodiments, the hardness and/or film stress of each of the 1 st sub-layer … … N-th sub-layer may be different, and in particular, for example, in some embodiments, the hardness of the 1 st sub-layer … … N-th sub-layer decreases in sequence and the film stress decreases gradually in a direction from the axis to the periphery in the radial direction of the capacitor hole. In this way, the supporting effect of the second lower electrode layer 15 on the first lower electrode layer 14 can be further improved, thereby further enhancing the stability of the lower electrode 16.
In some embodiments, referring to fig. 2e and fig. 2p, the first lower electrode layer 14 and the second lower electrode layer 15 are collectively defined as a lower electrode 16, and the diameter of the lower electrode 16 is not greater than 40nm.
The smaller the size of the capacitor, the more likely the capacitor will be tilted or collapsed. The diameter of the columnar (pilar) capacitance tends to be on the scale of tens of nanometers, and thus tilting and shifting of the capacitance occurs very easily. The capacitor preparation method provided by the embodiment of the disclosure is compatible with a capacitor preparation process with a very small size (for example, a pilar capacitor), and can be applied to a process for preparing a capacitor with a small size, for example, the diameter of the lower electrode 16 is not more than 40nm, not more than 30nm or not more than 20nm, so as to alleviate and avoid the problems that the subsequent steps for preparing a dielectric layer and an upper electrode of the capacitor are difficult to be smoothly carried out due to inclination and offset existing in the capacitor preparation process with the very small size, thereby providing a capacitor structure with the very small size, stability and reliability.
In some embodiments, the thickness of the first lower electrode layer along the radial direction of the capacitor hole is 10-15nm, and the thickness of the second lower electrode layer along the radial direction of the capacitor hole is 15-30nm.
In the above embodiment, the second lower electrode layer 15 mainly plays a role of supporting the first lower electrode layer 14, and the first lower electrode layer 14 mainly plays a role of a capacitor electrode plate, and when the ratio of the thickness of the second lower electrode layer 15 to the thickness of the first lower electrode layer 14 is small, the effect of improving the inclination and offset of the capacitor column is limited because the thickness of the second lower electrode layer 15 in the lower electrode 16 is small; when the ratio of the thickness of the second bottom electrode layer 15 to the thickness of the first bottom electrode layer 14 is large, the performance of the capacitor structure is affected to some extent due to the small thickness of the first bottom electrode layer 14 in the bottom electrode 16. Therefore, the thickness of the second bottom electrode layer 15 is slightly larger than that of the first bottom electrode layer 14, so that the capacitance performance of the capacitor structure can be considered while the beneficial effects of improving the inclination and the offset of the capacitor column are better obtained.
The presently disclosed embodiments provide two embodiments of preparing a lower electrode 16, as shown in fig. 2 c-2 e, in a first embodiment, a first lower electrode layer 14 and a second lower electrode layer 15 are formed within the capacitive aperture 12, the first lower electrode layer 14 covering the inner surface of the capacitive aperture 12 and forming a cavity 121 within the capacitive aperture 12, the second lower electrode layer 15 filling the cavity 121, comprising: forming a first lower electrode material layer 141, wherein the first lower electrode material layer 141 covers the inner surface of the capacitor hole 12 and the upper surface of the laminated structure 11, and the first lower electrode material layer 141 forms a cavity 121 (see fig. 2 c) in the capacitor hole 12; forming a second lower electrode material layer 151, the second lower electrode material layer 151 filling the cavity 121 and covering the top of the first lower electrode material layer 141 (see fig. 2 d); the top of the second bottom electrode material layer 151 and the first bottom electrode material layer 141 are etched to expose the third support layer 115, and the remaining first bottom electrode material layer 141 and the second bottom electrode material layer 151 are respectively defined as the first bottom electrode layer 14 and the second bottom electrode layer 15 (see fig. 2 e).
In practice, the first lower electrode layer 14 may be formed by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD) at 550-650 ℃, and the material of the first lower electrode layer 14 includes, but is not limited to, titanium (Ti), titanium nitride (TiN), tungsten (W), or the like. The step of etching the second lower electrode material layer 151 and the top of the first lower electrode material layer 141 to expose the third support layer 115 may employ a wet or dry etching process, such as a plasma etching process, a Chemical Mechanical Polishing (CMP) process, or the like. In some embodiments, as shown in fig. 2e, after the etching process is performed to expose the third support layer 115, the second lower electrode layer 15 and/or the first lower electrode layer 14 is flush with the upper surface of the third support layer 115. It should be appreciated that in some other embodiments, the upper surfaces of the second lower electrode layer 15, the first lower electrode layer 14, and the third support layer 115 may not be flush, only the third support layer 115 needs to be exposed.
In a specific embodiment, forming the second bottom electrode material layer 151 includes: the second lower electrode material layer 151 is formed at a temperature ranging from 470 to 530 ℃.
In practice, the second lower electrode layer 15 may be prepared at 470-530 ℃ using one or more of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD) processes. In the above temperature range, the size and morphology of the filling material crystal grains are better, the formed lattice stress is more controllable, the hardness of the prepared second bottom electrode layer 15 is moderate, and the film stress is small enough, so that a better stress improvement effect can be generated on the first bottom electrode layer 14.
The first lower electrode layer 14 and the second lower electrode layer 15 formed in the first embodiment described above together constitute the lower electrode 16.
After forming the lower electrode 16 according to the first embodiment described above, referring next to fig. 2f, the method further includes: forming a mask layer 17 and a patterned photoresist layer 18 on the mask layer 17 over the first lower electrode layer 14, the second lower electrode layer 15, and the third support layer 115; the mask layer 17 includes a first mask layer 171, a second mask layer 172, and a third mask layer 173, wherein the material of the first mask layer 171 is the same as the material of the third support layer 115.
The first mask layer and the third support layer are made of the same material, so that the support effect of the support structure on the lower electrode is better, the problems of inclination and offset of the lower electrode are better improved, and the problem that the subsequent opening failure is caused by the influence of inclination and offset of the lower electrode when the support structure is etched to form the opening, and the subsequent capacitor manufacturing step cannot be smoothly performed is avoided. In addition, the first mask layer can protect the surfaces of the third support layer, the first lower electrode layer and the second lower electrode layer from being etched in the etching process, so that the support effect of the support structure and the performance of the capacitor structure are guaranteed. Further, the first mask layer made of the same material as the third support layer can also control the height difference between the third support layer and the first lower electrode layer, so that the surface morphology of the capacitor is controlled.
In practice, the mask layer 17 may be formed by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD), wherein the material of the first mask layer 171 may include, but is not limited to, siCN, the material of the second mask layer 172 may include, but is not limited to, carbon, and the material of the third mask layer 173 may include, but is not limited to, siON.
Photolithography is an important process in manufacturing semiconductor structures, as feature sizes are continuously reduced, so that the difficulty of photolithography is continuously increased, and when patterns are defined in a photoresist layer, since a semiconductor substrate (including a metal layer and a dielectric layer) under the photoresist layer has a relatively high reflection coefficient, an exposure light source is easily reflected on the surface of the semiconductor substrate, so that deformation or dimensional deviation of the photoresist patterns is caused, and incorrect transfer of mask patterns is caused. In order to eliminate the reflection phenomenon of the light source, a Dielectric Anti-reflection coating (DARC) is generally formed on the surface of the semiconductor substrate, and the material of the Dielectric Anti-reflection coating is typically silicon oxynitride or the like. The third mask layer 173 in the above embodiment may function as a dielectric anti-reflective coating.
Next, referring to fig. 2g to fig. 2j, after forming the mask layer 17 and the patterned photoresist layer 18 on the mask layer 17, the method further includes: etching the mask layer 17 based on the patterned photoresist layer 18, transferring a photoresist layer pattern to the first mask layer 171, and forming a first opening 191, wherein the first opening 191 exposes a partial region of at least one of the first lower electrode layers 14 and a portion of the third support layer 115; etching the third support layer 115 using the first mask layer 171 as a mask to form a second opening 19, wherein the second opening 19 exposes the second sacrificial layer 114 (see fig. 2 g); removing the second sacrificial layer 114 to expose the second support layer 113 (see fig. 2 h); etching the second support layer 113 to form a third opening 20, wherein the third opening 20 exposes the first sacrificial layer 112 (see fig. 2 i); the first sacrificial layer 112 is removed, exposing the first support layer 111 (see fig. 2 j), and the remaining first support layer 111, second support layer 113 and third support layer 115 define a support structure.
Because the first lower electrode layer and the second lower electrode layer jointly form a stable lower electrode structure, in the process of forming an opening by adopting a photoetching technology and an etching process, the problem that an etching solution is difficult to fully contact with the first sacrificial layer in a subsequent wet etching process due to the failure of the opening can be avoided because the lower electrode is inclined or deviated to cause alignment deviation to cause failure of the opening, and further the problem that the manufacturing of the capacitor structure is failed because the first sacrificial layer cannot be completely removed is avoided.
In practice, the third support layer 115 and the second support layer 113 may be etched using, for example, photolithography and etching processes to form the first, second, and third openings 191, 19, and 20. Methods of removing the first sacrificial layer 112 and the second sacrificial layer 114 include, but are not limited to, using dilute hydrofluoric acid (DHF) or hydrofluoric acid (HF) and ammonia fluoride (NH) 4 F) The materials of the first sacrificial layer 112 and the second sacrificial layer 114 are selectively etched away by a wet etching method, and the first lower electrode layer 14 and the second lower electrode layer 15, and the first support layer 111, the second support layer 113 and the third support layer 115 remain. Specifically, the first sacrificial layer 112 and the second sacrificial layer 114 are sequentially etched, respectively, and the second sacrificial layer 114 is etched first and then the first sacrificial layer 112 is etched.
As shown in fig. 2c, 2k to 2p, in the second embodiment of forming the lower electrode 16, a first lower electrode layer 14 and a second lower electrode layer 15 are formed in the capacitor hole 12, the first lower electrode layer 14 covers the inner surface of the capacitor hole 12 and forms a cavity 121 in the capacitor hole 12, and the second lower electrode layer 15 fills the cavity 121, including: forming a first lower electrode material layer 141, wherein the first lower electrode material layer 141 covers the inner surface of the capacitor hole 12 and the upper surface of the laminated structure 11, and the first lower electrode material layer 141 forms a cavity 121 (see fig. 2 c) in the capacitor hole 12; removing the top of the first lower electrode material layer 141 to expose the third support layer 115, wherein the remaining first lower electrode material layer 141 is defined as a first lower electrode layer 14, and the first lower electrode layer 14 forms a cavity 121 (see fig. 2 k) within the capacitor hole 12; the second lower electrode material layer 151 is formed, and the second lower electrode material layer 151 fills the cavity 121 and covers the top of the first lower electrode layer 14 and the third support layer 115 (see fig. 2 l).
Next, referring to fig. 2m, after forming the second lower electrode material layer 151, the method further includes: forming a mask layer 17 and a patterned photoresist layer 18 on the mask layer 17 over the second lower electrode material layer 151; the mask layer 17 includes a second mask layer 172 and a third mask layer 173, and the top of the second bottom electrode material layer 151 is used as a part of the mask layer.
The second lower electrode material layer is not only filled in the cavity, but also covers the tops of the first lower electrode layer and the third supporting layer, has better supporting effect on the first lower electrode layer, and can better solve the problems that the first lower electrode layer is easy to incline and deviate due to stress and the like. In addition, the top of the second lower electrode material layer may function as a first mask layer among the mask layers, and thus a process of forming the first mask layer may be saved with respect to the first embodiment described above.
In practical applications, the first lower electrode material layer 141, the second lower electrode material layer 151, and the second mask layer 172 and the third mask layer 173 in the mask layer 17 may be formed by a method similar to that in the first embodiment, and will not be described herein. The step of removing the top of the first lower electrode material layer 141 to expose the third support layer 115 may employ a wet or dry etching process, such as a plasma etching process, a Chemical Mechanical Polishing (CMP) process, or the like.
Next, referring to fig. 2n to 2q, after forming the mask layer 17 and the patterned photoresist layer 18 on the mask layer 17, the method further includes: etching the third mask layer 173, the second mask layer 172 and the top of the second lower electrode material layer 151 based on the patterned photoresist layer 18, transferring a photoresist layer pattern to the second lower electrode material layer 151, forming a first opening 191, the first opening 191 exposing a partial region of at least one of the first lower electrode layers 14 and a portion of the third support layer 115; etching the third support layer 115 with the patterned second bottom electrode material layer 151 as a mask to form a second opening 19, wherein the second opening 19 exposes the second sacrificial layer 114 (see fig. 2 n); removing the second sacrificial layer 114 to expose the second support layer 113 (see fig. 2 o); etching the second support layer 113 to form a third opening 20, and removing the second lower electrode material layer covering the third support layer 115 and the top of the first lower electrode layer 14, the third opening 20 exposing the first sacrificial layer 112, the remaining second lower electrode material layer being defined as the second lower electrode layer 15 (see fig. 2 p); the first sacrificial layer 112 is removed, exposing the first support layer 111 (see fig. 2 q), and the remaining first support layer 111, second support layer 113 and third support layer 115 define a support structure.
In practical operation, the first opening 191, the second opening 19, and the third opening 20, and the removal of the first sacrificial layer 112 and the second sacrificial layer 114 may be formed by a method similar to that in the first embodiment, and will not be described herein.
In some specific embodiments, the first sacrificial layer 112 and the second sacrificial layer 114 have a high etch selectivity with respect to the second lower electrode material layer 151.
In the above embodiment, the openings are formed in the supporting layer to remove the first sacrificial layer and the second sacrificial layer, so as to facilitate the subsequent process of manufacturing the capacitor structure. The first sacrificial layer 112 and the second sacrificial layer 114 have a high etching selectivity relative to the second lower electrode material layer 151, so that when the first sacrificial layer and the second sacrificial layer are removed by wet etching, the second lower electrode material layer is not affected basically, and therefore the supporting effect of the second lower electrode material layer on the first lower electrode layer is not affected, and further the problems of inclination, offset and the like of the capacitor column are avoided.
The lower electrode 16 formed by the second lower electrode layer 15 and the first lower electrode layer 14 is formed in accordance with the second embodiment.
Next, after forming the lower electrode 16 and removing the first sacrificial layer 112 according to either of the above two embodiments and exposing the first support layer 111, referring to fig. 3, the method further includes: forming a dielectric layer 32 on exposed surfaces of the first and second lower electrode layers 14 and 15 and the first and third support layers 111 and 115; an upper electrode 33 is formed on the surface of the dielectric layer 32.
The embodiment of the disclosure further provides a semiconductor structure, referring to fig. 3, and as shown in the fig. 3, the semiconductor structure includes:
a substrate 10;
a support structure 30 positioned above the substrate 10, the support structure 30 including a capacitive aperture 12 therein extending through the support structure 30;
a lower electrode 16 located in the capacitor hole 12, wherein the lower electrode 16 includes a first lower electrode layer 14 and a second lower electrode layer 15, the first lower electrode layer 14 covers the bottom and the side wall of the capacitor hole 12 and forms a cavity 121, and the second lower electrode layer 15 is filled in the cavity 121; wherein the stress in the second lower electrode layer 15 is smaller than the stress in the first lower electrode layer 14.
Because the cavity of the first lower electrode layer is filled with the second lower electrode layer, and the stress in the second lower electrode layer is smaller than that in the first lower electrode layer, the second lower electrode layer can be stably and well supported, so that the stability of the capacitor column is enhanced, and inclination is not easy to occur.
In practice, the base 10 includes, for example, but is not limited to, a substrate of elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a substrate of composite semiconductor material (e.g., a silicon germanium (SiGe) substrate) Bottom, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The substrate may be doped or undoped, or contain both doped and undoped regions therein. The substrate may also include one or more dopants (n - Or p - ) A region; if the substrate comprises a plurality of doped regions, these regions may have the same or different conductivity and/or doping concentration. These doped regions are referred to as "wells" and may be used to define individual device regions. Referring to fig. 3, in a particular embodiment, the base 10 includes a doped or undoped silicon substrate 101, a conductive contact layer 102 is included over the substrate 101, and the conductive material may include a metallic material, such as metallic tungsten (W).
Referring to fig. 3, the support assembly 30 includes a first support layer 111, a second support layer 113, and a third support layer 115, where materials of the first support layer 111, the second support layer 113, and the third support layer 115 include, but are not limited to, nitrides, and materials of the first support layer 111, the second support layer 113, and the third support layer 115 may be the same or different, and specifically, a material of the first support layer 111 may be an insulating material containing B, such as SiBN, and the hardness of the material may be reduced due to doping B, so that the morphology of the capacitor hole 12 formed by, for example, an etching method is better. The materials of the second support layer 113 and the third support layer 115 may be C-containing insulating materials, such as SiCN, which has a good hardness and can support the lower electrode 16. The material of the first lower electrode layer 14 includes, but is not limited to, titanium (Ti), titanium nitride (TiN), tungsten (W), or the like, and the thickness of the first lower electrode layer 14 may be, for example, 10nm to 15nm.
In some embodiments, the material of the second lower electrode layer 15 may include a conductive or nonconductive material, preferably a material with good filling property and small film stress, for example, including but not limited to a crystalline material containing silicon. In practical operation, the material of the second bottom electrode layer 15 includes, but is not limited to, polysilicon, silicon germanium, etc., which has excellent filling property, can fully fill the cavity 121 of the first electrode layer 14, and has small stress of the formed film layer, which can well support the first bottom electrode layer 14, and avoid the problems of inclination, offset, etc. of the capacitor column.
In some embodiments, the crystalline material comprising silicon has a grain size of less than 1nm.
Preferably, the crystalline material comprising silicon has a grain size of less than 0.1nm. The smaller the grain size of the material is, the better the filling performance is, and the cavity of the first lower electrode layer with the size of tens of nanometers is easier to fill; in addition, the smaller the grain size of the material, the smaller the formed lattice stress, and the smaller the stress of the finally formed second lower electrode layer, the better the supporting effect on the first lower electrode layer.
In some embodiments, referring to fig. 3, the diameter of the lower electrode 16 is no greater than 40nm.
The smaller the size of the capacitor, the more likely the capacitor will be tilted or collapsed. The diameter of the pilar capacitance tends to be on the scale of tens of nanometers, and therefore tilting and shifting of the capacitance occurs very easily. The capacitor structure provided in the embodiment of the present disclosure is manufactured by using the manufacturing method in the foregoing embodiment, and may be manufactured in a very small size, for example, a small-size capacitor with a diameter of the lower electrode 16 not greater than 40nm, not greater than 30nm, or not greater than 20nm, where the foregoing lower electrode structure may alleviate and avoid the problems of tilting, offset, and the like of the manufactured very small-size capacitor, and implement a very small-size and stable and reliable capacitor structure.
In some embodiments, referring to fig. 3, the thickness of the first lower electrode layer along the radial direction of the capacitor hole is 10-15nm, and the thickness of the second lower electrode layer along the radial direction of the capacitor hole is 15-30nm.
In the above embodiment, the second lower electrode layer 15 mainly plays a role of supporting the first lower electrode layer 14, and the first lower electrode layer 14 mainly plays a role of a capacitor electrode plate, and when the ratio of the thickness of the second lower electrode layer 15 to the thickness of the first lower electrode layer 14 is small, the effect of improving the inclination and offset of the capacitor column is limited because the thickness of the second lower electrode layer 15 in the lower electrode 16 is small; when the ratio of the thickness of the second bottom electrode layer 15 to the thickness of the first bottom electrode layer 14 is large, the performance of the capacitor structure is affected to some extent due to the small thickness of the first bottom electrode layer 14 in the bottom electrode 16. Therefore, the thickness of the second bottom electrode layer 15 is slightly larger than that of the first bottom electrode layer 14, so that the beneficial effects of improving the inclination and the offset of the capacitor column can be better achieved, and meanwhile, the performance of the capacitor structure is considered.
In some embodiments, referring to fig. 3, the semiconductor structure further includes: a dielectric layer 32 covering the lower electrode 16 and the support structure 30, and an upper electrode 33 covering the dielectric layer 32.
In practice, the material of the dielectric layer 32 includes, but is not limited to, aluminum oxide, silicon nitride, silicon oxide, zirconium oxide, combinations thereof, or the like. The material of the upper electrode 33 includes, but is not limited to, titanium (Ti), titanium nitride (TiN), tungsten (W), or the like. The lower electrode 16 and the dielectric layer 32 and the upper electrode 33 together form a complete capacitor structure.
In summary, in the disclosure, a capacitor hole is formed in a stacked structure on a substrate, then a first bottom electrode layer and a second bottom electrode layer are formed in the capacitor hole, the first bottom electrode layer covers an inner surface of the capacitor hole and forms a cavity in the capacitor hole, the second bottom electrode layer fills the cavity, and the first bottom electrode layer and the second bottom electrode layer together form a bottom electrode. The second lower electrode layer fills the cavity of the first lower electrode layer, and the stress in the second lower electrode layer is smaller than that in the first lower electrode layer, so that the situation that the capacitor column is easy to incline due to overlarge stress of a single first lower electrode can be improved. And then can improve when the etching opening skew that leads to because of the electric capacity post slope, the supporting layer that causes can't normally open to can't fully get rid of the bottom oxide layer, make can't reserve abundant space for the upper electrode, thereby lead to the problem of whole electric capacity inefficacy.
It should be noted that the method for manufacturing a semiconductor structure and the semiconductor structure provided in the embodiments of the present disclosure may be applied to any integrated circuit including the structure. The features of the embodiments described in the present invention may be combined arbitrarily without any conflict.
The foregoing description of the preferred embodiments of the present disclosure is not intended to limit the scope of the present disclosure, but is intended to cover any modifications, equivalents, and improvements within the spirit and principles of the present disclosure.
Claims (20)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a laminated structure on the substrate;
etching the laminated structure to form a capacitor hole;
forming a first lower electrode layer and a second lower electrode layer in the capacitor hole, wherein the first lower electrode layer covers the inner surface of the capacitor hole and forms a cavity in the capacitor hole, and the second lower electrode layer fills the cavity; wherein,
the stress in the second lower electrode layer is less than the stress in the first lower electrode layer.
2. The method of manufacturing a semiconductor structure of claim 1, wherein the material of the second bottom electrode layer comprises a crystalline material comprising silicon.
3. The method of manufacturing a semiconductor structure according to claim 2, wherein the crystalline material comprising silicon has a grain size of less than 1nm.
4. The method of manufacturing a semiconductor structure according to claim 1, wherein the first lower electrode layer and the second lower electrode layer are collectively defined as a lower electrode, and wherein a diameter of the lower electrode is not more than 40nm.
5. The method of manufacturing a semiconductor structure according to claim 1 or 4, wherein a thickness of the first lower electrode layer in a radial direction of the capacitor hole is 10 to 15nm, and a thickness of the second lower electrode layer in a radial direction of the capacitor hole is 15 to 30nm.
6. The method of manufacturing a semiconductor structure according to claim 1, wherein forming a stacked structure on the substrate, and etching the stacked structure to form the capacitor hole, comprises:
forming the laminated structure on the substrate, wherein the laminated structure at least comprises a first supporting layer, a first sacrificial layer, a second supporting layer, a second sacrificial layer and a third supporting layer;
and etching the laminated structure along the direction perpendicular to the substrate to expose the substrate and form the capacitor hole.
7. The method of manufacturing a semiconductor structure according to claim 6, wherein forming a first lower electrode layer and a second lower electrode layer in the capacitor hole, the first lower electrode layer covering an inner surface of the capacitor hole and forming a cavity in the capacitor hole, the second lower electrode layer filling the cavity, comprises:
forming a first lower electrode material layer, wherein the first lower electrode material layer covers the inner surface of the capacitor hole and the upper surface of the laminated structure, and a cavity is formed in the capacitor hole;
forming a second lower electrode material layer filling the cavity and covering the top of the first lower electrode material layer;
and etching the second lower electrode material layer and the top of the first lower electrode material layer to expose the third supporting layer, wherein the rest of the first lower electrode material layer and the second lower electrode material layer are respectively defined as the first lower electrode layer and the second lower electrode layer.
8. The method of claim 7, wherein etching the top of the second bottom electrode layer and the first bottom electrode layer exposes the third support layer, the method further comprising:
Forming a mask layer and a patterned photoresist layer on the mask layer over the first lower electrode layer, the second lower electrode layer and the third support layer; the mask layer comprises a first mask layer, a second mask layer and a third mask layer, wherein the material of the first mask layer is the same as that of the third support layer.
9. The method of claim 8, wherein after forming the mask layer and the patterned photoresist layer on the mask layer, the method further comprises:
etching the mask layer based on the patterned photoresist layer, transferring the photoresist layer pattern to the first mask layer, and forming a first opening, wherein part of the area of at least one first lower electrode layer and part of the third supporting layer are exposed by the first opening;
etching the third supporting layer by taking the first mask layer as a mask to form a second opening, wherein the second opening exposes the second sacrificial layer;
removing the second sacrificial layer to expose the second supporting layer;
etching the second supporting layer to form a third opening, wherein the third opening exposes the first sacrificial layer;
And removing the first sacrificial layer to expose the first supporting layer, wherein the rest of the first supporting layer, the second supporting layer and the third supporting layer are defined as supporting structures.
10. The method of manufacturing a semiconductor structure according to claim 6, wherein forming a first lower electrode layer and a second lower electrode layer in the capacitor hole, the first lower electrode layer covering an inner surface of the capacitor hole and forming a cavity in the capacitor hole, the second lower electrode layer filling the cavity, comprises:
forming a first lower electrode material layer, wherein the first lower electrode material layer covers the inner surface of the capacitor hole and the upper surface of the laminated structure, and a cavity is formed in the capacitor hole;
removing the top of the first lower electrode material layer to expose the third supporting layer, wherein the rest of the first lower electrode material layer is defined as a first lower electrode layer, and the first lower electrode layer forms a cavity in the capacitor hole;
and forming a second lower electrode material layer, wherein the second lower electrode material layer fills the cavity and covers the tops of the first lower electrode layer and the third support layer.
11. The method of manufacturing a semiconductor structure of claim 10, wherein after forming the second bottom electrode material layer, the method further comprises:
forming a mask layer and a patterned photoresist layer on the mask layer over the second lower electrode material layer; the mask layer comprises a second mask layer and a third mask layer, and the top of the second lower electrode material layer is used as a part of the mask layer.
12. The method of claim 11, wherein after forming the mask layer and the patterned photoresist layer on the mask layer, the method further comprises:
etching the top of the third mask layer, the second mask layer and the second lower electrode material layer based on the patterned photoresist layer, transferring a photoresist layer pattern to the second lower electrode material layer, and forming a first opening exposing a partial region of at least one of the first lower electrode layers and a partial of the third support layer;
etching the third support layer by taking the patterned second lower electrode material layer as a mask to form a second opening, wherein the second opening exposes the second sacrificial layer;
Removing the second sacrificial layer to expose the second supporting layer;
etching the second support layer to form a third opening, and removing the second lower electrode material layer covering the third support layer and the top of the first lower electrode layer, wherein the third opening exposes the first sacrificial layer, and the rest of the second lower electrode material layer is defined as the second lower electrode layer;
and removing the first sacrificial layer to expose the first supporting layer, wherein the rest of the first supporting layer, the second supporting layer and the third supporting layer are defined as supporting structures.
13. The method of manufacturing a semiconductor structure according to any one of claims 7 to 12, wherein forming the second lower electrode material layer includes:
the second lower electrode material layer is formed at a temperature ranging from 470 to 530 ℃.
14. The method of manufacturing a semiconductor structure according to claim 9 or 12, wherein after removing the first sacrificial layer and exposing the first support layer, the method further comprises:
forming a dielectric layer on the exposed surfaces of the first and second lower electrode layers and the first and third support layers;
An upper electrode is formed on a surface of the dielectric layer.
15. A semiconductor structure, comprising:
a substrate;
a support structure above the substrate, the support structure including a capacitive aperture therethrough;
the lower electrode is positioned in the capacitor hole, wherein the lower electrode comprises a first lower electrode layer and a second lower electrode layer, the first lower electrode layer covers the bottom and the side wall of the capacitor hole and forms a cavity, and the second lower electrode layer is filled in the cavity; wherein the stress in the second lower electrode layer is less than the stress in the first lower electrode layer.
16. The semiconductor structure of claim 15, wherein the material of the second bottom electrode layer comprises a crystalline material comprising silicon.
17. The semiconductor structure of claim 16, wherein the crystalline material comprising silicon has a grain size of less than 1nm.
18. The semiconductor structure of claim 15, wherein the diameter of the lower electrode is no greater than 40nm.
19. The semiconductor structure of claim 15 or 18, wherein the thickness of the first lower electrode layer in the radial direction of the capacitor hole is 10-15nm, and the thickness of the second lower electrode layer in the radial direction of the capacitor hole is 15-30nm.
20. The semiconductor structure of claim 15, wherein the semiconductor structure further comprises:
a dielectric layer covering the lower electrode and the support structure, and an upper electrode covering the dielectric layer.
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| CN202211091178.2A CN117715408A (en) | 2022-09-07 | 2022-09-07 | Manufacturing method of semiconductor structure and semiconductor structure |
| PCT/CN2022/123898 WO2024050907A1 (en) | 2022-09-07 | 2022-10-08 | Semiconductor structure manufacturing method and semiconductor structure |
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| CN202211091178.2A CN117715408A (en) | 2022-09-07 | 2022-09-07 | Manufacturing method of semiconductor structure and semiconductor structure |
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| CN202211091178.2A Pending CN117715408A (en) | 2022-09-07 | 2022-09-07 | Manufacturing method of semiconductor structure and semiconductor structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN117715408A (en) |
| WO (1) | WO2024050907A1 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100438781B1 (en) * | 2001-12-05 | 2004-07-05 | 삼성전자주식회사 | Metal - Insulator - Metal capacitor and Method for manufacturing the same |
| KR20120042574A (en) * | 2010-10-25 | 2012-05-03 | 에스케이하이닉스 주식회사 | Semiconductor device and method for forming the same |
| CN114520195A (en) * | 2020-11-19 | 2022-05-20 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
| CN114824083A (en) * | 2021-01-29 | 2022-07-29 | 中国科学院微电子研究所 | Semiconductor device and preparation method thereof |
-
2022
- 2022-09-07 CN CN202211091178.2A patent/CN117715408A/en active Pending
- 2022-10-08 WO PCT/CN2022/123898 patent/WO2024050907A1/en unknown
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| Publication number | Publication date |
|---|---|
| WO2024050907A1 (en) | 2024-03-14 |
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