CN117713866A - Medium-power low-additional amplitude modulation multifunctional chip - Google Patents
Medium-power low-additional amplitude modulation multifunctional chip Download PDFInfo
- Publication number
- CN117713866A CN117713866A CN202311755046.XA CN202311755046A CN117713866A CN 117713866 A CN117713866 A CN 117713866A CN 202311755046 A CN202311755046 A CN 202311755046A CN 117713866 A CN117713866 A CN 117713866A
- Authority
- CN
- China
- Prior art keywords
- port
- transistor
- unit
- resistor
- phase shifter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 61
- 230000003321 amplification Effects 0.000 claims description 8
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 8
- 230000010354 integration Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 230000008859 change Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention discloses a middle power low additional amplitude modulation multifunctional chip, which comprises a 1-minute 2 power distributor and two transceiving channels, wherein the input port of a numerical control attenuator unit of each transceiving channel is a chip signal input end, the output port of each transceiving channel is connected with the input port of a middle power receiving amplifier unit, the output port of each receiving amplifier unit is connected with the receiving port of a transceiving switch unit, the public port of each transceiving switch unit is connected with the first port of a numerical control low additional amplitude modulation phase shifter unit, the transmitting port is connected with the input port of a middle power transmitting amplifier unit, and the output port of each transmitting amplifier unit is a chip signal output end; the first port of the power divider is a common port of the chip, and the second port and the third port are respectively connected with the second ports of the numerical control low-additional amplitude modulation phase shifter units of the two transceiving channels. The phase-shifting antenna can output medium-power signals, reduce phase-shifting additional amplitude modulation parameters, improve the integration level of the phased-array antenna, and optimize the performance of side lobes of the antenna.
Description
Technical Field
The invention belongs to the technical field of phased array front end chips, and particularly relates to a middle-power low-additional amplitude modulation multifunctional chip.
Background
In an antenna system of a phased array system, an amplitude-phase multifunctional chip is an important component for carrying out beam forming and has the functions of power distribution, receiving and transmitting channel switching, numerical control phase shifting, numerical control attenuation, radio frequency signal amplification and the like. The conventional multifunctional chip has insufficient power output capability, and needs additional medium power chips to be matched for use, so that the additional amplitude modulation introduced during phase shifting treatment is large, thereby causing the performance deterioration of antenna sidelobes and restricting the development of high performance and high integration of the phased array antenna.
Disclosure of Invention
The invention aims to provide a medium-power low-additional amplitude modulation multifunctional chip which can output medium-power signals, reduce phase-shift additional amplitude modulation parameters, improve the integration level of a phased array antenna and optimize the performance of side lobes of the antenna.
In order to achieve the above object, an aspect of the present invention provides a mid-power low-additional amplitude modulation multifunctional chip, the chip including a 1-to-2 power divider and two transceiver channels, each transceiver channel including a mid-power transmit amplifier unit, a transceiver switch unit, a digitally controlled low-additional amplitude modulation phase shifter unit, a digitally controlled attenuator unit, a mid-power receive amplifier unit;
the receiving and transmitting switch unit is used for switching the receiving and transmitting states of the chip, the numerical control low-additional amplitude modulation phase shifter unit is used for realizing the phase control of the receiving and transmitting channels, the numerical control attenuator unit is used for realizing the amplitude control of the receiving channels, the medium power receiving amplifier unit is used for realizing the signal amplification of the receiving channels, and the medium power transmitting amplifier unit is used for realizing the signal amplification of the transmitting channels;
the input port of the numerical control attenuator unit is a receiving signal input end of the chip, the output port of the numerical control attenuator unit is connected with the input port of the middle power receiving amplifier unit, the output port of the middle power receiving amplifier unit is connected with the receiving port of the receiving and transmitting switch unit, the public port of the receiving and transmitting switch unit is connected with the first port of the numerical control low-additional amplitude modulation phase shifter unit, the transmitting port of the receiving and transmitting switch unit is connected with the input port of the middle power transmitting amplifier unit, and the output port of the middle power transmitting amplifier unit is a transmitting signal output end of the chip;
the first port of the 1-division 2 power divider is a common port of the chip, and the second port and the third port are respectively connected with the second ports of the numerical control low-additional amplitude modulation phase shifter units of the two receiving and transmitting channels.
Preferably, the digitally controlled low add-on amplitude modulation phase shifter unit comprises a 45 degree phase shifter unit, a 22.5 degree phase shifter unit, a 90 degree phase shifter unit, an 11.25 degree phase shifter unit, a 5.625 degree phase shifter unit, a 180 degree phase shifter unit and a first driver unit which are sequentially connected, wherein control ports of the 45 degree phase shifter unit, the 22.5 degree phase shifter unit, the 90 degree phase shifter unit, the 11.25 degree phase shifter unit, the 5.625 degree phase shifter unit and the 180 degree phase shifter unit are all connected with an output port of the first driver unit;
the 45-degree phase shifter unit, the 90-degree phase shifter unit and the 180-degree phase shifter unit adopt a switch Gao Ditong filter structure, and the 22.5-degree phase shifter unit, the 11.25-degree phase shifter unit and the 5.625-degree phase shifter unit adopt T-shaped structures.
Preferably, the 45 degree phase shifter unit, the 90 degree phase shifter unit and the 180 degree phase shifter unit are low additional amplitude modulation digitally controlled phase shifters, and the low additional amplitude modulation digitally controlled phase shifters comprise a radio frequency input port, a radio frequency output port, a first control port, a second control port, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor, a first inductor, a second inductor and a third inductor;
the first port of the first transistor is connected with the first port of the second transistor, the first port of the seventh transistor, the first port of the eighth transistor and the first control port, the second port of the first transistor is connected with the second port of the third transistor and the first port of the first resistor, the third port of the first transistor is connected with the third port of the fifth transistor and the radio frequency input port, the second port of the second transistor is connected with the second port of the fourth transistor and the first port of the second resistor, the third port of the second transistor is connected with the third port of the sixth transistor and the first port of the radio frequency output port, the first port of the first transistor is connected with the second port of the third transistor, the third port of the third transistor is grounded, the third port of the fourth transistor is connected with the second port of the seventh transistor, the second port of the second inductor is connected with the second port of the third inductor, the third port of the third transistor is connected with the third port of the eighth transistor, the third port of the third inductor is connected with the third port of the third inductor, the third port of the third transistor is connected with the third port of the third inductor is grounded.
Preferably, the numerical control attenuator unit comprises a 4dB attenuator unit, a 0.25dB attenuator unit, a 2dB attenuator unit, a 1dB attenuator unit, a 0.5dB attenuator unit, an 8dB attenuator unit and a second driver unit which are sequentially connected, wherein control ports of the 4dB attenuator unit, the 0.25dB attenuator unit, the 2dB attenuator unit, the 1dB attenuator unit, the 0.5dB attenuator unit and the 8dB attenuator unit are all connected with an output port of the second driver unit;
the 0.25dB attenuator unit, the 0.5dB attenuator unit, the 1dB attenuator unit and the 2dB attenuator unit adopt deformed T-shaped structures to realize smaller attenuation values, and the 4dB attenuator unit and the 8dB attenuator unit adopt T-shaped structures to realize larger attenuation values.
Preferably, the transceiver switch unit includes a common port, a third control port, a fourth control port, a fifth control port, a sixth control port, a transmitting port, a receiving port, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, and a thirteenth resistor;
the first port of the ninth transistor is connected with the first port of the third resistor, the second port of the ninth transistor is connected with the second port and the common port of the tenth transistor, the third port of the ninth transistor is connected with the second port of the eleventh transistor, the second port of the twelfth transistor, the second port of the fifteenth transistor, the second port of the sixteenth transistor, the first port of the tenth transistor is connected with the second port of the fourth resistor, the third port of the tenth transistor is connected with the second port of the thirteenth transistor, the second port of the fourteenth transistor, the transmitting port is connected with the first port of the fifth resistor, the first port of the eleventh transistor is connected with the first port of the eleventh resistor, the third port of the eleventh transistor is connected with the ground, the first port of the thirteenth transistor is connected with the third port of the thirteenth resistor, the third port of the thirteenth transistor is connected with the ground, the first port of the thirteenth transistor is connected with the seventeenth port of the thirteenth transistor, the seventeenth port of the seventeenth transistor is connected with the seventeenth port of the seventeenth transistor, the seventeenth transistor is connected with the thirteenth port of the seventeenth transistor, the seventeenth port of the seventeenth transistor is connected with the third port of the seventeenth transistor, the seventeenth transistor is connected with the ground, the seventeenth port of the seventeenth transistor is connected with the third port. The third port of the eighteenth transistor is grounded, the second port of the third resistor is connected with the second port of the seventh resistor, the second port of the eighth resistor and the third control port, the second port of the fourth resistor is connected with the second port of the fifth resistor, the second port of the sixth resistor and the fourth control port, the second port of the ninth resistor is connected with the second port of the eleventh resistor and the fifth control port, and the second port of the tenth resistor is connected with the second port of the twelfth resistor and the sixth control port.
Preferably, the medium power transmitting amplifier unit adopts a cascade amplifying structure of a common source common gate amplifier and a common source amplifier;
the common-source common-gate amplifier comprises a PVT compensation bias circuit, wherein the PVT compensation bias circuit is connected with a gate voltage port of the common-source common-gate amplifier and provides bias voltage for the common-source common-gate amplifier;
the power port of the common-source common-gate amplifier is connected with the power port of the common-source amplifier, the input port of the common-source common-gate amplifier is the input port of the medium-power transmitting amplifier unit, the output port of the common-source common-gate amplifier is connected with the input port of the common-source amplifier, and the output port of the common-source amplifier is the output port of the medium-power transmitting amplifier unit.
Preferably, the middle power receiving amplifier unit adopts a self-bias common source amplifying structure and comprises a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a fourth inductor, a fifth inductor, a sixth inductor, a seventh inductor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a nineteenth transistor;
the first port of the fourth capacitor is connected with the second port of the numerical control attenuator unit, the second port of the fourth capacitor is connected with the first port of the fourth inductor, the first port of the fourteenth resistor and the first port of the fifth capacitor, the second port of the fourth inductor is grounded, the second port of the fourteenth resistor is connected with the second port of the fifth capacitor, the first port of the sixteenth resistor and the first port of the nineteenth transistor, the second port of the sixteenth resistor is connected with the first port of the seventh capacitor, the second port of the nineteenth transistor is connected with the first port of the sixth capacitor, the first port of the fifteenth resistor is connected with the second port of the fifteenth resistor and grounded, the third port of the nineteenth transistor is connected with the first port of the fifth inductor, the second port of the seventh inductor is connected with the second port of the seventh capacitor, the first port of the seventh inductor is connected with the power supply port, the second port of the seventh inductor is connected with the eighth port of the eighth capacitor, and the eighth port of the eighth capacitor is connected with the eighth port of the eighth capacitor.
The medium-power low-additional amplitude modulation multifunctional chip can output medium-power signals, reduce phase-shift additional amplitude modulation parameters, improve the integration level of the phased array antenna and optimize the side lobe performance of the antenna.
Drawings
The following describes the embodiments of the present invention in further detail with reference to the drawings.
FIG. 1 is a schematic diagram of a medium power low add-on AM multifunction chip according to one embodiment of the invention.
Fig. 2 is a schematic diagram of the structure of a digitally controlled low add-on amplitude shifter unit according to one embodiment of the present invention.
Fig. 3 is a circuit diagram of a low add-on amplitude modulation digitally controlled phase shifter according to one embodiment of the present invention.
Fig. 4 is a schematic structural view of a digitally controlled attenuator unit according to an embodiment of the present invention.
Fig. 5 is a circuit diagram of a transceiving switching unit according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a medium power transmit amplifier unit according to one embodiment of the invention.
Fig. 7 is a circuit diagram of a medium power receive amplifier unit in one embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. Like parts in the drawings are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and that this invention is not limited to the details given herein.
An embodiment of the present invention provides a mid-power low-additional amplitude modulation multifunctional chip, as shown in fig. 1, where the mid-power low-additional amplitude modulation multifunctional chip of the embodiment of the present invention includes a 1-to-2 power divider and two transceiver channels, each transceiver channel includes a mid-power transmit amplifier unit, a transceiver switch unit, a digitally controlled low-additional amplitude modulation phase shifter unit, a digitally controlled attenuator unit, and a mid-power receive amplifier unit.
The receiving and transmitting switch unit is used for switching the receiving and transmitting states of the chip, the numerical control low-additional amplitude modulation phase shifter unit is used for realizing the phase control of the receiving and transmitting channels, the numerical control attenuator unit is used for realizing the amplitude control of the receiving channels, the medium power receiving amplifier unit is used for realizing the signal amplification of the receiving channels, and the medium power transmitting amplifier unit is used for realizing the signal amplification of the transmitting channels.
The first port of the 1-division 2 power divider is a common port of the chip, and the second port and the third port are respectively connected with the second ports (input ports) of the numerical control low-additional amplitude modulation phase shifter units of the two transceiving channels.
In the receiving channel, the input port of the numerical control attenuator unit is the receiving signal input end of the chip, the output port of the numerical control attenuator unit is connected with the input port of the middle power receiving amplifier unit, the output port of the middle power receiving amplifier unit is connected with the receiving port of the receiving and transmitting switch unit, and the public port of the receiving and transmitting switch unit is connected with the first port (output port) of the numerical control low additional amplitude modulation phase shifter unit.
In the transmitting channel, the 1-division 2 power divider and the numerical control low-additional amplitude modulation phase shifter unit are connected in the same way as the receiving channel. The transmitting port of the receiving and transmitting switch unit is connected with the input port of the middle power transmitting amplifier unit, and the output port of the middle power transmitting amplifier unit is a transmitting signal output end of the chip.
Preferably, the digitally controlled low additional amplitude modulation phase shifter unit is a six bit digitally controlled low additional amplitude modulation phase shifter unit and the digitally controlled attenuator unit is a six bit digitally controlled attenuator unit.
As shown in fig. 2, the digitally controlled low add-on amplitude-modulation phase shifter unit comprises a 45 degree phase shifter unit, a 22.5 degree phase shifter unit, a 90 degree phase shifter unit, an 11.25 degree phase shifter unit, a 5.625 degree phase shifter unit, a 180 degree phase shifter unit and a first driver unit which are connected in sequence, wherein control ports of all the phase shifter units are connected with output ports of the driver unit.
The 45-degree phase shifter unit, the 90-degree phase shifter unit and the 180-degree phase shifter unit use a switch high-low pass filter structure, and a signal path is converted through a switch transistor, so that a high-pass filter and a low-pass filter are selected, and phase change of signals under different states is realized. The 22.5-degree phase shifter unit, the 11.25-degree phase shifter unit and the 5.625-degree phase shifter unit adopt T-shaped structures, and the through path and the T-shaped phase shifting path of signals are switched by the switching transistor, so that the phase change of the signals in different states is realized.
The 45 degree phase shifter unit, the 90 degree phase shifter unit and the 180 degree phase shifter unit are low additional amplitude modulation numerical control phase shifters, and as shown in fig. 3, the low additional amplitude modulation numerical control phase shifters comprise a radio frequency input port RF in RF output port RF out The first control port (P control signal) SWP, the second control port (N control signal) SWN, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the first resistor R1, the second resistor R2, the first capacitor C1, the second capacitor C2, the third capacitor C3, the first inductor L1, the second inductor L2, and the third inductor L3.
Wherein the first port of the first transistor M1 is connected with the first port of the second transistor M2, the first port of the seventh transistor M7, the first port of the eighth transistor M8 and the first control port SWP, the second port of the first transistor M1 is connected with the second port of the third transistor M3 and the first port of the first resistor R1, the third port of the first transistor M1 is connected with the third port of the fifth transistor M5 and the radio frequency input portRF in A second port of the second transistor M2 is connected with a second port of the fourth transistor M4 and a first port of the second resistor R2, a third port of the second transistor M2 is connected with a third port of the sixth transistor M6 and a radio frequency output port RF out The first port of the third transistor M3 is connected to the first port of the fourth transistor M4, the first port of the fifth transistor M5, the first port of the sixth transistor M6, the second control port SWN, the third port of the third transistor M3 is grounded, the third port of the fourth transistor M4 is grounded, the second port of the fifth transistor M5 is connected to the second port of the seventh transistor M7, the first port of the second inductor L2, the second port of the sixth transistor M6 is connected to the second port of the eighth transistor M8, the first port of the third inductor L3, the third port of the seventh transistor M7 is grounded, the second port of the first resistor R1 is connected to the first port of the first capacitor C1, the second port of the second capacitor R2 is connected to the first port of the second capacitor C2, the second port of the first capacitor C1 is connected to the second port of the second capacitor C2, the third port of the third capacitor C3 is connected to the second port of the third capacitor C3, and the third port of the third capacitor C3 is connected to the ground.
As shown in fig. 4, the digitally controlled attenuator unit includes a 4dB attenuator unit, a 0.25dB attenuator unit, a 2dB attenuator unit, a 1dB attenuator unit, a 0.5dB attenuator unit, an 8dB attenuator unit, and a second driver unit, which are sequentially connected, and control ports of all the attenuator units are connected to output ports of the second driver unit.
The 0.25dB attenuator unit, the 0.5dB attenuator unit, the 1dB attenuator unit and the 2dB attenuator unit adopt deformed T-shaped structures, the path branches of the structures are communicated by using microstrip lines, the resistances of the bypass branches of the T-shaped structures of the transistor switches are used for switching the attenuation values of the signal paths, and smaller attenuation values can be realized; the 4dB attenuator unit and the 8dB attenuator unit adopt T-shaped attenuation switching structures, and the structures can realize larger attenuation values by switching a low-loss microstrip line straight-through path and a high-loss T-shaped resistance attenuation path through a switching transistor.
As shown in fig. 5, the transceiver switch unit adopts a double-pole triple-throw structure, and includes a common port COM, a third control port SW1N, a fourth control port SW1P, a fifth control port SW2N, a sixth control port SW2P, a transmitting port T, a receiving port R, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13.
Wherein the first port of the ninth transistor M9 is connected to the first port of the third resistor R3, the second port of the ninth transistor M9 is connected to the second port of the tenth transistor M10, the common port COM, the third port of the ninth transistor M9 is connected to the second port of the eleventh transistor M11, the second port of the twelfth transistor M12, the second port of the fifteenth transistor M15, the second port of the sixteenth transistor M16, the first port of the tenth transistor M10 is connected to the second port of the fourth resistor R4, the third port of the tenth transistor M10 is connected to the second port of the thirteenth transistor M13, the second port of the fourteenth transistor M14, the emission port T, the first port of the eleventh transistor M11 is connected to the first port of the fifth resistor R5, the third port of the eleventh transistor M11 is grounded, the first port of the twelfth transistor M12 is connected to the first port of the sixth resistor R6, the third port of the twelfth transistor M12 is grounded, the first port of the thirteenth transistor M13 is connected to the first port of the seventh resistor R7, the third port of the thirteenth transistor M13 is grounded, the first port of the fourteenth transistor M14 is connected to the first port of the eighth resistor R8, the third port of the fourteenth transistor M14 is grounded, the first port of the fifteenth transistor M15 is connected to the first port of the ninth resistor R9, the third port of the fifteenth transistor M15 is connected to the second port of the eighteenth resistor M18, the receiving port R, the first port of the sixteenth transistor M16 is connected to the first port of the tenth resistor R10, the third port of the sixteenth transistor M16 is connected to the second port of the seventeenth transistor M17, the first port of the thirteenth resistor R13 is connected to the first port of the seventeenth resistor R11, the third port of the seventeenth transistor M17 is connected to the second port of the thirteenth resistor R13 and grounded, the first port of the eighteenth transistor M18 is connected to the first port of the twelfth resistor R12, the third port of the eighteenth transistor M18 is grounded, the second port of the third resistor R3 is connected to the second port of the seventh resistor R7, the second port of the eighth resistor R8, and the third control port SW1N, the second port of the fourth resistor R4 is connected to the second port of the fifth resistor R5, the second port of the sixth resistor R6, and the fourth control port SW1P, the second port of the ninth resistor R9 is connected to the second port of the eleventh resistor R11, and the fifth control port SW2N, and the second port of the tenth resistor R10 is connected to the second port of the twelfth resistor R12 and the sixth control port SW 2P. The third to sixth control ports SW1N, SW1P, SW2N, SW P may be connected to output ports of the other driver units, respectively.
As shown in fig. 6, the mid-power transmit amplifier unit employs a cascode configuration of cascode and cascode amplifiers, the unit having a power supply port VDD, an input port RF in Output port RF out The method comprises the steps of carrying out a first treatment on the surface of the The cascode amplifier comprises a power supply port, an input port and an output port, and comprises a PVT compensation bias circuit with a Process Voltage Temperature (PVT) compensation function; the common source amplifier comprises a power supply port, an input port and an output port, and the direct current bias of the amplifier is realized through a self-bias circuit.
The power port of the common-source common-gate amplifier is connected with the power port of the common-source amplifier, the PVT compensation bias circuit is connected with the gate voltage port of the common-source common-gate amplifier to provide bias voltage for the common-source common-gate amplifier, the input port of the common-source common-gate amplifier is the input port of the medium-power transmitting amplifier unit, the output port of the common-source common-gate amplifier is connected with the input port of the common-source amplifier, and the output port of the common-source amplifier is the output port of the medium-power transmitting amplifier unit.
As shown in fig. 7, the middle power receiving amplifier unit adopts a self-bias common source amplifying structure, and includes a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, a seventh inductor L7, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, and a nineteenth transistor M19.
Wherein the first port of the fourth capacitor C4 is connected to the second port of the digitally controlled attenuator unit, the second port of the fourth capacitor C4 is connected to the first port of the fourth inductor L4, the first port of the fourteenth resistor R14, the first port of the fifth capacitor C5, the second port of the fourth inductor L4 is grounded, the second port of the fourteenth resistor R14 is connected to the second port of the fifth capacitor C5, the first port of the sixteenth resistor R16, the first port of the nineteenth transistor M19, the second port of the sixteenth resistor R16 is connected to the first port of the seventh capacitor C7, the first port of the fifteenth resistor R15 is connected to the second port of the fifteenth resistor R15, the third port of the ninth transistor M19 is connected to the first port of the fifth inductor L5, the second port of the fifth inductor L5 is connected to the first port of the seventh inductor C7, the first port of the eighth inductor C7, the seventh port of the eighth transistor M19 is connected to the first port of the eighth inductor C7, the eighth port of the eighth inductor C8, the eighth port of the eighth inductor C7 is connected to the eighth port of the eighth inductor C7, the eighth port of the eighth inductor C8 out The second port of the ninth capacitor C9 is connected to ground.
The medium-power low-additional amplitude modulation multifunctional chip provided by the embodiment of the invention can realize the functions of dual-channel receiving and transmitting switching, high-precision amplitude control, low-additional amplitude modulation phase control, medium-power amplification and the like, can improve antenna sidelobe suppression and output medium-power signals, and realizes the high-performance and high-integration development of a phased array antenna.
While certain exemplary embodiments of the present invention have been described above by way of illustration only, it will be apparent to those of ordinary skill in the art that modifications may be made to the described embodiments in various different ways without departing from the spirit and scope of the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive of the scope of the invention, which is defined by the appended claims.
Claims (7)
1. The chip is characterized by comprising a 1-minute 2 power distributor and two transceiving channels, wherein each transceiving channel comprises a medium power transmitting amplifier unit, a transceiving switch unit, a numerical control low-additional amplitude modulation phase shifter unit, a numerical control attenuator unit and a medium power receiving amplifier unit;
the receiving and transmitting switch unit is used for switching the receiving and transmitting states of the chip, the numerical control low-additional amplitude modulation phase shifter unit is used for realizing the phase control of the receiving and transmitting channels, the numerical control attenuator unit is used for realizing the amplitude control of the receiving channels, the medium power receiving amplifier unit is used for realizing the signal amplification of the receiving channels, and the medium power transmitting amplifier unit is used for realizing the signal amplification of the transmitting channels;
the input port of the numerical control attenuator unit is a receiving signal input end of the chip, the output port of the numerical control attenuator unit is connected with the input port of the middle power receiving amplifier unit, the output port of the middle power receiving amplifier unit is connected with the receiving port of the receiving and transmitting switch unit, the public port of the receiving and transmitting switch unit is connected with the first port of the numerical control low-additional amplitude modulation phase shifter unit, the transmitting port of the receiving and transmitting switch unit is connected with the input port of the middle power transmitting amplifier unit, and the output port of the middle power transmitting amplifier unit is a transmitting signal output end of the chip;
the first port of the 1-division 2 power divider is a common port of the chip, and the second port and the third port are respectively connected with the second ports of the numerical control low-additional amplitude modulation phase shifter units of the two receiving and transmitting channels.
2. The chip of claim 1, wherein the digitally controlled low add-on amplitude-modulation phase shifter unit comprises a 45 degree phase shifter unit, a 22.5 degree phase shifter unit, a 90 degree phase shifter unit, an 11.25 degree phase shifter unit, a 5.625 degree phase shifter unit, a 180 degree phase shifter unit, and a first driver unit connected in sequence, wherein control ports of the 45 degree phase shifter unit, the 22.5 degree phase shifter unit, the 90 degree phase shifter unit, the 11.25 degree phase shifter unit, the 5.625 degree phase shifter unit, and the 180 degree phase shifter unit are all connected to an output port of the first driver unit;
the 45-degree phase shifter unit, the 90-degree phase shifter unit and the 180-degree phase shifter unit adopt a switch Gao Ditong filter structure, and the 22.5-degree phase shifter unit, the 11.25-degree phase shifter unit and the 5.625-degree phase shifter unit adopt T-shaped structures.
3. The chip of claim 2, wherein the 45 degree phase shifter element, the 90 degree phase shifter element, and the 180 degree phase shifter element are low additional amplitude modulation digitally controlled phase shifters comprising a radio frequency input port, a radio frequency output port, a first control port, a second control port, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor, a first inductor, a second inductor, a third inductor;
the first port of the first transistor is connected with the first port of the second transistor, the first port of the seventh transistor, the first port of the eighth transistor and the first control port, the second port of the first transistor is connected with the second port of the third transistor and the first port of the first resistor, the third port of the first transistor is connected with the third port of the fifth transistor and the radio frequency input port, the second port of the second transistor is connected with the second port of the fourth transistor and the first port of the second resistor, the third port of the second transistor is connected with the third port of the sixth transistor and the first port of the radio frequency output port, the first port of the first transistor is connected with the second port of the third transistor, the third port of the third transistor is grounded, the third port of the fourth transistor is connected with the second port of the seventh transistor, the second port of the second inductor is connected with the second port of the third inductor, the third port of the third transistor is connected with the third port of the eighth transistor, the third port of the third inductor is connected with the third port of the third inductor, the third port of the third transistor is connected with the third port of the third inductor is grounded.
4. A chip according to any one of claims 1-3, wherein the digitally controlled attenuator unit comprises a 4dB attenuator unit, a 0.25dB attenuator unit, a 2dB attenuator unit, a 1dB attenuator unit, a 0.5dB attenuator unit, an 8dB attenuator unit and a second driver unit, which are connected in sequence, wherein the control ports of the 4dB attenuator unit, the 0.25dB attenuator unit, the 2dB attenuator unit, the 1dB attenuator unit, the 0.5dB attenuator unit and the 8dB attenuator unit are all connected with the output port of the second driver unit;
the 0.25dB attenuator unit, the 0.5dB attenuator unit, the 1dB attenuator unit and the 2dB attenuator unit adopt deformed T-shaped structures to realize smaller attenuation values, and the 4dB attenuator unit and the 8dB attenuator unit adopt T-shaped structures to realize larger attenuation values.
5. The chip of any one of claims 1-4, wherein the transceiver switch unit includes a common port, a third control port, a fourth control port, a fifth control port, a sixth control port, a transmit port, a receive port, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor;
the first port of the ninth transistor is connected with the first port of the third resistor, the second port of the ninth transistor is connected with the second port and the common port of the tenth transistor, the third port of the ninth transistor is connected with the second port of the eleventh transistor, the second port of the twelfth transistor, the second port of the fifteenth transistor, the second port of the sixteenth transistor, the first port of the tenth transistor is connected with the second port of the fourth resistor, the third port of the tenth transistor is connected with the second port of the thirteenth transistor, the second port of the fourteenth transistor, the transmitting port is connected with the first port of the fifth resistor, the first port of the eleventh transistor is connected with the first port of the eleventh resistor, the third port of the eleventh transistor is connected with the ground, the first port of the thirteenth transistor is connected with the third port of the thirteenth resistor, the third port of the thirteenth transistor is connected with the ground, the first port of the thirteenth transistor is connected with the seventeenth port of the thirteenth transistor, the seventeenth port of the seventeenth transistor is connected with the seventeenth port of the seventeenth transistor, the seventeenth transistor is connected with the thirteenth port of the seventeenth transistor, the seventeenth port of the seventeenth transistor is connected with the third port of the seventeenth transistor, the seventeenth transistor is connected with the ground, the seventeenth port of the seventeenth transistor is connected with the third port. The third port of the eighteenth transistor is grounded, the second port of the third resistor is connected with the second port of the seventh resistor, the second port of the eighth resistor and the third control port, the second port of the fourth resistor is connected with the second port of the fifth resistor, the second port of the sixth resistor and the fourth control port, the second port of the ninth resistor is connected with the second port of the eleventh resistor and the fifth control port, and the second port of the tenth resistor is connected with the second port of the twelfth resistor and the sixth control port.
6. The chip of any one of claims 1-5, wherein the mid-power transmit amplifier unit employs a cascode amplifier and cascode amplifier configuration;
the common-source common-gate amplifier comprises a PVT compensation bias circuit, wherein the PVT compensation bias circuit is connected with a gate voltage port of the common-source common-gate amplifier and provides bias voltage for the common-source common-gate amplifier;
the power port of the common-source common-gate amplifier is connected with the power port of the common-source amplifier, the input port of the common-source common-gate amplifier is the input port of the medium-power transmitting amplifier unit, the output port of the common-source common-gate amplifier is connected with the input port of the common-source amplifier, and the output port of the common-source amplifier is the output port of the medium-power transmitting amplifier unit.
7. The chip of any one of claims 1-6, wherein the medium power receiving amplifier unit adopts a self-bias common source amplifying structure, and includes a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a fourth inductor, a fifth inductor, a sixth inductor, a seventh inductor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, and a nineteenth transistor;
the first port of the fourth capacitor is connected with the second port of the numerical control attenuator unit, the second port of the fourth capacitor is connected with the first port of the fourth inductor, the first port of the fourteenth resistor and the first port of the fifth capacitor, the second port of the fourth inductor is grounded, the second port of the fourteenth resistor is connected with the second port of the fifth capacitor, the first port of the sixteenth resistor and the first port of the nineteenth transistor, the second port of the sixteenth resistor is connected with the first port of the seventh capacitor, the second port of the nineteenth transistor is connected with the first port of the sixth capacitor, the first port of the fifteenth resistor is connected with the second port of the fifteenth resistor and grounded, the third port of the nineteenth transistor is connected with the first port of the fifth inductor, the second port of the seventh inductor is connected with the second port of the seventh capacitor, the first port of the seventh inductor is connected with the power supply port, the second port of the seventh inductor is connected with the eighth port of the eighth capacitor, and the eighth port of the eighth capacitor is connected with the eighth port of the eighth capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311755046.XA CN117713866A (en) | 2023-12-19 | 2023-12-19 | Medium-power low-additional amplitude modulation multifunctional chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311755046.XA CN117713866A (en) | 2023-12-19 | 2023-12-19 | Medium-power low-additional amplitude modulation multifunctional chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117713866A true CN117713866A (en) | 2024-03-15 |
Family
ID=90144077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311755046.XA Pending CN117713866A (en) | 2023-12-19 | 2023-12-19 | Medium-power low-additional amplitude modulation multifunctional chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117713866A (en) |
-
2023
- 2023-12-19 CN CN202311755046.XA patent/CN117713866A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2021196404A1 (en) | Low phase deviation digital-controlled radio frequency attenuator | |
| CN110380708B (en) | Ultra-wideband amplitude-phase compensation digital switch attenuator circuit | |
| EP4080765A1 (en) | Ultra-wideband two-phase phase shifter | |
| WO2021098196A1 (en) | Ultra-wideband attenuator | |
| CN113794453B (en) | Multi-mode high-efficiency MMIC power amplifier and implementation method thereof | |
| CN110190830B (en) | Dual-band miniaturized digital phase shifter | |
| WO2021098195A1 (en) | High-frequency switch-type phase shifter | |
| US6806792B2 (en) | Broadband, four-bit, MMIC phase shifter | |
| CN114826174B (en) | Microwave power amplifier capable of realizing polarization mode selection | |
| CN111082773B (en) | X/Ku wave band amplitude-phase control transceiver chip | |
| Alhamed et al. | A multi-standard 15-57 GHz 4-channel receive beamformer with 4.8 dB midband NF for 5G applications | |
| CN117713866A (en) | Medium-power low-additional amplitude modulation multifunctional chip | |
| Zhou et al. | A Ka-band low power consumption MMIC core chip for T/R modules | |
| CN112350686A (en) | Differential numerical control attenuator based on inductance compensation | |
| CN115765679A (en) | Low-additional-phase-shift numerical control attenuator with amplitude calibration function and design method | |
| CN113193851B (en) | Numerical control phase shifter for X wave band | |
| JP4211128B2 (en) | Multi-channel high-frequency signal supply device | |
| CN110957993A (en) | Terahertz full 360-degree reflection-type phase shifter based on SiGe process | |
| CN113824466A (en) | Ultra-wideband radio frequency transceiving switch adopting novel clamping resistor | |
| CN114244316A (en) | Broadband switch control attenuation unit and broadband switch type attenuator | |
| CN114389571A (en) | Broadband switch control attenuation unit and broadband switch type attenuator | |
| Sayginer et al. | An 8-element 2–16 GHz phased array receiver with reconfigurable number of beams in SiGe BiCMOS | |
| JPH0583086A (en) | Analog variable phase shifter for microwave signal | |
| Koh et al. | A Q-band (40–45 GHz) 16-element phased-array transmitter in 0.18-μm SiGe BiCMOS technology | |
| RU2802412C1 (en) | Ultra-wideband double discharge phase shifter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |