CN117713807A

CN117713807A - Delay phase-locked loop circuit and multi-phase clock signal duty cycle adjustment method

Info

Publication number: CN117713807A
Application number: CN202311730183.8A
Authority: CN
Inventors: 黄景林; 张亮; 李伟; 沈旭真; 宁志华; 郑志恒
Original assignee: Hangzhou Silan Microelectronics Co Ltd
Current assignee: Hangzhou Silan Microelectronics Co Ltd
Priority date: 2023-12-15
Filing date: 2023-12-15
Publication date: 2024-03-15

Abstract

The invention discloses a delay phase-locked loop circuit and a multi-phase clock signal duty ratio adjusting method. Comprising the following steps: the pulse width adjusting circuit is used for converting an input clock signal into a reference clock signal, and the pulse width of the reference clock signal is smaller than that of the input clock signal; a voltage controlled delay line for generating a plurality of delayed clock signals of a reference clock signal; a control loop for feedback-controlling delay times of the voltage-controlled delay lines according to the plurality of delay clock signals so that delays of rising edges of the plurality of delay clock signals are kept uniform; and the pulse width recovery circuit is used for obtaining a frequency multiplication signal according to the plurality of delay clock signals and carrying out frequency division processing on the frequency multiplication signal to obtain an output clock signal with a set first duty ratio. The delay phase-locked loop circuit can ensure that the duty ratio of an output clock signal is maintained at 50%, can avoid abnormal operation of some applications with specific requirements on the signal duty ratio, and is beneficial to improving the stability and the reliability of a system.

Description

Delay phase-locked loop circuit and multi-phase clock signal duty cycle adjustment method

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a delay phase-locked loop circuit and a multi-phase clock signal duty ratio adjustment method.

Background

In general, a clock signal is widely used as a signal for synchronizing operation timings of a semiconductor device. When a clock signal applied from an external device is used inside a semiconductor device, a delay or clock skew caused by an internal circuit may be generated. Delay locked loop (Delay Locked Loop, DLL) circuits can perform the function of synchronizing an internal clock signal with an external clock signal by compensating for such delays. In particular, DLL circuits are widely used in synchronous memory devices, such as Synchronous Dynamic Random Access Memories (SDRAM), which require synchronous operations for clock signals.

However, in most applications, it is required that not only the internal clock signal and the external clock signal have the same frequency, but also they have the same Duty Cycle, and that the Duty Cycle can be maintained at 50% most of the time. The DLL circuit generally includes a phase detector, a charge pump, a loop filter, and a Voltage Controlled Delay Line (VCDL), the input of which is a clock signal of 50% duty ratio, and as the operation speed of a semiconductor device increases, a phenomenon in which the clock signal is distorted such that the duty ratio of the clock signal cannot be maintained at 50% through a multi-stage delay unit often occurs, which may result in abnormal operation of a Double Data Rate (DDR) SDRAM using both a rising edge and a falling edge of the clock signal. Therefore, in many applications, the DLL circuit is required to perform not only phase locking of the synchronous clock signal but also Duty Cycle Correction (DCC) operations, but these schemes require additional circuit designs to correct the duty cycle variation generated by the delay line, increasing circuit cost and power consumption. Also, in the case where DCC and phase locking are simultaneously performed, DCC may affect phase locking, resulting in an operation error.

Disclosure of Invention

In order to solve the technical problems, the invention provides a delay phase-locked loop circuit and a multi-phase clock signal duty cycle adjusting method, which can ensure that the duty cycle of an output clock signal can be maintained at 50%, and improve the stability and reliability of a system.

According to an aspect of the present invention, there is provided a delay locked loop circuit comprising: the pulse width adjusting circuit is used for converting an input clock signal into a reference clock signal, and the pulse width of the reference clock signal is smaller than that of the input clock signal; a voltage-controlled delay line which receives the reference clock signal and the control signal, generates a plurality of delayed clock signals of the reference clock signal according to the reference clock signal and the control signal, and feeds back two delayed clock signals with a phase difference of 360 degrees in the plurality of delayed clock signals to a control loop as feedback signals; a control loop for receiving the feedback signal and outputting the control signal to the voltage-controlled delay line according to the feedback signal; and a pulse width recovery circuit receiving the plurality of delayed clock signals and generating a plurality of output clock signals having a first duty cycle from every two delayed clock signals 180 ° out of phase.

Optionally, the pulse width adjustment circuit includes: a first D flip-flop having a first input terminal for receiving a power supply voltage, a first clock terminal for receiving the input clock signal, a first output terminal for outputting the reference clock signal, and a first reset terminal; and a delay for delaying the reference clock signal to obtain a reset signal applied to the first reset terminal of the first D flip-flop.

Optionally, the pulse width adjustment circuit further includes: and the first buffer is connected with the first output end of the first D trigger and used for buffering and outputting the reference clock signal.

Optionally, the pulse width adjustment circuit is configured to control the second duty cycle of the reference clock signal by setting an internal delay of the first D flip-flop and a delay provided by the delay.

Optionally, the pulse width recovery circuit includes a plurality of pulse width recovery units, where an input of each pulse width recovery unit is configured to receive a first delayed clock signal and a second delayed clock signal with a phase difference of 180 ° from the plurality of delayed clock signals, perform frequency multiplication according to the first delayed clock signal and the second delayed clock signal to obtain a frequency multiplication signal, and perform the frequency division processing on the frequency multiplication signal to obtain output clock signals corresponding to the first delayed clock signal and the second delayed clock signal.

Optionally, each pulse width recovery unit includes: an or circuit having an input for receiving the first and second delayed clock signals and an output for outputting the multiplied signal; a second D flip-flop having a second input terminal for receiving a power supply voltage, a second clock terminal for receiving an inverted signal of the first delayed clock signal, and a second output terminal for outputting a second flip-flop signal; a third D flip-flop having a third input terminal for receiving a power supply voltage, a third clock terminal for receiving an inverted signal of the second delayed clock signal, and a third output terminal for outputting a third flip-flop signal; a fourth D flip-flop having a second reset terminal for receiving the second flip-flop signal, a fourth clock terminal for receiving the multiplied signal, a fourth input terminal and a first negative input terminal shorted to each other, and a first positive output terminal for providing an output clock signal corresponding to the first delayed clock signal; a fifth D flip-flop having a third reset terminal for receiving the third flip-flop signal, a fifth clock terminal for receiving the multiplied signal, a fifth input terminal and a second negative input terminal shorted to each other, and a second positive output terminal for providing an output clock signal corresponding to the second delayed clock signal.

Optionally, each pulse width recovery unit further includes: a first inverter for receiving a first delayed clock signal and outputting an inverted signal of the first delayed clock signal; a second inverter for receiving a second delayed clock signal and outputting an inverted signal of the second delayed clock signal; the second buffer is connected with the first positive output end of the fourth D trigger and is used for buffering and outputting an output clock signal corresponding to the first delay clock signal; and the third buffer is connected with the second positive output end of the fifth D trigger and is used for buffering and outputting the output clock signal corresponding to the second delay clock signal.

Optionally, the second reset terminal of the fourth D flip-flop and the third reset terminal of the fifth D flip-flop are configured to trigger reset when in low level, and enable operation when in high level.

Optionally, the fourth D flip-flop and the fifth D flip-flop are configured to enable operation when the second flip-flop signal and the third flip-flop signal are at a high level, respectively, and trigger flip-flop at a rising edge of the multiplied signal, so as to obtain output clock signals corresponding to the first delay clock signal and the second delay clock signal, respectively.

Optionally, the pulse width recovery circuit is configured to trigger the corresponding output clock signal flip of every two 180 ° phase difference according to the trigger edges of every two 180 ° phase difference delayed clock signals, and the time interval of the trigger edges of every two 180 ° phase difference delayed clock signals is half period of the corresponding output clock signal of every two 180 ° phase difference.

Optionally, the plurality of output clock signals output by the pulse width recovery circuit are sequentially delayed by 1/N cycles, where N represents the number of the plurality of delayed clock signals input to the pulse width recovery circuit, and N is an integer greater than or equal to 2.

Optionally, the control loop includes a phase detector for comparing third and fourth delayed clock signals having a phase difference of 360 ° among the plurality of delayed clock signals to generate a charge control signal or a discharge control signal of the charge pump, a charge pump for generating a current output signal according to the charge control signal or the discharge control signal, and a filter for generating a direct current voltage for controlling a delay time of the voltage controlled delay line according to the current output signal.

Optionally, the filter is a low pass filter.

Optionally, the first duty cycle is equal to 50%.

Optionally, the duty cycle of the input clock signal is the same as or different from the duty cycle of the output clock signal.

Optionally, the plurality of delayed clock signals are sequentially delayed by 1/N cycles, where N represents the number of the plurality of delayed clock signals input to the pulse width recovery circuit, and N is an integer greater than or equal to 2.

According to another aspect of the present invention, there is provided a multi-phase clock signal duty cycle adjustment method, including: converting an input clock signal into a reference clock signal, wherein the pulse width of the reference clock signal is smaller than that of the input clock signal; generating a plurality of delayed clock signals of the reference clock signal according to the reference clock signal and the control signal, and feeding back two delayed clock signals with a phase difference of 360 degrees in the plurality of delayed clock signals to the control loop as feedback signals; outputting the control signal to a voltage-controlled delay line according to the feedback signal; and generating a plurality of output clock signals having a first duty cycle from each two delayed clock signals 180 ° out of phase.

Optionally, the generating the output clock signal with the first duty cycle from each two delayed clock signals 180 ° out of phase comprises: obtaining a frequency multiplication signal according to every two delayed clock signals with the phase difference of 180 degrees, and carrying out frequency division processing on the frequency multiplication signal to obtain an output clock signal with a first duty ratio.

Optionally, the generating the output clock signal with the first duty cycle from each two delayed clock signals 180 ° out of phase comprises: according to the triggering edges of every two delayed clock signals with the phase difference of 180 degrees, triggering the corresponding every two output clock signals with the phase difference of 180 degrees to turn over, wherein the time interval of the triggering edges of every two delayed clock signals with the phase difference of 180 degrees is the half period of the corresponding every two output clock signals with the phase difference of 180 degrees.

Optionally, the first duty cycle is equal to 50%.

In summary, the delay locked loop circuit of the present invention converts an input clock signal with a certain pulse width into a pulse signal with a narrow pulse width according to a trigger edge of the input clock signal by the pulse width adjustment circuit, so that the voltage controlled delay line can generate a plurality of delay clock signals based on the pulse signal, and then obtains a frequency multiplication signal according to the plurality of delay clock signals by using the pulse width recovery circuit, and performs a divide-by-two processing on the frequency multiplication signal, thereby obtaining an output square wave signal with a duty ratio of 50%.

The delay phase-locked loop circuit can obtain an output clock signal with a constant 50% duty cycle, thereby overcoming the problem of distortion of the transmission duty cycle of a delay line of the DLL circuit, avoiding abnormal operation of certain systems with requirements on the signal duty cycle when being applied to the systems, and being beneficial to improving the stability and the reliability of the systems.

In addition, the output clock signal is not obtained by respectively delaying the rising edge and the falling edge of the input clock signal, but triggers the turning of the output clock signal according to the single edge of the delay clock signal, so that only a certain single edge delay of the delay clock signal is consistent, and the delay time of the two edges is not required to be the same.

In addition, the delay phase-locked loop circuit of the invention uses the pulse width adjusting circuit and the pulse width recovering circuit to overcome the problem of the distortion of the transmission duty ratio of the voltage-controlled delay line, compared with the prior art, only the rising edge delay time of the output waveform of the voltage-controlled delay line is consistent, thereby relaxing the requirement on the voltage-controlled delay line, and being beneficial to simplifying the design, reducing the cost and improving the compatibility of the system.

In addition, the single edge in the delay phase-locked loop circuit is a rising edge or a falling edge, when the trigger in the pulse width recovery circuit is a rising edge trigger, the rising edge delay time is consistent, and when the trigger in the pulse width recovery circuit is a falling edge trigger, the falling edge delay time is consistent.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 shows a block diagram of a prior art delay locked loop circuit.

Fig. 2 shows a schematic block diagram of a prior art voltage controlled delay line.

Fig. 3 shows a multiphase clock output waveform diagram of a prior art voltage controlled delay line.

Fig. 4 shows a block diagram of a delay locked loop circuit according to an embodiment of the present invention.

Fig. 5 shows an output waveform of a delay locked loop circuit according to an embodiment of the present invention.

Fig. 6 shows a block diagram of a pulse width adjustment circuit according to an embodiment of the present invention.

Fig. 7 shows an operation waveform diagram of a pulse width adjustment circuit according to an embodiment of the present invention.

Fig. 8 shows a block diagram of a pulse width recovery unit according to an embodiment of the present invention.

Fig. 9 shows an operation waveform diagram of a pulse width recovery unit according to an embodiment of the present invention.

Detailed Description

In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

Fig. 1 shows a block diagram of a prior art delay locked loop circuit. As shown in fig. 1, a prior art delay locked loop circuit 100 includes a voltage controlled delay line 110, a phase detector 120, a charge pump 130, and a filter 140. The input clock signal CKIN is delayed by the voltage-controlled delay line 110 to obtain a plurality of output clock signals (e.g., output clock signals OCK0-OCK 8), wherein each of the output clock signals OCK is delayed by an angle with respect to the input clock signal CKIN. The phase detector 120 receives any two output clock signals (e.g., output clock signals OCK0 and OCK 8) that differ by 8 phases for comparing the phases of the output clock signal OCK0 and the output clock signal OCK8 to generate the control signals UP and DN of the charge pump. The charge pump 130 receives the control signals UP and DN and generates a current output signal Iout based on the control signals UP and DN. The filter 140 is, for example, a low-pass filter, and is input to receive the current output signal Iout and output a dc voltage VC according to the current output signal Iout. The voltage-controlled delay line 110 receives the dc voltage VC and is used as a voltage control signal for the voltage-controlled delay line unit to control the delay time of the voltage-controlled delay line. For example, when the time difference between the rising edges of the output clock signal OCK8 and the output clock signal OCK0 exceeds one clock cycle, the phase detector 120 generates the control signal UP to control the charge pump 130 to charge the capacitor in the filter 140, increasing the voltage value of the DC voltage VC, which increases the DC voltage VC to reduce the delay time of the voltage controlled delay line 110, thereby enabling the alignment of the phases between the output clock signals OCK0 and OCK 8.

Fig. 2 shows a schematic block diagram of a prior art voltage controlled delay line. As shown in FIG. 2, the prior art voltage-controlled delay line 110 includes a voltage bias circuit 111 and a plurality of cascaded delay cells 112 (e.g., delay cell 112_1, delay cell 112_2 … …, delay cell 112_n+1, and delay cell 112_n+2), where n+.. The voltage bias circuit 111 is used for converting the direct voltage VC into a voltage-controlled current, and then mirroring the current through a current mirror formed by PMOS transistors P1 and P2 to generate bias voltages Vp and Vn driving the plurality of cascaded delay cells 112. Each stage of delay unit 112 provides a clock output signal OCK according to an input clock signal, for example, delay unit 112_1 obtains an output clock signal OCK0 according to an input clock signal CKIN, delay unit 112_2 obtains an output clock signal OCK1 according to the output clock signal OCK0, delay unit 112_n+1 obtains an output clock signal OCK (n) according to the clock signal output by delay unit 112_n, delay unit 112_n+2 obtains an output clock signal OCK (n+1) according to the output clock signal OCK (n), and the output clock signal OCK0 has a delay of a certain angle relative to the input clock signal CKIN, the output clock signal OCK1 has a delay of a certain angle relative to the output clock signal OCK0, and so on.

Fig. 3 shows a multiphase clock output waveform diagram of a prior art voltage controlled delay line. Fig. 3 shows output waveforms of the output clock signals OCK (n) and OCK (n+1). As shown in fig. 3, in the transmission process of the voltage-controlled delay line, due to the device difference between the delay units, the rising edge of the output clock signal OCK (n+1) is delayed by the delay time tr with respect to the rising edge of the output clock signal OCK (n), the falling edge of the output clock signal OCK (n+1) is delayed by the delay time tf with respect to the falling edge of the output clock signal OCK (n), the delay times of the rising edge and the falling edge between the output clock signals OCK (n+1) and OCK (n) are not uniform, and thus the rising edge and the falling edge of the output waveform of the voltage-controlled delay line are difficult to match, which in turn leads to distortion of the clock waveform. As can be seen, the performance requirement of the voltage-controlled delay line 110 in the prior art is very high, so as to ensure that the delays of the rising edge and the falling edge of the clock signal can be matched in the transmission process, otherwise, the clock waveform will be distorted in the high-speed transmission process, and serious distortion of the output clock signal is caused. In order to avoid serious distortion of the clock that may be caused at the end of the clock network, DCC circuits are typically embedded in the clock network in the prior art, but these schemes all require additional circuit designs to correct for the duty cycle variations generated by the delay line, increasing circuit cost and power consumption. Also, in the case where DCC and phase locking are performed simultaneously, the DCC circuit may affect the phase locking, resulting in an operation error.

The present invention will be described in detail with reference to the accompanying drawings.

Fig. 4 shows a block diagram of a delay locked loop circuit according to an embodiment of the present invention. As shown in fig. 4, the delay locked loop circuit 200 of the embodiment of the present invention includes a voltage controlled delay line 210, a control loop 220, a pulse width adjustment circuit 230, and a pulse width recovery circuit 240.

The pulse width adjustment circuit 230 is configured to convert the input clock signal CKIN into a reference clock signal CKREF, where the input clock signal CKIN has a set first duty cycle (e.g., 50% duty cycle), and the reference clock signal CKREF has a second duty cycle that is less than or equal to the first duty cycle. It should be noted that the duty cycle of the reference clock signal CKREF is not particularly limited by the present invention, and those skilled in the art may set the duty cycle of the reference clock signal CKREF to a certain value according to a specific application, for example, may set the duty cycle of the reference clock signal CKREF to 25%, 30% or 50%.

An input of the voltage controlled delay line 210 is coupled to an output of the pulse width adjustment circuit 230 to take the reference clock signal CKREF as an input and to output a delayed signal of the reference clock signal CKREF, e.g., delayed clock signals DCK0-DCK8. The voltage-controlled delay line 210 has the same structure as the voltage-controlled delay line 110 described above, and includes a plurality of delay units (not shown in the figure) in cascade, each delay unit being configured to obtain a corresponding delay signal thereof according to an input clock signal, for example, a first delay unit of the plurality of delay units is configured to receive the reference clock signal CKREF as an input and output a delay signal of the reference clock signal CKREF, that is, a delay clock signal DCK0; the remaining delay cells of the plurality of delay cells receive as input the output of the immediately preceding delay cell and output a corresponding increased delay signal of the reference clock signal CKREF, e.g., delay clock signal DCK0 delayed by 1/N period of the reference clock signal CKREF relative to the reference clock signal CKREF, delay clock signal DCK1 delayed by 2/N period of the reference clock signal CKREF relative to the reference clock signal CKREF, and so on until DCKN is delayed from the reference clock signal CKREF by the entire period of the reference clock signal CKREF, where N is an integer greater than 2.

An output waveform diagram of a delay locked loop circuit of an embodiment of the present invention is shown in fig. 5, and in fig. 5, an input clock signal CKIN, a reference clock signal CKREF, a plurality of delay signals DCK0-DCK8 of the reference clock CKREF generated by the voltage controlled delay line 210, and a plurality of output clock signals OCk0-OCk8 are shown. The DLL circuit 200 divides the entire period of the reference clock signal CKREF into a plurality of sub-phases, and in an exemplary embodiment, the DLL circuit 200 divides the entire period of the reference clock signal CKREF into 8 sub-phases. Thus, it can be seen that DCK0 delays 1/8 period of the reference clock CKREF, DCK1 delays 2/8 period of the reference clock CKREF, and so on until DCK7 delays the full period of the reference clock CKREF.

With continued reference to fig. 4, a control loop 220 is coupled to the voltage controlled delay line 210 for comparing two delayed clock signals (e.g., delayed clock signals DCK0 and DCK8 in fig. 5) generated by the voltage controlled delay line 210 that are 360 ° out of phase with each other and generating a dc voltage VC in a manner that maintains phase alignment between the two delayed clock signals to control the delay time of each delay element in the voltage controlled delay line 210. In more detail, the control loop 220 includes a phase detector 221 receiving the delayed clock signals DCK0 and DCK8, the phase detector 221 being configured to generate the control signal UP/DN of the charge pump 222 based on a phase difference between the delayed clock signals DCK0 and DCK 8. The charge pump 222 receives the control signal UP/DN as a current switching signal of the charge pump 222, so that the charge pump 222 can obtain a current output signal Iout. The filter 223 receives the current output signal Iout and outputs a dc voltage VC to the voltage controlled delay line 210, thereby controlling the phase alignment between the delayed clock signals DCK0 and DCK 8. The filter 223 is illustratively a low pass filter (and may be, for example, a capacitor coupled between the output of the charge pump 222 and ground), although other filtering techniques may be used.

In some exemplary embodiments, the phase detector 221 is configured to generate the charge control signal UP to control the charge pump 222 to charge the capacitor in the filter 223 such that the dc voltage VC increases and in turn such that the delay time of the delay unit in the voltage controlled delay line 210 decreases when the time difference of the rising edges between the delayed clock signals DCK8 and DCK0 exceeds one period (i.e., 360 °). When the time difference between the rising edges of the delayed clock signals DCK8 and DCK0 is smaller than one period, the phase detector 221 generates the discharge control signal DN to control the charge pump 222 to discharge the capacitor in the filter 223, so that the dc voltage VC is reduced, and then the delay time of the delay unit in the voltage-controlled delay line 210 is increased, and the control loop 220 finally stabilizes the phase difference between the delayed clock signals DCK8 and DCK0 at one period by repeating the above operations. The charge control signal UP is a square wave signal, and the discharge control signal DN is an inactive level signal (e.g., a low level signal), for example.

A pulse width recovery circuit 240 is coupled to the output of the voltage-controlled delay line 210, and the pulse width recovery circuit 240 recovers the duty cycle of the plurality of delayed clock signals DCK0-DCK7 outputted to the voltage-controlled delay line 210 to the preset first duty cycle, for example, recovers the duty cycle of the delayed clock signals DCK0-DCK7 to 50%, so as to obtain a plurality of output clock signals OCk0-OCK7. Specifically, the pulse width recovery circuit 240 includes a plurality of pulse width recovery units (e.g., pulse width recovery units 241_1-241_4), and an input of each pulse width recovery unit 241 is configured to receive two delayed clock signals of the plurality of delayed clock signals having a phase difference equal to 1/2 period of the reference clock signal CKREF (i.e., a phase difference equal to 180 °) and recover a duty cycle thereof to 50% to obtain a corresponding output clock signal OCK. For example, the pulse width recovery unit 241_1 has an input for receiving delayed clock signals DCK0 and DCK4 having a phase difference of 180 ° and recovering the duty ratios thereof to 50% to obtain output clock signals OCK0 and OCK4; the pulse width recovery unit 241_2 has an input for receiving delayed clock signals DCK1 and DCK5 having a phase difference of 180 ° and recovering the duty ratio thereof to 50% to obtain output clock signals OCK1 and OCK5, and so on.

As shown in fig. 5, among the plurality of output clock signals OCK0 to OCK7, the output clock signals OCK0 and OCK4 are obtained by pulse width recovery from delayed clock signals DCK0 and DCK4 having a phase difference of 180 °, the output clock signals OCK1 and OCK5 are obtained by pulse width recovery from delayed clock signals DCK1 and DCK5 having a phase difference of 180 °, and so on. Also, taking the output clock signal OCK0 as an example, the output clock signal OCK0 toggles to a high level when the rising edge of the delayed clock signal DCK0 arrives, the output clock signal OCK0 toggles to a low level when the rising edge of the delayed clock signal DCK4 arrives, and the half period of the output clock signal OCK0 is equal to the rising edge interval time of the delayed clock signals DCK0 and DCK 4. Further, the plurality of output clock signals OCK0-OCK7 are sequentially delayed by 1/N cycles, where N represents the number of the plurality of delayed clock signals DCK0-DCK7 input to the pulse width recovery circuit 240, and N is an integer of 2 or more.

It should be noted that, the number of pulse width recovery units 241 in the pulse width recovery circuit 240 is not limited to the above embodiment, and a person skilled in the art may determine the number of pulse width recovery units 241 according to the number of delayed clock signals DCK output by the voltage-controlled delay line 210, for example, the number of delayed clock signals DCK may be divided by 2 to obtain the number of pulse width recovery units 241. In addition, the trigger edge of the output clock signal OCK of the present embodiment is not limited to a rising edge, and is determined according to the type of the flip-flop in the pulse width recovery circuit, and is a rising edge when the flip-flop in the pulse width recovery circuit is a rising edge trigger, and is a falling edge when the flip-flop in the pulse width recovery circuit is a falling edge.

Fig. 6 and fig. 7 are a block diagram and an operation waveform diagram respectively showing a pulse width adjusting circuit according to an embodiment of the present invention. As shown in fig. 6, the pulse width adjustment circuit 230 of the present embodiment includes a D flip-flop DFF0, a buffer BUF0, and a delay 231. The D-flip-flop DFF0 has an input coupled to the supply voltage VDD, a clock coupled to the input clock signal CKIN, an output coupled to the input of the delay 231, a reset coupled to the output of the delay 231, and an output. An input of the buffer BUF0 is coupled to an output of the D flip-flop DFF0, and an output of the buffer BUF0 is for outputting the reference clock signal CKREF. Wherein the D flip-flop DFF0 is triggered by the rising edge of the reference clock signal CKREF and transmits data of an input terminal (i.e., the power supply voltage VDD) to an output terminal, so that the first flip-flop signal F1 is set to a high level (or logic "1"). The delay 231 is configured to delay the high level first flip-flop signal F1 for a set first time to obtain a reset signal RSTN0, where the reset signal RSTN0 enables the reset terminal of the D flip-flop DFF0, so that the D flip-flop DFF0 resets and sets the output terminal of the first flip-flop signal F1 to a low level (or logic "0"), thereby obtaining the first flip-flop signal F1 with the set duty cycle at the output terminal of the D flip-flop DFF 0. It will be appreciated that the pulse width of the first flip-flop signal F1 depends on the internal delay of the D flip-flop DFF0 and the first delay provided by the delay 231, and that a person skilled in the art can obtain the first flip-flop signal F1 of a specific pulse width by specifically designing the first delay of the delay 231. The buffer BUF0 is used for buffering the first flip-flop signal F1 of the D flip-flop DFF0 and obtaining the reference clock signal CKREF. It will be appreciated that the device delay of the buffer BUF0 is particularly small, so that the reference clock signal CKREF has approximately the same phase and pulse width as the first flip-flop signal F1 of the D flip-flop DFF 0.

As shown in fig. 7, when the rising edge of the input clock signal CKIN arrives, the D flip-flop DFF0 is triggered to start, so that the reference clock signal CKREF is inverted from a low level to a high level, and after the high level signal is delayed by the delay 231 for a first time, the reset terminal of the D flip-flop DFF0 is enabled, so that the D flip-flop DFF0 is reset, and then the reference clock signal CKREF is hopped from the high level to the low level again.

Fig. 8 and 9 are a block diagram and an operation waveform diagram, respectively, illustrating a pulse width recovery unit according to an embodiment of the present invention. As shown in fig. 8, the pulse width recovery unit 241 of the present embodiment includes OR gates OR, D flip-flops DFF1 to DFF4, inverters INV1 and INV2, and buffers BUF1 and BUF2. Wherein an input of the OR circuit OR is coupled to an output of the voltage controlled delay line 210 to receive two delayed clock signals having a set phase difference among the plurality of delayed clock signals DCK. Taking the delayed clock signals DCK0 and DCK4 as an example, one input terminal of the OR circuit OR is used for receiving the delayed clock signal DCK0, the other input terminal is used for receiving the delayed clock signal DCK4, and the OR circuit OR is used for obtaining the frequency multiplication signal SigA according to the logic relationship between the delayed clock signals DCK0 and DCK 4. An input terminal of the inverter INV1 is coupled to the delayed clock signal DCK0, and an output terminal thereof is configured to output an inverted signal DCK0b of the delayed clock signal DCK 0. An input end of the inverter INV2 is coupled to the delayed clock signal DCK4, and an output end thereof is configured to output an inverted signal DCK4b of the delayed clock signal DCK 4. The D flip-flop DFF1 has a clock terminal coupled to the inverted signal DCK0b of the delayed clock signal DCK0, an input terminal coupled to the power supply voltage VDD, and an output terminal for outputting the second flip-flop signal F2. The D flip-flop DFF2 has a clock terminal coupled to the inverted signal DCK4b of the delayed clock signal DCK4, an input terminal coupled to the power supply voltage VDD, and an output terminal for outputting the third flip-flop signal F3. The D flip-flop DFF3 has a reset terminal coupled to the second flip-flop signal F2, a clock terminal coupled to the multiplied signal SigA, a positive output terminal for providing the output clock signal OCK0, and a negative output terminal for shorting to its own input terminal. The D flip-flop DFF4 has a reset terminal coupled to the third flip-flop signal F3, a clock terminal coupled to the multiplied signal SigA, a positive output terminal for providing the output clock signal OCk4, and a negative output terminal for shorting to its own input terminal. Buffers BUF1 and BUF2 are coupled to positive output terminals of D flip-flops DFF3 and DFF4, respectively, to buffer output signals of D flip-flops DFF3 and DFF4 to obtain output clock signals OCK0 and OCK4.

The operation principle of the pulse width recovery unit of the present embodiment is explained below with reference to fig. 8 and 9. As shown in fig. 9, the delayed clock signals DCK0 and DCK4 perform a frequency doubling function after being passed through the OR circuit OR and generate the frequency doubling signal SigA. Since the clock terminal of the D flip-flop DFF1 receives the inverted signal DCK0b of the delayed clock signal DCK0, the clock terminal of the D flip-flop DFF2 receives the inverted signal DCK4b of the delayed clock signal DCK4, and the clock terminals of the D flip-flops DFF1 and DFF2 are rising edge triggered, the D flip-flops DFF1 and DFF2 are triggered by the falling edges of the delayed clock signals DCK0 and DCK4, respectively, to transmit the power supply voltage VDD of the input terminal to the output terminal. As shown in fig. 9, at time t1, the falling edge of the delayed clock signal DCK0 comes, and the second flip-flop signal F2 is flipped from the low level to the high level. At time t3, when the falling edge of the delay time signal DCK4 comes, the third flip-flop signal F3 is flipped from the low level to the high level. In addition, the reset terminals of the D flip-flops DFF3 and DFF4 are configured to trigger reset at a low level, and the D flip-flops normally operate at a high level, so that the D flip-flops DFF3 and DFF4 are enabled to operate at time t1 and time t3, respectively.

In the present embodiment, the D flip-flops DFF3 and DFF4 are configured to perform frequency division operation on the frequency-multiplied signal SigA to obtain output clock signals OCK0 and OCK4, respectively. As shown in fig. 9, before time t2, the positive output terminal of the D flip-flop DFF3 is logic "0", the negative output terminal is logic "1", and at time t2, when the 2 nd rising edge of the frequency multiplication signal SigA arrives, the D flip-flop DFF3 is triggered and transmits the data of the input terminal to the positive output terminal, that is, the logic "1" of the negative output terminal is transmitted to the positive output terminal, at this time, the positive output terminal of the D flip-flop DFF3 is logic "1", the negative output terminal is logic "0", and thus the output clock signal OCK0 jumps from the low level to the high level. At time t4, when the 3 rd rising edge of the frequency multiplication signal SigA arrives, the D flip-flop DFF3 is triggered again, at this time, the positive output terminal of the D flip-flop DFF3 transitions to logic "0", the negative output terminal transitions to logic "1", and thus the output clock signal OCK0 transitions from high level to low level. Meanwhile, before time t4, the positive output terminal of the D flip-flop DFF4 is logic "0", the negative output terminal is "1", so that when the 3 rd rising edge of the frequency-multiplied signal SigA arrives at time t4, the D flip-flop DFF4 is triggered, and as a result, the positive output terminal of the D flip-flop DFF4 becomes logic "1", the negative output terminal becomes logic "0", and thus the output clock signal OCK4 transitions from the low level to the high level at time t 4. At time t5, when the 4 th rising edge of the frequency multiplication signal SigA arrives, the outputs of the D flip-flops DFF3 and DFF4 are triggered to flip again, so the output clock signal OCK0 transitions from a low level to a high level, the output clock signal OCK4 transitions from a high level to a low level, and then the above-described processes are repeated sequentially.

As can be seen from the above description, the present invention implements the frequency division 2 principle by shorting the negative and input terminals of the D flip-flops DFF3 and DFF4 together, so that the outputs of the D flip-flops DFF3 and DFF4 flip-flop once during one cycle of the multiplied signal SigA. And because the period of the frequency multiplication signal SigA is constant, the high level time and the low level time of the output ends of the D flip-flop DFF3 and the DFF4 can be kept equal, namely, a constant 50% duty ratio can be obtained on the finally obtained output clock signal without an additional DCC circuit, thereby being beneficial to reducing the circuit cost.

The pulse width adjustment circuit 230 and the pulse width recovery unit 241 may be implemented by other circuit configurations as long as the functions of pulse width adjustment and recovery can be achieved, and the above embodiments are not limited thereto.

It should be noted that the edge trigger type of the flip-flop in the pulse width recovery unit 241 is not limited to the above embodiment, and a person skilled in the art may select a rising edge trigger flip-flop or a falling edge trigger flip-flop according to the specific situation.

In summary, the delay locked loop circuit of the present invention converts a square wave signal with a duty ratio of 50% into a pulse signal through a pulse width adjustment circuit, and inputs the pulse signal into a voltage-controlled delay line, so that the voltage-controlled delay line can generate a plurality of delay clock signals based on the pulse signal, and then obtains a frequency multiplication signal according to the plurality of delay clock signals by using a pulse width recovery circuit, and performs a divide-by-two process on the frequency multiplication signal, thereby obtaining an output square wave signal with a duty ratio of 50%. The delay phase-locked loop circuit can obtain an output clock signal with a constant 50% duty cycle, thereby overcoming the problem of distortion of the transmission duty cycle of a delay line of the DLL circuit, avoiding abnormal operation of certain systems with requirements on the signal duty cycle when being applied to the systems, and being beneficial to improving the stability and the reliability of the systems.

In addition, the delay phase-locked loop circuit of the invention uses the pulse width adjusting circuit and the pulse width recovering circuit to overcome the problem of the distortion of the transmission duty ratio of the voltage-controlled delay line, compared with the prior art, only the rising edge of the output waveform of the voltage-controlled delay line is consistent, thereby relaxing the requirement on the voltage-controlled delay line, and being beneficial to simplifying the design, reducing the cost and improving the compatibility of the system.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Finally, it should be noted that: it is apparent that the above examples are only illustrative of the present invention and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.

Claims

1. A delay locked loop circuit, comprising:

the pulse width adjusting circuit is used for converting an input clock signal into a reference clock signal, and the pulse width of the reference clock signal is smaller than that of the input clock signal;

a voltage-controlled delay line which receives the reference clock signal and the control signal, generates a plurality of delayed clock signals of the reference clock signal according to the reference clock signal and the control signal, and feeds back two delayed clock signals with a phase difference of 360 degrees in the plurality of delayed clock signals to a control loop as feedback signals;

a control loop for receiving the feedback signal and outputting the control signal to the voltage-controlled delay line according to the feedback signal; and

and the pulse width recovery circuit receives the plurality of delayed clock signals and generates a plurality of output clock signals with a first duty ratio according to every two delayed clock signals with a phase difference of 180 degrees.

2. The delay locked loop circuit of claim 1, wherein the pulse width adjustment circuit comprises:

a first D flip-flop having a first input terminal for receiving a power supply voltage, a first clock terminal for receiving the input clock signal, a first output terminal for outputting the reference clock signal, and a first reset terminal; and

And the delayer is used for delaying the reference clock signal to obtain a reset signal applied to the first reset end of the first D flip-flop.

3. The delay locked loop circuit of claim 2, wherein the pulse width adjustment circuit further comprises:

and the first buffer is connected with the first output end of the first D trigger and used for buffering and outputting the reference clock signal.

4. The delay locked loop circuit of claim 2 wherein the pulse width adjustment circuit is configured to control the second duty cycle of the reference clock signal by setting an internal delay of the first D flip-flop and a delay provided by the delay.

5. The delay locked loop circuit of claim 1 wherein the pulse width recovery circuit comprises a plurality of pulse width recovery units,

the input of each pulse width recovery unit is used for receiving a first delay clock signal and a second delay clock signal with a phase difference of 180 degrees in the plurality of delay clock signals, frequency-increasing according to the first delay clock signal and the second delay clock signal to obtain a frequency multiplication signal, and frequency-dividing processing is carried out on the frequency multiplication signal to obtain output clock signals corresponding to the first delay clock signal and the second delay clock signal.

6. The delay locked loop circuit of claim 5 wherein each of said pulse width recovery units comprises:

an or circuit having an input for receiving the first and second delayed clock signals and an output for outputting the multiplied signal;

a second D flip-flop having a second input terminal for receiving a power supply voltage, a second clock terminal for receiving an inverted signal of the first delayed clock signal, and a second output terminal for outputting a second flip-flop signal;

a third D flip-flop having a third input terminal for receiving a power supply voltage, a third clock terminal for receiving an inverted signal of the second delayed clock signal, and a third output terminal for outputting a third flip-flop signal;

a fourth D flip-flop having a second reset terminal for receiving the second flip-flop signal, a fourth clock terminal for receiving the multiplied signal, a fourth input terminal and a first negative input terminal shorted to each other, and a first positive output terminal for providing an output clock signal corresponding to the first delayed clock signal;

a fifth D flip-flop having a third reset terminal for receiving the third flip-flop signal, a fifth clock terminal for receiving the multiplied signal, a fifth input terminal and a second negative input terminal shorted to each other, and a second positive output terminal for providing an output clock signal corresponding to the second delayed clock signal.

7. The delay locked loop circuit of claim 6 wherein each of said pulse width recovery units further comprises:

a first inverter for receiving a first delayed clock signal and outputting an inverted signal of the first delayed clock signal;

a second inverter for receiving a second delayed clock signal and outputting an inverted signal of the second delayed clock signal;

the second buffer is connected with the first positive output end of the fourth D trigger and is used for buffering and outputting an output clock signal corresponding to the first delay clock signal; and

and the third buffer is connected with the second positive output end of the fifth D trigger and is used for buffering and outputting the output clock signal corresponding to the second delay clock signal.

8. The delay locked loop circuit of claim 6 wherein the second reset terminal of the fourth D flip-flop and the third reset terminal of the fifth D flip-flop are configured to trigger a reset when low and to enable operation when high.

9. The delay locked loop circuit of claim 8 wherein the fourth D flip-flop and the fifth D flip-flop are configured to enable operation when the second flip-flop signal and the third flip-flop signal are high, respectively, and trigger toggling at a rising edge of the multiplied signal to obtain output clock signals corresponding to the first delay clock signal and the second delay clock signal, respectively.

10. The delay locked loop circuit of claim 1 wherein the pulse width recovery circuit is configured to trigger a corresponding flip of each two 180 ° out of phase output clock signals based on the trigger edges of each two 180 ° out of phase delay clock signals, and wherein the time interval between the trigger edges of each two 180 ° out of phase delay clock signals is a corresponding half cycle of each two 180 ° out of phase output clock signals.

11. The delay locked loop circuit of claim 10 wherein the plurality of output clock signals output by the pulse width recovery circuit are sequentially delayed by 1/N cycles, where N represents the number of the plurality of delayed clock signals input to the pulse width recovery circuit and N is an integer greater than or equal to 2.

12. The delay locked loop circuit of claim 1, wherein the control loop comprises a phase detector, a charge pump, and a filter,

wherein the phase detector is configured to compare third and fourth delayed clock signals having a phase difference of 360 ° among the plurality of delayed clock signals to generate a charge control signal or a discharge control signal of the charge pump,

the charge pump is used for generating a current output signal according to the charge control signal or the discharge control signal,

The filter is used for generating a direct current voltage for controlling the delay time of the voltage-controlled delay line according to the current output signal.

13. The delay locked loop circuit of claim 12, wherein the filter is a low pass filter.

14. The delay locked loop circuit of claim 1, wherein the first duty cycle is equal to 50%.

15. The delay locked loop circuit of claim 1, wherein a duty cycle of the input clock signal is the same as or different from a duty cycle of the output clock signal.

16. The delay locked loop circuit of claim 1 wherein the plurality of delayed clock signals are sequentially delayed by 1/N cycles, where N represents the number of the plurality of delayed clock signals input to the pulse width recovery circuit and N is an integer greater than or equal to 2.

17. A method for adjusting duty cycle of a multiphase clock signal, comprising:

converting an input clock signal into a reference clock signal, wherein the pulse width of the reference clock signal is smaller than that of the input clock signal;

generating a plurality of delay clock signals of the reference clock signal according to the reference clock signal and the control signal, and feeding back two delay clock signals with a phase difference of 360 degrees in the plurality of delay clock signals as feedback signals to a control loop;

Outputting the control signal to a voltage-controlled delay line according to the feedback signal; and

a plurality of output clock signals having a first duty cycle are generated from each two delayed clock signals 180 DEG out of phase.

18. The method of claim 17, wherein generating an output clock signal having a first duty cycle from each two delayed clock signals 180 ° out of phase comprises:

obtaining a frequency multiplication signal according to every two delayed clock signals with the phase difference of 180 degrees, and carrying out frequency division processing on the frequency multiplication signal to obtain an output clock signal with a first duty ratio.

19. The method of claim 18, wherein generating an output clock signal having a first duty cycle from each two delayed clock signals 180 ° out of phase comprises:

according to the triggering edges of every two delayed clock signals with the phase difference of 180 degrees, triggering the corresponding every two output clock signals with the phase difference of 180 degrees to turn over, wherein the time interval of the triggering edges of every two delayed clock signals with the phase difference of 180 degrees is the half period of the corresponding every two output clock signals with the phase difference of 180 degrees.

20. The method of claim 17, wherein the first duty cycle is equal to 50%.