CN117712180A - Dielectric isolation two-section gate metal oxide thin film transistor structure and manufacturing method thereof - Google Patents

Abstract

The invention relates to a dielectric isolation two-section gate metal oxide thin film transistor structure and a manufacturing method thereof. A dielectric-isolated two-segment gate metal oxide thin film transistor structure comprising: a substrate; stacking sequentially from bottom to top over the substrate: the gate layer, the gate dielectric layer and the channel layer; a source electrode layer and a drain electrode layer are respectively arranged on the left side and the right side of the upper surface of the channel layer; the grid layer comprises a first metal grid section, an isolation medium section and a second metal grid section which are spliced in sequence in the horizontal direction, and the work function of the second metal grid section is lower than that of the first metal grid section. The invention greatly reduces the electric leakage problem of the IGZO TFT device.

Description

Dielectric isolation two-section gate metal oxide thin film transistor structure and manufacturing method thereof

Technical Field

The invention relates to the field of transistors, in particular to an asymmetric dielectric isolation two-section gate metal oxide thin film transistor structure and a manufacturing method thereof.

Background

Dynamic Random Access Memory (DRAM) plays a vital role in the development of cloud computing, edge computing, internet of things, and artificial intelligence. In recent years, DRAM is facing the well-known problem of "memory walls," i.e., the performance differences between CPU and memory. Meanwhile, with the miniaturization of feature sizes and chip areas, the sizes of transistors and capacitors in the conventional 1t1c DRAM architecture are continuously reduced, and the 1t1c DRAM is facing challenges such as increased leakage current, continuously shortened retention time, and increased power consumption.

The indium-gallium-zinc-oxygen thin film transistor (IGZO TFT) has the characteristics of low electric leakage, high mobility, low-temperature large-area deposition, low cost and the like, and the capacitor-free 2T0C DRAM formed by the IGZO TFT is expected to solve the problem of a memory wall of the traditional 1T1C DRAM. To increase the retention time of DRAM devices, reducing the leakage current of IGZO TFTs has become a new challenge.

At present, a common process method for reducing the leakage of the IGZO TFT is a thermal annealing process, so that the defect of a material is repaired, but the effect of reducing the leakage is close to a limit.

For this purpose, the present invention is proposed.

Disclosure of Invention

The invention mainly aims to provide a dielectric isolation two-section gate metal oxide thin film transistor structure and a manufacturing method thereof, which greatly reduce the electric leakage problem of devices.

In order to achieve the above object, the present invention provides the following technical solutions.

The first aspect of the present invention provides a dielectric-isolated two-segment gate metal oxide thin film transistor structure comprising:

a substrate;

stacking sequentially from bottom to top over the substrate: the gate layer, the gate dielectric layer and the channel layer;

a source electrode layer and a drain electrode layer are respectively arranged on the left side and the right side of the upper surface of the channel layer;

the grid layer comprises a first metal grid section, an isolation medium section and a second metal grid section which are spliced in sequence in the horizontal direction, and the work function of the second metal grid section is lower than that of the first metal grid section.

Further improvements are possible on this basis, as listed below.

Further, the difference between the work function of the first metal gate segment and the work function of the second metal gate segment is 0.05V-1.5V.

Further, the first metal gate section adopts Mo, and the second metal gate section adopts Al.

Further, the second metal gate segment is covered by only one of the source layer and the drain layer, and the first metal gate segment is covered by only the other; and the length of the first metal gate section covered is longer than that of the second metal gate section covered, and the length direction is along the splicing direction.

Further, the second metal gate segment is covered only by the drain layer.

Further, the channel layer adopts at least one of IGZO, IZO, ITO, inO, znO, tiO.

Further, the isolation medium section adopts at least one of oxide, nitride, carbide and organic matters.

Further, mo is used for the source layer and the drain layer.

Further, the gate dielectric layer covers the upper surface and the side wall of the gate layer, the channel layer covers the upper surface and the side wall of the gate dielectric layer, and the source layer and the drain layer both cover the upper surface and the side wall of the channel layer.

A second aspect of the present invention provides a method of fabricating a dielectric-isolated two-segment gate metal oxide thin film transistor structure of the first aspect, comprising:

forming a first metal layer on a substrate;

forming an isolation medium layer on the first metal layer, wherein the medium isolation layer at least forms a first side wall on one side wall of the first metal layer;

thinning the isolation medium layer to expose the upper surface of the first metal layer;

forming a second metal layer, covering the isolation medium layer and the first metal layer, and forming a second side wall on the side wall of the first side wall by the second metal layer, wherein the work function of the second metal layer is smaller than that of the first metal layer;

thinning the second metal layer to expose the upper surface of the first metal layer;

forming a gate dielectric layer to cover the first metal layer, the isolation dielectric layer and the second metal layer;

forming a channel layer to cover the gate dielectric layer;

forming a conductive layer over the channel layer;

and patterning the conductive layer to form a source electrode layer and a drain electrode layer respectively.

In conclusion, compared with the prior art, the invention achieves the following technical effects:

(1) The grid layer is spliced by two metals with different work functions, so that the electric leakage problem of the device can be reduced by utilizing the work function difference of the two metals;

(2) The two metals with different work functions are separated by an isolation medium, which affects the electric field in the channel, thereby further reducing the leakage problem of the device;

(3) Optimizing the difference between the work function of the first metal gate segment and the work function of the second metal gate segment can further improve the leakage problem;

(4) The leakage problem can be further improved by optimizing the size difference of the first metal gate segment and the second metal gate segment covered by the source/drain;

(5) The provided manufacturing method is simple in flow and compatible with the existing integration process.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.

FIG. 1 is a schematic diagram of a dielectric isolation two-segment gate metal oxide thin film transistor according to the present invention;

fig. 2 to 9 are schematic views of structures obtained at each step in the manufacturing method provided by the present invention.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.

The invention provides a dielectric isolation two-section gate metal oxide thin film transistor structure as shown in figure 1, which comprises: a substrate (not shown in the figures); a gate layer, a gate dielectric layer 4 and a channel layer 5 which are stacked in sequence from bottom to top above the substrate; source layer 61 and drain layer 62 are provided on the left and right sides of the upper surface of channel layer 5, respectively.

The grid layer comprises a first metal grid section 1, an isolation medium section 2 and a second metal grid section 3 which are spliced in sequence in the horizontal direction, and the work function of the second metal grid section 3 is lower than that of the first metal grid section 1. Although only the structure in which the first metal gate segment 1 is located on the left side is illustrated in fig. 1, the scope of the present invention is not limited. The splicing in the invention can be left-to-right splicing or right-to-left splicing. In other words, the first metal gate segment and the source layer are located on the same side, and the second metal gate segment and the drain layer are located on the same side; the second metal gate segment and the source layer may be located on the same side, and the first metal gate segment and the drain layer may be located on the same side. Typically, to significantly reduce leakage, the second metal gate segment is covered by only one of the source and drain layers and the first metal gate segment is covered by the other.

Therefore, the grid is formed by two metals with different work functions and isolated by a medium, so that the electric leakage problem of the device can be reduced, and the defect of the traditional thermal annealing process can be overcome. Meanwhile, the structure of the invention can be further combined with a thermal annealing process, and the invention is not limited to this.

In the transistor shown in fig. 1, the substrate may be any substrate commonly used for semiconductor devices, and may be a silicon-based substrate, for example, one of bulk silicon, SOI, strained silicon, geSi, and silicon oxide, or a substrate of a group iii-v material.

The first metal gate segment 1 and the second metal gate segment 3 may be independently selected from TaC, tiN, taTbN, taErN, taYbN, taSiN, hfSiN, moSiN, ruTax, niTax, moNx, tiSiN, tiCN, taAlC, tiAlN, taN, ptSix, ni3Si, pt, ru, ir, mo, ti, al, cr, au, cu, ag, hfRu, ruOx, and the like, as long as the selection thereof satisfies the requirement of the work function difference.

In some embodiments, the difference between the work function of the first metal gate segment 1 and the work function of the second metal gate segment 3 is 0.05V to 1.5V.

In some embodiments, the first metal gate segment 1 is Mo and the second metal gate segment 3 is Al.

The isolation medium segment 2 may be a stack of one or more of aluminum oxide, silicon oxynitride, tantalum oxide, hafnium oxide, silicon nitride, tantalum oxide, zirconium oxide, or the like.

The gate dielectric layer 4 may be one or more of aluminum oxide, silicon oxynitride, tantalum oxide, hafnium oxide, silicon nitride, tantalum oxide, zirconium oxide, or the like.

The channel layer 5 may be at least one of IGZO, IZO, ITO, inO, znO, tiO to obtain high field effect mobility and good electrical stability.

The source layer 61 and the drain layer 62 may be made of a metal or a doped semiconductor, and may be TaC, tiN, taTbN, taErN, taYbN, taSiN, hfSiN, moSiN, ruTax, niTax, moNx, tiSiN, tiCN, taAlC, tiAlN, taN, ptSix, ni3Si, pt, ru, ir, mo, ti, al, cr, au, cu, ag, hfRu, ruOx, or the like. The materials of the source and drain layers may be the same or different.

In some embodiments, the length of the first metal gate segment 1 covered is greater than the length of the second metal gate segment 3 covered, the length direction being the direction along the splice. By "covered" is meant herein covered by either the source layer or the drain layer, and this size difference can be used to further reduce leakage problems. As shown in fig. 1, the length of the first metal gate segment 1 covered is L1, and the length of the second metal gate segment 3 covered is L2, where L1 > L2.

In some embodiments, the stack of the gate layer, the gate dielectric layer 4, the channel layer 5, and the source/drain layer takes a "wrap-around" shape, for example, as shown in fig. 1, the gate dielectric layer 4 covers the upper surface and sidewalls of the gate layer, the channel layer 5 covers the upper surface and sidewalls of the gate dielectric layer 4, and the source layer 61 and the drain layer 62 each cover the upper surface and sidewalls of the channel layer.

In some embodiments, the source layer 61 and the drain layer 62 may be isolated by a suitable dielectric material, which is not shown in fig. 1.

The invention also provides a manufacturing method of the transistor shown in fig. 1, and the method has simple flow and the following steps.

In step S1, a first metal layer 1' is formed on the substrate by sputtering or the like, as shown in fig. 2, and this layer serves as the first metal gate segment in fig. 1.

In step S2, an isolation dielectric layer 2 'is formed on the first metal layer, and the isolation dielectric layer 2' forms a first sidewall on at least one sidewall of the first metal layer, as shown in fig. 3. Generally, in order to reduce the operation difficulty, first side walls are formed on two opposite side walls of the first metal layer 1', and the first side wall on one side can be removed in a subsequent process. Or in actual manufacturing, the first side wall can be formed on the right side or the left side of the first metal layer only by combining means such as a mask plate.

In step S3, the isolation dielectric layer 2' may be thinned by CMP or the like, so as to expose the upper surface of the first metal layer.

In step S4, a second metal layer 3 'is formed by sputtering, etc. to cover the isolation dielectric layer 2' and the first metal layer 1', and the second metal layer 3' forms a second sidewall on the sidewall of the first sidewall 21, as shown in fig. 4, the work function of the second metal layer 3 'is smaller than that of the first metal layer 1'. In actual manufacturing, the order of forming the first metal layer 3' and the second metal layer 1' may be changed, but it is generally preferable to form first because the first metal layer 1' is large in size.

Step S5, thinning the second metal layer 3 'by means of CMP and the like so as to expose the upper surface of the first metal layer 1'; the first sidewall 21 and the second sidewall 31 on the left side are removed again as shown in fig. 5. The reserved first side wall 21 serves as an isolation medium section of fig. 1, and the reserved second side wall 31 serves as a second metal gate section of fig. 1.

In step S6, a gate dielectric layer 4 is formed to cover the first metal layer 1', the isolation dielectric layer 2' and the second metal layer 3', as shown in fig. 6.

In step S7, a channel layer 5 is formed to cover the gate dielectric layer 4, as shown in fig. 7.

In step S8, a conductive layer 6 is formed over the channel layer 5, as shown in fig. 8.

In step S9, the conductive layer 6 is patterned to form a source layer 61 and a drain layer 62, respectively, as shown in fig. 9.

The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims (9)

1. A dielectric-isolated two-segment gate metal oxide thin film transistor structure comprising:

a substrate;

stacking sequentially from bottom to top over the substrate: the gate layer, the gate dielectric layer and the channel layer;

a source electrode layer and a drain electrode layer are respectively arranged on the left side and the right side of the upper surface of the channel layer;

the grid layer comprises a first metal grid section, an isolation medium section and a second metal grid section which are spliced in sequence in the horizontal direction, and the work function of the second metal grid section is lower than that of the first metal grid section.

2. The dielectric-isolated two-segment gate metal oxide thin film transistor structure of claim 1, wherein a difference between a work function of the first metal gate segment and a work function of the second metal gate segment is between 0.05V and 1.5V.

3. The dielectric-isolated two-segment gate metal-oxide thin film transistor structure of claim 1, wherein the second metal gate segment is covered by only one of the source layer and the drain layer, and the first metal gate segment is covered by only the other; preferably, the length of the first metal gate section covered is greater than the length of the second metal gate section covered, and the length direction is along the splicing direction.

4. A dielectric-isolated two-segment gate metal-oxide thin film transistor structure as claimed in claim 3, wherein the second metal gate segment is covered only by a drain layer.

5. The dielectric-isolated two-segment gate metal-oxide thin film transistor structure of any of claims 1-4, wherein the channel layer employs at least one of IGZO, IZO, ITO, inO, znO, tiO.

6. The dielectric-isolated two-segment gate metal-oxide thin film transistor structure of any of claims 1-4, wherein the isolated dielectric segment is at least one of an oxide, a nitride, a carbide, and an organic.

7. The dielectric-isolated two-segment gate metal-oxide thin film transistor structure of any of claims 1-4, wherein the source and drain layers comprise Mo.

8. The two-segment gate metal oxide thin film transistor structure of any of claims 1-4, wherein the gate dielectric layer covers an upper surface and sidewalls of the gate layer, the channel layer covers an upper surface and sidewalls of the gate dielectric layer, and the source layer and the drain layer both cover an upper surface and sidewalls of the channel layer.

9. The method for manufacturing the dielectric-isolated two-segment gate metal oxide thin film transistor structure according to any one of claims 1 to 8, comprising:

forming a first metal layer on a substrate;

forming an isolation medium layer on the first metal layer, wherein the medium isolation layer at least forms a first side wall on one side wall of the first metal layer;

thinning the isolation medium layer to expose the upper surface of the first metal layer;

forming a second metal layer, covering the isolation medium layer and the first metal layer, and forming a second side wall on the side wall of the first side wall by the second metal layer, wherein the work function of the second metal layer is smaller than that of the first metal layer;

thinning the second metal layer to expose the upper surface of the first metal layer;

forming a gate dielectric layer to cover the first metal layer, the isolation dielectric layer and the second metal layer;

forming a channel layer to cover the gate dielectric layer;

forming a conductive layer over the channel layer;

and patterning the conductive layer to form a source electrode layer and a drain electrode layer respectively.