CN117711963A - All-intermetallic compound interconnection chip with preferential orientation and preparation method and application thereof - Google Patents
All-intermetallic compound interconnection chip with preferential orientation and preparation method and application thereof Download PDFInfo
- Publication number
- CN117711963A CN117711963A CN202311634918.7A CN202311634918A CN117711963A CN 117711963 A CN117711963 A CN 117711963A CN 202311634918 A CN202311634918 A CN 202311634918A CN 117711963 A CN117711963 A CN 117711963A
- Authority
- CN
- China
- Prior art keywords
- metallization layer
- under
- bump metallization
- bump
- intermetallic compound
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000765 intermetallic Inorganic materials 0.000 title claims abstract description 64
- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 238000001465 metallisation Methods 0.000 claims abstract description 139
- 229910000679 solder Inorganic materials 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 238000000034 method Methods 0.000 claims abstract description 55
- 239000013078 crystal Substances 0.000 claims abstract description 26
- 238000003466 welding Methods 0.000 claims abstract description 22
- 230000008569 process Effects 0.000 claims abstract description 18
- 238000007731 hot pressing Methods 0.000 claims abstract description 9
- 238000009713 electroplating Methods 0.000 claims description 31
- 238000004519 manufacturing process Methods 0.000 claims description 18
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 14
- 229910052733 gallium Inorganic materials 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000006835 compression Effects 0.000 claims description 2
- 238000007906 compression Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 abstract description 3
- 238000002844 melting Methods 0.000 abstract description 3
- 239000010949 copper Substances 0.000 description 27
- 238000006243 chemical reaction Methods 0.000 description 8
- 238000005219 brazing Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000012536 packaging technology Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004377 microelectronic Methods 0.000 description 3
- 229910005538 GaSn Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910020888 Sn-Cu Inorganic materials 0.000 description 2
- 229910019204 Sn—Cu Inorganic materials 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002159 nanocrystal Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- KQZLRWGGWXJPOS-NLFPWZOASA-N 1-[(1R)-1-(2,4-dichlorophenyl)ethyl]-6-[(4S,5R)-4-[(2S)-2-(hydroxymethyl)pyrrolidin-1-yl]-5-methylcyclohexen-1-yl]pyrazolo[3,4-b]pyrazine-3-carbonitrile Chemical compound ClC1=C(C=CC(=C1)Cl)[C@@H](C)N1N=C(C=2C1=NC(=CN=2)C1=CC[C@@H]([C@@H](C1)C)N1[C@@H](CCC1)CO)C#N KQZLRWGGWXJPOS-NLFPWZOASA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229940125877 compound 31 Drugs 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
The invention discloses a preferred orientation all-intermetallic compound interconnection chip and a preparation method and application thereof, wherein the preferred orientation all-intermetallic compound interconnection chip comprises a first under-bump metallization layer prepared on a first substrate and a second under-bump metallization layer prepared on a second substrate; preparing lead-free solder micro-bumps on the first under-bump metallization layer; and placing the lead-free solder micro-bump and the second bump lower metallization layer in contact, and performing hot-pressing bonding treatment to form micro-welding spots, thereby completing the preparation of the preferred-orientation all-intermetallic compound interconnection chip. The method realizes the precise regulation and control of the morphology and the crystal orientation of the interfacial IMC crystal grains at low process temperature, and rapidly forms the full IMC welding spots with high melting point, high thermal stability and preferred orientation, thereby realizing the preparation of the full intermetallic compound at the preferred orientation under the low temperature condition.
Description
Technical Field
The invention belongs to the technical field of microelectronic manufacturing, and relates to an all-intermetallic compound interconnection chip with preferred orientation, and a preparation method and application thereof.
Background
The three-dimensional packaging technology integrates a semiconductor technology CMOS process and an advanced packaging structure, breaks through the limitation of the traditional packaging structure in a plane space, realizes flexible modularized integration of chips of different sizes, functions and types in a three-dimensional direction and vertical stacking interconnection of system chips, and reduces the packaging volume by 35%, reduces the power consumption by 50% and improves the bandwidth by 8 times by three-dimensional system packaging. Therefore, three-dimensional packaging technology is a key technology to be solved in microelectronic manufacturing technology development and industry upgrades.
The key of the three-dimensional packaging technology is to utilize Micro-bump (Micro-bump) and through silicon vias (Through Silicon Via, TSV) technologies to realize stacked interconnection in the vertical direction of the multichip through multiple reflows. Thus, the already interconnected micro-pads are required to withstand subsequent reflow processes without failure due to reflow, rapid growth of intermetallic compounds (Intermetallic Compound, IMC), etc.; meanwhile, with the progress acceleration of miniaturization, multifunction and high performance, the number of chip layers in the multilayer stacked structure is continuously increased, the thickness is thinner and thinner, and the reliability problems such as thermal mismatch, warpage and the like in the reflow interconnection process are aggravated. In addition, as electronic fabrication continues to advance toward miniaturization, the size of interconnect pads in three-dimensional packages is also continuously reduced, and in the future, the size of interconnect pads in three-dimensional packages is below 10 μm, which makes the Under Bump Metallization (UBM) in three-dimensional packages contain only a few or even one die, the effect of UBM crystal orientation on interfacial IMC nucleation and growth will be more pronounced, while IMC crystals have strong anisotropy in electrical, thermal and force properties, which significantly affects the reliability of micro-pads, and even may cause some micro-pads to fail in advance. In the prior art, interconnection welding is generally required at high temperature to obtain IMC crystals with preferred orientation, but high-temperature treatment can cause thermal damage to a substrate such as a wafer and affect material performance. The preparation method and structure of an all-intermetallic compound interconnection welding spot disclosed in Chinese patent CN104690383 and the intermetallic compound bonding method and bonding structure for stacking 3D packaging chips disclosed in Chinese patent CN104716059 mainly solve the problem of how to obtain an all-preferential orientation IMC interconnection chip. However, the above patent does not fully consider that the preferred orientation single crystal Cu has complex process and high cost and cannot be applied to the microelectronics industry. The method for controlling the crystal orientation and microstructure of the all-intermetallic compound micro-interconnection welding spot disclosed in Chinese patent CN 112103262B mainly solves the problem of how to replace a single crystal Cu under-bump metallization layer with complex process and high cost by utilizing a nano twin crystal Cu under-bump metallization layer with preferred orientation to obtain the all-preferred orientation IMC interconnection chip. However, the reflow process in the above patent still requires a relatively high temperature, which can warp the chip or the thin IC carrier and affect the reliability of the subsequent electronic device.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides an all-intermetallic compound interconnection chip with preferred orientation, and a preparation method and application thereof, thereby solving the technical problems that the substrate is thermally damaged and the reliability of an electronic device is influenced when an IMC crystal with preferred orientation is prepared under the high-temperature condition in the prior art.
The microcosmic appearance of the preferentially oriented micro-convex points is difficult, and the micro-convex points are in service at high temperature to generate a large number of Kendall holes, so that the performance and the reliability of the micro-convex points are affected.
The invention is realized by the following technical scheme:
a preparation method of a preferentially oriented all-intermetallic compound interconnection chip comprises the following steps:
preparing a first under bump metallization layer with preferred orientation on a first substrate, and preparing a second under bump metallization layer with preferred orientation on a second substrate; preparing lead-free solder micro-bumps on the first under-bump metallization layer;
and placing the lead-free solder micro-bump and the second bump lower metallization layer in contact, and performing hot-pressing bonding treatment to form micro-welding spots, thereby completing the preparation of the preferentially oriented all-intermetallic compound interconnection chip.
Preferably, the first under bump metallization layer and the second under bump metallization layer are any one of <111> preferred orientation nano twin crystal Ni, <111> preferred orientation nano twin crystal Cu and preferred orientation nano crystal Cu.
Preferably, the lead-free solder micro-bump is any one of gallium, gallium-based lead-free solder and In-based solder.
Preferably, the process of preparing the lead-free solder micro-bump on the first under-bump metallization layer specifically comprises the following steps: preparing a first under-bump metallization layer on the first substrate by adopting a direct current electroplating or pulse electroplating method, carrying out annealing treatment on the first under-bump metallization layer, depositing the lead-free solder on the annealed first under-bump metallization layer by adopting an electroplating deposition method, and then carrying out reflow to obtain the lead-free solder micro-bump.
Preferably, the reflux temperature is 100 to 150 ℃.
Preferably, the temperature is 100-150 ℃ and the pressure is not less than 20g during thermocompression bonding.
Preferably, the temperature gradient is not less than 500 ℃/cm during the thermocompression bonding.
Preferably, the thickness of the first under bump metallization layer and the second under bump metallization layer is 2-5 μm, and the diameter of the lead-free solder micro bump is less than 30 μm.
The full intermetallic compound interconnection chip with preferred orientation is prepared by the method;
the preferred orientation all-intermetallic compound interconnection chip comprises a first substrate, a first under-bump metallization layer on the first substrate, a second substrate and a second under-bump metallization layer on the second substrate, wherein the first under-bump metallization layer and the second under-bump metallization layer are connected through intermetallic compounds, and intermetallic compound crystal grains have ridge-shaped morphology and preferred directions.
The full intermetallic compound interconnection chip with preferred orientation is applied to the technical field of semiconductors.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention discloses a preparation method of a preferred orientation full intermetallic compound interconnection chip, which forms a lead-free micro bump at extremely low hot-press bonding temperature, ensures that an intermetallic compound with preferred orientation is formed at the interface of a first bump lower metallization layer and is used as a seed layer for subsequent reaction; the brazing method has the advantages that the pressure or the temperature gradient is applied during the brazing reaction, so that the microstructure of the intermetallic compound is controlled, the preferred orientation IMCs micro-salient points are formed, the mechanical properties such as thermal circulation, thermal shock and fatigue of the micro-salient points and the electromigration and thermal migration resistance are improved, the growth rate of the intermetallic compound at the interface is accelerated, and the manufacturing efficiency of all intermetallic compound welding spots is remarkably improved; the formed preferred orientation full IMC micro-bump with specific morphology has better thermal stability, can reliably serve for a long time above 300 ℃, improves the service reliability of the preferred orientation IMC micro-bump under the conditions of long-time high temperature and high current density, has good compatibility with the existing semiconductor and packaging technology, has simple technology and low cost, and is suitable for large-scale production. The method realizes the precise regulation and control of the morphology and the crystal orientation of the interfacial IMC crystal grains at low process temperature, and rapidly forms the full IMC welding spots with high melting point, high thermal stability and preferred orientation, thereby realizing the preparation of the full intermetallic compound at the preferred orientation under the low temperature condition.
Further, the first under bump metallization layer and the second under bump metallization layer are any one of <111> preferred orientation nano twin crystal Ni, <111> preferred orientation nano twin crystal Cu and preferred orientation nano crystal Cu, so that the under bump metallization layer with high reliability can be obtained.
Furthermore, the lead-free solder micro-bump is any one of gallium, gallium-based lead-free solder and In-based solder, and the gallium, gallium-based lead-free solder and In-based solder are low-temperature lead-free solder, so that the preparation of all intermetallic compounds at low temperature is effectively realized.
Further, the process of preparing the lead-free solder micro-bump on the first under-bump metallization layer specifically comprises the following steps: preparing a first under-bump metallization layer on the first substrate by adopting a direct current electroplating or pulse electroplating method, carrying out annealing treatment on the first under-bump metallization layer, depositing the lead-free solder on the annealed first under-bump metallization layer by adopting an electroplating deposition method, and then carrying out reflow to obtain the lead-free solder micro-bump, thereby effectively realizing the preparation of the lead-free solder micro-bump on the first under-bump metallization layer.
Further, the reflux is 100-150 ℃, so that a preferred orientation interface intermetallic compound seed layer is formed at the interface.
Furthermore, the temperature is 100-150 ℃ and the pressure is not less than 20g during hot press bonding, so that a pressure field is generated in the interconnection structure, and the upper chip and the lower chip can better form interconnection welding spots under the low-temperature condition.
Furthermore, in the hot-press bonding process, the temperature gradient is not less than 500 ℃/cm, so that the interconnection welding spots can quickly form full IMCs welding spots.
Further, the thicknesses of the first under bump metallization layer and the second under bump metallization layer are 2-5 μm, and the diameter of the lead-free solder micro bump is smaller than 30 μm, so that the interconnection reliability of the lead-free solder micro bump is ensured in the process of preparing an interconnection chip.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a method for preparing an all intermetallic compound interconnection chip with preferred orientation in the invention;
FIG. 2 is a schematic structural diagram of step 1 of embodiment 1 of the present invention;
FIG. 3 is a schematic diagram of the micro bump structure in step 1 of embodiment 1 of the present invention;
FIG. 4 is a schematic diagram of the structure of the applied pressure and temperature difference in step 2 of the embodiment 1 of the present invention;
FIG. 5 is a schematic structural view of the preferred orientation all IMCs welding spots prepared by the invention.
Wherein: 10. the first substrate, 20, the first under bump metallization layer, 30, the lead-free solder micro bump, 40, the second substrate, 50, the second under bump metallization layer.
Detailed Description
So that those skilled in the art can appreciate the features and effects of the present invention, a general description and definition of the terms and expressions set forth in the specification and claims follows. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, and in the event of a conflict, the present specification shall control.
The theory or mechanism described and disclosed herein, whether right or wrong, is not meant to limit the scope of the invention in any way, i.e., the present disclosure may be practiced without limitation to any particular theory or mechanism.
All features such as values, amounts, and concentrations that are defined herein in the numerical or percent ranges are for brevity and convenience only. Accordingly, the description of a numerical range or percentage range should be considered to cover and specifically disclose all possible sub-ranges and individual values (including integers and fractions) within the range.
Herein, unless otherwise indicated, "comprising," "including," "having," or similar terms encompass the meanings of "consisting of … …" and "consisting essentially of … …," e.g., "a includes a" encompasses the meanings of "a includes a and the other and" a includes a only.
In this context, not all possible combinations of the individual technical features in the individual embodiments or examples are described in order to simplify the description. Accordingly, as long as there is no contradiction between the combinations of these technical features, any combination of the technical features in the respective embodiments or examples is possible, and all possible combinations should be considered as being within the scope of the present specification.
As shown in FIG. 1, the invention provides a preparation method of a preferred orientation all-intermetallic compound interconnection chip, which comprises the following steps:
s1: preparing a first under bump metallization layer with preferred orientation on a first substrate, and preparing a second under bump metallization layer with preferred orientation on a second substrate; preparing lead-free solder micro-bumps on the first under-bump metallization layer;
in a preferred embodiment, the first under bump metallization layer and the second under bump metallization layer are any one of <111> preferred orientation nano twin Ni, <111> preferred orientation nano twin Cu, and preferred orientation nano Cu. The lead-free solder micro-bump is any one of gallium, gallium-based lead-free solder and In-based solder.
In addition, the process for preparing the lead-free solder micro-bump on the first under-bump metallization layer comprises the following steps: preparing a first under-bump metallization layer on the first substrate by adopting a direct current electroplating or pulse electroplating method, carrying out annealing treatment on the first under-bump metallization layer, depositing the lead-free solder on the annealed first under-bump metallization layer by adopting an electroplating deposition method, and then carrying out reflow, wherein the reflow temperature is 100-150 ℃, so as to obtain the lead-free solder micro-bump.
The thickness of the first under bump metallization layer and the second under bump metallization layer is 2-5 μm, and the diameter of the lead-free solder micro bump is less than 30 μm, preferably 1-30 μm.
In addition, the first substrate and the second substrate are made of copper and have the same arrangement pattern;
s2: and placing the lead-free solder and the second under-bump metallization layer in contact, and performing hot-pressing bonding treatment to form micro-welding spots so as to finish the preparation of the preferred-orientation all-intermetallic compound interconnection chip.
Wherein the temperature is 100-150 ℃ and the pressure is not less than 20g during hot press bonding. The temperature gradient is not less than 500 ℃/cm.
In the step, lead-free solder micro-bumps and the second bump lower metallization layer are aligned one by one and placed in contact, micro-welding spots are rapidly formed at low temperature by a hot pressing method, different pressure fields and temperature differences are applied in the process, namely, a certain temperature gradient or pressure is formed in the combined body, the temperature gradient direction is led to the first metal bonding pad from the second metal bonding pad until the low-temperature lead-free solder bumps are melted and then all the brazing reaction is converted into intermetallic compounds; the temperature gradient is defined as T/D, where T is the temperature difference between the first substrate and the second substrate and D is the distance between the first substrate and the second substrate.
The intermetallic compound forms a growth on the first under bump metallization layer. As the material, hot-pressing temperature, temperature gradient and pressure of the under-bump metallization layer and the solder are the most important factors affecting the rapid formation of preferred full IMCs welding spots at low temperature, the growth rate of the interfacial intermetallic compound increases with the increase of the temperature gradient.
Meanwhile, the invention also discloses a preferred orientation all-intermetallic compound interconnection chip which is prepared by the method;
the preferred orientation all-intermetallic compound interconnection chip comprises a first substrate, a first under-bump metallization layer on the first substrate, a second substrate and a second under-bump metallization layer on the second substrate, wherein the first under-bump metallization layer and the second under-bump metallization layer are connected through intermetallic compounds, and intermetallic compound crystal grains have ridge-shaped morphology and preferred directions.
The invention replaces monocrystalline Cu UBMs which have complicated process and high cost and cannot be applied to the electronic industry by utilizing the preferred orientation nano twin Ni, cu and nano Cu UBMs which have excellent performance, simple process and low cost; and then successfully preparing the low Wen Jiaji lead-free solder and forming gallium-based lead-free micro-bumps at extremely low thermal compression bonding temperature (100-150 ℃) so as to ensure that Cu with preferred orientation is formed at the interface of the first under-bump metallization layer 9 Ga 4 An intermetallic compound as a seed layer for subsequent reactions; the brazing method has the advantages that the pressure or the temperature gradient is applied during the brazing reaction, so that the microstructure of the intermetallic compound is controlled, the preferred orientation IMCs micro-salient points are formed, the mechanical properties such as thermal circulation, thermal shock and fatigue of the micro-salient points and the electromigration and thermal migration resistance are improved, the growth rate of the intermetallic compound at the interface is accelerated, and the manufacturing efficiency of all intermetallic compound welding spots is remarkably improved; formed preferred orientation full IMC micro-convex point with specific shapeThe alloy has good thermal stability and can be reliably used for a long time at the temperature of above 300 ℃; due to<111>The preferred orientation nano twin crystal Ni and Cu have excellent effect of inhibiting the Kendall holes, so that the service reliability of the preferred orientation IMC micro-salient point under the conditions of long-time high temperature and high current density is improved; has good compatibility with the existing semiconductor and packaging technology, simple technology, low cost and suitability for mass production
Meanwhile, the invention also discloses application of the all-intermetallic compound interconnection chip with preferred orientation in the technical field of semiconductors.
The invention will be further illustrated with reference to specific examples. It is to be understood that these examples are illustrative of the present invention and are not intended to limit the scope of the present invention. Further, it is understood that various changes and modifications may be made by those skilled in the art after reading the teachings of the present invention, and such equivalents are intended to fall within the scope of the claims appended hereto.
The following examples use instrumentation conventional in the art. The experimental methods, in which specific conditions are not noted in the following examples, are generally conducted under conventional conditions or under conditions recommended by the manufacturer. The following examples used various starting materials, unless otherwise indicated, were conventional commercial products, the specifications of which are conventional in the art. In the description of the present invention and the following examples, "%" means weight percent, and "parts" means parts by weight, and ratios means weight ratio, unless otherwise specified.
Example 1
As shown in fig. 2, 3, 4 and 5, a method for preparing a preferred orientation all IMCs interconnection chip at low temperature in the present invention may be implemented by the following specific process steps:
step one: providing a first substrate 10, preparing 5 mu m high-density <111> preferred orientation nano twin crystal Ni and <111> preferred orientation nano twin crystal Cu which are used as under-bump metallization layers on the first substrate 10 by adopting a direct current or pulse electroplating method, namely, annealing the under-bump metallization layers, electroplating low-temperature gallium on the under-bump metallization layers, and forming lead-free solder micro-bumps 30 with the diameter of 30 mu m after reflow, wherein the reflow temperature is preferably 100 ℃; providing a second substrate 50, and preparing 5 mu m preferred orientation nanocrystalline Cu as an under bump metallization layer by adopting a direct current or pulse electroplating method, namely a second under bump metallization layer 40, so that the array patterns of the first under bump metallization layer 20 and the second under bump metallization layer 40 are the same;
step two: aligning the lead-free solder micro-bumps 30 with the second under-bump metallization layers 40 one by one and placing the lead-free solder micro-bumps in contact with each other to form a combination;
step three: heating the assembly formed in the second step to 100deg.C for thermocompression bonding, and simultaneously applying a temperature difference to the assembly to make the temperature gradient through the first under bump metallization layer 30 5×10 2 At a temperature of about DEG C/cm, and in a direction of a temperature gradient from the second under bump metallization layer 20 to the first under bump metallization layer 40 until a braze reaction is fully converted to a preferred orientation Cu after melting of the low Wen Jiaji micro bump 9 Ga 4 And (3) the intermetallic compound 31 is used for obtaining the preferred orientation full IMC interconnection micro-bump.
Example 2
As shown in fig. 2, 3, 4 and 5, the method for preparing the preferred orientation all IMCs interconnection chip at low temperature can be realized through the following specific process steps:
step one: providing a first substrate 10, preparing 3 mu m high-density <111> preferred orientation nano twin crystal Ni serving as an under-bump metallization layer on the first substrate by adopting a direct current or pulse electroplating method, namely, carrying out annealing treatment on the under-bump metallization layer, electroplating low-temperature metal Ga on the under-bump metallization layer 20, and forming a lead-free solder micro-bump 30 with the diameter of 10 mu m after reflow, wherein the reflow temperature is 150 ℃; providing a second substrate 50, and preparing 3 mu m high-density nanocrystalline Cu with excellent performance on the second substrate by adopting a direct current or pulse electroplating method as an under bump metallization layer, namely a second under bump metallization layer 40, so that the array patterns of the first under bump metallization layer 30 and the second under bump metallization layer 40 are the same;
step two: aligning the lead-free solder micro-bumps 30 with the second under-bump metallization layers 40 one by one and placing the lead-free solder micro-bumps in contact with each other to form a combination;
step three: heating the combination body formed in the second step to 150 ℃ for hot-press bonding process, wherein the pressure is that the brazing reaction is completely converted into Cu with preferred orientation after the Ga-based micro-convex points are melted 9 Ga 4 And (3) obtaining the preferred orientation full IMC interconnection micro-convex points by the intermetallic compound.
Example 3
As shown in fig. 2, 3 and 4, the method for preparing the preferred orientation full IMCs welding spot for 3D packaging at low temperature can be realized by the following specific process steps:
step one: providing a first substrate 10, preparing at least one first metal bonding pad on the first substrate by adopting physical vapor deposition, electroplating and magnetron sputtering methods, preparing 5 mu m high-density <111> preferred orientation nano twin crystal Cu serving as an under-bump metallization layer, namely a first under-bump metallization layer 20, annealing the under-bump metallization layer, electroplating low-temperature metal GaSn on the under-bump metallization layer, and forming a lead-free solder micro-bump 30 with the diameter of 30 mu m after reflow, wherein the reflow temperature is 150 ℃; providing a second substrate 40, preparing at least one second metal pad on the second substrate by adopting a physical vapor deposition, electroplating and magnetron sputtering method, and preparing 50 mu m high-density <111> preferred orientation nano twin crystal Cu serving as an under bump metallization layer, namely a second under bump metallization layer 50, on the second substrate by adopting a direct current or pulse electroplating method, so that the array patterns of the first under bump metallization layer 20 and the second under bump metallization layer 50 are the same;
step two: aligning the Sn-Cu micro-bumps with the second under-bump metallization layers 50 one by one and placing the Sn-Cu micro-bumps in contact with each other to form a combination;
step three: the assembly formed in the second heating step is heated to 150 ℃ for braze welding and reflow, and simultaneously pressure and a temperature field (the temperature of the upper pressing substrate is high, the temperature of the bearing substrate is low, and finally a temperature difference is formed on the upper substrate and the lower substrate) are simultaneously applied to the assembly, so that the temperature gradient passing through the first under bump metallization layer 20 is 1 multiplied by 10 4 ℃/cm 2 And warmThe gradient direction is directed from the second under bump metallization layer 50 to the first under bump metallization layer 20 until the soldering reaction is completely changed into the preferred orientation Cu after the GaSn micro-bumps are melted 9 Ga 5 And (3) obtaining the preferred orientation full IMC interconnection micro-convex points by the intermetallic compound.
Example 4
The invention provides a preparation method of a preferred orientation all-intermetallic compound interconnection chip, which comprises the following steps:
s1: preparing a first under bump metallization layer with preferred orientation on a first substrate, and preparing a second under bump metallization layer with preferred orientation on a second substrate; preparing lead-free solder micro-bumps on the first under-bump metallization layer;
the first under bump metallization layer and the second under bump metallization layer are nano twin Ni with preferred orientation of <111 >. The lead-free solder micro-bump is in gallium solder.
In addition, the process for preparing the lead-free solder micro-bump on the first under-bump metallization layer comprises the following steps: preparing a first under-bump metallization layer on the first substrate by adopting a direct current electroplating or pulse electroplating method, carrying out annealing treatment on the first under-bump metallization layer, depositing the lead-free solder on the annealed first under-bump metallization layer by adopting an electroplating deposition method, and then carrying out reflow, wherein the reflow temperature is 100 ℃, so as to obtain the lead-free solder micro-bump.
The thicknesses of the first under bump metallization layer and the second under bump metallization layer are 2 mu m, and the diameters of the lead-free solder micro bumps are 5 mu m.
In addition, the first substrate and the second substrate are made of copper and have the same arrangement pattern;
s2: and placing the lead-free solder and the second under-bump metallization layer in contact, and performing hot-pressing bonding treatment to form micro-welding spots so as to finish the preparation of the preferred-orientation all-intermetallic compound interconnection chip.
Wherein the temperature is 100 ℃ and the pressure is 20g during the thermocompression bonding. The temperature gradient was 500℃cm.
Example 5
The invention provides a preparation method of a preferred orientation all-intermetallic compound interconnection chip, which comprises the following steps:
s1: preparing a first under bump metallization layer with preferred orientation on a first substrate, and preparing a second under bump metallization layer with preferred orientation on a second substrate; preparing lead-free solder micro-bumps on the first under-bump metallization layer;
the first under bump metallization layer and the second under bump metallization layer are nano twin crystal Cu with preferred orientation of <111 >. The lead-free solder micro-bump is gallium indium lead-free solder.
In addition, the process for preparing the lead-free solder micro-bump on the first under-bump metallization layer comprises the following steps: preparing a first under-bump metallization layer on the first substrate by adopting a direct current electroplating or pulse electroplating method, carrying out annealing treatment on the first under-bump metallization layer, depositing the lead-free solder on the annealed first under-bump metallization layer by adopting an electroplating deposition method, and then carrying out reflow, wherein the reflow temperature is 120 ℃, so as to obtain the lead-free solder micro-bump.
The thicknesses of the first under bump metallization layer and the second under bump metallization layer are 3 mu m, and the diameters of the lead-free solder micro bumps are 10 mu m.
In addition, the first substrate and the second substrate are made of copper and have the same arrangement pattern;
s2: and placing the lead-free solder and the second under-bump metallization layer in contact, and performing hot-pressing bonding treatment to form micro-welding spots so as to finish the preparation of the preferred-orientation all-intermetallic compound interconnection chip.
Wherein the temperature is 120 ℃ and the pressure is 30g during hot press bonding. The temperature gradient was 520℃C/cm.
Example 6
The invention provides a preparation method of a preferred orientation all-intermetallic compound interconnection chip, which comprises the following steps:
s1: preparing a first under bump metallization layer with preferred orientation on a first substrate, and preparing a second under bump metallization layer with preferred orientation on a second substrate; preparing lead-free solder micro-bumps on the first under-bump metallization layer;
the first under bump metallization layer and the second under bump metallization layer are any one of nanocrystalline Cu with preferred orientation. The lead-free solder micro-bump is an In-based solder.
In addition, the process for preparing the lead-free solder micro-bump on the first under-bump metallization layer comprises the following steps: preparing a first under-bump metallization layer on the first substrate by adopting a direct current electroplating or pulse electroplating method, carrying out annealing treatment on the first under-bump metallization layer, depositing the lead-free solder on the annealed first under-bump metallization layer by adopting an electroplating deposition method, and then carrying out reflow, wherein the reflow temperature is 150 ℃, so as to obtain the lead-free solder micro-bump.
The thicknesses of the first under bump metallization layer and the second under bump metallization layer are 5 mu m, and the diameters of the lead-free solder micro bumps are 30 mu m.
In addition, the first substrate and the second substrate are made of copper and have the same arrangement pattern;
s2: and placing the lead-free solder and the second under-bump metallization layer in contact, and performing hot-pressing bonding treatment to form micro-welding spots so as to finish the preparation of the preferred-orientation all-intermetallic compound interconnection chip.
Wherein the temperature is 150 ℃ and the pressure is 30g during hot press bonding. The temperature gradient was 600℃C/cm.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the scope of the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present invention may be modified or substituted equally without departing from the spirit and scope of the technical solution of the present invention.
Claims (10)
1. The preparation method of the preferentially oriented all-intermetallic compound interconnection chip is characterized by comprising the following steps of:
preparing a first under bump metallization layer with preferred orientation on a first substrate, and preparing a second under bump metallization layer with preferred orientation on a second substrate; preparing lead-free solder micro-bumps on the first under-bump metallization layer;
and placing the lead-free solder micro-bump and the second bump lower metallization layer in contact, and performing hot-pressing bonding treatment to form micro-welding spots, thereby completing the preparation of the preferentially oriented all-intermetallic compound interconnection chip.
2. The method for manufacturing a preferred-orientation all-intermetallic compound interconnection chip according to claim 1, wherein the first under-bump metallization layer and the second under-bump metallization layer are both any one of <111> preferred-orientation nano twin Ni, <111> preferred-orientation nano twin Cu and preferred-orientation nano Cu.
3. The method for manufacturing a preferred orientation all intermetallic compound interconnection chip according to claim 1, wherein the lead-free solder micro bump is any one of gallium, gallium-based lead-free solder and In-based solder.
4. The method for manufacturing a preferred orientation all intermetallic compound interconnection chip according to claim 1, wherein the process for manufacturing the lead-free solder micro bump on the first under bump metallization layer comprises the following steps: preparing a first under-bump metallization layer on the first substrate by adopting a direct current electroplating or pulse electroplating method, carrying out annealing treatment on the first under-bump metallization layer, depositing the lead-free solder on the annealed first under-bump metallization layer by adopting an electroplating deposition method, and then carrying out reflow to obtain the lead-free solder micro-bump.
5. The method for producing a preferred orientation of all-intermetallic compound interconnect chip of claim 4 wherein the reflow temperature is 100-150 ℃.
6. The method for manufacturing an all-intermetallic compound interconnection chip with preferred orientation according to claim 1, wherein the temperature is 100-150 ℃ and the pressure is not less than 20g during thermocompression bonding.
7. The method for manufacturing a preferred orientation all-intermetallic compound interconnect chip of claim 1 wherein the thermal compression bonding process has a temperature gradient of not less than 500 ℃/cm.
8. The method for manufacturing a preferred orientation all intermetallic compound interconnection chip according to claim 1, wherein the thickness of the first under bump metallization layer and the second under bump metallization layer is 2-5 μm, and the diameter of the lead-free solder micro bump is less than 30 μm.
9. A preferentially oriented all intermetallic interconnect chip, characterized in that it is produced by the method of any one of claims 1 to 8;
the preferred orientation all-intermetallic compound interconnection chip comprises a first substrate, a first under-bump metallization layer on the first substrate, a second substrate and a second under-bump metallization layer on the second substrate, wherein the first under-bump metallization layer and the second under-bump metallization layer are connected through intermetallic compounds, and intermetallic compound crystal grains have ridge-shaped morphology and preferred directions.
10. The use of a preferentially oriented all-intermetallic interconnect chip as claimed in claim 9 in the field of semiconductor technology.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311634918.7A CN117711963A (en) | 2023-11-30 | 2023-11-30 | All-intermetallic compound interconnection chip with preferential orientation and preparation method and application thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311634918.7A CN117711963A (en) | 2023-11-30 | 2023-11-30 | All-intermetallic compound interconnection chip with preferential orientation and preparation method and application thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117711963A true CN117711963A (en) | 2024-03-15 |
Family
ID=90143438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311634918.7A Pending CN117711963A (en) | 2023-11-30 | 2023-11-30 | All-intermetallic compound interconnection chip with preferential orientation and preparation method and application thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117711963A (en) |
-
2023
- 2023-11-30 CN CN202311634918.7A patent/CN117711963A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20190319007A1 (en) | Low temperature bonded structures | |
| US8592995B2 (en) | Method and structure for adhesion of intermetallic compound (IMC) on Cu pillar bump | |
| US7576435B2 (en) | Low-cost and ultra-fine integrated circuit packaging technique | |
| US8003512B2 (en) | Structure of UBM and solder bumps and methods of fabrication | |
| US6362090B1 (en) | Method for forming flip chip bump and UBM for high speed copper interconnect chip using electroless plating method | |
| US8901735B2 (en) | Connector design for packaging integrated circuits | |
| CN101304014B (en) | Semiconductor chip and manufacturing method thereof | |
| US20060201997A1 (en) | Fine pad pitch organic circuit board with plating solder and method for fabricating the same | |
| Zhan et al. | Assembly and reliability characterization of 3D chip stacking with 30μm pitch lead-free solder micro bump interconnection | |
| US20060276022A1 (en) | Capping copper bumps | |
| JPH10509278A (en) | Flip-chip technology core metal solder knob | |
| US6716738B2 (en) | Method of fabricating multilayered UBM for flip chip interconnections by electroplating | |
| US20080308297A1 (en) | Ubm Pad, Solder Contact and Methods for Creating a Solder Joint | |
| US7874475B2 (en) | Method for the planar joining of components of semiconductor devices and a diffusion joining structure | |
| JP4130508B2 (en) | Solder bonding method and electronic device manufacturing method | |
| CN115411006A (en) | Micro-welding point based on nanocrystalline copper matrix and preparation method thereof | |
| US5795619A (en) | Solder bump fabricated method incorporate with electroless deposit and dip solder | |
| JP2018093001A (en) | Electronic device and manufacturing method of electronic device | |
| TW200845251A (en) | Bump structure for semiconductor device | |
| CN117711963A (en) | All-intermetallic compound interconnection chip with preferential orientation and preparation method and application thereof | |
| CN104465573B (en) | It is a kind of that the cylindrical bump packaging structure of reaction interface layer is used as using FeNi alloys or FeNiP alloys | |
| EP1734569B1 (en) | Process for producing semiconductor module | |
| CN110744163A (en) | Heat migration resistant micro welding spot structure and preparation method thereof | |
| TWI220304B (en) | Flip-chip package substrate and flip-chip bonding process thereof | |
| CN112103262B (en) | Method for controlling crystal orientation and microstructure of all-intermetallic compound micro-interconnection welding spot |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |