CN117709279A - Three-dimensional integrated circuit layout method, three-dimensional integrated circuit layout device, electronic equipment and storage medium - Google Patents
Three-dimensional integrated circuit layout method, three-dimensional integrated circuit layout device, electronic equipment and storage medium Download PDFInfo
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Abstract
The application provides a three-dimensional integrated circuit layout method, a three-dimensional integrated circuit layout device, electronic equipment and a storage medium, and relates to the technical field of integrated circuits. The method comprises the following steps: obtaining layout design of bottom crystal grains in the three-dimensional integrated circuit, wherein top crystal grains are stacked on the bottom crystal grains; according to the power ground network of the bottom layer crystal grain, the positions of all ports in the layout design of the bottom layer crystal grain are adjusted; according to the positions of all ports in the layout design of the bottom layer crystal grain and the port mapping relation of the bottom layer crystal grain and the top layer crystal grain, the positions of all ports in the top layer crystal grain are adjusted; and according to the positions of all the ports in the top-layer crystal grains, carrying out layout on the top-layer crystal grains to obtain the layout design of the top-layer crystal grains. The method and the device can realize collaborative layout of the stacked crystal grains in the three-dimensional integrated circuit and ensure timing sequence convergence of the stacked crystal grains.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a three-dimensional integrated circuit layout method, apparatus, electronic device, and storage medium.
Background
With the increasing integration level of integrated circuits, the development of integrated circuit technology according to "moore's law is gradually slowed, and in order to break through the limitation of" moore's law, "three-dimensional integrated circuit design (3D-IC) has become an important breakthrough.
The difficulty and emphasis of three-dimensional integrated circuit design is on the layout of multiple dies (die), and how to implement a multi-die collaborative layout is a technical obstacle for 3D-IC development.
The existing layout method can only independently layout and route a plurality of die, and the layout stage cannot perform time sequence optimization at the same time, so that the time sequence established among the plurality of die is difficult to converge.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a three-dimensional integrated circuit layout method, a device, electronic equipment and a storage medium, so as to realize collaborative layout of stacked grains in a three-dimensional integrated circuit and ensure timing convergence of the stacked grains.
In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
in a first aspect, embodiments of the present application provide a three-dimensional integrated circuit layout method, the method including:
obtaining layout design of bottom crystal grains in a three-dimensional integrated circuit, wherein top crystal grains are stacked on the bottom crystal grains;
According to the power ground network of the bottom layer crystal grain, the positions of all ports in the layout design of the bottom layer crystal grain are adjusted;
according to the positions of all ports in the layout design of the bottom layer crystal grain and the port mapping relation between the bottom layer crystal grain and the top layer crystal grain, the positions of all ports in the top layer crystal grain are adjusted;
and according to the positions of all the ports in the top layer crystal grain, carrying out layout on the top layer crystal grain to obtain the layout design of the top layer crystal grain.
Optionally, the obtaining the layout design of the bottom layer die in the three-dimensional integrated circuit includes:
obtaining a floor plan of the bottom layer crystal grain;
and laying out the bottom layer crystal grains according to the layout of the bottom layer crystal grains and the interface delay constraint of the bottom layer crystal grains to obtain the layout design of the bottom layer crystal grains.
Optionally, before the layout of the bottom layer die is performed according to the layout of the bottom layer die and the interface delay constraint of the bottom layer die to obtain the layout design of the bottom layer die, the method further includes:
obtaining a path list of each port in the bottom layer crystal grain, wherein the path list comprises: a plurality of transmission paths;
Calculating the complete delay of the transmission paths between the bottom layer crystal grain and the top layer crystal grain;
calculating external delays of the plurality of transmission paths on the top-layer die;
and calculating the constraint absolute delay value of each port according to the complete delay and the external delay to obtain the interface delay constraint of the bottom layer crystal grain.
Optionally, the adjusting the position of each port in the layout design of the bottom die according to the power-ground network of the bottom die includes:
determining a first power grid which is within a preset range with the physical units connected with each port according to the positions of the physical units connected with each port on the bottom layer crystal grain in the layout design of the bottom layer crystal grain;
and placing each port in the corresponding first position area according to the first position area of the first power grid on the bottom layer crystal grain.
Optionally, the determining, according to the position of the physical unit connected to each port in the layout design of the bottom die on the bottom die, the first power grid connected to the physical unit connected to each port in a preset range includes:
If the number of the physical units connected with each port is one, determining the position coordinates of the physical units connected with each port on the bottom layer crystal grain;
and determining a first power grid which is within a preset range with the position coordinate.
Optionally, the determining, according to the position of the physical unit connected to each port in the layout design of the bottom die on the bottom die, the first power grid connected to the physical unit connected to each port in a preset range includes:
if the number of the physical units connected with each port is a plurality of, calculating an average position coordinate according to the position coordinates of the physical units connected with each port on the bottom layer crystal grain;
and determining a first power grid which is within a preset range with the average position coordinate.
Optionally, the placing each port in the corresponding first location area according to the first location area of the first power grid on the bottom die includes:
judging whether the first position area meets the placement requirements of all ports corresponding to the first power grid or not according to the area of the first position area;
If the first position area does not meet the placement requirements of all ports corresponding to the first power grid, determining a second power grid of a physical unit connected with the remaining ports within a preset range;
and placing the remaining ports in a second position area on the bottom layer crystal grain according to the second position area of the second power grid.
Optionally, before determining the second power grid of the physical unit connected to the remaining ports within the preset range if the first location area does not meet the placement requirements of all the ports corresponding to the first power grid, the method further includes:
sequencing the external delays of all ports corresponding to the first power grid according to the external delays of all ports corresponding to the first power grid;
determining the number of the ports which can be placed in the first position area according to the area of the first position area;
and determining the remaining ports with the minimum external delay according to the number of the placeable ports and the sequencing of the external delays of all the ports.
In a second aspect, embodiments of the present application further provide a three-dimensional integrated circuit layout apparatus, the apparatus including:
A bottom layer grain layout design obtaining module, configured to obtain a layout design of a bottom layer grain in a three-dimensional integrated circuit, where a top layer grain is stacked on the bottom layer grain;
the bottom layer crystal grain port position adjusting module is used for adjusting the positions of all ports in the layout design of the bottom layer crystal grain according to the power ground network of the bottom layer crystal grain;
the top layer crystal grain port position adjusting module is used for adjusting the positions of all ports in the top layer crystal grain according to the positions of all ports in the layout design of the bottom layer crystal grain and the port mapping relation between the bottom layer crystal grain and the top layer crystal grain;
and the top-layer crystal grain layout design module is used for carrying out layout on the top-layer crystal grains according to the positions of all ports in the top-layer crystal grains to obtain the layout design of the top-layer crystal grains.
Optionally, the bottom layer grain layout design obtaining module is specifically configured to obtain a layout of the bottom layer grain; and laying out the bottom layer crystal grains according to the layout of the bottom layer crystal grains and the interface delay constraint of the bottom layer crystal grains to obtain the layout design of the bottom layer crystal grains.
Optionally, before the obtaining module of the underlying die layout design, the apparatus further includes:
A path list obtaining module, configured to obtain a path list of each port in the bottom layer die, where the path list includes: a plurality of transmission paths;
the complete delay calculation module is used for calculating the complete delay of the transmission paths between the bottom layer crystal grain and the top layer crystal grain;
an external delay calculation module, configured to calculate external delays of the plurality of transmission paths on the top-layer die;
and the absolute constraint calculating module is used for calculating the constraint absolute delay value of each port according to the complete delay and the external delay to obtain the interface delay constraint of the bottom layer crystal grain.
Optionally, the bottom layer grain port position adjustment module includes:
the first power supply network determining unit is used for determining a first power supply grid which is in a preset range with the physical units connected with each port according to the positions of the physical units connected with each port on the bottom layer crystal grain in the layout design of the bottom layer crystal grain;
and the first port placement unit is used for placing each port in the corresponding first position area according to the first position area of the first power grid on the bottom layer die.
Optionally, the first power network determining unit is specifically configured to determine a position coordinate of the physical unit connected to each port on the bottom layer die if the number of the physical units connected to each port is one; and determining a first power grid which is within a preset range with the position coordinate.
Optionally, the first power network determining unit is further configured to calculate an average position coordinate according to position coordinates of the plurality of physical units connected to each port on the bottom layer die if the number of physical units connected to each port is multiple; and determining a first power grid which is within a preset range with the average position coordinate.
Optionally, the first port placement unit includes:
the placement requirement judging unit is used for judging whether the first position area meets the placement requirements of all ports corresponding to the first power grid according to the area of the first position area;
a second power network determining unit, configured to determine a second power grid within a preset range of a physical unit connected to the remaining ports if the first location area does not meet the placement requirements of all ports corresponding to the first power grid;
And the remaining port placing unit is used for placing the remaining ports in a second position area on the bottom layer crystal grain according to the second position area of the second power grid.
Optionally, before the second power network determining unit, the apparatus further includes:
the delay sequencing unit is used for sequencing the external delays of all the ports corresponding to the first power grid according to the external delays of all the ports corresponding to the first power grid;
a port number determining unit, configured to determine, according to an area of the first location area, a number of ports that can be placed in the first location area;
and the remaining port determining unit is used for determining the remaining port with the minimum external delay according to the number of the placeable ports and the ordering of the external delays of all the ports.
In a third aspect, embodiments of the present application further provide an electronic device, including: a processor, a storage medium and a bus, the storage medium storing program instructions executable by the processor, the processor and the storage medium communicating over the bus when the electronic device is running, the processor executing the program instructions to perform the steps of the three-dimensional integrated circuit layout method according to any of the first aspects.
In a fourth aspect, embodiments of the present application further provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the three-dimensional integrated circuit layout method according to any of the first aspects.
The beneficial effects of this application are:
according to the three-dimensional integrated circuit layout method, the device, the electronic equipment and the storage medium, after the positions of all ports on the bottom layer crystal grains are adjusted based on the power ground network of the bottom layer crystal grains, the positions of all the ports in the top layer crystal grains are adjusted according to the port mapping relation of the bottom layer crystal grains and the top layer crystal grains, the top layer crystal grains are laid out according to the positions of all the ports in the top layer crystal grains after adjustment, so that layout design of the top layer crystal grains is obtained, static time sequence analysis and adjustment are carried out on the layout design of the bottom layer crystal grains and the layout design of the top layer crystal grains, collaborative layout of stacked crystal grains in the three-dimensional integrated circuit is achieved, and time sequence convergence of the stacked crystal grains is guaranteed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a three-dimensional integrated circuit layout method according to an embodiment of the present application;
FIG. 2 is a second flow chart of a layout method of a three-dimensional integrated circuit according to an embodiment of the present disclosure;
FIG. 3 is a flowchart illustrating a three-dimensional integrated circuit layout method according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a transmission path according to an embodiment of the present application;
fig. 5 is a flow chart diagram of a three-dimensional integrated circuit design method according to an embodiment of the present application;
fig. 6 is a flowchart of a three-dimensional integrated circuit design method according to an embodiment of the present application;
fig. 7 is a flowchart of a three-dimensional integrated circuit design method according to an embodiment of the present application;
fig. 8 is a flow chart of a three-dimensional integrated circuit design method according to an embodiment of the present application;
FIG. 9 is a schematic flow chart eight of a three-dimensional integrated circuit design method according to an embodiment of the present disclosure;
fig. 10 is a schematic structural diagram of a three-dimensional integrated circuit layout device according to an embodiment of the present application;
fig. 11 is a schematic diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
Furthermore, the terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that, without conflict, features in embodiments of the present application may be combined with each other.
Chip design is an important step in the chip fabrication process and can be divided into front-end design and back-end design. The front end is mainly responsible for logic implementation, while the back end is mainly responsible for changing the design of the front end into a real schematic and layout (scheme & layout), streaming and mass production.
The main process of chip back-end design includes: data import, floor plan (Floorplan), layout optimization (Placement), clock tree synthesis (Clock Tree Synthesis, CTS), routing (Route), and signature (Sign off).
The data importing stage is used for importing design data required by the back-end design, and the design data comprises: the front-end design is followed by synthesis to generate a Gate-Level netlist (Gate-Level net list), an integrated circuit design constraint (Synopsys Design Constraints, SDC) file with timing constraints and clock definitions, and physical design cell library data.
It should be noted that, the gate level netlist includes the logic connection relations of the cells on each layer of dies in the three-dimensional integrated circuit design, and the logic connection relations between the dies of each layer, the SDC file imported in the data importing stage is the time sequence constraint information of the whole three-dimensional integrated circuit, and the time sequence constraint information of the dies of each layer needs to be calculated in addition according to the logic connection relations of the cells on the dies of each layer.
The floor planning stage is used to complete the design of I/O Pad, physical layout of macro cells, standard cell layout constraints, and power network layout implementation. The I/O Pad is reserved in advance, the macro unit is mainly placed according to the time sequence requirement, the standard unit defines a specific area range and is automatically placed by a tool according to layout constraint information, and the power supply network layout is used for completing a reasonable power supply network required by the chip during work.
And the layout optimization stage is used for automatically placing the standard cells according to the gate-level netlist and the time sequence constraint information after the layout planning is completed.
The clock tree synthesis stage is used for driving all time sequence units, clock networks and buffers used by the time sequence units and the clock networks in the design to form a physical clock tree according to clock requirements in the chip.
The wiring stage is used for connecting the input/output ports of each unit module by using the interconnection lines according to the connection relation of the circuit under the condition of meeting the process rule, the wiring layer limit, the line width and the line interval limit and the electrical performance constraint of reliable insulation of each line network.
In the layout optimization stage, the prior art only considers Manhattan distances between cluster units and between units in a two-dimensional plane, but in the three-dimensional integrated circuit design, stacked grains cannot realize time sequence optimization of the stacked grains in a mode of calculating optimal distance dissociation between the units.
Specific implementations of the three-dimensional integrated circuit layout method are described in detail below with reference to the accompanying drawings and examples.
Referring to fig. 1, a first flowchart of a three-dimensional integrated circuit layout method according to an embodiment of the present application is shown in fig. 1, where the method may include:
s101: and obtaining the layout design of the bottom layer crystal grain in the three-dimensional integrated circuit, wherein the top layer crystal grain is stacked on the bottom layer crystal grain.
In an embodiment, a three-dimensional integrated circuit includes a plurality of dies stacked in a vertical direction, wherein at least a bottom die (bottom die) and a top die (top die) stacked on the bottom die may be included.
The layout design of the bottom layer crystal grain is that the standard cells are initially placed according to the gate-level netlist and the time sequence constraint information, specifically, an electronic design automation (Electronics Design Automation, EDA) tool can be adopted to automatically place the standard cells in a specific area range of the bottom layer crystal grain according to the layout constraint information and the time sequence constraint information.
S102: and adjusting the positions of all ports in the layout design of the bottom crystal grain according to the power ground network of the bottom crystal grain.
In this embodiment, in order to ensure that the timing sequence of the bottom die and the top die can be optimized at the same time, after the standard cells are automatically placed, the positions of the I/O cells in the bottom die and the top die need to be adjusted, each port in the I/O cells serves as a bridge for connecting signals inside the chip and package pins, and the placement positions of each port in the I/O cells are adjusted to synchronously optimize the timing sequences of the bottom die and the top die.
Specifically, in order to ensure that the time sequence of the bottom layer crystal grain and the top layer crystal grain can be optimized at the same time, the time sequence violation of a transmission path between the bottom layer crystal grain and the top layer crystal grain caused by the layout design of the bottom layer crystal grain is avoided, after the standard unit is automatically placed on the bottom layer crystal grain, the layout design of the bottom layer crystal grain is firstly subjected to time sequence analysis, the transmission path with the time sequence violation on the bottom layer crystal grain is determined, the position of an IO port corresponding to the transmission path with the time sequence violation on the bottom layer crystal grain is adjusted, the distance of the transmission path is shortened, and the time sequence violation of the transmission path on the bottom layer crystal grain is repaired.
Acquiring power network planning information of a bottom layer crystal grain, wherein the power network planning information comprises the following steps: the method comprises the steps of planning a through silicon via area on a bottom layer grain, planning a power network of the bottom layer grain, planning a power network of a top layer grain, and planning power pins between the bottom layer grain and the top layer grain.
Wherein, the power network planning of the bottom layer crystal grain comprises: the power ground network formed by a plurality of power lines VDD and ground lines VSS on the underlying die, specifically, the power lines VDD and ground lines VSS are alternately arranged in parallel in both the horizontal direction and the vertical direction, so as to form a large number of power grids on the underlying die.
According to the position relation between the physical units connected with each port on the bottom layer crystal grain and each power grid, determining a target power grid which meets the preset position relation with the position relation of the physical units connected with each port, and according to the position area defined by the target power grid in the bottom layer crystal grain, adjusting the position of the corresponding port to the position area corresponding to the target power grid.
In some embodiments, the positional relationship may be a distance between the physical unit to which each port is connected and each power grid.
In some embodiments, after the layout and port positions of the bottom die are adjusted, an interface timing model and a physical information model of the top die are generated. Wherein the interface timing model may include: each port establishes time and hold time constraint values for each input port and internal delay values for each output port. The physical information model may include: the bottom layer grain size, the signal port name, the metal layer where the signal port is located, the pin position, the power and ground pin position, and the no-wiring area.
It should be noted that, the physical units to which the ports are connected may be obtained from the gate level netlist.
S103: and adjusting the positions of all ports in the top layer crystal grain according to the positions of all ports in the layout design of the bottom layer crystal grain and the port mapping relation of the bottom layer crystal grain and the top layer crystal grain.
In this embodiment, after the adjustment of the positions of the ports in the bottom die is completed, the positions of the ports in the top die need to be adjusted according to the positions of the ports in the bottom die.
Specifically, the port mapping relationship between the bottom layer grain and the top layer grain is obtained from the gate level netlist of the three-dimensional integrated circuit design, the port mapping relationship is used for indicating the one-to-one corresponding interconnection mapping relationship between each port in the bottom layer grain and each port in the bottom layer grain, the position of each port in the top layer grain is determined according to the port mapping relationship between the bottom layer grain and the top layer grain and the position of each port in the bottom layer grain, and the placement of each port position in the I/O unit of the top layer grain is completed according to the position of each port in the top layer grain.
Illustratively, the port mapping relationship of the bottom die and the top die is recorded in the gate level netlist in the form of a port interconnect mapping table.
It should be noted that, in addition to adjusting the placement position of the IO port on the top die according to the placement position of the IO port on the bottom die, the placement position of the power port on the top die is also consistent with the placement position of the power port on the top die.
S104: and according to the positions of all the ports in the top-layer crystal grains, carrying out layout on the top-layer crystal grains to obtain the layout design of the top-layer crystal grains.
In this embodiment, after the placement of each port in the top-level die is completed, according to the interface logic corresponding to each signal port in the top-level die in the gate-level netlist, the interface logic corresponding to each signal port is placed in the preset range of each signal port, and then the cells in the interface logic are automatically placed by using an EDA tool, so as to complete the layout of the top-level die, and obtain the layout design of the top-level die.
The interface logic corresponding to the signal port comprises: all standard cells and registers between the input port to the data port of the sequential cell, or from the output port of the sequential cell to the output port. Standard cells may include, for example: logic gate unit, driving unit, time sequence unit, operation unit, and mixed logic unit.
In some embodiments, the EDA tool, when laying out the top die, needs to layout the top die according to the shape size of the bottom die, the placement location of macro cells (macro blocks), forbidden layout areas, row and wire track definitions, and SDC files of the three-dimensional integrated circuit specified in the layout of the top die.
After the layout design of the top-layer crystal grain is obtained, taking the SOC top layer where the bottom-layer crystal grain and the top-layer crystal grain are located as a static time sequence analysis object, obtaining a port time sequence report between the bottom-layer crystal grain and the top-layer crystal grain, wherein the port time sequence report comprises the following steps: the time sequence content of the port with the connection relation between the bottom layer crystal grain and the top layer crystal grain; analyzing the reason of the violations of the path (path) of the port with the timing violations related in the interface timing comprises, and adjusting the port of the bottom-layer crystal grain or the top-layer crystal grain and the corresponding interface logic according to the analysis result to complete the collaborative layout of the bottom-layer crystal grain and the top-layer crystal grain.
The analysis result is used for indicating that the number of buffers contained between two registers between ports of the bottom die and the top die is larger than a preset number.
According to the three-dimensional integrated circuit layout method provided by the embodiment, after the positions of all ports on the bottom layer crystal grains are adjusted based on the power ground network of the bottom layer crystal grains, the positions of all ports in the top layer crystal grains are adjusted according to the port mapping relation of the bottom layer crystal grains and the top layer crystal grains, the top layer crystal grains are laid out according to the positions of all ports in the top layer crystal grains after adjustment, so that the layout design of the top layer crystal grains is obtained, static time sequence analysis and adjustment are carried out on the layout design of the bottom layer crystal grains and the layout design of the top layer crystal grains based on the layout design of the bottom layer crystal grains, the collaborative layout of stacked crystal grains in the three-dimensional integrated circuit is realized, and the time sequence convergence of the stacked crystal grains is ensured.
In a possible implementation manner, please refer to fig. 2, which is a second flowchart of the three-dimensional integrated circuit layout method provided in the embodiment of the present application, as shown in fig. 2, the process of S101 obtaining the layout design of the bottom die in the three-dimensional integrated circuit may include:
s201: and obtaining the layout of the bottom layer crystal grain.
S202: and laying out the bottom layer crystal grains according to the layout of the bottom layer crystal grains and the interface delay constraint of the bottom layer crystal grains to obtain the layout design of the bottom layer crystal grains.
In this embodiment, the floor plan of the underlying die is obtained during the floor plan (Floorplan) phase of the chip design, which specifies: the shape size of the underlying die, placement of macro cells (macro blocks), forbidden layout areas, row heights, and routing track definitions.
The interface delay constraint of the bottom layer crystal grain comprises: the independent delay constraint of each port on the bottom layer crystal grain and the associated delay constraint between each port on the bottom layer crystal grain and each port on the top layer crystal grain can be used for carrying out time sequence analysis according to the paths related to each port in the gate level netlist to determine the interface delay constraint of the bottom layer crystal grain.
And reading the files corresponding to the floor planning and the interface delay constraint of the bottom layer crystal grain into an EDA tool, and carrying out global layout and detailed layout on the bottom layer crystal grain by the EDA tool according to the specified information in the floor planning and the delay constraint conditions required by the interface delay constraint, namely finishing the placement of the standard unit in a specified area.
In some embodiments, when the EDA tool is used for laying out the bottom layer crystal grains, all interface signals need to be defined as an ideal network, the ideal network ensures that input signals and output signals of the signal network are all ideal jump signals and signals with infinite driving capability, a buffer is not needed to be inserted into the signal network, and the signal network is processed according to zero delay when being subjected to time sequence analysis.
It should be noted that, since the three-dimensional integrated circuit is composed of stacked dies, and the EDA tool can perform layout optimization for only one die at a time, when performing layout optimization on the three-dimensional integrated circuit, the underlying die needs to be defined as a top layer of a system-on-a-chip (SOC), and hierarchical layout optimization is performed for the underlying die alone.
According to the three-dimensional integrated circuit layout method provided by the embodiment, the bottom layer crystal grains are laid out according to the layout planning of the bottom layer crystal grains and the interface delay constraint, so that the layout design of the bottom layer crystal grains can meet the layout planning requirement and the basic time sequence constraint, the bottom layer crystal grains and the top layer crystal grains can be better subjected to collaborative layout, and the collaborative layout efficiency of the three-dimensional integrated circuit is improved.
In a possible implementation manner, please refer to fig. 3, which is a flowchart of a three-dimensional integrated circuit layout method provided in an embodiment of the present application, as shown in fig. 3, before the step S202 of laying out the bottom die according to the layout of the bottom die and the interface delay constraint of the bottom die to obtain the layout design of the bottom die, the method may further include:
s301: obtaining a path list of each port in the bottom layer crystal grain, wherein the path list comprises: a plurality of transmission paths.
In this embodiment, by analyzing the gate netlist, a plurality of transmission paths for each port on the underlying die are determined from the gate netlist, where the transmission paths are data transmission paths where signals start from the input port, pass through the start register, the standard cell, and the end register to the output port.
In the three-dimensional integrated circuit design, the transmission path is divided into two parts, one part is positioned on the bottom layer crystal grain, the other part is positioned on the bottom layer crystal grain, specifically, one part taking the input port as a starting point is positioned on the bottom layer crystal grain, and the other part taking the output port as an ending point is positioned on the top layer crystal grain; alternatively, a portion starting at the input port may be located on the underlying die, and another portion ending at the output port may be located on the underlying die.
S302: the complete delay of the multiple transmission paths between the bottom die and the top die is calculated.
In this embodiment, the complete delay is the delay of the signal from the input port to the output port, and the complete delay total_del of each transmission path is determined by calculating the actual time and standard time of the signal from the input port to the output port.
S303: external delays of the multiple transmission paths on the top die are calculated.
In this embodiment, the external delay is a time delay of a partial path of the top die on the transmission path, and the external delay ext_del of each transmission path is determined by calculating a difference between an actual time and a standard time of a signal from a start point of the partial path of the top die to an output port, or from an input port to an end point of the partial path of the top die.
For example, please refer to fig. 4, which is a schematic diagram of a transmission path provided in the embodiment of the present application, as shown in fig. 4, the signal transmission delay from the input port to the output port is a complete delay total_del of the transmission path, the delay of a part of the transmission paths on the top layer die is an external delay ext_del, and the delay of a part of the transmission paths on the bottom layer die is an internal delay int_del.
In some embodiments, if the input port is located on the bottom die, the external delay ext_del of the transmission path may be obtained by calculating a difference between the internal delay int_del and the complete delay total_del from the input port to the end point of the transmission path on the bottom die; if the input port is located on the top die, the external delay ext_del from the input port to the endpoint of the transmission path on the top die can be calculated directly.
S304: and calculating the constraint absolute delay value of each port according to the complete delay and the external delay to obtain the interface delay constraint of the bottom layer crystal grain.
In this embodiment, according to the complete delay total_del and the external delay ext_del of each transmission path, an external delay ratio path_ratio of each transmission path is calculated, and specifically, the external delay ratio path_ratio is a ratio of the external delay ext_del to the complete delay total_del.
Since each port may have multiple transmission paths, the maximum external delay ratio path_ratio may be determined as the interface delay constraint ratio of each port according to the external delay ratio path_ratio of the multiple transmission paths corresponding to each port, and the constraint absolute delay value of each port may be obtained according to the clock period corresponding to the register connected to each port and the interface delay constraint ratio of each port. The constraint absolute delay value of each port can be obtained according to the product of the interface delay constraint proportion of each port and the clock period, and the interface delay constraint of the bottom crystal grain comprises: constrained absolute delay values for each port on the underlying die.
According to the three-dimensional integrated circuit layout method provided by the embodiment, the constraint absolute delay value of each port is calculated according to the complete delay and the external delay of the transmission paths corresponding to each port, so that the interface delay constraint of the bottom crystal grain is obtained, the layout design is carried out on the bottom crystal grain based on the interface delay constraint of the bottom crystal grain, the bottom crystal grain is ensured to meet the time sequence requirement, and therefore the time sequence synchronous optimization of the bottom crystal grain and the top crystal grain is better ensured.
In a possible implementation manner, please refer to fig. 5, which is a flow chart of a three-dimensional integrated circuit design method provided in an embodiment of the present application, as shown in fig. 5, the step S102 of adjusting the positions of the ports in the layout design of the bottom die according to the power ground network of the bottom die may include:
s401: and determining a first power grid which is in a preset range with the physical units connected with each port according to the positions of the physical units connected with each port on the bottom layer crystal grain in the layout design of the bottom layer crystal grain.
S402: each port is placed in a corresponding first location area based on a first location area of the first power grid on the underlying die.
In this embodiment, the physical unit connected to each port refers to a first-level physical unit connected to each port, that is, a physical unit connected adjacent to each port, and the position of the physical unit connected to each port on the underlying die is represented by the position coordinates of the physical unit on the underlying die.
According to the position coordinates of the physical units connected with each port on the bottom layer crystal grain and the central position coordinates of the power grids on the bottom layer crystal grain, the distance between the physical units connected with each port and the power grids is calculated, and according to the distance between the physical units connected with each port and the power grids, the power grid with the distance between the physical units connected with each port and the power grids within a preset range is determined to be used as the first power grid.
In some embodiments, the power grid closest to the physical unit to which each port is connected may be determined as the first power grid.
In other embodiments, a plurality of power grids having a distance within a preset range from the physical unit to which each port is connected may be determined as candidate power grids, and one power grid may be randomly selected from the candidate power grids as the first power grid.
The first position area is an area with a certain area formed by the power line and the ground line of the first power grid on the bottom layer crystal grain, and the port corresponding to the first power grid determined through the above is placed in the first position area according to the position of the first position area on the bottom layer crystal grain.
By adopting the mode, each port on the bottom layer crystal grain is placed, so that the reasonable placement of all port positions on the bottom layer crystal grain is ensured.
In a possible implementation manner, please refer to fig. 6, which is a flowchart of a three-dimensional integrated circuit design method provided in this embodiment of the present application, as shown in fig. 6, the step S401 of determining, according to a position on an underlying die of a physical unit connected to each port in a layout design of the underlying die, a first power grid within a preset range with respect to the physical unit connected to each port may include:
s501: if the number of the physical units connected with each port is one, determining the position coordinates of the physical units connected with each port on the underlying crystal grain.
S502: and determining a first power grid which is within a preset range with the position coordinates.
In this embodiment, if there is only one first-stage physical unit connected to each port, the distance between the physical unit and each power grid may be calculated according to the position coordinates x_loc and y_loc of the physical unit on the bottom layer die and the central position coordinates of each power grid on the bottom layer die, and the power grid whose distance from the physical unit is within the preset range may be determined as the first power grid according to the distance between the physical unit and each power grid.
In another possible implementation manner, please refer to fig. 7, which is a flowchart of a three-dimensional integrated circuit design method provided in this embodiment, as shown in fig. 7, the step S401 of determining, according to a position of a physical unit connected to each port in a layout design of an underlying die on the underlying die, a first power grid within a preset range with respect to the physical unit connected to each port may include:
s601: if the number of the physical units connected with each port is multiple, calculating an average position coordinate according to the position coordinates of the multiple physical units connected with each port on the bottom layer crystal grain.
S602: and determining a first power grid which is within a preset range with the average position coordinate.
In this embodiment, if the number of first-stage physical units connected to each port is multiple, the average position coordinates x '_loc and y' _loc may be calculated according to the position coordinates x_loc and y_loc of the multiple physical units on the bottom layer die, the distance between the average position coordinate point and each power grid may be calculated according to the average position coordinates and the central position coordinates of each power grid on the bottom layer die, and the power grid whose distance from the average position coordinate point is within the preset range may be determined as the first power grid according to the distance between the average position coordinate point and each power grid.
According to the three-dimensional integrated circuit design method provided by the embodiment, the first power grid of the physical unit in the preset range is determined according to the position of the physical unit connected with the port on the bottom layer crystal grain, so that the port is placed in the first position area of the first power grid on the bottom layer crystal grain, and the reasonable placement of the port position on the bottom layer crystal grain is ensured.
In a possible implementation manner, referring to fig. 8, as shown in fig. 8, for a seventh flowchart of a three-dimensional integrated circuit design method provided in an embodiment of the present application, the step S402 of placing each port in a corresponding first location area according to a first location area of a first power grid on an underlying die may include:
s701: and judging whether the first position area meets the placement requirements of all ports corresponding to the first power grid according to the area of the first position area.
In this embodiment, since the area of the first location area corresponding to the first power grid is limited, and the number of ports that can be placed in the first location area is limited, it is necessary to determine whether all the ports corresponding to the first power grid can be placed in the first location area.
Specifically, according to the area of the first position area and the area occupied by each port, judging whether the total area of each port corresponding to the first power grid is smaller than or equal to the area of the first position area, if the total area of each port of the first power grid is smaller than or equal to the area of the first position area, determining that the first position area meets the placement requirements of all ports corresponding to the first power grid; if the total area of each port of the first power grid is larger than the area of the first position area, determining that the first position area does not meet the placement requirements of all ports corresponding to the first power grid.
And if the first position area meets the placing requirements of all the ports corresponding to the first power grid, placing all the ports corresponding to the first power grid in the first position area.
S702: if the first position area does not meet the placement requirements of all the ports corresponding to the first power grid, determining a second power grid of the physical units connected with the remaining ports within a preset range.
In this embodiment, if the first location area does not meet the placement requirements of all the ports corresponding to the first power grid, a portion of the ports corresponding to the first power grid that matches the area of the first location area is placed in the first location area, and for the remaining ports corresponding to the first power grid, the second power grid is redetermined for the remaining ports in the manner of S401-S402 as described above.
In some embodiments, a candidate power grid for each port may be determined according to S401-S402 described above, and other power grids than the first power grid may be selected as the second power grid from the candidate power grids for each port.
In other embodiments, other power grids than the first power grid, which are within a preset range from the physical unit connected to the remaining ports, are determined as the second power grid according to the distance between the physical unit connected to the remaining ports and each power grid.
S703: the remaining ports are placed in a second location area on the underlying die according to a second location area of the second power grid.
In this embodiment, the second location area is an area with a certain area formed by the power line and the ground line of the second power grid on the bottom layer die, and according to the location of the second location area on the bottom layer die, the remaining ports corresponding to the determined second power grid are placed in the second location area.
In a possible implementation manner, please refer to fig. 9, which is a flowchart eight of the three-dimensional integrated circuit design method provided in the embodiment of the present application, as shown in fig. 9, before determining, in S702, that the physical units connected to the remaining ports are in the second power grid within the preset range if the first location area does not meet the placement requirements of all the ports corresponding to the first power grid, the method may further include:
S801: and sequencing the external delays of all the ports corresponding to the first power grid according to the external delays of all the ports corresponding to the first power grid.
S802: the number of ports that can be placed in the first location area is determined based on the area of the first location area.
S803: and determining the remaining ports with minimum external delay according to the number of the placeable ports and the sequencing of the external delays of all the ports.
In this embodiment, in order to ensure that the placement positions of the ports are optimal, the placement positions of the ports may be determined according to the time delay condition of each port, and if the first location area does not meet the placement requirements of all the ports corresponding to the first power grid, all the ports corresponding to the first power grid need to be ordered, specifically, the external delays of all the ports corresponding to the first power grid are ordered according to the external delays of all the ports corresponding to the first power grid, for example, the external delays of all the ports corresponding to the first power grid may be ordered in order from large to small or from small to large.
And for all the ports after sequencing, determining the number of the ports which can be placed in the first position area according to the area of the first position area and the area of the ports, placing the ports with the corresponding number of the ports with the largest delay sequencing in the first position area according to the number of the ports which can be placed and the ports after sequencing according to external delay, and determining the smallest remaining ports in the delay sequencing except the number of the ports which can be placed.
According to the three-dimensional integrated circuit design method provided by the embodiment, the corresponding number of ports are placed in the first position area according to the area of the first position area, the second power grid is redetermined for the remaining ports, and the remaining ports are placed in the second position area corresponding to the second power grid, so that all the ports can be placed in the optimal area, and the optimal time sequence of the bottom layer crystal grains is ensured.
On the basis of the method embodiment, the embodiment of the application also provides a three-dimensional integrated circuit layout device. Referring to fig. 10, a schematic structural diagram of a three-dimensional integrated circuit layout device according to an embodiment of the present application is shown in fig. 10, where the device may include:
a bottom die layout design obtaining module 101, configured to obtain a layout design of a bottom die in the three-dimensional integrated circuit, where a top die is stacked on the bottom die;
the bottom layer grain port position adjusting module 102 is used for adjusting the positions of all ports in the layout design of the bottom layer grain according to the power ground network of the bottom layer grain;
the top-level die port position adjustment module 103 is configured to adjust the positions of the ports in the top-level die according to the positions of the ports in the layout design of the bottom-level die and the port mapping relationship between the bottom-level die and the top-level die;
The top-level die layout design module 104 is configured to layout the top-level die according to the positions of the ports in the top-level die, so as to obtain a layout design of the top-level die.
Optionally, the bottom die layout design obtaining module 101 is specifically configured to obtain a layout of the bottom die; and laying out the bottom layer crystal grains according to the layout of the bottom layer crystal grains and the interface delay constraint of the bottom layer crystal grains to obtain the layout design of the bottom layer crystal grains.
Optionally, before the obtaining module 101 is designed by the underlying die layout, the apparatus may further include:
the path list obtaining module is configured to obtain a path list of each port in the bottom layer die, where the path list includes: a plurality of transmission paths;
the complete delay calculation module is used for calculating the complete delay of the transmission paths between the bottom layer crystal grain and the top layer crystal grain;
the external delay calculating module is used for calculating external delays of the transmission paths on the top-layer crystal grains;
and the absolute constraint calculation module is used for calculating the constraint absolute delay value of each port according to the complete delay and the external delay to obtain the interface delay constraint of the bottom crystal grain.
Optionally, the bottom die port position adjustment module 102 includes:
The first power supply network determining unit is used for determining a first power supply grid which is in a preset range with the physical units connected with each port according to the positions of the physical units connected with each port on the bottom layer crystal grain in the layout design of the bottom layer crystal grain;
and the first port placement unit is used for placing each port in the corresponding first position area according to the first position area of the first power grid on the bottom layer die.
Optionally, the first power network determining unit is specifically configured to determine a position coordinate of a physical unit connected to each port on the underlying die if the number of physical units connected to each port is one; and determining a first power grid which is within a preset range with the position coordinates.
Optionally, the first power network determining unit is further configured to calculate an average position coordinate according to position coordinates of the plurality of physical units connected to each port on the underlying die if the number of physical units connected to each port is multiple; and determining a first power grid which is within a preset range with the average position coordinate.
Optionally, the first port placement unit includes:
the placement requirement judging unit is used for judging whether the first position area meets the placement requirements of all ports corresponding to the first power grid according to the area of the first position area;
The second power supply network determining unit is used for determining a second power supply grid which is in a preset range with the physical units connected with the remaining ports if the first position area does not meet the placement requirements of all the ports corresponding to the first power supply grid;
and the remaining port placing unit is used for placing the remaining ports in the second position area according to the second position area of the second power grid on the bottom layer die.
Optionally, before the second power network determining unit, the apparatus may further include:
the delay sequencing unit is used for sequencing the external delays of all the ports corresponding to the first power grid according to the external delays of all the ports corresponding to the first power grid;
the port number determining unit is used for determining the number of the ports which can be placed in the first position area according to the area of the first position area;
and the residual port determining unit is used for determining the residual port with the minimum external delay according to the number of the placeable ports and the ordering of the external delays of all the ports.
The foregoing apparatus is used for executing the method provided in the foregoing embodiment, and its implementation principle and technical effects are similar, and are not described herein again.
The above modules may be one or more integrated circuits configured to implement the above methods, for example: one or more application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASICs), or one or more microprocessors, or one or more field programmable gate arrays (Field Programmable Gate Array, abbreviated as FPGAs), etc. For another example, when a module above is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processor that may invoke the program code. For another example, the modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
Referring to fig. 11, which is a schematic diagram of an electronic device provided in an embodiment of the present application, as shown in fig. 11, the electronic device 200 may include: processor 201, storage medium 202, and bus, storage medium 202 stores program instructions executable by processor 201, and when electronic device 200 is operated, processor 201 and storage medium 202 communicate via the bus, and processor 201 executes the program instructions to perform the above-described method embodiments. The specific implementation manner and the technical effect are similar, and are not repeated here.
Optionally, the present invention further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor performs the above-mentioned method embodiments.
In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.
The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (english: processor) to perform some of the steps of the methods according to the embodiments of the invention. And the aforementioned storage medium includes: u disk, mobile hard disk, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk, etc.
The foregoing is merely illustrative of embodiments of the present invention, and the present invention is not limited thereto, and any changes or substitutions can be easily made by those skilled in the art within the technical scope of the present invention, and the present invention is intended to be covered by the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (11)
1. A method of three-dimensional integrated circuit layout, the method comprising:
obtaining layout design of bottom crystal grains in a three-dimensional integrated circuit, wherein top crystal grains are stacked on the bottom crystal grains;
according to the power ground network of the bottom layer crystal grain, the positions of all ports in the layout design of the bottom layer crystal grain are adjusted;
according to the positions of all ports in the layout design of the bottom layer crystal grain and the port mapping relation between the bottom layer crystal grain and the top layer crystal grain, the positions of all ports in the top layer crystal grain are adjusted;
and according to the positions of all the ports in the top layer crystal grain, carrying out layout on the top layer crystal grain to obtain the layout design of the top layer crystal grain.
2. The method of claim 1, wherein the obtaining a layout design of an underlying die in the three-dimensional integrated circuit comprises:
Obtaining a floor plan of the bottom layer crystal grain;
and laying out the bottom layer crystal grains according to the layout of the bottom layer crystal grains and the interface delay constraint of the bottom layer crystal grains to obtain the layout design of the bottom layer crystal grains.
3. The method of claim 2, wherein the laying out the underlying die based on a floor plan of the underlying die and interface delay constraints of the underlying die, the method further comprising, prior to obtaining the layout design of the underlying die:
obtaining a path list of each port in the bottom layer crystal grain, wherein the path list comprises: a plurality of transmission paths;
calculating the complete delay of the transmission paths between the bottom layer crystal grain and the top layer crystal grain;
calculating external delays of the plurality of transmission paths on the top-layer die;
and calculating the constraint absolute delay value of each port according to the complete delay and the external delay to obtain the interface delay constraint of the bottom layer crystal grain.
4. The method of claim 1, wherein adjusting the locations of the ports in the layout design of the underlying die based on the power-ground network of the underlying die comprises:
Determining a first power grid which is within a preset range with the physical units connected with each port according to the positions of the physical units connected with each port on the bottom layer crystal grain in the layout design of the bottom layer crystal grain;
and placing each port in the corresponding first position area according to the first position area of the first power grid on the bottom layer crystal grain.
5. The method of claim 4, wherein determining a first power grid within a predetermined range with each port-connected physical unit based on the location on the underlying die of each port-connected physical unit in the layout design of the underlying die, comprises:
if the number of the physical units connected with each port is one, determining the position coordinates of the physical units connected with each port on the bottom layer crystal grain;
and determining a first power grid which is within a preset range with the position coordinate.
6. The method of claim 4, wherein determining a first power grid within a predetermined range with each port-connected physical unit based on the location on the underlying die of each port-connected physical unit in the layout design of the underlying die, comprises:
If the number of the physical units connected with each port is a plurality of, calculating an average position coordinate according to the position coordinates of the physical units connected with each port on the bottom layer crystal grain;
and determining a first power grid which is within a preset range with the average position coordinate.
7. The method of claim 4, wherein the placing each port in the corresponding first location area according to the first location area of the first power grid on the underlying die comprises:
judging whether the first position area meets the placement requirements of all ports corresponding to the first power grid or not according to the area of the first position area;
if the first position area does not meet the placement requirements of all ports corresponding to the first power grid, determining a second power grid of a physical unit connected with the remaining ports within a preset range;
and placing the remaining ports in a second position area on the bottom layer crystal grain according to the second position area of the second power grid.
8. The method of claim 7, wherein if the first location area does not meet the placement requirements of all ports corresponding to the first power grid, before determining a second power grid that is within a preset range with respect to physical units connected to remaining ports, the method further comprises:
Sequencing the external delays of all ports corresponding to the first power grid according to the external delays of all ports corresponding to the first power grid;
determining the number of the ports which can be placed in the first position area according to the area of the first position area;
and determining the remaining ports with the minimum external delay according to the number of the placeable ports and the sequencing of the external delays of all the ports.
9. A three-dimensional integrated circuit layout apparatus, the apparatus comprising:
a bottom layer grain layout design obtaining module, configured to obtain a layout design of a bottom layer grain in a three-dimensional integrated circuit, where a top layer grain is stacked on the bottom layer grain;
the bottom layer crystal grain port position adjusting module is used for adjusting the positions of all ports in the layout design of the bottom layer crystal grain according to the power ground network of the bottom layer crystal grain;
the top layer crystal grain port position adjusting module is used for adjusting the positions of all ports in the top layer crystal grain according to the positions of all ports in the layout design of the bottom layer crystal grain and the port mapping relation between the bottom layer crystal grain and the top layer crystal grain;
and the top-layer crystal grain layout design module is used for carrying out layout on the top-layer crystal grains according to the positions of all ports in the top-layer crystal grains to obtain the layout design of the top-layer crystal grains.
10. An electronic device, comprising: a processor, a storage medium and a bus, the storage medium storing program instructions executable by the processor, the processor and the storage medium communicating over the bus when the electronic device is running, the processor executing the program instructions to perform the steps of the three-dimensional integrated circuit layout method of any one of claims 1 to 8.
11. A computer-readable storage medium, characterized in that the storage medium has stored thereon a computer program which, when executed by a processor, performs the steps of the three-dimensional integrated circuit layout method according to any of claims 1 to 8.
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