CN117637740A - Method and device for determining through silicon vias in chip, electronic equipment and storage medium - Google Patents

Method and device for determining through silicon vias in chip, electronic equipment and storage medium Download PDF

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Publication number
CN117637740A
CN117637740A CN202311601451.6A CN202311601451A CN117637740A CN 117637740 A CN117637740 A CN 117637740A CN 202311601451 A CN202311601451 A CN 202311601451A CN 117637740 A CN117637740 A CN 117637740A
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cross
chip
layer
target
determining
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窦强
栾晓琨
马卓
王立明
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Feiteng Technology Changsha Co ltd
Phytium Technology Co Ltd
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Feiteng Technology Changsha Co ltd
Phytium Technology Co Ltd
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Priority to CN202311601451.6A priority Critical patent/CN117637740A/en
Publication of CN117637740A publication Critical patent/CN117637740A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention provides a method and a device for determining a through silicon via in a chip, electronic equipment and a storage medium, and relates to the technical field of chip design. The method for determining the through silicon vias in the chip comprises the following steps: determining a plurality of grid points in a preset coordinate system of a target layer according to the preset distance; performing power consumption analysis according to the power consumption information of the target chip, and determining the positions of a plurality of initial cross-chip-layer through silicon vias in a preset coordinate system; determining target grid points corresponding to the positions of the initial cross-chip layer through silicon vias in a preset coordinate system according to the positions of the initial cross-chip layer through silicon vias; determining a target cross-chip layer through silicon via according to the target grid points, wherein the target cross-chip layer through silicon via comprises: a first cross-chip layer through silicon via for connecting to a power terminal of an external power source. And a power consumption analysis mode is adopted, a reasonable target grid point is obtained based on a preset coordinate system, and the first cross-chip layer through silicon vias determined according to the target grid point are more reasonable and accurate.

Description

Method and device for determining through silicon vias in chip, electronic equipment and storage medium
Technical Field
The present invention relates to the field of chip design technologies, and in particular, to a method and apparatus for determining through silicon vias in a chip, an electronic device, and a storage medium.
Background
As the characteristic dimensions of transistors reach the nanometer level, the power consumption and delay issues of interconnects between transistors are gradually becoming a big factor limiting chip performance. The common 2D (two-dimensional) integrated circuit has overlong wiring, so that the operation speed of the chip is reduced, and the power consumption is increased. The 3D (three-dimensional) integrated circuit can effectively reduce the wiring length, improve the operation speed and reduce the power consumption. Interconnections between different layers of the 3D integrated circuit are through TSVs (through-chip-layer silicon vias).
In the related art, the dense TSV distribution affects the logic unit distribution, wiring resources and processes; the sparse TSV distribution affects the power supply of the upper and lower chips.
How to reasonably arrange the cross-chip layer silicon through holes becomes the problem to be solved.
Disclosure of Invention
The present invention aims to solve the above-mentioned problems of the prior art, and provides a method, a device, an electronic device and a storage medium for determining through silicon vias in a chip.
In order to achieve the above purpose, the technical scheme adopted by the embodiment of the invention is as follows:
in a first aspect, an embodiment of the present invention provides a method for determining a through silicon via in a chip, including:
Determining a plurality of grid points in a preset coordinate system of a target layer according to the preset distance;
performing power consumption analysis according to the power consumption information of the target chip, and determining the positions of a plurality of initial cross-chip-layer through silicon vias in a preset coordinate system;
determining target grid points corresponding to the positions of the initial cross-chip layer through silicon vias in the preset coordinate system according to the positions of the initial cross-chip layer through silicon vias;
determining a target cross-chip layer through silicon via according to the target grid points, wherein the target cross-chip layer through silicon via comprises: a first cross-chip layer through silicon via for connecting to a power terminal of an external power source.
Optionally, after the determining the target cross-chip layer through silicon vias according to the target grid points, the method further includes:
projecting a first logic unit in a connection relation layer of the target layer to the target layer, wherein the target layer further comprises: a second logic unit;
determining a connecting line between the projected first logic unit and the second logic unit with a connecting relationship in the target layer;
determining a first grid point nearest to the connecting line from a plurality of grid points of the target layer as a second cross-chip layer through silicon via for a connecting unit, wherein the target cross-chip layer through silicon via comprises: the second cross-chip layer through silicon via.
Optionally, the method further comprises:
if the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias are coincident, re-determining a second grid point from a plurality of grid points of the target layer according to the connecting line;
and taking the second grid points as the second cross-chip layer silicon through holes.
Optionally, the method further comprises:
performing thermal simulation according to preset chip thickness, logic unit distribution, position information and radius information of the target cross-chip layer through silicon vias, and obtaining simulation temperatures of grid points in the preset coordinate system;
determining a third grid point from the grid points according to the simulated temperature of each grid point and a preset temperature threshold value;
and determining a third cross-chip layer through silicon via for heat dissipation according to the third grid point, wherein the target cross-chip layer through silicon via comprises: and a third cross-chip layer through silicon via.
Optionally, after the third through-chip-layer silicon vias for heat dissipation are determined according to the third grid points, the method further includes:
judging whether the third cross-chip layer through silicon vias are overlapped with the second cross-chip layer through silicon vias in the target layer or not;
If yes, re-determining a fourth grid point from the grid points of the target layer, and taking the fourth grid point as the second cross-chip layer through silicon via;
and according to the preset chip thickness, the logic unit distribution, the position information and the radius information of the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias, performing thermal simulation again, and determining a fifth grid point as the third cross-chip layer through silicon vias again until a first thermal simulation result meets a first preset condition to obtain a final target cross-chip layer through silicon via.
Optionally, after the thermal simulation is performed again according to the preset chip thickness, the logic unit distribution, the position information and the radius information of the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias, and the fifth grid point is redetermined as the third cross-chip layer through silicon vias until the first thermal simulation result meets the first preset condition, and the final target cross-chip layer through silicon vias are obtained, the method further includes:
performing time sequence evaluation according to the target cross-chip layer through silicon vias to obtain a first time sequence evaluation result;
If the first time sequence evaluation result does not meet a second preset condition, a sixth grid point is redetermined from the grid points of the target layer, and the sixth grid point is used as the second cross-chip layer through silicon via;
and according to the preset chip thickness, the logic unit distribution, the position information and the radius information of the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias, performing thermal simulation again, and determining a seventh grid point as the third cross-chip layer through silicon vias again until a second thermal simulation result meets the first preset condition and a second time sequence evaluation result meets the second preset condition to obtain a final target cross-chip layer through silicon via.
Optionally, before the projecting the first logic unit in the connection relation layer of the target layer to the target layer, the method further includes:
performing thermal simulation according to preset logic unit density, and determining the number and positions of initial second cross-chip-layer through silicon vias;
the determining a first grid point closest to the connecting line from a plurality of grid points of the target layer includes:
and determining a first grid point nearest to the connecting line from a plurality of grid points of the target layer according to the number and the positions of the initial second cross-chip layer through silicon vias.
In a second aspect, an embodiment of the present invention further provides a through silicon via determining device in a chip, including:
the determining module is used for determining a plurality of grid points in a preset coordinate system of the target layer according to the preset distance; performing power consumption analysis according to the power consumption information of the target chip, and determining the positions of a plurality of initial cross-chip-layer through silicon vias in a preset coordinate system; determining target grid points corresponding to the positions of the initial cross-chip layer through silicon vias in the preset coordinate system according to the positions of the initial cross-chip layer through silicon vias; determining a target cross-chip layer through silicon via according to the target grid points, wherein the target cross-chip layer through silicon via comprises: a first cross-chip layer through silicon via for connecting to a power terminal of an external power source.
Optionally, the apparatus further includes:
the projection module is configured to project a first logic unit in a connection relation layer of the target layer to the target layer, where the target layer further includes: a second logic unit;
the first determining module is used for determining a connecting line between the projected first logic unit and the second logic unit with the connection relation in the target layer; determining a first grid point nearest to the connecting line from a plurality of grid points of the target layer as a second cross-chip layer through silicon via for a connecting unit, wherein the target cross-chip layer through silicon via comprises: the second cross-chip layer through silicon via.
Optionally, the apparatus further includes:
a second determining module, configured to, if the first cross-chip layer through silicon via and the second cross-chip layer through silicon via overlap, re-determine, according to the connection line, a second grid point from among the plurality of grid points of the target layer; and taking the second grid points as the second cross-chip layer silicon through holes.
Optionally, the apparatus further includes:
the simulation module is used for performing thermal simulation according to the preset chip thickness, logic unit distribution, the position information and the radius information of the target cross-chip layer through silicon vias, and obtaining the simulation temperature of each grid point in the preset coordinate system;
a third determining module, configured to determine a third grid point from the plurality of grid points according to the simulated temperatures of the grid points and a preset temperature threshold; and determining a third cross-chip layer through silicon via for heat dissipation according to the third grid point, wherein the target cross-chip layer through silicon via comprises: and a third cross-chip layer through silicon via.
Optionally, the apparatus further includes:
the judging module is used for judging whether the third cross-chip layer through silicon vias are overlapped with the second cross-chip layer through silicon vias in the target layer or not;
A fourth determining module, configured to, if yes, re-determine a fourth grid point from the plurality of grid points of the target layer, and use the fourth grid point as the second cross-chip layer through silicon via; and according to the preset chip thickness, the logic unit distribution, the position information and the radius information of the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias, performing thermal simulation again, and determining a fifth grid point as the third cross-chip layer through silicon vias again until a first thermal simulation result meets a first preset condition to obtain a final target cross-chip layer through silicon via.
Optionally, the apparatus further includes:
the evaluation module is used for carrying out time sequence evaluation according to the target cross-chip layer through silicon vias to obtain a first time sequence evaluation result; if the first time sequence evaluation result does not meet a second preset condition, a sixth grid point is redetermined from the grid points of the target layer, and the sixth grid point is used as the second cross-chip layer through silicon via; and according to the preset chip thickness, the logic unit distribution, the position information and the radius information of the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias, performing thermal simulation again, and determining a seventh grid point as the third cross-chip layer through silicon vias again until a second thermal simulation result meets the first preset condition and a second time sequence evaluation result meets the second preset condition to obtain a final target cross-chip layer through silicon via.
Optionally, the apparatus further includes:
a fifth determining module, configured to perform thermal simulation according to a preset logic unit density, and determine the number and positions of the initial second through-chip-layer silicon vias;
the first determining module is specifically configured to determine, according to the number and the positions of the initial second through-chip-layer silicon vias, a first grid point closest to the connection line from among the multiple grid points of the target layer.
In a third aspect, an embodiment of the present invention further provides an electronic device, including: a memory storing a computer program executable by the processor, and a processor implementing the method for determining through silicon vias in a chip according to any of the above first aspects when the processor executes the computer program.
In a fourth aspect, an embodiment of the present invention further provides a computer readable storage medium, where a computer program is stored, where the computer program is read and executed to implement the method for determining through silicon vias in a chip according to any of the first aspects.
The beneficial effects of the invention are as follows: the embodiment of the invention provides a method for determining a through silicon via in a chip, which comprises the following steps: determining a plurality of grid points in a preset coordinate system of a target layer according to the preset distance; performing power consumption analysis according to the power consumption information of the target chip, and determining the positions of a plurality of initial cross-chip-layer through silicon vias in a preset coordinate system; determining target grid points corresponding to the positions of the initial cross-chip layer through silicon vias in a preset coordinate system according to the positions of the initial cross-chip layer through silicon vias; determining a target cross-chip layer through silicon via according to the target grid points, wherein the target cross-chip layer through silicon via comprises: a first cross-chip layer through silicon via for connecting to a power terminal of an external power source. By adopting the power consumption analysis mode, the position of the initial cross-chip layer through silicon via can be accurately determined, the normalization processing is carried out on the basis of a plurality of grid points in a preset coordinate system, reasonable target grid points are obtained, the first cross-chip layer through silicon via is determined according to the target grid points, and the design of the first cross-chip layer through silicon via for connecting a power supply terminal of an external power supply can be more reasonable and accurate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for determining through silicon vias in a chip according to an embodiment of the present application;
fig. 2 is a schematic distribution diagram of a first cross-chip layer through silicon via in a preset coordinate system according to an embodiment of the present application;
fig. 3 is a second schematic flow chart of a method for determining through silicon vias in a chip according to an embodiment of the present application;
fig. 4 is a schematic distribution diagram of through-silicon vias of a cross-chip layer in a preset coordinate system according to an embodiment of the present application;
fig. 5 is a flowchart of a method for determining through silicon vias in a chip according to an embodiment of the present application;
fig. 6 is a flow chart diagram of a method for determining through silicon vias in a chip according to an embodiment of the present application;
fig. 7 is a schematic diagram of distribution of through-silicon vias in a preset coordinate system according to an embodiment of the present application;
Fig. 8 is a flowchart of a method for determining through silicon vias in a chip according to an embodiment of the present application;
fig. 9 is a flowchart of a method for determining through silicon vias in a chip according to an embodiment of the present application;
fig. 10 is a flow chart seventh of a method for determining through silicon vias in a chip according to an embodiment of the present application;
fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that, if the terms "upper", "lower", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or an azimuth or the positional relationship that is commonly put when the product of the application is used, it is merely for convenience of description and simplification of the description, and does not indicate or imply that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and therefore should not be construed as limiting the present application.
Furthermore, the terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that, without conflict, features in embodiments of the present application may be combined with each other.
The method for determining the through silicon vias in the chip is applied to electronic equipment, and the electronic equipment can be any one of the following: desktop computers, notebook computers, tablet computers, smartphones, etc. may be implemented by, but not limited to, chip design software integrated therein.
The following explains a method for determining through silicon vias in a chip provided in an embodiment of the present application.
Fig. 1 is a schematic flow chart of a method for determining through silicon vias in a chip according to an embodiment of the present application, as shown in fig. 1, the method may include:
s101, determining a plurality of grid points in a preset coordinate system of a target layer according to the preset distance.
The preset distance may indicate a minimum spacing between two adjacent cross-chip layer through silicon vias.
In some embodiments, the preset distance is determined according to the minimum process spacing requirements, noise limits of through-chip-layer silicon vias, and the like; and then, establishing a rectangular coordinate system along the horizontal axis direction and the vertical axis direction, and constructing a cell array by taking the preset distance as the length of the minimum cell to obtain a plurality of grid points in the preset coordinate system of the target layer.
In addition, the plurality of grid points may also be referred to as a dummy TSV (cross-chip layer through silicon via) array.
S102, performing power consumption analysis according to the power consumption information of the target chip, and determining the positions of a plurality of initial cross-chip-layer through silicon vias in a preset coordinate system.
According to different processes, power consumption analysis is performed according to power consumption information of a target chip, so that the minimum density meeting design requirements is obtained, wherein the minimum density refers to the minimum density of the positions of a plurality of initial cross-chip-layer through silicon vias.
It should be noted that the locations of the plurality of initial cross-chip layer through silicon vias may be locations called PG (Power Ground).
S103, determining target grid points corresponding to the positions of the initial cross-chip layer through silicon vias in a preset coordinate system according to the positions of the initial cross-chip layer through silicon vias;
in the embodiment of the present application, according to the position of each initial cross-chip layer through silicon via, a grid point closest to the position of each initial cross-chip layer through silicon via is determined in a plurality of grid points of a preset coordinate system, a closest grid point corresponding to the position of each initial cross-chip layer through silicon via is obtained, and the closest grid point corresponding to the position of each initial cross-chip layer through silicon via is used as a target grid point corresponding to the position of each initial cross-chip layer through silicon via.
It is worth to say that the positions of the initial cross-chip layer through silicon vias determined by adopting the power consumption analysis mode are more accurate, and the target grid points corresponding to the positions of the initial cross-chip layer through silicon vias are determined in the grid points of the preset coordinate system, so that the determined target grid points are more accurate and reasonable.
Fig. 2 is a schematic distribution diagram of a first cross-chip layer through silicon via in a preset coordinate system according to an embodiment of the present application, where as shown in fig. 2, the first cross-chip layer through silicon via includes: a. b, c, d, e, f, each first cross-chip layer through silicon via is distributed on a grid point.
S104, determining a target cross-chip layer through silicon via according to the target grid points.
The target cross-chip layer through silicon via comprises: a first cross-chip layer through silicon via for connecting to a power terminal of an external power source.
In some embodiments, the plurality of target grid points may be referred to as a plurality of first cross-chip layer through silicon vias for connecting to a VDD operating voltage terminal of an external power supply, and VSS generally refers to a common ground terminal.
In the embodiment of the application, the plurality of target grid points are used as the first cross-chip layer through silicon vias, so that the first cross-chip layer through silicon vias for connecting the power supply terminals of the external power supply can be determined reasonably and accurately.
In summary, an embodiment of the present invention provides a method for determining a through silicon via in a chip, including: determining a plurality of grid points in a preset coordinate system of a target layer according to the preset distance; performing power consumption analysis according to the power consumption information of the target chip, and determining the positions of a plurality of initial cross-chip-layer through silicon vias in a preset coordinate system; determining target grid points corresponding to the positions of the initial cross-chip layer through silicon vias in a preset coordinate system according to the positions of the initial cross-chip layer through silicon vias; determining a target cross-chip layer through silicon via according to the target grid points, wherein the target cross-chip layer through silicon via comprises: a first cross-chip layer through silicon via for connecting to a power terminal of an external power source. By adopting the power consumption analysis mode, the position of the initial cross-chip layer through silicon via can be accurately determined, and the normalized processing is carried out on the basis of a plurality of grid points in a preset coordinate system, so that reasonable target grid points are obtained, the first cross-chip layer through silicon via is determined according to the target grid points, the first cross-chip layer through silicon via for connecting a power supply terminal of an external power supply can be designed more reasonably and accurately, and the index states of a time sequence process and the like of the chip are better.
Fig. 3 is a second schematic flow chart of a method for determining through-silicon vias in a chip according to an embodiment of the present application, as shown in fig. 3, in a chip design, for a three-dimensional integrated circuit, for example, a 3D integrated circuit, the integrated circuit may include multiple layers, and optionally, after the process of determining a target through-chip layer through-silicon via according to a target grid point in S104, the method may further include:
s201, projecting a first logic unit in a connection relation layer of the target layer to the target layer.
Wherein, the target layer further comprises: and a second logic unit. The connection layer may be a layer having a connection relationship with the target layer in the multilayer integrated circuit, may be an adjacent layer, or may be any other layer than the target layer, and is referred to as a "first layer" in the following embodiments, and the target layer is referred to as a "second layer".
By way of example, the target layer may be a first layer in a multi-layer integrated circuit, the connection layer may be a second layer in a multi-layer integrated circuit, or the connection layer may be a third layer in a multi-layer integrated circuit.
In some embodiments, the coordinates of the first logic units in the first layer are extracted, and the coordinates of the plurality of first logic units are marked in a coordinate system corresponding to the second layer to realize projection, where the second layer includes: a plurality of second logic cells and a plurality of projected first logic cells.
S202, determining a connecting line between the projected first logic unit and the projected second logic unit with the connection relation in the target layer.
And performing linear connection between a projected first logic unit and a projected second logic unit with a connection relationship to obtain a connection line between the first logic unit and the second logic unit.
S203, determining a first grid point closest to the connecting line from a plurality of grid points of the target layer as a second cross-chip layer through silicon via for the connecting unit.
The target cross-chip layer through silicon via comprises: and a second cross-chip layer through silicon via. The projected first logic unit and the projected first logic unit are corresponding, and the projected first logic unit and the projected second logic unit with the connection relationship can also be regarded as the first logic unit and the second logic unit with the connection relationship, and the second logic unit in the second layer is connected with the first logic unit in the first layer through the second cross-chip layer through silicon vias.
In some embodiments, the distance between each vertex of the plurality of grid points and the connecting line may be calculated, and the grid point closest to the connecting line is selected as the first grid point. Alternatively, a part of the preset vertices of the area around the connection line may be determined from a plurality of preset vertices, and from the part of the preset vertices, the grid point closest to the part of the preset vertices is selected as the first grid point.
It should be noted that, determining the first grid point closest to the connecting line as the second cross-chip layer through silicon via can make the wiring path of the chip shortest, and realize reasonable design, so that the line delay can be reduced, and the timing sequence convergence and timing sequence repair of the integrated circuit are ensured.
In the embodiment of the application, there are multiple groups of logic units, each group of logic units includes a first logic unit and a second logic unit after projection with a connection relationship, and if a grid point closest to the first group of logic units is the same to-be-selected grid point as a grid point closest to the second group of logic units, a first alternative grid point of the first group of logic units and a second alternative grid point of the second group of logic units are respectively determined. The first candidate vertexes are vertexes which are the second closest to the first group of logic units, and the second candidate vertexes are vertexes which are the second closest to the second group of logic units.
Calculating the sum of distances from each logic unit in the first group of logic units to the grid points to be selected respectively to obtain a first sum value; calculating the sum of the distances from each logic unit in the second group of logic units to the grid points to be selected respectively to obtain a second sum value; calculating the sum of the distances from each logic unit in the first group of logic units to the first alternative grid points respectively to obtain a third sum value; and calculating the sum of the distances from each logic unit in the second group of logic units to the second alternative grid point respectively to obtain a fourth sum value. Calculating the sum of the first sum value and the fourth sum value to obtain a fifth sum value; calculating the sum of the second sum value and the third sum value to obtain a sixth sum value; if the fifth sum is larger than the sixth sum, taking the grid point to be selected as a target grid point corresponding to the second group of logic units, and taking the first alternative grid point as a target grid point corresponding to the first group of logic units; and if the fifth sum value is smaller than the sixth sum value, taking the grid point to be selected as the target grid point corresponding to the first group of logic units, and taking the second alternative grid point as the target grid point corresponding to the second group of logic units.
In summary, from the multiple grid points of the target layer, the first grid point closest to the connection line is determined and used as the second cross-chip layer through silicon via for the connection unit, so that the line delay of the chip can be effectively reduced, and the timing convergence of the chip is ensured.
Fig. 4 is a schematic distribution diagram of through-chip vias in a preset coordinate system according to an embodiment of the present application, where, as shown in fig. 4, the preset coordinate system may include: the first logic units, the second logic units, the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias after the plurality of projection.
Optionally, fig. 5 is a flowchart third of a method for determining a through silicon via in a chip according to an embodiment of the present application, as shown in fig. 5, where the method may further include:
s301, if the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias are overlapped, the second grid points are determined again from the grid points of the target layer according to the connecting lines.
S302, taking the second grid points as second cross-chip layer through silicon vias.
In some embodiments, if the first and second cross-chip layer through-silicon vias coincide, then according to the connection line, selecting a grid point second closest to the connection line from the multiple grids of the target layer as the second grid point, and using the grid point as the second cross-chip layer through-silicon via, so as to avoid that the first and second cross-chip layer through-silicon vias select the same grid point.
Optionally, fig. 6 is a flowchart of a method for determining a through silicon via in a chip according to an embodiment of the present application, as shown in fig. 6, where the method may further include:
s401, performing thermal simulation according to preset chip thickness, logic unit distribution, position information and radius information of a target cross-chip layer through silicon via, and obtaining simulation temperatures of grid points in a preset coordinate system.
The target cross-chip layer through silicon via may include: the first cross-chip layer through silicon via and the second cross-chip layer through silicon via. The logic cell distribution includes: distribution of the second logic cells and distribution of the projected first logic cells.
In some embodiments, thermal simulation is performed on the chip according to the preset chip thickness, the distribution of the second logic units, the distribution of the first logic units after projection, the position information and the radius information of the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias, so as to obtain the simulation temperature of each grid point in the preset coordinate system.
S402, determining a third grid point from the grid points according to the simulated temperature of each grid point and a preset temperature threshold value.
In the embodiment of the present application, it is determined whether the simulated temperature of each grid point is greater than or equal to the preset temperature threshold, and if so, the grid point is regarded as a third grid point.
S403, determining a third cross-chip layer through silicon via for heat dissipation according to the third grid point.
The target cross-chip layer through silicon via comprises: and a third cross-chip layer through silicon via.
In other words, in this embodiment, heat dissipation can be performed by inserting through-chip-layer through-silicon vias at the location where hot spots occur, so that the heat dissipation effect of the chip is better.
Fig. 7 is a schematic diagram of distribution of through-chip vias in a preset coordinate system according to an embodiment of the present application, where, as shown in fig. 7, the preset coordinate system may include: the first logic units, the second logic units, the first cross-chip layer through silicon vias, the second cross-chip layer through silicon vias and the third cross-chip layer through silicon vias after the projection.
Optionally, fig. 8 is a flowchart fifth of a method for determining a through silicon via in a chip according to an embodiment of the present application, as shown in fig. 8, after the process of determining a third cross-chip layer through silicon via for heat dissipation according to the third grid point in S403, the method may further include:
s501, judging whether the third cross-chip layer through silicon vias are overlapped with the second cross-chip layer through silicon vias in the target layer.
And S502, if yes, re-determining a fourth grid point from the grid points of the target layer, and taking the fourth grid point as a second cross-chip layer through silicon via.
In this embodiment of the present application, if the third cross-chip layer through silicon via and the second cross-chip layer through silicon via overlap, the fourth grid point needs to be determined again, and the fourth grid point is taken as the second cross-chip layer through silicon via, and the fourth grid point may be the grid point closest to the connecting line.
S503, according to preset chip thickness, logic unit distribution, position information and radius information of the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias, performing thermal simulation again, and determining a fifth grid point as a third cross-chip layer through silicon via again until a first thermal simulation result meets a first preset condition to obtain a final target cross-chip layer through silicon via.
And the first thermal simulation result is a simulation result obtained by performing thermal simulation after the fifth grid point is redetermined as the third cross-chip layer through silicon via. The logic cell distribution includes: distribution of the second logic cells and distribution of the projected first logic cells.
After the second cross-chip layer through silicon vias are changed, performing thermal simulation again according to preset chip thickness, logic unit distribution, position information and radius information of the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias, determining simulation temperatures of all grid points again, and determining a fifth grid point from the plurality of grid points according to the determined simulation temperatures of all grid points and a preset temperature threshold; and taking the fifth grid point as a third cross-chip layer through silicon via until the first thermal simulation result meets a first preset condition, and obtaining a final target cross-chip layer through silicon via.
In summary, the wiring is performed based on the third cross-chip layer through silicon vias, so that the heat dissipation of the chip can meet the first preset condition, that is, the designed chip can meet the heat dissipation requirement.
Optionally, fig. 9 is a flowchart of a method for determining a through silicon via in a chip according to an embodiment of the present application, as shown in fig. 9, after performing thermal simulation again according to preset chip thickness, logic unit distribution, position information and radius information of a first through silicon via and a second through silicon via, and determining a fifth grid point as a third through silicon via again, until a first thermal simulation result meets a first preset condition, and after obtaining a final target through silicon via, the method may further include:
s601, performing time sequence evaluation according to a target cross-chip layer through silicon via to obtain a first time sequence evaluation result;
the target cross-chip layer through silicon via comprises: the first, second and third cross-chip layer through silicon vias.
S602, if the first time sequence evaluation result does not meet the second preset condition, re-determining a sixth grid point from the grid points of the target layer, and taking the sixth grid point as a second cross-chip layer through silicon via.
S603, performing thermal simulation again according to the preset chip thickness, logic unit distribution, position information and radius information of the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias, and determining a seventh grid point as a third cross-chip layer through silicon via again until a second thermal simulation result meets a first preset condition, and a second time sequence evaluation result meets a second preset condition, so that a final target cross-chip layer through silicon via is obtained.
And the second thermal simulation result is a simulation result of performing thermal simulation after determining the seventh grid point as the third cross-chip layer through silicon via.
In the embodiment of the application, when the first time sequence evaluation result does not meet the second preset condition, the second cross-chip layer through silicon via is adjusted; and then, according to the preset chip thickness, logic unit distribution, position information and radius information of the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias, performing thermal simulation again, and adjusting the third cross-chip layer through silicon vias until the second thermal simulation result meets the first preset condition and the second time sequence evaluation result meets the second preset condition, so as to obtain the final target cross-chip layer through silicon vias.
In summary, the wiring is performed based on the reasonably set final target cross-chip layer through silicon vias, so that the requirements of heat dissipation and time sequence of the chip can be met simultaneously.
Optionally, fig. 10 is a flowchart of a method for determining a through silicon via in a chip according to an embodiment of the present application, as shown in fig. 10, before the process of projecting, in S201, a first logic unit in a connection relation layer of a target layer to the target layer, the method may further include:
s701, performing thermal simulation according to preset logic unit density, and determining the number and positions of initial second cross-chip-layer through silicon vias;
the determining a first grid point closest to the connection line from among the plurality of grid points of the target layer in S203 may include:
s702, determining a first grid point closest to the connecting line from a plurality of grid points of a target layer according to the number and the positions of the initial second cross-chip layer through silicon vias.
It should be noted that, for the heat dissipation cross-chip layer through silicon via layout, pre-layout before the second cross-chip layer through silicon via may also be performed. And performing thermal simulation with the preset logic unit density of fifty percent, so as to determine the number and the positions of the initial second cross-chip layer through silicon vias, then performing layout on the second cross-chip layer through silicon vias, and finally performing thermal simulation verification.
In summary, the embodiment of the present application provides a method for determining a through silicon via in a chip, including: the first cross-chip layer silicon through hole is determined according to the target grid points, so that the first cross-chip layer silicon through hole for connecting a power supply terminal of an external power supply can be designed more reasonably and accurately; from a plurality of grid points of the target layer, determining a first grid point closest to the connecting line as a second cross-chip layer silicon through hole for the connecting unit, so that the line delay of the chip can be effectively reduced, and the timing sequence convergence of the chip is ensured; the final target cross-chip layer through silicon vias based on reasonable arrangement are used for wiring, so that the heat dissipation of the chip can be simultaneously met, and the time sequence can meet the requirements.
The following describes a through-silicon via determining device, an electronic device, a storage medium, and the like in a chip for performing the through-silicon via determining method in the chip provided in the present application, and specific implementation processes and technical effects thereof refer to relevant contents of the through-silicon via determining method in the chip, which are not described in detail below.
The embodiment of the invention also provides a device for determining the through silicon vias in the chip, which comprises the following steps:
the determining module is used for determining a plurality of grid points in a preset coordinate system of the target layer according to the preset distance; performing power consumption analysis according to the power consumption information of the target chip, and determining the positions of a plurality of initial cross-chip-layer through silicon vias in a preset coordinate system; determining target grid points corresponding to the positions of the initial cross-chip layer through silicon vias in the preset coordinate system according to the positions of the initial cross-chip layer through silicon vias; determining a target cross-chip layer through silicon via according to the target grid points, wherein the target cross-chip layer through silicon via comprises: a first cross-chip layer through silicon via for connecting to a power terminal of an external power source.
Optionally, the apparatus further includes:
the projection module is configured to project a first logic unit in a connection relation layer of the target layer to the target layer, where the target layer further includes: a second logic unit;
the first determining module is used for determining a connecting line between the projected first logic unit and the second logic unit with the connection relation in the target layer; determining a first grid point nearest to the connecting line from a plurality of grid points of the target layer as a second cross-chip layer through silicon via for a connecting unit, wherein the target cross-chip layer through silicon via comprises: the second cross-chip layer through silicon via.
Optionally, the apparatus further includes:
a second determining module, configured to, if the first cross-chip layer through silicon via and the second cross-chip layer through silicon via overlap, re-determine, according to the connection line, a second grid point from among the plurality of grid points of the target layer; and taking the second grid points as the second cross-chip layer silicon through holes.
Optionally, the apparatus further includes:
the simulation module is used for performing thermal simulation according to the preset chip thickness, logic unit distribution, the position information and the radius information of the target cross-chip layer through silicon vias, and obtaining the simulation temperature of each grid point in the preset coordinate system;
A third determining module, configured to determine a third grid point from the plurality of grid points according to the simulated temperatures of the grid points and a preset temperature threshold; and determining a third cross-chip layer through silicon via for heat dissipation according to the third grid point, wherein the target cross-chip layer through silicon via comprises: and a third cross-chip layer through silicon via.
Optionally, the apparatus further includes:
the judging module is used for judging whether the third cross-chip layer through silicon vias are overlapped with the second cross-chip layer through silicon vias in the target layer or not;
a fourth determining module, configured to, if yes, re-determine a fourth grid point from the plurality of grid points of the target layer, and use the fourth grid point as the second cross-chip layer through silicon via; and according to the preset chip thickness, the logic unit distribution, the position information and the radius information of the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias, performing thermal simulation again, and determining a fifth grid point as the third cross-chip layer through silicon vias again until a first thermal simulation result meets a first preset condition to obtain a final target cross-chip layer through silicon via.
Optionally, the apparatus further includes:
The evaluation module is used for carrying out time sequence evaluation according to the target cross-chip layer through silicon vias to obtain a first time sequence evaluation result; if the first time sequence evaluation result does not meet a second preset condition, a sixth grid point is redetermined from the grid points of the target layer, and the sixth grid point is used as the second cross-chip layer through silicon via; and according to the preset chip thickness, the logic unit distribution, the position information and the radius information of the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias, performing thermal simulation again, and determining a seventh grid point as the third cross-chip layer through silicon vias again until a second thermal simulation result meets the first preset condition and a second time sequence evaluation result meets the second preset condition to obtain a final target cross-chip layer through silicon via.
Optionally, the apparatus further includes:
a fifth determining module, configured to perform thermal simulation according to a preset logic unit density, and determine the number and positions of the initial second through-chip-layer silicon vias;
the first determining module is specifically configured to determine, according to the number and the positions of the initial second through-chip-layer silicon vias, a first grid point closest to the connection line from among the multiple grid points of the target layer.
The foregoing apparatus is used for executing the method provided in the foregoing embodiment, and its implementation principle and technical effects are similar, and are not described herein again.
The above modules may be one or more integrated circuits configured to implement the above methods, for example: one or more application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), or one or more microprocessors (digital singnal processor, abbreviated as DSP), or one or more field programmable gate arrays (Field Programmable Gate Array, abbreviated as FPGA), or the like. For another example, when a module above is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processor that may invoke the program code. For another example, the modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
Fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present application, as shown in fig. 11, where the electronic device includes: a processor 101, and a memory 102.
The memory 102 is used for storing a program, and the processor 101 calls the program stored in the memory 102 to execute the above-described method embodiment. The specific implementation manner and the technical effect are similar, and are not repeated here.
Optionally, the present invention also provides a program product, such as a computer readable storage medium, comprising a program for performing the above-described method embodiments when being executed by a processor.
In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.
The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (english: processor) to perform some of the steps of the methods according to the embodiments of the invention. And the aforementioned storage medium includes: u disk, mobile hard disk, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk, etc.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A method for determining through silicon vias in a chip, comprising:
determining a plurality of grid points in a preset coordinate system of a target layer according to the preset distance;
performing power consumption analysis according to the power consumption information of the target chip, and determining the positions of a plurality of initial cross-chip-layer through silicon vias in a preset coordinate system;
determining target grid points corresponding to the positions of the initial cross-chip layer through silicon vias in the preset coordinate system according to the positions of the initial cross-chip layer through silicon vias;
determining a target cross-chip layer through silicon via according to the target grid points, wherein the target cross-chip layer through silicon via comprises: a first cross-chip layer through silicon via for connecting to a power terminal of an external power source.
2. The method of claim 1, wherein after the determining the target cross-chip layer through silicon vias from the target grid points, the method further comprises:
projecting a first logic unit in a connection relation layer of the target layer to the target layer, wherein the target layer further comprises: a second logic unit;
determining a connecting line between the projected first logic unit and the second logic unit with a connecting relationship in the target layer;
Determining a first grid point nearest to the connecting line from a plurality of grid points of the target layer as a second cross-chip layer through silicon via for a connecting unit, wherein the target cross-chip layer through silicon via comprises: the second cross-chip layer through silicon via.
3. The method according to claim 2, wherein the method further comprises:
if the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias are coincident, re-determining a second grid point from a plurality of grid points of the target layer according to the connecting line;
and taking the second grid points as the second cross-chip layer silicon through holes.
4. The method according to claim 2, wherein the method further comprises:
performing thermal simulation according to preset chip thickness, logic unit distribution, position information and radius information of the target cross-chip layer through silicon vias, and obtaining simulation temperatures of grid points in the preset coordinate system;
determining a third grid point from the grid points according to the simulated temperature of each grid point and a preset temperature threshold value;
and determining a third cross-chip layer through silicon via for heat dissipation according to the third grid point, wherein the target cross-chip layer through silicon via comprises: and a third cross-chip layer through silicon via.
5. The method of claim 4, wherein after the determining a third cross-chip layer through silicon via for heat dissipation according to the third grid point, the method further comprises:
judging whether the third cross-chip layer through silicon vias are overlapped with the second cross-chip layer through silicon vias in the target layer or not;
if yes, re-determining a fourth grid point from the grid points of the target layer, and taking the fourth grid point as the second cross-chip layer through silicon via;
and according to the preset chip thickness, the logic unit distribution, the position information and the radius information of the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias, performing thermal simulation again, and determining a fifth grid point as the third cross-chip layer through silicon vias again until a first thermal simulation result meets a first preset condition to obtain a final target cross-chip layer through silicon via.
6. The method of claim 5, wherein after the thermally simulating again based on the preset chip thickness, the logic cell distribution, the location information of the first cross-chip layer through silicon via and the second cross-chip layer through silicon via, and the radius information, and the re-determining the fifth grid point as the third cross-chip layer through silicon via, until the first thermal simulating result meets the first preset condition, and obtaining the final target cross-chip layer through silicon via, the method further comprises:
Performing time sequence evaluation according to the target cross-chip layer through silicon vias to obtain a first time sequence evaluation result;
if the first time sequence evaluation result does not meet a second preset condition, a sixth grid point is redetermined from the grid points of the target layer, and the sixth grid point is used as the second cross-chip layer through silicon via;
and according to the preset chip thickness, the logic unit distribution, the position information and the radius information of the first cross-chip layer through silicon vias and the second cross-chip layer through silicon vias, performing thermal simulation again, and determining a seventh grid point as the third cross-chip layer through silicon vias again until a second thermal simulation result meets the first preset condition and a second time sequence evaluation result meets the second preset condition to obtain a final target cross-chip layer through silicon via.
7. The method of claim 2, wherein prior to projecting the first logical unit in the connection relation layer of the target layer to the target layer, the method further comprises:
performing thermal simulation according to preset logic unit density, and determining the number and positions of initial second cross-chip-layer through silicon vias;
The determining a first grid point closest to the connecting line from a plurality of grid points of the target layer includes:
and determining a first grid point nearest to the connecting line from a plurality of grid points of the target layer according to the number and the positions of the initial second cross-chip layer through silicon vias.
8. A through-silicon via determining apparatus in a chip, comprising:
the determining module is used for determining a plurality of grid points in a preset coordinate system of the target layer according to the preset distance; performing power consumption analysis according to the power consumption information of the target chip, and determining the positions of a plurality of initial cross-chip-layer through silicon vias in a preset coordinate system; determining target grid points corresponding to the positions of the initial cross-chip layer through silicon vias in the preset coordinate system according to the positions of the initial cross-chip layer through silicon vias; determining a target cross-chip layer through silicon via according to the target grid points, wherein the target cross-chip layer through silicon via comprises: a first cross-chip layer through silicon via for connecting to a power terminal of an external power source.
9. An electronic device, comprising: a memory storing a computer program executable by the processor, and a processor implementing the method of determining through silicon vias in a chip according to any of the preceding claims 1-7 when the computer program is executed by the processor.
10. A computer readable storage medium, characterized in that the storage medium has stored thereon a computer program which, when read and executed, implements the through silicon via determination method in a chip according to any of the preceding claims 1-7.
CN202311601451.6A 2023-11-28 2023-11-28 Method and device for determining through silicon vias in chip, electronic equipment and storage medium Pending CN117637740A (en)

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