CN117709253A

CN117709253A - Chip testing method and device, electronic equipment and readable storage medium

Info

Publication number: CN117709253A
Application number: CN202410145891.3A
Authority: CN
Inventors: 李作骏; 闫世显; 陈明宇; 卢天越; 唐丹; 包云岗
Original assignee: Beijing Open Source Chip Research Institute
Current assignee: Beijing Open Source Chip Research Institute
Priority date: 2024-02-01
Filing date: 2024-02-01
Publication date: 2024-03-15
Anticipated expiration: 2044-02-01
Also published as: CN117709253B

Abstract

The application provides a chip testing method, a device, electronic equipment and a readable storage medium, and relates to the technical field of chip development, wherein the method comprises the following steps: setting up a chip test system in the simulator, sending a first reading operation instruction to a first virtual memory controller through a virtual processor, and dispatching the first operation instruction to a virtual port physical layer through the first virtual memory controller; reading data from the second virtual memory through the virtual port physical layer and performing signal conversion processing to obtain a read value of the signal conversion processing and storing the read value into the first virtual memory; and responding to a second read operation instruction sent to the second virtual memory controller by the virtual processor, extracting a read value from the first virtual memory, and determining whether the function of the virtual chip meets the preset chip function design requirement according to the read value. The method can test the performances of the processor and the memory controller of the chip at the same time.

Description

Chip testing method and device, electronic equipment and readable storage medium

Technical Field

The present disclosure relates to the field of chip testing technologies, and in particular, to a chip testing method, a device, an electronic apparatus, and a readable storage medium.

Background

The read operation function is an important function in the chip computing system, and when the chip computing system is designed, the read operation function of the chip computing system needs to be tested.

In the related art, a computing system of a chip can be tested through a field programmable gate array (Field Programmable Gate Array, FPGA), and compared with a method using software simulation, the method using the FPGA to test the chip can shorten the test iteration period. The chip computing system at least comprises a processor, a memory controller and a port physical layer, but because the FPGA lacks a virtual port physical layer with the same interface as the chip memory controller, the function test of the virtual memory controller and the function test of the memory processor can not be performed when the chip computing system is tested in the related technology.

That is, the related art method cannot perform a functional test on a memory controller in a chip computing system.

Disclosure of Invention

The embodiment of the application provides a chip testing method, a chip testing device, electronic equipment and a readable storage medium, so as to solve the problem that a method for effectively testing chips is lacking in the prior art.

In a first aspect, an embodiment of the present application provides a method for testing a chip, including:

A chip test system is built in a simulator, the chip test system comprises a virtual chip, a first virtual memory controller, a virtual port physical layer and a first virtual memory, the virtual chip comprises a virtual processor, a second virtual memory controller and a second virtual memory,

sending, by the virtual processor, a first read operation instruction to the first virtual memory controller, and scheduling, by the first virtual memory controller, the first operation instruction and sending the first operation instruction to the virtual port physical layer; the communication protocol between the virtual port physical layer and the second virtual memory controller is different;

reading data from the second virtual memory through the virtual port physical layer and performing signal conversion processing to obtain a reading value of the signal conversion processing and storing the reading value into the first virtual memory;

and responding to a second read operation instruction sent to the second virtual memory controller by the virtual processor, extracting the read value from the first virtual memory, and determining whether the function of the virtual chip meets the preset chip function design requirement according to the read value.

In a second aspect, an embodiment of the present application provides a chip testing system, including: the virtual memory system comprises a virtual chip, a first virtual memory controller, a virtual port physical layer and a first virtual memory, wherein the virtual chip comprises a virtual processor, a second virtual memory controller and a second virtual memory;

The virtual processor is configured to send a first read operation instruction to the first virtual memory controller;

the first virtual memory controller is configured to schedule the first read operation instruction and send the first read operation instruction to the virtual port physical layer;

the virtual port physical layer is used for reading data from the second virtual memory and performing signal conversion processing to obtain a reading value of the signal conversion processing and storing the reading value into the first virtual memory; the communication protocol between the virtual port physical layer and the second virtual memory controller is different;

and the second virtual memory controller is used for responding to a second read operation instruction sent by the virtual processor, extracting the read value from the first virtual memory, and determining whether the function of the virtual chip meets the preset chip function design requirement according to the read value.

In a third aspect, an embodiment of the present application further provides a chip testing apparatus, including:

the system comprises a building module, a testing module and a testing module, wherein the building module is used for building a chip testing system in a simulator, the chip testing system comprises a virtual chip, a first virtual memory controller, a virtual port physical layer and a first virtual memory, and the virtual chip comprises a virtual processor, a second virtual memory controller and a second virtual memory;

The sending module is used for sending a first reading operation instruction to the first virtual memory controller through the virtual processor, and dispatching the first reading operation instruction to the virtual port physical layer through the first virtual memory controller; the communication protocol between the virtual port physical layer and the second virtual memory controller is different;

the first reading module is used for reading data from the second virtual memory through the virtual port physical layer and performing signal conversion processing so as to obtain a reading value of the signal conversion processing and storing the reading value into the first virtual memory;

and the second reading module is used for responding to a second reading operation instruction sent to the second virtual memory controller by the virtual processor, extracting the reading value from the first virtual memory and determining whether the function of the virtual chip meets the preset chip function design requirement according to the reading value.

In a fourth aspect, embodiments of the present application further provide an electronic device, including a processor;

a memory for storing the processor-executable instructions;

wherein the processor is configured to execute the instructions to implement the method of the first aspect.

In a fifth aspect, embodiments of the present application also provide a computer-readable storage medium, which when executed by a processor of an electronic device, causes the electronic device to perform the method of the first aspect.

In this embodiment of the present application, a first read operation instruction is sent to a first memory controller by a virtual processor, data is read from a second virtual memory by the first virtual memory controller and a virtual port physical layer, after signal conversion processing is performed on the read data, the read data is not directly sent to the second virtual memory controller, but is stored in the first virtual memory, and the second memory controller obtains a read value from the first virtual memory according to the second read operation instruction sent by the virtual processor, so as to determine whether the function of the virtual chip meets the preset chip function design requirement according to the read value. The testing process is completed through the virtual processor and the second virtual memory controller, so that the finally obtained test result of the read operation can reach the preset chip function design requirement only under the condition that the functions of the virtual processor and the second virtual memory controller reach the preset chip function design requirement. Based on the test result of the read operation obtained by the method of the embodiment, the read operation functions of the virtual processor and the second virtual memory controller can be reflected at the same time, and the problem that in the related art, the virtual port physical layer and the second virtual memory controller in the virtual chip have different communication protocols due to the fact that the virtual port physical layer with the same interface as the second virtual memory controller is lacking in the simulator, so that the functions of the second virtual memory controller cannot be tested is solved.

The foregoing description is only an overview of the technical solutions of the present application, and may be implemented according to the content of the specification in order to make the technical means of the present application more clearly understood, and in order to make the above-mentioned and other objects, features and advantages of the present application more clearly understood, the following detailed description of the present application will be given.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 is a schematic diagram of an application scenario of a chip testing method provided in an embodiment of the present application;

FIG. 2 is a flowchart illustrating steps of a method for testing a chip according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a chip computing system according to an embodiment of the present disclosure;

FIG. 4 is a flowchart illustrating steps of another method for testing a chip according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a chip test system according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a chip test system according to an embodiment of the present disclosure;

FIG. 7 is a flowchart illustrating steps of a method for testing a chip according to an embodiment of the present application;

FIG. 8 is a flowchart illustrating steps of a method for testing a chip according to an embodiment of the present application;

FIG. 9 is a schematic diagram of another chip testing system according to an embodiment of the present disclosure;

FIG. 10 is a block diagram of a chip test apparatus according to an embodiment of the present invention;

FIG. 11 is a block diagram of an electronic device provided by an embodiment of the present invention;

fig. 12 is a block diagram of another electronic device in accordance with another embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type and not limited to the number of objects, e.g., the first object may be one or more. Furthermore, the term "and/or" as used in the specification and claims to describe an association of associated objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The term "plurality" in the embodiments of the present application means two or more, and other adjectives are similar thereto.

Fig. 1 is a schematic view of an application scenario of a chip testing method provided in an embodiment of the present application, and referring to fig. 1, the application scenario includes at least an emulator, in which a chip testing system is built, the chip testing system includes a virtual chip, and the virtual chip includes a virtual processor, a second memory controller, and a second virtual memory. The chip test system also comprises a time sequence control module, wherein the time sequence control module at least comprises a first virtual memory controller, a virtual port physical layer and a first virtual memory.

In the development process of the chip, the chip needs to be tested, and after the development of the chip is completed, the physical chip can be obtained through streaming processing according to the virtual chip. Further, in the chip development process, it is necessary to design a computing system of the chip and test the computing system of the chip. Wherein the testing includes at least a read operation test of the chip. Specifically, the portion to be tested is a System on Chip (SoC), where the SoC System includes at least: a processor, a memory controller, a port physical layer, and a memory. In the related art, when a chip test can be performed using an emulator (e.g., FPGA), but the kind of the emulator with its own virtual module is limited, it is difficult to deploy a processor, a memory controller, a port physical layer, and a storage medium for designing the chip in the emulator.

For example, the emulator interfaces with a Physical Layer (PHY) of the virtual port, unlike the memory controller that is designed when the chip is designed. Illustratively, when designing a chip, the downward interfaces of the designed memory controller are Double Data Rate (DDR) and PHY interfaces (DDR PHY Interface, DFI) interfaces, while the virtual port physical layer of the emulator itself does not have a DFI interface. This may result in the emulator having a second virtual memory controller corresponding to the designed memory controller that is different from the communication protocol between the virtual port physical layer. Because the second virtual memory controller is different from the communication protocol between the physical layers of the virtual ports, the related art only can test the processor in the chip, but cannot test the memory controller.

In order to solve the problems in the related art, the present application provides a chip test method, by constructing a chip test system including a virtual chip, a first virtual memory controller, a virtual port physical layer and a first virtual memory, sending a first read operation instruction to the first virtual memory controller (Memory Controller, MC) through a virtual processor in the virtual chip, scheduling the first operation instruction by the first virtual memory controller, sending the first operation instruction to the virtual port physical layer (PHY), reading data from a second virtual memory through the virtual port physical layer, performing signal conversion processing, obtaining a read value of the signal conversion processing, and storing the read value in the first virtual memory of a timing control module. And sending a second reading operation instruction to the second virtual memory controller through the virtual processor, extracting a reading value from the first virtual memory, and determining whether the reading operation of the virtual chip meets the preset test requirement according to the reading value.

The chip testing method provided in the embodiment of the present application is described in detail below with reference to fig. 2 through a specific embodiment.

Fig. 2 is a flowchart of steps of a method for testing a chip according to an embodiment of the present application, as shown in fig. 2, the method may include:

step 101, a chip test system is built in a simulator.

The chip test system comprises a virtual chip, a first virtual memory controller, a virtual port physical layer and a first virtual memory, wherein the virtual chip comprises a virtual processor and a second virtual memory controller.

Illustratively, the first virtual memory controller, the virtual port Physical Layer (PHY), the first virtual memory, the second virtual memory, the virtual processor, and the second virtual memory controller are all self-contained virtual modules in the emulator. For example, the simulator may be a simulator provided for an FPGA.

By way of example, a virtual chip is a chip designed by a virtual module in an emulator in the process of developing the chip. The chip development process comprises a test process of the chip, and after the chip development is completed, the physical chip can be obtained through streaming processing according to the virtual chip. For example, after the chip development is completed, the physical chip is obtained by stream processing according to the designed virtual chip, and the virtual processor in the virtual chip corresponds to the physical processor in the physical chip, and the processing logic of the virtual processor is the same as that of the physical processor. The second virtual memory controller in the virtual chip corresponds to the memory controller in the physical chip, and the processing logic between the second virtual memory controller and the memory controller is identical to that between the second virtual memory controller and the memory controller.

Further, the second virtual memory corresponds to the designed memory. The memory may be of various types, for example, a double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR4 SDRAM) chip, a DDR3 chip, or other types of memory.

In particular, the DDR memory is a common memory, and is suitable for various computing systems and electronic devices, and DDR can be used as a memory to improve the data storage performance and the data access performance of the computing system. For example, DDR may be applied to personal computers, servers, embedded systems, graphics processing systems, multimedia processing systems, network devices, large-scale data centers, scientific computing systems, artificial intelligence devices, internet of things devices, and various high-performance computing systems. DDR has high speed performance, high bandwidth and low power consumption characteristics, making it an integral part of modern computing systems.

Step 102, sending, by the virtual processor, a first read operation instruction to the first virtual memory controller, and scheduling, by the first virtual memory controller, the first read operation instruction and sending the first read operation instruction to the virtual port physical layer.

Referring to fig. 3, the physical chip includes at least a processor, a memory controller, a port physical layer, and a storage medium. The processor and the memory controller have the same interface, so that data and commands can be transmitted between the processor and the memory controller, the memory controller and the port physical layer have the same interface, the memory controller and the port physical layer can transmit data and commands, the port physical layer and the storage medium have the same interface, and the memory controller and the port physical layer can transmit data and commands.

However, in an emulator, the interface between the native virtual port physical layer and the virtual memory controller may be different, which results in different communication protocols between the two. For example, in this embodiment, the communication protocol between the virtual port physical layer and the second virtual memory controller is different. Further, the downward interfaces of the virtual port physical layer and the second virtual memory controller are different, resulting in a different communication protocol between the virtual port physical layer and the second virtual memory controller. For example, the virtual port physical layer interface is an advanced extensible interface (Advanced eXtensible Interface, AXI 4), and the downstream interface of the second virtual memory controller is a DFI.

The communication protocols between the virtual port physical layer and the second virtual memory controller are different, so that the virtual port physical layer and the second virtual memory controller cannot directly perform data interaction and cannot directly perform instruction transmission.

For example, the first read operation instruction is sent to the first virtual memory controller through the virtual processor, and the first virtual memory controller schedules the first read operation instruction according to a preset scheduling policy, and sends the scheduled first read operation instruction to the virtual port physical layer in the form of a digital signal. For example, the preset scheduling policy may be a bandwidth maximum and/or a latency minimum.

For example, in the case where the emulator is an FPGA, the first virtual memory controller and the virtual port physical layer may be integrated in the same virtual module.

And 103, reading data from the second virtual memory through the virtual port physical layer and performing signal conversion processing to obtain a reading value of the signal conversion processing and storing the reading value into the first virtual memory.

After the virtual port physical layer receives the first reading operation instruction, reading data from the physical address in the second virtual memory according to the physical address in the first operation instruction. Wherein the physical address is an address where data to be read is loaded in the second virtual memory. After the virtual port physical layer reads data from the second virtual memory, the virtual port physical layer converts the data of the analog signal into the data of the digital signal, and stores the converted data into the first virtual memory as a read value.

For example, the data stored in the second virtual memory may be data that is written into the second virtual memory according to a write operation instruction sent to the first virtual memory controller by the virtual processor, or may be data that is written into the second virtual memory by another processor.

Step 104, responding to the second read operation instruction sent to the second virtual memory controller by the virtual processor, extracting the read value from the first virtual memory, and determining whether the function of the virtual chip meets the preset chip function design requirement according to the read value.

For example, a second read operation instruction is sent to the second virtual memory controller by the virtual processor, the second virtual memory controller schedules the second read operation instruction, and a read value is extracted from the first virtual memory according to the scheduled second read operation instruction.

For example, the preset chip function design requirements include: the read value obtained from the read operation is correct. And under the condition that the read value is correct, determining that the function of the virtual chip meets the preset chip function design requirement.

In the related technology, the chip can be tested through a software simulation environment, but the common software simulation environment has the problem of low simulation speed, and the chip with complex system and large test load cannot be completely and accurately accessed and stored in a short time by using the software simulation environment.

For simulators (such as FPGA) with a faster simulation speed, there is a virtual port physical layer in the simulator, which is different from an interface of a designed virtual memory controller of a designed chip, so that in a chip test system built in the simulator, the virtual memory controller of the virtual chip and the virtual port physical layer cannot directly perform data interaction, and therefore, the method in the related art can only test the virtual processor, but cannot test the virtual memory controller.

In this embodiment of the present application, a first read operation instruction is sent to a first memory controller by a virtual processor, data is read from a second virtual memory by the first virtual memory controller and a virtual port physical layer, after signal conversion processing is performed on the read data, the read data is not directly sent to the second virtual memory controller, but is stored in the first virtual memory, and the second memory controller obtains a read value from the first virtual memory according to the second read operation instruction sent by the virtual processor, so as to determine whether the function of the virtual chip meets the preset chip function design requirement according to the read value. The testing process is completed through the virtual processor and the second virtual memory controller, so that the finally obtained test result of the read operation can reach the preset chip function design requirement only under the condition that the functions of the virtual processor and the second virtual memory controller reach the preset chip function design requirement. Therefore, based on the test result of the read operation obtained by the method of the embodiment, the read operation functions of the virtual processor and the second virtual memory controller can be reflected at the same time, and the problem that in the related art, the second virtual memory controller cannot be tested because the virtual port physical layer with the same interface as the chip memory controller is lacking in the simulator, so that the communication protocols between the virtual port physical layer and the second virtual memory controller in the virtual chip are different is solved.

Fig. 4 is a flowchart illustrating steps of another method for testing a chip provided in the present application, and referring to fig. 4, the method may include the following steps:

step 201, a chip test system is built in a simulator.

Specifically, the chip test system comprises a virtual chip, a first virtual memory controller, a virtual port physical layer and a first virtual memory, wherein the virtual chip comprises a virtual processor, a second virtual memory controller and a second virtual memory.

The method of this step is described in the foregoing step 101, and will not be described here again.

Step 202, sending, by the virtual processor, a first read operation instruction to the first virtual memory controller, and scheduling, by the first virtual memory controller, the first read operation instruction to be sent to the virtual port physical layer.

The method of this step is described in the foregoing step 102, and will not be described herein.

In step 203, the data is read from the second virtual memory through the virtual port physical layer and subjected to signal conversion processing, so as to obtain a read value of the signal conversion processing and store the read value into the first virtual memory.

Specifically, the communication protocol between the virtual port physical layer and the second virtual memory controller is different.

The method of this step is described in the foregoing step 103, and will not be described here again.

In one embodiment, the first read operation instruction includes a plurality of first sub-read operation instructions, each having a respective first physical address.

Specifically, the physical address is the physical address in the second virtual memory of the data that the first sub-read operation instruction needs to read.

Correspondingly, in step 203, the step of reading data from the second virtual memory through the virtual port physical layer and performing signal conversion processing may include the following sub-steps:

in sub-step 2031, in response to a first sub-read operation instruction, data is read from a first physical address of a second virtual memory through a virtual port physical layer according to a first physical address corresponding to the first sub-read operation instruction, and signal conversion processing is performed on the read data to obtain a plurality of read values.

Specifically, the first memory controller schedules a plurality of first sub-read operation instructions, sends the scheduled first sub-read operation instructions to the virtual port physical layer, the virtual port physical layer receives the scheduled first sub-read operation instructions, reads data from the second virtual memory according to first physical addresses corresponding to the first sub-read operation instructions, converts the obtained data in an analog format into data in a digital signal format, and achieves signal conversion processing of the read data, wherein the data after signal conversion processing is read values according to the first sub-read operation instructions.

The read values and the first sub-read operation instructions are in one-to-one correspondence, and each read value has a first physical address corresponding to each read value.

In one embodiment, the chip test system further comprises a fourth virtual memory; step 203 may comprise the following sub-steps:

sub-step 2033, storing the first read operation instruction in a fourth virtual memory in response to the first read operation instruction issued by the virtual processor.

The fourth virtual memory is a virtual memory set in the chip test system in the process of developing the chip. And after the chip development is completed, the entity memory corresponding to the fourth virtual memory is not included in the entity chip obtained through the streaming processing.

The fourth virtual memory includes a read command memory and a write command memory for buffering commands that the first virtual memory controller and the virtual port physical layer fail to receive in time.

Sub-step 2034, after receiving, by the first virtual memory controller, the instruction to complete the function guarantee operation for the second virtual memory, sends the first read operation instruction stored in the fourth virtual memory to the virtual port physical layer to read data from the second virtual memory through the virtual port physical layer.

Specifically, the function guarantee operation is used for enabling the second virtual memory to perform correct read-write operation. For example, the function assurance operation may include a refresh operation, and/or a calibration operation.

Illustratively, the refresh complete instruction is configured to indicate that the refresh operation is complete for the second virtual memory, and the calibration complete instruction is configured to indicate that the calibration operation is complete for the second virtual memory. The calibration operation may include Zone delimiter (ZQ) calibration, among others.

For example, by the virtual processor, instructions to refresh and/or calibrate the first virtual memory controller are sent to the first virtual memory controller, which, based on the instructions, controls the second virtual memory to refresh and/or calibrate. After the refresh is complete, and/or the calibration is complete, an instruction is issued indicating that the corresponding operation is complete.

In this embodiment, after receiving, by the first virtual memory controller, an instruction for performing a function guarantee operation by the second virtual memory, a first read operation instruction stored in the fourth virtual memory is sent to the virtual port physical layer, so that data is read from the second virtual memory by the virtual port physical layer, instead of immediately sending the first read operation instruction to the virtual port physical layer in response to the first read operation instruction sent by the virtual processor, which can avoid the problem that the data transmission bus is blocked because the read and write operation cannot be performed in the process of performing the function guarantee operation by the second virtual memory.

In one embodiment, the chip test system further includes a fourth virtual memory, and step 203 may include the sub-steps of:

sub-step 2035, storing the first read operation instruction in a fourth virtual memory in response to the first read operation instruction issued by the virtual processor.

The method of this step is described in the foregoing step 2033, and will not be described here again.

Sub-step 2036, obtaining a second design timing parameter for the second virtual memory controller when the second virtual memory controller is designed.

The second design time sequence parameter is used for determining the instruction sending time matched with the second design time sequence parameter when the read-write operation instruction is sent subsequently.

The second design time sequence parameter refers to the time sequence parameter used by the designed chip when sending the read-write operation instruction in the chip development process. According to the second design time sequence parameter, the time interval between the sending of the read-write operation instruction and the sending of the read-write operation instruction again can be determined after the reading-write operation instruction is sent, and therefore the instruction sending time of the next read-write operation instruction can be determined based on the second design time sequence parameter and the time of sending the last read-write operation instruction, and the read-write operation instruction is sent at the instruction sending time.

Sub-step 2037, sends the first read operation instructions stored in the fourth virtual memory to the virtual port physical layer to read data from the second virtual memory through the virtual port physical layer according to the second design timing parameters.

And determining an instruction sending time for sending the first reading operation instruction according to the second design time sequence parameter, and sending the first reading operation instruction to the virtual port physical layer.

In one embodiment, the clock frequency at which the virtual processor is run in the emulator is less than the design frequency at which the virtual processor is designed.

Step 204, obtaining a first design timing parameter of the second virtual memory controller when designing the second virtual memory controller.

Specifically, the first design time sequence parameter is used for determining the read-write time matched with the first design time sequence parameter when the read-write operation is executed subsequently, and acquiring the read-write data at the read-write time.

Further, the design timing parameters refer to timing parameters used when the designed chip performs read-write operations during the process of developing the chip. For example, the first design timing parameter is a memory timing used during a chip read and write operation, for example, the first design timing parameter may include a column address strobe delay (ColumnAddress Strobe Latency, CL), which is a column address strobe (ColumnAddress Strobe, CAS) delay time, representing the time required to issue a command to read data, which may be expressed in cycles.

In step 205, in response to the second read operation instruction sent by the virtual processor to the second virtual memory controller, a read value is extracted from the first virtual memory according to the first design timing parameter, so as to determine whether the performance of the virtual chip meets the preset chip performance design requirement according to the read time when the read value is obtained.

Illustratively, the preset chip performance design requirements include: the response time of the virtual chip is smaller than or equal to a preset response time threshold. Further, according to the moment of acquiring the read value, the response time of acquiring the virtual chip is calculated.

And determining whether the performance of the virtual chip meets the preset chip performance design requirement or not under the condition that the calculated response time is smaller than or equal to the preset response time threshold value according to the moment of acquiring the read value.

For example, in the case that the virtual processor issues a plurality of read operation instructions, or a plurality of read and write operation instructions, the time when the first instruction is issued is acquired, and the time when the read value is read according to the last read operation instruction, the duration between the two times is determined as the response time of the virtual chip.

In an example, the virtual processor sends a second read operation instruction to the second virtual memory controller, determines a time delay from the second virtual memory controller to the reading of the data based on the first design timing parameter, and determines a time to fetch the read value from the first virtual memory based on a time and a time delay at which the second virtual memory controller issues the second read operation instruction.

In the chip development process, it is necessary to design a chip and test the performance of the designed chip. Specifically, virtual chips are built and run in an emulator (e.g., FPGA) to test chip performance. However, when designing a chip, the clock frequency of some design modules (such as a design processor) in the design chip is relatively high, and the clock frequency of the system operation of the simulator is generally limited, for example, the clock frequency of the design processor may be higher than 3GHz, and the clock frequency of the simulator system operation can only reach hundreds of MHz. Therefore, in order to run the design chip in the emulator, it is necessary to perform down-conversion processing on a module having a higher clock frequency in the design chip so that the emulator can successfully run the virtual chip constructed for the design chip. For example, it is desirable to reduce the clock frequency of the design processor to the range of clock frequencies in which the system operates in the emulator.

After the design processor in the design chip computing system is subjected to frequency reduction processing, the obtained virtual processor can normally operate according to the data processing logic of the design processor, but after some design modules (such as storage media) in the design chip are subjected to frequency reduction processing according to the frequency reduction proportion of the design processor, the modules may have abnormal operation, so that the chip test result is inaccurate. For example, for a storage medium in a design chip computing system, the storage medium needs to operate at a particular higher frequency because of its own performance. For example, the storage medium is a synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM) chip, when the SDRAM is operated in Delay-Locked Loop off (DLL off) mode, the PHY supporting the DLL off mode is required, and the SDRAM chip needs to be refreshed periodically to ensure the correctness of the data. Because of the limitation of the SDRAM refresh calibration interval, in the DLL mode, although the SDRAM and a processor (such as a CPU) can achieve equal-proportion frequency reduction, the chip access test is inaccurate due to the refresh frequency difference.

After the down conversion processing is performed on each module, the behavior of part of the modules changes, so that the performance (such as access capability) of the chip computing system is tested inaccurately. Therefore, when a virtual chip is built in the simulator, it is difficult to perform equal-scale down-conversion on each module in the virtual chip. However, if only some of the design modules in the design chip are down-converted, the test result will be inaccurate. For example, when only the design processor is subjected to the frequency-reducing process, but not the design storage medium, the clock frequency of the virtual storage medium is equal to that of the design virtual storage medium, and the clock frequency of the virtual processor is lower than that of the design processor, the processor (for example, a central processing unit) is subjected to frequency-reducing, and the storage medium (for example, an SDRAM chip) is not subjected to frequency-reducing, which can cause high test performance of the central processing unit (Central Processing Unit, CPU).

In the related art, the access delay can be simulated by adding simple fixed delay, but the fixed delay is not necessarily suitable for designing a chip, so that a method for adding the fixed delay cannot simulate the actual access behavior of the designed chip, and the test result of the chip is inaccurate. The clock gating can be utilized to decouple the timing dependency of the processor and the storage medium to test the chip performance at the emulator, but the timing model does not support the DFI protocol, the memory controller of the DFI interface cannot be verified, and the timing provided by the timing model can reduce the emulation speed of the entire computing system during read and write operations.

In this embodiment, the test result of the read operation obtained based on the method of this embodiment may reflect the read operation functions of the virtual processor and the second virtual memory controller at the same time, so as to solve the problem that in the related art, the performance of the second virtual memory controller cannot be tested due to the different communication protocols between the physical layer of the virtual port in the emulator and the second virtual memory controller in the virtual chip. The design time sequence parameter according to which the read value is obtained from the second virtual memory controller is used for obtaining the read value at the read-write time matched with the first design time sequence parameter when the read-write operation is executed subsequently, so that the time sequence of the read value is obtained and is consistent with the time sequence of the read value obtained from the design chip. Therefore, under the condition that the clock frequency of the virtual processor running in the simulator is smaller than the design frequency when the virtual processor is designed, the virtual chip can acquire the read value at the read-write time matched with the first design time sequence parameter, and whether the performance of the virtual chip meets the preset chip performance design requirement can be accurately determined according to the time of acquiring the read value. Based on the method of the embodiment, the accuracy of the read operation performance of the test virtual chip is improved.

In one embodiment, the clock frequency of the second virtual memory is greater than the clock frequency of the second virtual memory controller to read data from the second virtual memory through the virtual port physical layer and perform signal conversion processing to obtain a signal conversion processed read value and store the signal conversion processed read value in the first virtual memory before the read value is extracted from the first virtual memory in response to a second read operation instruction sent to the second virtual memory controller by the virtual processor. Therefore, the second virtual memory controller can timely acquire the read value from the first virtual memory according to the second read operation instruction sent by the virtual processor, so that accuracy of the obtained judgment result is ensured when the read operation performance of the virtual chip is judged according to the read value.

In one embodiment, the second read operation instruction includes a plurality of second sub-read operation instructions, each having a respective second physical address.

In step 205, in response to a second read operation instruction sent by the virtual processor to the second virtual memory controller, the fetching of the read value from the first virtual memory may include the sub-steps of:

Sub-step 2051, determining, from the first physical addresses corresponding to the read values, a target first physical address identical to the second physical address, according to the second physical address of the second sub-read operation instruction.

Each read value stored in the second virtual memory has a corresponding first physical address, which is the physical address where the read value is loaded in the second virtual memory.

For example, the second physical address of the second sub-read operation instruction is compared with the plurality of first physical addresses to obtain a target first physical address that matches the second physical address among the plurality of first physical addresses.

In a sub-step 2052, the read value corresponding to the target first physical address is determined as the read value corresponding to the second sub-read operation instruction.

The first read operation instruction comprises a plurality of first sub-read operation instructions, each having a respective first physical address, and a plurality of read values obtained from the second virtual memory according to the plurality of first sub-read operation instructions, each having a respective first physical address.

And selecting a read value corresponding to the target first physical address matched with the second physical address from a plurality of read values stored in the first virtual memory according to the second physical address of the second sub-read operation instruction, and taking the read value as the read value obtained according to the second sub-read operation instruction. The read value is the data to be read by the second sub-read operation instruction.

Step 2053, retrieving a read value corresponding to the second sub-read operation instruction from the first virtual memory.

Under the condition that the execution sequence of a first read operation instruction directly sent to the first virtual memory controller through the virtual processor is different from that of a second read operation instruction sent to the second virtual memory controller through the virtual processor, and the second virtual memory controller reads data, matching of physical addresses of two read operation instructions can be completed by comparing a first physical address of a read value obtained through the first read operation instruction with a second physical address of the second read operation instruction, so that correctness of the read value obtained from the first virtual memory by the second virtual memory controller is ensured.

In one embodiment, step 205 may include the sub-steps of:

sub-step 2053, performing protocol conversion on the read value according to the communication protocol of the second virtual memory controller to obtain a converted read value;

the communication protocol of the second virtual memory controller and the communication protocol of the virtual port physical layer are different, and the communication protocol of the read value read from the second virtual memory through the virtual port physical layer is different from the communication protocol of the second virtual memory controller.

And carrying out protocol conversion on the read value according to the communication protocol of the second virtual memory controller to obtain a converted read value, wherein the converted read value meets the communication protocol requirement of the second virtual memory controller.

Sub-step 2054, transmitting, by the second virtual memory controller, the converted read value to the virtual processor.

Illustratively, the second virtual memory controller and the virtual processor have the same communication protocol therebetween, and the second virtual memory controller transmits the converted read value to the virtual processor through the same communication protocol as the virtual processor.

In step 2055, it is determined, by the virtual processor, whether the function of the virtual chip meets the preset chip function design requirement according to the converted read value.

For example, the function of the chip meets the preset chip function design requirement, including that the read value read from the second virtual memory is correct when the read operation is performed.

For example, the virtual processor stores an expected read value corresponding to the read value, compares the read value with the expected read value, and determines that the function of the virtual chip meets the preset chip function design requirement under the condition that the read value and the expected read value are the same. Further, the expected read value is data written into the second virtual memory for the virtual processor to read from the second virtual memory according to the first read operation instruction.

The virtual processor calculates a response time from issuing the first read command to acquiring the read value according to the obtained converted read value, and determines that the read operation reaches a preset test requirement when the response time is less than or equal to a preset time threshold.

And carrying out protocol conversion on the read value according to a communication protocol of the second virtual memory controller to obtain a converted read value, and receiving and identifying the converted read value by the second virtual memory controller, so that the second virtual memory controller can obtain data in the second virtual memory, and judging whether the read operation of the virtual chip meets the preset test requirement according to the received and identified read value in the subsequent processing process.

The following is an exemplary description of a read operation test among the access tests.

In one embodiment, the chip test system further comprises a third virtual memory and a virtual write data comparator.

After step 201, further includes:

and step 206, responding to the first write operation instruction sent by the virtual processor, and writing the data sent by the virtual processor into a third virtual memory to obtain first write data.

The third virtual memory is, for example, a virtual module for testing chip performance during the chip development phase. And after the chip development is completed, the streaming processing is carried out to obtain the entity chip, wherein the entity chip does not comprise a memory entity corresponding to the third virtual memory.

In step 207, in response to the second write operation instruction of the second virtual memory controller, the data sent by the second virtual memory controller is written into the virtual write data comparator, so as to obtain second write data.

Illustratively, the second write operation instruction includes a write operation command, and write data that needs to be written in the virtual write data comparator.

Step 208, obtaining the first write data through the comparator, comparing the first write data with the second write data, and determining whether the function of the virtual chip meets the preset chip function design requirement according to the obtained comparison result.

Further, when the chip test is performed, a series of read-write operation instructions can be sent out through the virtual processor, data is written in the second virtual memory through the write operation instructions, the previously written data is read from the second virtual memory through the read operation instructions, and whether the functions of the virtual chip meet the preset chip function design requirements is determined according to the read data.

For example, in the case that the first write data and the second write data are the same, it is determined that the function of the virtual chip meets the preset chip function design requirement. And under the condition that the first write data and the second write data are different, determining that the functions of the virtual chip do not reach the preset chip function design requirements.

In this embodiment, when the first write data obtained according to the first write operation instruction sent by the virtual processor and the second write data obtained according to the second write operation instruction of the second virtual memory controller simultaneously reach the preset test requirement, the comparison result of the first write data and the second write data only reaches the preset test requirement. Based on the test result of the write operation obtained by the method of the embodiment, the write operation functions of the virtual processor and the second virtual memory controller can be reflected at the same time, and the problem that the functions of the virtual memory controller cannot be tested due to different communication protocols between the virtual port physical layer in the simulator and the virtual memory controller in the virtual chip in the related art is solved.

In one embodiment, the clock frequency of the virtual processor in the emulator is less than the design frequency at which the virtual processor is designed.

The clock frequency of the virtual processor in the simulator is smaller than the design frequency when the virtual processor is designed, and is equivalent to the frequency reduction processor for the virtual processor designed when the chip is designed. When the chip development is completed and the streaming processing is performed according to the virtual chip to obtain the physical chip, the clock frequency of the physical processor in the physical chip is equal to the design frequency of the designed virtual processor.

Correspondingly, step 207 may comprise the following sub-steps:

sub-step 2071, obtaining a first design timing parameter of a second virtual memory controller when the second virtual memory controller is designed; the first design time sequence parameter is used for determining the read-write time matched with the first design time sequence parameter when the read-write operation is executed subsequently, and acquiring read-write data at the read-write time.

The first design timing parameter is described in the foregoing step 204, and is not described herein.

Sub-step 2072, responding to the second write operation instruction sent to the second virtual memory controller by the virtual processor, and writing the data sent by the second virtual memory controller into the virtual write data comparator according to the first design time sequence parameter to obtain the second write data.

The virtual processor sends a second write operation instruction to the second virtual memory controller, the second virtual memory sends the second write operation instruction, the time delay of writing data is determined according to the first design time sequence parameter, the time of writing the data is determined according to the time delay, and the virtual write data comparator obtains the data sent by the second virtual memory controller at the time to obtain the second write data.

According to the first design time sequence parameter, the data sent by the second virtual memory controller are obtained and used as second write data, so that under the condition that the clock frequency of a virtual processor running in the simulator is smaller than the design frequency when the virtual processor is designed, the second write data which can accurately reflect the write operation performance of the virtual chip can be obtained according to the design time sequence parameter, the second write data can be compared with the first write data extracted from the third virtual memory, and whether the write operation performance of the virtual chip meets the preset test requirement is determined according to the comparison result.

In one embodiment, after sub-step 2027, further comprising:

sub-step 2028, the get dummy write data comparator gets the write time of the second write data.

Specifically, the writing time of the second writing data is obtained through the virtual writing data comparator.

Sub-step 2029, determining whether the performance of the virtual chip meets the preset chip performance design requirement according to the writing time.

For example, the response time of the virtual chip is obtained according to the writing time, and the performance of the virtual chip is determined to reach the preset chip performance design requirement under the condition that the response time is smaller than or equal to the preset response time threshold.

For example, according to the write time of the second write data obtained by the virtual write data comparator and the time of the second write operation instruction sent by the second virtual memory controller, the response time of the virtual chip is obtained according to the difference between the two times.

In one embodiment, referring to FIG. 5, a chip test system includes a virtual processor, a second virtual memory controller, a timing control module, a memory interface generator, and a second virtual memory.

The memory interface generator is a memory interface generator (Memory Interface Generator, MIG) provided by Xilinx, where the MIG includes a memory controller and a PHY, and in the embodiment shown in fig. 5, the MIG includes a memory control corresponding to the first virtual memory controller in the foregoing embodiment, and the MIG includes a PHY corresponding to the virtual port physical layer in the foregoing embodiment. Wherein the second virtual memory is DDR4 SDRAM.

Further, in the embodiment shown in fig. 5, the up interface of the MC (the second virtual memory controller in the foregoing embodiment) in the CPU minimum computing system is an on-chip bus interface, for example, the on-chip bus interface may be AXI4, and the down interface of the MC is a DFI interface. Correspondingly, in the embodiment shown in fig. 5, the interface of the second virtual memory controller to the virtual processor is a first interface, the first interface is an AXI4 interface, the interface of the second virtual memory controller to the timing control module is a second interface, and the second interface is a DFI interface. Further, the interface of the time sequence control module, which is in butt joint with the second virtual memory controller, is a second interface, and the interface of the time sequence control module, which is in butt joint with the memory interface generator, is a first interface.

The downward interface of the second virtual memory controller is a DFI interface, the interface of the memory interface generator is an AXI4 interface, the interfaces between the second virtual memory controller and the memory interface generator are different, and correspondingly, the communication protocols between the second virtual memory controller and the memory interface generator are also different. Specifically, the downward interface of the second virtual memory controller is different from the interface of the virtual port physical layer in the memory interface generator, and the communication protocol between the downward interface and the interface is different. Therefore, the second virtual memory controller cannot directly send an instruction to the memory interface generator, and the data read from the second virtual memory by the memory interface generator cannot be directly returned to the second virtual memory controller.

The interfaces of the memory interface generator and the virtual processor are AXI4 interfaces, and the virtual processor may directly send the instruction to the memory interface generator, for example, the first read operation instruction (the command a in fig. 5) in the foregoing embodiment may directly send the instruction to the memory interface generator through the virtual processor.

Illustratively, in testing chip performance, the virtual processor issues instructions, including commands and data, through two branches. Specifically, the first branch is: sending write data A and a command A to a time sequence controller module through a virtual processor; the other branch is: and sending the command and the data to a second virtual memory controller through the virtual processor, and sending the data B and the command B to a time sequence controller module by the second virtual memory controller.

Further, aiming at the problem that the PHY of the DFI interface is absent in the simulator (for example, FPGA), the performance of the MC of the DFI interface cannot be verified in the FPGA, the write data can be written into the first virtual storage medium through the first branch and the timing control module, the read data can be read out from the AXI4 interface of the memory interface generator, converted into the DFI protocol format through the timing control module, and then forwarded to the second virtual memory controller.

Specifically, referring to fig. 6, the chip test system includes a virtual processor, a first virtual memory controller, a timing control module, a second virtual memory controller, a virtual port physical layer, and a second virtual memory.

Referring to fig. 6, the timing control module includes a timing parameter register, a read data controller, a write data comparator, a write data memory, a write command memory, a read data memory, a command controller, and a read command memory.

The read data memory corresponds to the first virtual memory in the foregoing embodiment, the write data memory corresponds to the third virtual memory in the foregoing embodiment, and the read command memory corresponds to the fourth virtual memory in the foregoing embodiment.

The virtual processor may be a CPU, a graphics processor (graphics processing unit, GPU), a special purpose processor, or other processor, among others. The second virtual memory controller is a memory controller in the chip to be tested and is mainly responsible for prefetching, scheduling and the like of the access command. The second virtual memory controller is equivalent to a main memory controller (Host MemoryController, MC) in the system, and in order to improve the memory access performance of the computing system, the second virtual memory controller generally reorders the memory access command sequence according to the medium state, so as to achieve the purposes of high bandwidth and low latency.

The timing control module is used for controlling command and data timing control so as to ensure that the memory access behavior timing sequence of a chip computing system (such as a SoC system) in the simulator FPGA is consistent with the actual memory access behavior timing sequence.

The time sequence parameter register is used for storing the real time sequence parameter configuration of the computing system. Specifically, the first design timing parameter, the second design timing parameter, and the third design timing parameter in the foregoing embodiments are stored.

The read data memory is used for caching read data read from the second virtual memory, a physical address corresponding to the read value and state information about whether the read value returns or not. The physical address corresponds to the first physical address in the foregoing embodiment, and is obtained by analyzing by an address decoding module in the read data controller, and the read data state information is updated according to the condition that the first virtual memory controller returns the read data.

The read data controller is used for ensuring that correct data can be read according to the second read operation command after disordered sequence, and simultaneously ensuring that returned read data meets the time sequence required by the second virtual memory controller. The read data controller comprises an address decoding module, wherein the address decoding module is used for carrying out address decoding on the first read command and the second read command according to a preset address mapping relation so as to obtain respective physical addresses, and taking out corresponding read values from the read data memory according to the second physical address of the second read command. In addition, the address decoding module also has a protocol conversion function and can process read commands of different protocols. For example, the first read command and the second read command respectively correspond to two different protocols, and the address decoding module may process the first read command and the second read command with different protocols, and may also perform communication protocol conversion on the read data. The read data return timing is determined by the first design timing parameter recorded by the timing parameter register.

The write command memory and the read command memory are responsible for storing read and write commands which are not processed by the first virtual memory controller.

The command controller is used for processing the read-write command on the first branch, and in fig. 6, the command controller is responsible for the read-write command scheduling, prefetching and the like of the command a so as to realize the access of the first branch with high bandwidth and low delay. The command controller comprises an address decoding module which can provide command physical address information for the write data storage module and the read data controller. The address decoding module also has a protocol conversion function and can process read commands of different protocols. For example, the command a and the command B are two different protocols, respectively, and the address decoding module may process the commands of the two different protocols.

The write data storage is responsible for storing write data of the first branch and physical address information corresponding to the write data. The write data of the first branch is the first write data sent by the virtual processor.

The write data comparator is used for comparing write data of the second branch with write data of the same physical address stored in the write data memory so as to verify the correctness of the write function of the second branch. The write data of the second branch is equivalent to the second write data sent by the second virtual memory controller in the foregoing embodiment.

Based on the chip test system of the embodiment, the speed of acquiring the read value from the second virtual memory and returning to the time sequence control module is faster than the speed of designing the actual chip computing system. Thus, the read value is buffered in the read data register of the timing control module and returned to the second virtual memory controller at an appropriate time. The problem of inaccurate test results caused by the fact that the clock frequency of the virtual processor is smaller than the design frequency when the virtual processor is designed because the virtual processor performs the frequency reduction processing and the second virtual memory does not perform the frequency reduction processing can be solved. The time sequence control module completes the matching of command addresses by comparing the physical addresses of the commands of the two branches, thereby ensuring the correctness of read data and the correctness of comparison logic of write data, and solving the problem that the sequences of the read commands and the write commands of the first branch and the second branch are inconsistent due to the instruction scheduling of the memory controller. In order to ensure that the maximum read latency of the first branch is smaller than the minimum read latency of the second branch, the DDR4 memory operates at a higher frequency, and a command scheduling module is added in the timing control module, and prefetch logic is used for scheduling the command sequence sent to the memory interface generator by the first branch according to the command information sent by the MC in the second branch.

Fig. 7 is a flowchart of specific steps of a method for testing a chip according to an embodiment of the present application. As shown in fig. 7, the method may include:

step S1, a chip test system is built in the simulator.

Wherein, the simulator is FPGA.

The method of this step is described in the foregoing step 201, and will not be described here again.

In step S2, the virtual processor sends a first read operation instruction to the read command memory, and sends a second read operation instruction to the second virtual memory controller.

Wherein the first read operation instruction includes a command a in fig. 6, and the second read operation instruction includes a read command B in fig. 6.

Specifically, the processor sends a first read operation instruction to the timing control module through the first branch, and sends a second read operation instruction to the second virtual memory controller through the second branch.

Referring to fig. 5 and 6, the first branch includes: virtual processor → timing control module → first virtual memory controller → virtual port physical layer → second virtual memory. The second branch includes: virtual processor→second virtual memory controller→timing control module.

The first branch is used for sending the actual read-write request to the second virtual memory in advance, taking the read data out of the second virtual memory and caching the read data, and storing the write data (write data A in fig. 6) into the time sequence control module for write data comparison. The maximum access delay of the first branch is smaller than the minimum access delay required by the second branch, so that the second branch access request can be timely responded.

It should be noted that, the second branch is a real access path of the computing system, the access request is processed by the timing control module, and after receiving the read command, the read time is determined according to the timing parameter, so as to send the data pre-fetched by the second branch to the second virtual memory controller. Write data is written into the second virtual memory and the write data memory of the time sequence control module through the first branch. The write data of the second branch is compared with the write data of the first branch stored in the time sequence control module in advance so as to judge the correctness of the write data. During this process the write data of the second branch is no longer written to the second virtual memory.

It should be noted that, referring to fig. 6, the instruction sent by the virtual processor to the timing control module through the first branch includes two signals, which are a command a and write data a, respectively. The instruction sent by the processor to the time sequence control module through the second branch circuit comprises two paths of signals, namely a command B and write data B. And when the read operation is performed, the data returned to the second virtual memory controller through the second branch is read data. That is, in fig. 6, data B is write data B or read value.

Specifically, in step S2, the processor sends a first read operation instruction to the timing control module, including: the virtual processor sends command a to a read command memory in the timing control module. In this step, the instruction issued by the processor is a read operation instruction, and the command a is a command for executing a read operation.

In step S3, the read command memory stores the first read operation command in response to the received first read operation command.

The first command in this step is command a shown in fig. 6.

In the substep S4, the read command controller obtains the first read operation command from the read command memory according to the second design timing parameter, and sends the first read operation command to the first virtual memory controller and the read command controller.

Illustratively, the first memory controller controls the first memory refresh in accordance with a refresh instruction sent by the processor and/or controls the first memory calibration in accordance with a calibration instruction sent by the processor.

After the first memory finishes refreshing, the first memory controller sends a refreshing completion instruction to the command controller, and after the first memory finishes calibrating, the first memory controller sends a calibrating instruction to the command controller.

The command controller responds to the received refresh completion command and/or calibration completion command, acquires a first command from the read command memory and sends the first command to the first virtual memory controller.

In step S5, the first virtual memory controller schedules the first read operation command and sends the first read operation command to the virtual port physical layer, and the virtual port physical layer reads data in the second virtual memory according to the first read operation command.

The method of this step is described in the foregoing step 202, and will not be described herein.

And S6, the virtual port physical layer converts the data in the analog signal format into the data in the digital format, and sends the data to a read data memory in the time sequence control module through the first virtual memory controller so as to store the read data memory.

The read data memory in this step corresponds to the first virtual memory in the foregoing embodiment.

Step S7, the read data controller reads the first design time sequence parameter from the time sequence parameter register, and controls the read data memory to send the stored read value to the second virtual memory controller according to the first design time sequence parameter.

The method of this step is described in the foregoing step 205, and will not be described here again.

Step S8, the second virtual memory controller sends the read value to the virtual processor, and the virtual processor determines whether the function of the virtual chip reaches the preset chip function design requirement according to the read value, and determines whether the performance of the virtual chip reaches the preset chip performance design requirement according to the moment of acquiring the read value.

In practice, the international standard (SPECint) provided by the standard performance assessment organization (Standard Performance Evaluation Corporation, SPEC) is one of the most common benchmark tests for CPU performance tests. However, the test method is complex, the simulation software is slow, and the quick iteration of the CPU test is difficult to realize. Memory controllers commonly used for chip streaming are often connected to the PHY through a DFI interface. The PHY commonly used for streaming typically comprises a digital part and an analog part, the analog part is not common on FPGAs, and the PHY lacks a DFI interface on FPGAs.

The chip test method provided by the embodiment solves the problem of inaccurate simulation precision caused by inconsistent clock frequency ratio of the storage medium and the processor when simulation is performed in the FPGA. The access address information is extracted and prefetched before the second virtual memory controller processes, so that the request sent to the PHY after the second virtual memory controller processes can be responded in time.

The chip test method provided by the embodiment solves the problem that the second virtual memory controller with the DFI interface cannot accelerate the simulation verification in the simulator FPGA because of the lack of the DFI interface PHY. And converting the PHY request of the DFI interface into a read-write request of the prefetch cache based on the physical MC through a protocol conversion request, so that the accurate simulation requirement of the second virtual memory controller is met under the condition that the time sequence DFI PHY is not met.

In the chip development process, the test of the chip comprises a memory access test, wherein the memory access test not only comprises a test of a read operation, but also comprises a test of a write operation. Further, the access test comprises an access function test and an access test, wherein the access function test is used for testing the accuracy of the access result. The access function test may include: read operation test, write operation test, sequential access test, boundary test, concurrent access test, timing adjustment test, and the like.

The access test needs to comprehensively consider various performances of access capability, for example, whether the response time of the access operation of the chip is less than or equal to a preset time threshold. The chip performance may be optimized based on test results of memory tests, including read operation tests, and/or write operation tests. When the test result does not meet the preset test requirement, the performance of the chip can be optimized by adjusting the type of the memory (such as the second virtual memory in the foregoing embodiment), optimizing the memory controller (such as the second virtual memory controller in the foregoing embodiment), optimizing the design bus, adjusting the cache policy, and the like. Furthermore, the chip performance parameters such as bandwidth, delay, period and the like can be reasonably balanced according to the characteristics and performance requirements of the application programs in the chip, so that the chip memory access efficiency is improved, and the system performance of the chip is optimized.

Through access test, the performance test results of the chip in various workloads and application programs can be obtained, wherein the performance test results comprise performance parameters such as calculation speed, throughput or response time. The computing power of different chips can be reasonably evaluated and compared through the performance test result of the memory test.

Fig. 8 is a flowchart of steps of another method for testing a chip according to an embodiment of the present application, and referring to fig. 8, the method may include the following steps:

and M1, constructing a chip test system in the simulator.

Wherein, the simulator is FPGA.

The method of this step is already described in the foregoing step S1, and will not be described here again.

The chip test system comprises a write data memory, a write data comparator,

And step M2, the virtual processor sends a first write operation instruction to the write data storage and sends a second write operation instruction to the second virtual memory controller.

Specifically, the processor sends a first write operation instruction to the timing control module through a first branch, and sends a second write operation instruction to the second memory controller through a second branch.

And step M3, the write data memory stores the data in the first write operation instruction to obtain first write data.

Wherein the write data memory corresponds to the third virtual memory in the foregoing embodiment.

And M4, the write data comparator reads the first design time sequence parameter from the time sequence parameter register, acquires and stores the write data in the first write operation instruction according to the first design time sequence parameter, and obtains second write data.

The method of this step is described in the foregoing step 2072, and will not be described here again.

And M5, comparing the first write data with the second write data by the write data comparator, determining whether the function of the virtual chip reaches the preset chip function design requirement according to the comparison result, and determining whether the performance of the virtual chip reaches the preset chip performance design requirement according to the moment of acquiring the second write data.

FIG. 9 is a schematic diagram of a chip test system according to an embodiment of the present application, and referring to FIG. 9, the system includes a virtual chip, a first virtual memory controller, a virtual port physical layer, and a first virtual memory, the virtual chip includes a virtual processor, a second virtual memory controller, and a second virtual memory;

the virtual processor is used for sending a first reading operation instruction to the first virtual memory controller;

the first virtual memory controller is used for scheduling a first read operation instruction and sending the first read operation instruction to the virtual port physical layer;

And the second virtual memory controller is used for responding to a second read operation instruction sent by the virtual processor, extracting a read value from the first virtual memory and determining whether the read operation of the virtual chip meets the preset test requirement according to the read value.

Referring now to fig. 10, which illustrates a chip testing apparatus provided in an embodiment of the present application, a chip testing apparatus 30 includes:

a building module 301, configured to build a chip test system in the simulator, where the chip test system includes a virtual chip, a first virtual memory controller, a virtual port physical layer, and a first virtual memory, and the virtual chip includes a virtual processor, a second virtual memory controller, and a second virtual memory;

a sending module 302, configured to send, by using the virtual processor, a first read operation instruction to the first virtual memory controller, schedule, by using the first virtual memory controller, the first operation instruction, and send the first operation instruction to the virtual port physical layer; the communication protocol between the virtual port physical layer and the second virtual memory controller is different;

a first reading module 303, configured to read data from the second virtual memory through the virtual port physical layer and perform signal conversion processing, so as to obtain a read value of the signal conversion processing and store the read value into the first virtual memory;

And the second read module 304 is configured to extract a read value from the first virtual memory in response to a second read operation instruction sent by the virtual processor to the second virtual memory controller, so as to determine whether the function of the virtual chip meets the preset chip function design requirement according to the read value.

Optionally, the clock frequency at which the virtual processor runs in the emulator is less than the design frequency at which the virtual processor is designed; the second reading module 304 may include:

the first acquisition sub-module is used for acquiring first design time sequence parameters of the second virtual memory controller when the second virtual memory controller is designed; the design time sequence parameters are used for determining the read-write time matched with the first design time sequence parameters when the read-write operation is executed subsequently, and acquiring read-write data at the read-write time;

the first fetching sub-module is used for responding to a second reading operation instruction sent to the second virtual memory controller by the virtual processor, and fetching a reading value from the first virtual memory according to the first design time sequence parameter.

Optionally, the chip testing apparatus 30 further includes:

the determining module is used for reading data from the second virtual memory through the virtual port physical layer, performing signal conversion processing to obtain a reading value of the signal conversion processing, storing the reading value into the first virtual memory, responding to a second reading operation instruction sent to the second virtual memory controller by the virtual processor, extracting the reading value from the first virtual memory according to the first design time sequence parameter, and determining whether the performance of the virtual chip meets the preset chip performance design requirement according to the reading time of the reading value.

Optionally, the chip test system further includes a third virtual memory and a virtual write data comparator, and the chip test apparatus 30 further includes:

the first writing module is used for responding to a first writing operation instruction sent by the virtual processor, writing data sent by the virtual processor into the third virtual memory, and obtaining first writing data;

the second writing module is used for responding to a second writing operation instruction of the second virtual memory controller, writing the data sent by the second virtual memory controller into the virtual writing data comparator, and obtaining second writing data;

the comparison module is used for obtaining the first write data through the virtual write data comparator, comparing the first write data with the second write data, and determining whether the function of the virtual chip meets the preset chip function design requirement according to the obtained comparison result.

Optionally, the clock frequency of the virtual processor in the emulator is less than the design frequency at which the virtual processor is designed; a second write module comprising:

the second acquisition sub-module is used for acquiring the first design time sequence parameter of the second virtual memory controller when the second virtual memory controller is designed; the first design time sequence parameter is used for determining the read-write time matched with the first design time sequence parameter when the read-write operation is executed subsequently, and acquiring read-write data at the read-write time;

And the third acquisition sub-module is used for responding to a second write operation instruction sent to the second virtual memory controller by the virtual processor, and writing the data sent by the second virtual memory controller into the virtual write data comparator according to the first design time sequence parameter to obtain second write data.

Optionally, the second writing module further includes:

a fourth obtaining sub-module, configured to obtain, after writing the data sent by the second virtual memory controller into the virtual write data comparator to obtain second write data, a write time of the second write data obtained by the virtual write data comparator;

the first determining submodule is used for determining whether the performance of the virtual chip meets the preset chip performance design requirement according to the writing time.

Optionally, the first read operation instruction includes a plurality of first sub-read operation instructions, each having a respective corresponding first physical address.

The first reading module 303 includes:

the first conversion sub-module is used for responding to the first sub-read operation instruction, reading data from the first physical address of the second virtual memory through the virtual port physical layer according to the first physical address corresponding to the first sub-read operation instruction, and performing signal conversion processing on the read data to obtain a plurality of read values. The read values and the first sub-read operation instructions are in one-to-one correspondence, and each read value has a first physical address corresponding to each read value.

Optionally, the second read operation instruction includes a plurality of second sub-read operation instructions, each having a respective second physical address; the second reading module 304 may further include:

the second determining submodule is used for determining a target first physical address which is the same as the second physical address from the first physical address corresponding to the read value according to the second physical address of the second sub-read operation instruction;

and the third determining submodule is used for determining the read value corresponding to the target first physical address as the read value corresponding to the second sub-read operation instruction.

And the second extraction submodule is used for extracting the reading value corresponding to the second sub-reading operation instruction from the first virtual memory.

Optionally, the second reading module 304 may include:

the second conversion module is used for carrying out protocol conversion on the read value according to the communication protocol of the second virtual memory controller to obtain a converted read value;

the first sending submodule is used for sending the converted read value to the virtual processor through the second virtual memory controller;

and the fourth determining submodule is used for determining whether the function of the virtual chip reaches the preset chip function design requirement according to the converted reading value through the virtual processor.

Optionally, the clock frequency of the second virtual memory is greater than the clock frequency of the second virtual memory controller, so that before the read value is extracted from the first virtual memory in response to the second read operation instruction sent to the second virtual memory controller by the virtual processor, the data is read from the second virtual memory through the virtual port physical layer and subjected to signal conversion processing to obtain a signal conversion processing read value, and the signal conversion processing read value is stored in the first virtual memory.

Optionally, the chip test system further includes a fourth virtual memory; the first reading module 303 may include:

a first storage sub-module for storing the first read operation instruction in the fourth virtual memory in response to the first read operation instruction issued by the virtual processor;

and the second sending submodule is used for sending the first reading operation instruction stored in the fourth virtual memory to the virtual port physical layer after receiving the instruction of the second virtual memory to finish the function guarantee operation through the first virtual memory controller so as to read data from the second virtual memory through the virtual port physical layer. And the function guarantee operation is used for enabling the second virtual memory to perform correct read-write operation.

Optionally, the first reading module 303 may include:

a second storage sub-module for storing the first read operation instruction in a fourth virtual memory in response to the first read operation instruction issued by the virtual processor;

a fifth obtaining sub-module, configured to obtain a second design timing parameter of the second virtual memory controller when the second virtual memory controller is designed; the second design time sequence parameter is used for determining the instruction sending time matched with the second design time sequence parameter when the read-write operation instruction is sent subsequently;

and the third sending submodule is used for sending the first reading operation instruction stored in the fourth virtual memory to the virtual port physical layer according to the second design time sequence parameter so as to read data from the second virtual memory through the virtual port physical layer.

In this embodiment of the present application, the testing process needs to be completed by the virtual processor and the second virtual memory controller together, so that only if the read operation performance of the virtual processor and the second virtual memory controller reach the preset test requirement, the finally obtained test result of the read operation can reach the preset test requirement. Based on the test result of the read operation obtained by the method of the embodiment, the read operation performance of the virtual processor and the second virtual memory controller can be reflected at the same time, and the problem that in the related art, the performance of the virtual memory controller cannot be tested because the virtual port physical layer with the same interface as the chip memory controller is lacking in the simulator, so that the communication protocol between the virtual port physical layer and the virtual memory controller in the virtual chip is different is solved.

Fig. 11 is a block diagram of an electronic device 400, according to an example embodiment. For example, electronic device 400 may be a mobile phone, computer, digital broadcast terminal, messaging device, game console, tablet device, medical device, exercise device, personal digital assistant, or the like.

Referring to fig. 11, an electronic device 400 may include one or more of the following components: a processing component 402, a memory 404, a power supply component 406, a multimedia component 408, an audio component 410, an input/output (I/O) interface 412, a sensor component 414, and a communication component 416.

The processing component 402 generally controls overall operation of the electronic device 400, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 402 may include one or more processors 420 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 402 can include one or more modules that facilitate interaction between the processing component 402 and other components. For example, the processing component 402 may include a multimedia module to facilitate interaction between the multimedia component 408 and the processing component 402.

Memory 404 is used to store various types of data to support operations at electronic device 400. Examples of such data include instructions for any application or method operating on electronic device 400, contact data, phonebook data, messages, pictures, multimedia, and so forth. The memory 404 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.

The power supply component 406 provides power to the various components of the electronic device 400. The power components 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 400.

The multimedia component 408 includes a screen between the electronic device 400 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may not only sense demarcations of touch or sliding actions, but also detect durations and pressures associated with touch or sliding operations. In some embodiments, the multimedia component 408 includes a front camera and/or a rear camera. When the electronic device 400 is in an operational mode, such as a photographing mode or a multimedia mode, the front-facing camera and/or the rear-facing camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

The audio component 410 is for outputting and/or inputting audio signals. For example, the audio component 410 includes a Microphone (MIC) for receiving external audio signals when the electronic device 400 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 404 or transmitted via the communication component 416. In some embodiments, audio component 410 further includes a speaker for outputting audio signals.

The I/O interface 412 provides an interface between the processing component 402 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc. These buttons may include, but are not limited to: homepage button, volume button, start button, and lock button.

The sensor assembly 414 includes one or more sensors for providing status assessment of various aspects of the electronic device 400. For example, the sensor assembly 414 may detect an on/off state of the electronic device 400, a relative positioning of the components, such as a display and keypad of the electronic device 400, the sensor assembly 414 may also detect a change in position of the electronic device 400 or a component of the electronic device 400, the presence or absence of a user's contact with the electronic device 400, an orientation or acceleration/deceleration of the electronic device 400, and a change in temperature of the electronic device 400. The sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects in the absence of any physical contact. The sensor assembly 414 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 414 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 416 is used to facilitate communication between the electronic device 400 and other devices, either wired or wireless. The electronic device 400 may access a wireless network based on a communication standard, such as WiFi, an operator network (e.g., 2G, 3G, 4G, or 5G), or a combination thereof. In one exemplary embodiment, the communication component 416 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component 416 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the electronic device 400 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements for implementing a chip testing method as provided by embodiments of the present application.

In an exemplary embodiment, a non-transitory computer-readable storage medium is also provided, such as memory 404, that includes instructions executable by processor 420 of electronic device 400 to perform the above-described method. For example, the non-transitory storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

Fig. 12 is a block diagram of an electronic device 500, according to an example embodiment. For example, electronic device 500 may be provided as a server. Referring to fig. 12, electronic device 500 includes a processing component 522 that further includes one or more processors and memory resources represented by memory 532 for storing instructions, such as applications, executable by processing component 522. The application programs stored in the memory 532 may include one or more modules each corresponding to a set of instructions. In addition, processing component 522 is configured to execute instructions to perform a chip testing method provided by embodiments of the present application.

The electronic device 500 may also include a power component 526 configured to perform power management of the electronic device 500, a wired or wireless network interface 550 configured to connect the electronic device 500 to a network, and an input output (I/O) interface 558. The electronic device 500 may operate based on an operating system stored in the memory 532, such as Windows Server, mac OS XTM, unixTM, linuxTM, freeBSDTM, or the like.

The embodiment of the application also provides a computer program product, which comprises a computer program, and a chip testing method realized when the computer program is executed by a processor.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

The foregoing description of the preferred embodiments of the present application is not intended to be limiting, but rather is intended to cover any and all modifications, equivalents, alternatives, and improvements within the spirit and principles of the present application.

The above detailed description of a chip testing method, device, electronic apparatus and readable storage medium provided in the present application applies specific examples to illustrate the principles and embodiments of the present application, where the above description of the embodiments is only used to help understand the method and core idea of the present application; meanwhile, as those skilled in the art will vary in the specific embodiments and application scope according to the ideas of the present application, the contents of the present specification should not be construed as limiting the present application in summary.

Claims

1. A method of testing a chip, comprising:

a chip test system is built in a simulator, wherein the chip test system comprises a virtual chip, a first virtual memory controller, a virtual port physical layer and a first virtual memory, and the virtual chip comprises a virtual processor, a second virtual memory controller and a second virtual memory;

sending, by the virtual processor, a first read operation instruction to the first virtual memory controller, and scheduling, by the first virtual memory controller, the first read operation instruction and sending the first read operation instruction to the virtual port physical layer; the communication protocol between the virtual port physical layer and the second virtual memory controller is different;

2. The method of claim 1, wherein a clock frequency at which the virtual processor is run in the emulator is less than a design frequency at which the virtual processor is designed;

the retrieving the read value from the first virtual memory in response to a second read operation instruction sent by the virtual processor to the second virtual memory controller includes:

acquiring a first design time sequence parameter of the second virtual memory controller when the second virtual memory controller is designed; the first design time sequence parameter is used for determining the read-write time matched with the first design time sequence parameter when the read-write operation is executed subsequently, and acquiring read-write data at the read-write time;

And responding to a second read operation instruction sent to the second virtual memory controller by the virtual processor, and extracting the read value from the first virtual memory according to the first design time sequence parameter.

3. The method of claim 2, further comprising, after reading data from the second virtual memory through the virtual port physical layer and performing signal conversion processing to obtain a read value of the signal conversion processing and storing the read value in the first virtual memory:

and responding to a second read operation instruction sent to the second virtual memory controller by the virtual processor, extracting the read value from the first virtual memory according to the first design time sequence parameter, and determining whether the performance of the virtual chip meets the preset chip performance design requirement according to the read moment of acquiring the read value.

4. The method of claim 1, wherein the chip test system further comprises a third virtual memory and a virtual write data comparator, and wherein after the chip test system is built in the emulator, further comprising:

responding to a first write operation instruction sent by the virtual processor, and writing data sent by the virtual processor into the third virtual memory to obtain first write data;

Responding to a second write operation instruction of the second virtual memory controller, and writing the data sent by the second virtual memory controller into the virtual write data comparator to obtain second write data;

and acquiring the first write data through the virtual write data comparator, comparing the first write data with the second write data, and determining whether the function of the virtual chip meets the preset chip function design requirement according to the obtained comparison result.

5. The method of claim 4, wherein a clock frequency of the virtual processor in the emulator is less than a design frequency at which the virtual processor is designed;

the responding to the second writing operation instruction sent to the second virtual memory controller by the virtual processor writes the data sent by the second virtual memory controller into the virtual writing data comparator to obtain second writing data, including:

And responding to a second write operation instruction sent to the second virtual memory controller by the virtual processor, and writing the data sent by the second virtual memory controller into the virtual write data comparator according to the first design time sequence parameter to obtain the second write data.

6. The method of claim 5, further comprising, after writing the data sent by the second virtual memory controller to the virtual write data comparator to obtain the second write data:

the virtual write data comparator is acquired to obtain the write-in time of the second write data;

and determining whether the performance of the virtual chip meets the preset chip performance design requirement according to the writing time.

7. The method of claim 1, wherein the first read operation instruction comprises a plurality of first sub-read operation instructions, each having a respective corresponding first physical address;

the reading data from the second virtual memory and performing signal conversion processing through the virtual port physical layer includes:

responding to the first sub-read operation instruction, reading data from the first physical address of the second virtual memory through the virtual port physical layer according to the first physical address corresponding to the first sub-read operation instruction, and performing signal conversion processing on the read data to obtain a plurality of read values;

The read values and the first sub-read operation instructions are in one-to-one correspondence, and each read value is provided with the corresponding first physical address.

8. The method of claim 7, wherein the second read operation instruction comprises a plurality of second sub-read operation instructions, each having a respective second physical address;

determining a target first physical address identical to the second physical address from the first physical address corresponding to the read value according to the second physical address of the second sub-read operation instruction;

determining a read value corresponding to the target first physical address as a read value corresponding to the second sub-read operation instruction;

and extracting a read value corresponding to the second sub-read operation instruction from the first virtual memory.

9. The method of claim 1, wherein in response to a second read operation instruction sent by the virtual processor to the second virtual memory controller, extracting the read value from the first virtual memory to determine whether a read operation of the virtual chip meets a preset test requirement based on the read value, comprises:

According to the communication protocol of the second virtual memory controller, carrying out protocol conversion on the read value to obtain a converted read value;

transmitting the converted read value to the virtual processor through the second virtual memory controller;

and determining whether the function of the virtual chip reaches the preset chip function design requirement or not according to the converted reading value through the virtual processor.

10. The method of claim 1 wherein the clock frequency of the second virtual memory is greater than the clock frequency of the second virtual memory controller to read data from the second virtual memory through the virtual port physical layer and perform signal conversion processing to obtain signal conversion processing read values and store the signal conversion processing read values in the first virtual memory before the read values are extracted from the first virtual memory in response to a second read operation instruction sent by the virtual processor to the second virtual memory controller.

11. The method of claim 1, wherein the chip test system further comprises a fourth virtual memory; the responding to the first read operation instruction sent by the virtual processor, reading data from the second virtual memory through the virtual port physical layer, comprising:

Storing a first read operation instruction in the fourth virtual memory in response to the first read operation instruction issued by the virtual processor;

after receiving an instruction of the second virtual memory to complete a function guarantee operation through the first virtual memory controller, sending the first read operation instruction stored in the fourth virtual memory to the virtual port physical layer to read data from the second virtual memory through the virtual port physical layer;

the function guarantee operation is used for enabling the second virtual memory to perform correct read-write operation.

12. The method of claim 1, wherein the chip test system further comprises a fourth virtual memory; the responding to the first read operation instruction sent by the virtual processor, reading data from the second virtual memory through the virtual port physical layer, comprising:

acquiring a second design time sequence parameter of the second virtual memory controller when the second virtual memory controller is designed; the second design time sequence parameter is used for determining the instruction sending time matched with the second design time sequence parameter when the read-write operation instruction is sent subsequently;

And sending the first read operation instruction stored in the fourth virtual memory to the virtual port physical layer according to the second design timing parameter so as to read data from the second virtual memory through the virtual port physical layer.

13. A chip testing system, comprising: the virtual memory system comprises a virtual chip, a first virtual memory controller, a virtual port physical layer and a first virtual memory, wherein the virtual chip comprises a virtual processor, a second virtual memory controller and a second virtual memory;

14. A chip testing apparatus, comprising:

15. An electronic device, comprising: a processor;

a memory for storing the processor-executable instructions;

wherein the processor is configured to execute the instructions to implement the method of any one of claims 1 to 12.

16. A computer readable storage medium, characterized in that instructions in the computer readable storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the method of any one of claims 1 to 12.