CN117707994A

CN117707994A - Request buffer, system, component, device and transmission method

Info

Publication number: CN117707994A
Application number: CN202410147573.0A
Authority: CN
Inventors: 武杨
Original assignee: Beijing Xiangdixian Computing Technology Co Ltd
Current assignee: Beijing Xiangdixian Computing Technology Co Ltd
Priority date: 2024-02-02
Filing date: 2024-02-02
Publication date: 2024-03-15

Abstract

The present disclosure provides a request buffer, system, component, apparatus, and transmission method. The request buffer comprises a first buffer module and a control module; the first cache module comprises a plurality of first cache units; the control module is configured to write the access request into the corresponding position in the corresponding first cache unit according to the access address and the request identifier in the access request when receiving the access request of the main equipment, wherein two access requests with adjacent writing positions in the first cache unit have the same request identifier and continuous access addresses; when the ready state of a first cache unit in the first cache module is valid, all access requests in the first cache unit are sent to the memory controller according to the writing position sequence in the first cache unit, and the first cache unit is switched to an idle state. The operation that the memory frequently closes the old page and opens the new page is reduced, so that the memory access performance is improved.

Description

Request buffer, system, component, device and transmission method

Technical Field

The disclosure relates to the technical field of access request processing, and in particular relates to a request buffer, a system, a component, equipment and a transmission method.

Background

Taking a general purpose computer as an example, the memory is physically comprised of a plurality of memory chip particles. And forming a 64-bit wide rank by a plurality of memory particles, and performing data read-write operation on a memory bus according to the data width. Each memory granule contains multiple banks, each bank resembling a two-dimensional data table, with data located by row and column addresses. When accessing, a row is opened through a row address, and then target data is selected from the row through a column address. Each bank can only open one line of data at a time, also known as opening one page.

In practical computer systems, a multi-Master (Master) system is a common scenario. In such a system, access requests may be mixed up due to multiple masters performing access operations simultaneously. Even though the access requests are address ordered when issued from each Master, the access requests of multiple masters arrive at the memory side in an out-of-order, promiscuous ordering, and the access order becomes random and no longer proceeds in the original order. Memory randomization in a multi-Master system results in frequent memory closing and opening of old and new pages, which incur significant additional performance costs, resulting in reduced memory performance.

Disclosure of Invention

The purpose of the present disclosure is to provide a request buffer, a system, a component, a device and a transmission method, which solve the technical problem that access performance is reduced due to access randomization of a multi-Master system in the prior art.

According to one aspect of the present disclosure, there is provided a request buffer connecting a memory controller and at least one host device, including a first cache module and a control module; the first cache module comprises a plurality of first cache units;

the control module is configured to write the access request into the corresponding position in the corresponding first cache unit according to the access address and the request identifier in the access request when receiving the access request of the main equipment, wherein two access requests with adjacent writing positions in the first cache unit have the same request identifier and continuous access addresses; the request identifier at least comprises a main equipment identifier;

when the ready state of a first cache unit in the first cache module is valid, all access requests in the first cache unit are sent to the memory controller according to the writing position sequence in the first cache unit, and the first cache unit is switched to an idle state.

In some embodiments, the request buffer further includes a first counter corresponding to each first cache unit, configured to record a number of access requests written in the corresponding first cache unit; each first cache unit caches N access requests at most;

the control module is further configured to set the ready state of the first cache unit to be valid when the number of the first counter records corresponding to the first cache unit reaches N.

In some embodiments, the request buffer further includes a second counter corresponding to each first buffer unit, configured to record a time when the corresponding first buffer unit maintains a non-idle state;

the control module is further configured to set the ready state of the first buffer unit to be valid when the time recorded by the second counter corresponding to the first buffer unit reaches a preset time.

In some embodiments, in the request buffer, a minimum access granularity of the access request is P bytes, each first cache unit caches N access requests at most, and an access address of the access request includes bits from 0 th to (D-1) th from low to high;

when the address of the access request includes an address bit corresponding to the minimum access granularity, the first address of the access request is identified as the (log ₂ P+ log ₂ N) bits to (D-1) th bit, the second addressing identifying the log th address of the memory address of the access request ₂ P bits to (log) ₂ P+ log ₂ N-1) information indicated by bits;

when the address of the access request does not include the address bit corresponding to the minimum access granularity, the first address of the access request is identified as the log th address of the access request ₂ Information indicated by N bits to (D-1) th bit, the second addressing is identified as 0 th bit to (log) of the address of the access request ₂ N-1) ratio ofInformation of bit indication;

the request identifier further comprises a corresponding first addressing identifier;

the control module is configured to write the access request into the corresponding position in the corresponding first cache unit according to the access address and the request identifier in the access request when the access request of the main device is received, and comprises the following steps:

the control module is configured to determine a corresponding first addressing identifier and a corresponding second addressing identifier according to an access address in the access request when receiving the access request of the main equipment, judge whether the access request with the same request identifier as the access request exists in the first cache module, if so, write the access request into a first cache unit where the access request with the same request identifier as the access request exists in the first cache module, wherein the writing position is a position indicated by the second addressing identifier of the access request;

Otherwise, the access request is written into a first cache unit in an idle state.

In some embodiments, in the above request buffer, the control module is configured to write the access request into a first cache unit in an idle state, and includes:

a control module configured to:

when a first buffer unit in an idle state exists in the first buffer module currently, writing the access request into the first buffer unit in the idle state;

when a first buffer unit in an idle state does not exist in the first buffer module currently but a first buffer unit in a ready state is valid, writing the access request into the first buffer unit after the first buffer unit is switched to the idle state;

when the first cache unit in the idle state does not exist in the first cache module currently and the first cache unit in which the ready state is valid does not exist, the ready state of the first cache unit which is in the first cache module and maintains the non-idle state for the longest time is switched to be valid, and after the first cache unit is switched to the idle state, the access request is written into the first cache unit in which the idle state is restored.

In some embodiments, in the request buffer, an information field of a first cache unit in a non-idle state includes a request identifier of an access request cached in the first cache unit;

The control module is configured to determine a corresponding first addressing identifier and a second addressing identifier according to an access address in the access request when receiving the access request of the master device, and determine whether the access request with the same request identifier as the access request exists in the first cache module, if yes, the access request is written into a first cache unit where the access request with the same request identifier as the access request exists in the first cache module, and the control module comprises:

the control module is further configured to determine a corresponding first addressing identifier and a corresponding second addressing identifier according to an access address in the access request when the access request of the master device is received, determine whether a first cache unit with the same request identifier as the request identifier of the access request in an information domain exists in the first cache module, and if so, write the access request into the first cache unit.

In some embodiments, in the request buffer, the first buffer module includes a read request buffer area and a write request buffer area, which are respectively used for buffering the read access request and the write access request, and the write request buffer area and the read request buffer area respectively include a plurality of first buffer units.

In some embodiments, in the request buffer, the request identifier further includes an access type.

In some embodiments, the request buffer further includes: a second cache module;

the control module is configured to write the write data corresponding to the write access request into the corresponding position in the second cache module and record corresponding data writing position information when receiving the write access request of the master device and the write data corresponding to the write access request, and write the write access request and the corresponding data writing position information into the corresponding position in the corresponding first cache unit according to the memory address and the request identifier in the write access request;

the control module is further configured to, when sending a write access request in a first cache unit to the memory controller, read write data corresponding to the write access request from the second cache module according to the data write-in position information corresponding to the write access request cached in the first cache unit, and send the write data to the memory controller.

In some embodiments, in the above request buffer, the control module is further configured to, when writing write data corresponding to a write access request into a corresponding location in the second cache module, return corresponding response information to the master device that issued the write access request.

In some embodiments, in the request buffer, the control module is further configured to, when receiving a read access request of the host device, determine whether a write access request with a matched access address exists in the first cache module according to an access address of the read access request, if so, read corresponding write data from the second cache module according to data write location information corresponding to the write access request with the matched access address in the first cache module, send the write data to the host device that sends the read access request, and return corresponding response information to the host device.

In some embodiments, in the request buffer, the first buffer module includes at least one first buffer area, where the at least one first buffer area is used to buffer access requests sent by different host devices, and each first buffer area includes a plurality of first buffer units.

In some embodiments, the request buffer further includes: the output buffer module is connected with the output end of the control module;

the control module is configured to send all access requests in a first cache unit to the memory controller according to the sequence of writing positions in the first cache unit when the ready state of the first cache unit in the first cache module is valid, and comprises the following steps:

The control module is configured to send all access requests in a first cache unit to the output buffer module for caching according to the sequence of the writing positions in the first cache unit when the ready state of the first cache unit in the first cache module is valid; the output buffer module is a first-in first-out buffer module.

In some embodiments, the request buffer further includes: the input buffer module is connected with the input end of the control module;

an input buffer module configured to:

caching an access request sent by the main equipment;

and sending the access requests cached in the input buffer module to the control module one by one.

In some embodiments, in the request buffer, the information field of the first cache unit includes a status bit, and the status bit includes a ready status bit and an idle status bit.

According to another aspect of the present disclosure, a system on a chip is provided, including a master device, a memory controller, a memory to be accessed, and a request buffer of any of the above embodiments.

According to another aspect of the present disclosure, there is provided an electronic assembly comprising the system-on-chip of any of the above embodiments.

According to another aspect of the present disclosure, there is provided an electronic device comprising the electronic assembly of any of the above embodiments.

According to another aspect of the present disclosure, there is provided a request transmission method including:

when an access request of a main device is received, writing the access request into a corresponding position in a corresponding first cache unit in a first cache module according to an access address and a request identifier in the access request, wherein two access requests with adjacent writing positions in the first cache unit have the same request identifier and continuous access addresses; the request identifier at least comprises a main equipment identifier;

Drawings

FIG. 1 is a schematic diagram of a connection structure of a request buffer according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of another connection structure of a request buffer according to one embodiment of the present disclosure;

fig. 3 is a flowchart of a request transmission method according to an embodiment of the disclosure.

Detailed Description

Before describing embodiments of the present disclosure, it should be noted that:

Some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.

The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.

The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.

It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

The invention aims to provide a request buffer, a system, a component, equipment and a transmission method, wherein the request buffer is connected with a memory controller and at least one main equipment and comprises a first cache module and a control module; the first cache module comprises a plurality of first cache units; the control module is configured to write the access request into the corresponding position in the corresponding first cache unit according to the access address and the request identifier in the access request when receiving the access request of the main equipment, wherein two access requests with adjacent writing positions in the first cache unit have the same request identifier and continuous access addresses; the request identifier at least comprises a main equipment identifier; when the ready state of a first cache unit in the first cache module is valid, all access requests in the first cache unit are sent to the memory controller according to the writing position sequence in the first cache unit, and the first cache unit is switched to an idle state.

In the reordering scheme, in the first cache module, the access requests sent by each main device are reordered according to the memory addresses, so that the original request sequence (the sequence when the main device is sent) can be restored to a great extent, and when the requests are sent to the memory controller, the sequential access can be realized to a certain extent, and the operations of frequently closing old pages and opening new pages of the memory are reduced, so that the memory access performance is improved.

One embodiment of the present disclosure provides a request buffer, as shown in fig. 1, connecting a memory controller and at least one master device, where the request buffer includes a first cache module and a control module; the first cache module comprises a plurality of first cache units; the control module is configured to write the access request into the corresponding position in the corresponding first cache unit according to the access address and the request identifier in the access request when receiving the access request of the main equipment, wherein two access requests with adjacent writing positions in the first cache unit have the same request identifier and continuous access addresses; the request identifier at least comprises a main equipment identifier; when the ready state of a first cache unit in the first cache module is valid, all access requests in the first cache unit are sent to the memory controller according to the writing position sequence in the first cache unit, and the first cache unit is switched to an idle state.

Wherein, two adjacent access requests in the first cache unit have the same request identifier and consecutive access addresses, which also indicates that the access requests written into the same first cache unit have the same request identifier and consecutive access addresses, and the arrangement sequence (writing position sequence) of each access request in the same first cache unit is also the access address sequence of each access request.

The first cache unit may be understood as an entry or table entry (entry) of the first cache module. Each cache unit (entry) includes an information field for caching written data (e.g., the above access request) and a data field for recording index information associated with the data field.

The information field may include a status bit, including a ready status bit and an idle status bit, where the ready status bit indicates that an access request in a corresponding first cache unit may be read or output when the ready status bit is valid, and indicates that the corresponding first cache unit is in an idle state (i.e., an empty state), i.e., where the number of access requests cached is 0, and indicates that the corresponding first cache unit is in a non-idle state (i.e., a non-empty state), i.e., where the number of access requests cached is greater than or equal to 1, when the idle status bit is invalid. In some embodiments, the control module is configured to, when writing an access request to a first cache location in an idle state, invalidate (i.e., switch from idle to non-idle) an idle state bit of the first cache location.

In some embodiments, the ready state of the first cache unit being valid means that the current first cache unit satisfies at least one of:

a) The current first cache unit is in a full state;

b) The first buffer unit maintains the non-idle state for a preset time at present;

c) When an access request received by the control module needs to be written into a first buffer unit in an idle state and the first buffer module does not currently have the first buffer unit in the idle state, the current first buffer unit is the first buffer unit with the longest time for maintaining the non-idle state in the first buffer module.

The above case a) may be understood as meaning that when a first cache unit is full, it indicates that the first cache unit cannot continue to write new access requests, and in this case, in order to avoid data being covered or overflowed, the access requests in the first cache unit need to be sent to the memory controller to perform the access operation.

The above case b) may be understood as that when a first cache unit has been maintained in a non-idle state for a preset time, which indicates that a set of access requests (access requests in the first cache unit) that are consecutive to the address are issued by a master device corresponding to the first cache unit for a certain time, other access requests associated with the address will not be rewritten in the first cache unit in a short time, and at this time, in order to avoid causing resource occupation and latency, the access requests in the first cache unit need to be sent to a memory controller to perform a memory access operation.

The above case c) may be understood that, when the access request received by the control module needs to be written into a first buffer unit in an idle state and the first buffer module does not currently have the first buffer unit in the idle state, if the access request is not written into the first buffer module at this time, it is likely to cause input blocking, so that it is required to select a first buffer unit from the first buffer modules, send the access request therein to the memory controller to execute the access operation, and put the first buffer unit in a space (i.e. put in the idle state) in time so as to be convenient for writing the access request. In the process of selecting a first cache unit from the first cache module, the following principle is adopted: the first cache unit in the first cache module that maintains the non-idle state for the longest time is selected, and for reasons, reference is made to the above case b), and details thereof are not repeated here.

In some embodiments, corresponding to the case a) above, the request buffer further comprises a first counter corresponding to each first cache unit, configured to record the number of access requests written in the corresponding first cache unit; each first cache unit caches N access requests at most;

Specifically, when the first buffer unit is switched to the idle state, a first counter corresponding to the first buffer unit is reset to an initial value, the first counter has two timing modes, and the first is: the initial value of the first counter is 0, and each time an access request is written into the first cache unit, the count value of the first counter is increased by 1, and when the count value reaches N, the control module sets the ready state of the corresponding first cache unit to be effective; the second is: the initial value of the first counter is N, each time an access request is written into the first cache unit, the count value of the first counter is reduced by 1, and when the count value reaches 0, the control module sets the ready state of the corresponding first cache unit to be effective.

In some embodiments, corresponding to the above case b), the request buffer further includes a second counter corresponding to each first cache unit, configured to record a time when the corresponding first cache unit maintains a non-idle state;

Specifically, when the control module writes an access request into a first buffer unit in an idle state, and the idle state bit of the first buffer unit is set to be invalid (i.e. the idle state is switched to a non-idle state), the second counter starts to count time. The second counter has two timing modes, the first is: the initial value of the second counter is 0, and every time a clock period is passed, the count value of the second counter is increased by 1, and when the count value reaches the preset clock period number (the preset time is divided by the single period time), the control module sets the ready state of the corresponding first buffer unit to be valid; the second is: the initial value of the second counter is the preset clock cycle number, the count value of the second counter is reduced by 1 every one clock cycle, and when the count value reaches 0, the control module sets the ready state of the corresponding first buffer unit to be valid.

The setting of the preset time needs to consider the delay tolerance of different types of chips or applications. For example, the graphics processor (Graphics Processing Unit, GPU) is a less delay sensitive device, a heavy bandwidth and a light delay, so a larger preset time can be set. The setting of the preset time for delay sensitive devices may be limited and a smaller preset time may be required.

In some embodiments, the minimum access granularity of the access requests is P bytes, each first cache unit caches at most N access requests, the access address of the access request including bits 0 to (D-1) from low to high;

when the address of the access request does not include the address bit corresponding to the minimum access granularity, the first address of the access request is identified as the log th address of the access request ₂ Information indicated by N bits to (D-1) th bit, the second addressing is identified as 0 th bit to (log) of the address of the access request ₂ N-1) information indicated by bits;

The minimum access granularity of the access request is P bytes, which means that the access bit width of the access request is an integer multiple of P bytes.

It can be understood that, since the minimum memory granularity of the access request is P bytes, when the memory address of the access request includes the address bit corresponding to the minimum memory granularity, if the memory address of the access request is to represent the address information in the minimum memory granularity, log is needed ₂ P bits (i.e. the lowest 0 th bit to (log) ₂ P-1) bits, co-log ₂ P bits), then log th of memory address of consecutive access requests ₂ The information indicated by the P bits and above is continuous, for example, the address of the 1 st access request (i.e. request 0) from a master is 16' b0000_0000_0000_0000 (the starting address is 0 th byte), if log ₂ P is 6, the address of the 2 nd access request (i.e., request 1) is 16' b0000_0000_0100_0000 (the starting address is 64 th byte), the address of the 3 rd access request (i.e., request 2) is 16' b0000_0000_1000_0000 (the starting address is 128 th byte), … …, the address of the 7 th access request (i.e., request 6) is 16' b0000_0001_1000_0000 (the starting address is 384 th byte), the address of the 8 th access request (i.e., request 7) is 16' b0000_0001_1100_0000 (the starting address is 448 th byte), and the 9 th access request is 16' b0000_0001_1100_0000 (the starting address is 448 th byte)The address of (i.e., request 8) is 16'b0000_0010_0000_0000 (the start address is the 512 th byte), and the address of (i.e., request 9) of the 10 th access request is 16' b0000_0010_0100_0000 (the start address is the 576 th byte).

Log of address of 1 st access request (i.e., request 0) ₂ The information indicated by the P bits (i.e. the 6 th bit) and more is 10' b00_0000_0000, the log th address of the 2 nd access request (i.e. request 1) ₂ The information indicated by the P bits (i.e. the 6 th bit) and above is 10' b00_0000_0001, the log of the address of the 3 rd access request (i.e. request 2) ₂ Information indicated by the P bits (i.e., the 6 th bit) and more is 10' b00_0000_0010, … …, the log of the address of the 7 th access request (i.e., request 6) ₂ The information indicated by the P bits (i.e. the 6 th bit) and more is 10' b00_0000_0110, the log of the address of the 8 th access request (i.e. request 7) ₂ The information indicated by the P bits (i.e. the 6 th bit) and more is 10' b00_0000_0111, the 9 th access request (i.e. request 8) is the log th access address ₂ The information indicated by the P bits (i.e. the 6 th bit) and above is 10' b00_0000_1000, the log of the address of the 10 th access request (i.e. request 9) ₂ The information indicated by the P bits (i.e., the 6 th bit) and more bits is 10' b00_0000_1001. I.e., log th of the 10 consecutive access requests (request 0 through request 9) ₂ The information indicated by the P bits (i.e., the 6 th bit) and more is continuous.

When each first cache unit caches at most N access requests (i.e., request 0 through request N-1), the write location information indicating the access requests in each first cache unit may be log ₂ N bits represent the log th address of the memory of the successive access requests ₂ The information indicated by the P bits and above is continuous, then the log th of the address of the access request is passed ₂ P bits to%log ₂ P+ log ₂ N-1) bits of information indicating the write location of the access request in the corresponding one of the first cache locations. It can be understood that the first cache location has the 0 th to (N-1) th write locations (N write locations in total), the log of the address of the access request ₂ P bits to (log) ₂ P+ log ₂ N-1) the number corresponding to the bit corresponds to the sequence number of the writing location (sequence number starting from 0). Therefore, the log th of the memory address of the access request can be used ₂ P bits to (log) ₂ P+ log ₂ N-1) bits of information corresponding to the bits are used as an addressing identifier (second addressing identifier) of the access request in the corresponding first cache unit, and according to the second addressing identifier, the writing position (entry index) of the access request in the corresponding first cache unit can be known.

For example, when log ₂ When N is 3, i.e., when each first cache unit caches 8 access requests at most, it is indicated that the 1 st to 8 th access requests (i.e., request 0 to request 7) can be cached in one first cache unit, and correspondingly, the 1 st access request (i.e., request 0) has the log of the access address ₂ P bits to (log) ₂ P+ log ₂ N-1) bits (i.e., 6 th bit to 8 th bit) indicate 3' b000 (i.e., 0 th write location) for the information, log of the address of the 2 nd access request (i.e., request 1) ₂ P bits to (log) ₂ P+ log ₂ N-1) bit (i.e., 6 th bit to 8 th bit) indicates 3' b001 (i.e., 1 st write location) of information, log of 3 rd access request (i.e., request 2) ₂ P bits to (log) ₂ P+ log ₂ N-1) bit (i.e., 6 th bit to 8 th bit) indicates 3' b010 (i.e., 2 nd write location) of information, … …, log 7 th access request (i.e., request 6) ₂ P bits to (log) ₂ P+ log ₂ N-1) bits (i.e., 6 th bit to 8 th bit) indicate 3' b110 (i.e., write location is 6 th write location), log of address of 8 th access request (i.e., request 7) ₂ P bits to (log) ₂ P+ log ₂ N-1) bits (i.e., 6 th bit to 8 th bit) indicate 3' b111 (i.e., the writing position is 7 th writing position).

Among the multiple consecutive access requests from the same master, there may be access requests with the same second address identifier, for example, the second address identifier of the 9 th access request (i.e. request 8) is 3'b000, which is the same as the second address identifier of the 1 st access request (i.e. request 0), and the second address identifier of the 10 th access request (i.e. request 9) is 3' b001, which is the same as the second address identifier of the 2 nd access request (i.e. request 1). But in a plurality of access requests with consecutive access addresses issued by the same master, the second address identifies that the same access request has a different higher address, i.e. (log ₂ P+ log ₂ N) bits and the above indicated information are different, e.g. log of address of the 1 st access request (i.e. request 0) ₂ P+ log ₂ N) bits to (D-1) th bit (i.e., 9 th bit to 15 th bit) indicate that the information is 7' b000_0000, the 9 th access request (i.e., request 8) is the (log) th address ₂ P+ log ₂ N) bits to (D-1) th bit (i.e., 9 th bit to 15 th bit) are 7' b000_0001, the (log) th address of the 2 nd access request (i.e., request 1) ₂ P+ log ₂ N) bits to (D-1) th bit (i.e., 9 th bit to 15 th bit) indicate that the information is 7' b000_0000, the 10 th access request (i.e., request 9) is the (log) th address ₂ P+ log ₂ N) bits to (D-1) th bit (i.e., 9 th bit to 15 th bit) indicate that the information is 7' b000_0001, so the (log) th of the address of the access request ₂ P+ log ₂ N) bits to (D-1) th bit as a first seekThe address identifier, together with the main device identifier, is used as a request identifier to determine the first cache unit corresponding to the access request.

However, in some existing protocols, the address bits corresponding to the minimum memory granularity are not required to be transmitted, i.e., the memory address of the access request received by the control module does not include the address bits corresponding to the minimum memory granularity, in which case the first address identifier of the access request is the log th address of the memory address of the access request ₂ Information indicated by N bits to (D-1) th bit, the second addressing is identified as 0 th bit to (log) of the address of the access request ₂ N-1) information indicated by bits.

In some embodiments, the control module may determine whether the first cache module has an access request with the same request identifier as the access request by polling each access request currently cached in the first cache module. Preferably, since access requests written into the same first cache location have the same request identification, only one access request in each first cache location in a non-idle state may be interrogated during polling to reduce the delay required to address (determine the first cache location written to) in the first cache module.

In some embodiments, to further reduce the latency required to address (determine the first cache location to write) in the first cache module, the information field of a first cache location in a non-idle state includes a request identification of the access request cached in the first cache location;

It will be understood that, since the access requests written into the same first cache unit have the same request identifier, when the first access request is written into the first cache unit, the request identifier of the access request may be written into the information field of the first cache unit, and then when it is determined whether there is an access request in the first cache module, the access request in the first cache module may not be polled, but only the information field of the cache unit in a non-idle state may be polled.

In some embodiments, the control module configured to write the access request into a first cache location in an idle state includes:

a control module configured to:

Specifically, when the access request received by the control module needs to be written into a first buffer unit in an idle state (i.e. there is no access request with the same request identifier as the access request in the first buffer module), the control module will first determine whether there is a first buffer unit in the idle state currently in the first buffer module, where the determination mode is to poll idle state bits in the information domain of each first buffer unit, and when the first buffer unit with the valid idle state bit is queried, the polling operation may be stopped, and the access request to be written is written into the corresponding position of the first buffer unit according to the information indicated by the second addressing identifier. While the direction of polling the idle state bits in the information fields of the respective first buffer units may be in order from the beginning to the end (from the low position to the high position), for example, in the configuration shown in fig. 1, the idle state bits in the information fields of the respective first buffer units may be polled in order from the 1 st first buffer unit (Entry 0) to the M-th first buffer unit (Entry M-1).

After all the first buffer units are polled, the control module will determine whether there is a first buffer unit with a ready state being valid at this time, if so, it indicates that the first buffer unit with an idle state will appear in the first buffer module immediately, and no excessive processing is needed at this time, after the first buffer unit is switched to an idle state, the access request is written into the first buffer unit with an idle state being restored, otherwise, the ready state of the first buffer unit with a longest time for maintaining the non-idle state in the current first buffer module is required to be switched to be valid, and after the first buffer unit is switched to an idle state, the access request is written into the first buffer unit with an idle state being restored.

In some embodiments, as shown in fig. 2, the first buffer module includes a read request buffer and a write request buffer for buffering read access requests and write access requests, respectively, and the write request buffer and the read request buffer include a plurality of first buffer units, respectively.

That is, in order to achieve separate management of read access requests and write access requests, a read request buffer and a write request buffer are divided in a first buffer module. Correspondingly, the control module is configured to, when receiving an access request of the master device, write the access request into a corresponding position in a corresponding first cache unit according to an access address and a request identifier in the access request, and includes:

The control module is configured to write the read access request into the corresponding position in the corresponding first cache unit in the read request cache region according to the memory address and the request identifier in the read access request when receiving the read access request of the master device;

when receiving a write access request of a master device, writing the write access request into a corresponding position in a corresponding first cache unit in a write request cache region according to an access address and a request identifier in the write access request.

It is understood that when the control module receives a read access request from the host device, only addressing operations are performed in the read request cache region, and when the control module receives a write access request from the host device, only addressing operations are performed in the write request cache region.

In other embodiments, separate management of read access requests and write access requests may be achieved without dividing the read request cache and the write request cache, but by adding an access type to the request identifier, i.e., the request identifier also includes an access type. That is, access requests written into the same first cache location have the same master identification, access type, and consecutive memory addresses.

In some embodiments, in a scenario where the first buffer module may buffer the write access request, the request buffer further includes: a second cache module;

That is, in the scenario that the first buffer module may buffer the write access request, the second buffer module may also buffer write data corresponding to the write access request, where when the write access request is sent to the memory controller according to the write location sequence, the memory controller may synchronously receive the corresponding write data, so that the memory controller may conveniently perform the corresponding write access operation.

In some embodiments, the control module is further configured to, when writing the write data corresponding to a write access request into the corresponding location in the second cache module, return corresponding response information to the master device that issues the write access request, so as to implement early response, and improve write access efficiency.

In some embodiments, the control module is further configured to, when receiving a read access request of the host device, determine whether a write access request with a matched access address exists in the first cache module according to the access address of the read access request, if so, read corresponding write data from the second cache module according to data write location information corresponding to the write access request with the matched access address in the first cache module, send the write data to the host device sending the read access request, and return corresponding response information to the host device.

The matching of the address of a read access request with the address of a write access request in the first cache module means that the data that the read access request wants to read from the memory is the data that the write access request wants to write into the memory, i.e. hit. Specifically, according to the access address of the read access request, a specific manner of judging whether the first cache module has the write access request with the matched access address may be: and judging whether the access address of the read access request is the same as the access address of any write access request in the first cache module, if so, determining that the write access request with the matched access address exists in the first cache module.

The specific way of judging whether the write access request with the matched access address exists in the first cache module according to the access address of the read access request under the conditions that the request identifier of the combined access request comprises a main device identifier and a first seek identifier, the second addressing identifier of the access request indicates the write position (entry index) of the access request in the corresponding first cache unit, and the information field of the first cache unit in a non-idle state comprises the request identifier of the access request cached in the first cache unit can be as follows: judging whether a first cache unit with the same first seek identifier as the first seek identifier of the read access request in an information domain exists in a first cache module according to the first seek identifier of the read access request, if so, further determining whether a corresponding write access request exists at a write-in position indicated by a second addressing identifier of the read access request in the first cache unit, and if so, determining that the write access request with the matched access address exists in the first cache module.

In the scenario that the first cache module includes a read request cache area and a write request cache area, according to an access address of the read access request, a specific manner of judging whether the first cache module has the write access request with the matched access address may be: judging whether a first cache unit with the same first seek identifier as the first seek identifier of the read access request in an information domain exists in a write request cache area according to the first seek identifier of the read access request, if so, further determining whether a corresponding write access request exists at a write position indicated by a second addressing identifier of the read access request in the first cache unit, and if so, determining that a write access request with a matched access address exists in a first cache module.

In the scenario that the request identifier further includes an access type, according to the access address of the read access request, a specific manner of determining whether a write access request with a matched access address exists in the first cache module may be: judging whether a first cache unit with the same access type as write access in an information domain exists in a first cache module according to a first seek identifier of the read access request, if so, further determining whether a corresponding write access request exists at a write-in position indicated by a second addressing identifier of the read access request in the first cache unit, and if so, determining that a write access request with a matched access address exists in the first cache module.

In some embodiments, each first cache unit has no binding relationship with each master device, that is, when the access request received by the control module needs to write into a first cache unit in an idle state, the selected first cache unit in the idle state is random, that is, each master device is equivalent to dynamically sharing the cache space of the first cache module.

Because each first cache unit has no binding relation with each Master device, when the control module receives an access request of a Master device, the control module needs to determine a corresponding first addressing identifier and a second addressing identifier according to an access address in the access request, inquire about a first cache unit in a non-idle state in the whole first cache module, determine whether a first cache unit with the same request identifier (including a Master device identifier Master ID and a first addressing identifier) in an information domain as the request identifier (including the Master device identifier Master ID and the first addressing identifier) of the access request exists, if yes, write the access request into the first cache unit, otherwise, randomly write the access request into the first cache unit in an idle state (meanwhile, write the request identifier of the access request into the information domain of the first cache unit).

In other embodiments, each of the primary devices may also statically share a cache space of the first cache module, where the corresponding first cache module includes at least one first cache region, where the at least one first cache region is used to cache access requests sent by different primary devices, and each first cache region includes a plurality of first cache units.

It can be understood that each first cache unit has a preset binding relationship with each master device (one first cache region corresponds to one master device), that is, which first cache units are used for caching which access request of the master device is preset, when the access request received by the control module needs to be written into a first cache unit in an idle state, according to a preset allocation scheme, the first cache unit in the idle state is selected from the first cache regions corresponding to the master device sending the access request, and the access request to be written is written into the corresponding position of the first cache unit according to the information indicated by the second addressing identifier of the first cache unit.

Because each first cache unit and each Master device have a preset binding relationship (one first cache region corresponds to one Master device), when receiving an access request of a Master device, the control module needs to determine a corresponding first addressing identifier and a corresponding second addressing identifier according to an access address in the access request, inquire a first cache unit in a non-idle state in the first cache region corresponding to the Master device identifier according to the Master device identifier (Master ID) of the Master device, determine whether a first cache unit in an information domain, in which the first addressing identifier is identical to the first addressing identifier of the access request, if yes, write the access request into the first cache unit, otherwise, write the access request into the first cache unit in an idle state in the first cache region (meanwhile, write the first addressing identifier of the access request into the information domain of the first cache unit).

For example, a Master device identifier (Master ID) of a Master device may be written in advance into an information field of a first cache unit having a preset binding relationship with the Master device (i.e., a first cache unit in a first cache area corresponding to the Master device), when an access request received by a control module needs to be written into a first cache unit in an idle state, according to the Master device identifier of the Master device sending the access request, the first cache unit in the idle state is selected from the first cache units in which the Master device identifier is written in the information field, and the access request to be written is written into a corresponding position of the first cache unit according to information indicated by the second addressing identifier.

In some embodiments, each first buffer may be a separate buffer module (buffer), and these buffer modules are collectively referred to as the first buffer modules.

In the case that the first buffer module includes at least one first buffer area and a read request buffer area and a write request buffer area need to be divided, the first buffer module may be divided into at least one first buffer area to correspond to different host devices respectively, then the read request buffer area and the write request buffer area are divided into each first buffer area, or the first buffer module may be divided into the read request buffer area and the write request buffer area first, then the read request buffer area is divided into at least one first buffer area to correspond to different host devices respectively, and the write request buffer area is divided into at least one first buffer area to correspond to different host devices respectively.

In some embodiments, the number of first cache units in the first cache module mainly considers the number X of the masters and the number Y of independent memory streams in each master (i.e. the number of modules in each master that can independently issue memory requests), where the closer the number of first cache units is to the product (x×y) of the two. It should be noted that, the number of the first cache units does not have to cover the number of modules that can independently issue access requests in all the master devices, which is only a theoretical expectation, and may be designed according to actual requirements.

Assuming that there are 5 masters, the number of independent memory streams of the first master is 5, the number of independent memory streams of the second master is 6, the number of independent memory streams of the third master is 4, the number of independent memory streams of the fourth master is 5, and the number of independent memory streams of the fifth master is 7, then the maximum demand for the number of first cache units in the first cache module is 27, which may actually be smaller than this number. In this example, assuming that the number of the first buffer units in the first buffer module is 20, the 20 first buffer units may be divided into 5 groups (5 first buffer areas), or may be equally divided into 5 groups, or may be divided into 5 groups according to the number proportion of the independent memory streams of each master device, and respectively correspond to the 5 master devices.

The number of access requests that can be buffered in the first buffer unit is related to the application characteristics of the respective master device and also to the delay tolerance.

After the control module sends all the access requests in the first buffer unit to the output buffer module for buffering according to the sequence of the writing positions in the first buffer unit, the output buffer module can take out an access request (the access request arranged at the forefront in the output buffer module) to send to the memory controller according to the first-in first-out principle every period, and the output blocking can be reduced on the basis of ensuring that the access request is sent to the memory controller according to the sequence in the first buffer module.

In some embodiments, to reduce input blocking at the input of the control module, the request buffer further includes: the input buffer module is connected with the input end of the control module;

an input buffer module configured to:

caching an access request sent by the main equipment;

The input buffer module may be a first-in first-out buffer module.

It should be noted that the control module may be: the circuit generated by sequentially integrating and laying out and wiring codes written by the hardware description language HDL can specifically write codes capable of realizing corresponding functions based on the hardware description language (such as Verilog language) according to the functions required to be realized by the control module in the disclosure, and then sequentially integrating and laying out and wiring the written codes, so that the control module in the disclosure is obtained.

Based on the same inventive concept, the embodiments of the present disclosure further provide a System On Chip (SOC) including a host device, a memory controller, a memory to be accessed, and the request buffer of any of the above embodiments.

Based on the same inventive concept, the embodiments of the present disclosure also provide an electronic assembly comprising the system-on-chip of any of the embodiments described above.

In some use scenarios, the product form of the electronic assembly is embodied as a graphics card; in other use cases, the product form of the electronic assembly is embodied as a CPU motherboard.

Based on the same inventive concept, the embodiments of the present disclosure also provide an electronic device including the above-described electronic component. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, a game console, or the like.

Based on the same inventive concept, the embodiments of the present disclosure further provide a request transmission method of a system on a chip, as shown in fig. 3, including:

step S110: when an access request of a main device is received, writing the access request into a corresponding position in a corresponding first cache unit in a first cache module according to an access address and a request identifier in the access request, wherein two access requests with adjacent writing positions in the first cache unit have the same request identifier and continuous access addresses; the request identifier at least comprises a main equipment identifier;

step S120: when the ready state of a first cache unit in the first cache module is valid, all access requests in the first cache unit are sent to the memory controller according to the writing position sequence in the first cache unit, and the first cache unit is switched to an idle state.

The specific implementation process of the request transmission method of the system on chip can refer to the request buffer in any of the above embodiments, and will not be described herein again.

While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A request buffer connecting a memory controller and at least one host device, comprising a first cache module and a control module; the first cache module comprises a plurality of first cache units;

the control module is configured to write the access request into the corresponding position in the corresponding first cache unit according to the access address and the request identifier in the access request when receiving the access request of the master device, wherein two access requests with adjacent writing positions in the first cache unit have the same request identifier and continuous access addresses; the request identification at least comprises a main equipment identification;

And when the ready state of one first cache unit in the first cache module is valid, sending all access requests in the first cache unit to the memory controller according to the writing position sequence in the first cache unit, and switching the first cache unit into an idle state.

2. The request buffer of claim 1, further comprising a first counter corresponding to each first cache location, configured to record a number of access requests written in the corresponding first cache location; each first cache unit caches N access requests at most;

the control module is further configured to set the ready state of a first cache unit to be valid when the number of records of the first counter corresponding to the first cache unit reaches N.

3. The request buffer of claim 1, further comprising a second counter corresponding to each first cache location configured to record a time when the corresponding first cache location maintains a non-idle state;

4. The request buffer of claim 1, the minimum access granularity of the access requests being P bytes, each first cache unit caching up to N access requests, the access addresses of the access requests comprising bits 0-1 (D-1) from low to high;

when the address of the access request includes the address bit corresponding to the minimum access granularity, the first address of the access request is identified as the (log ₂ P+ log ₂ N) bits to (D-1) th bit, the second addressing identifying the log th address of the access request ₂ P bits to (log) ₂ P+ log ₂ N-1) bit indicated messageExtinguishing;

when the access address of the access request does not comprise the address bit corresponding to the minimum access granularity, the first address identification of the access request is the log-th address of the access request ₂ N bits to (D-1) th bit of information, the second addressing identifying the 0 th bit to (log) of the address of the access request ₂ N-1) information indicated by bits;

The control module is configured to, when receiving an access request of the master device, write the access request into a corresponding position in a corresponding first cache unit according to an access address and a request identifier in the access request, and includes:

the control module is configured to determine the corresponding first addressing identifier and second addressing identifier according to an access address in the access request when receiving the access request of the master device, and determine whether the access request with the same request identifier as the access request exists in the first cache module, if yes, the access request is written into the first cache unit in the first cache module, where the access request with the same request identifier as the access request exists, and the writing position is the position indicated by the second addressing identifier of the access request;

5. The request buffer of claim 4, the control module configured to write the access request into a first cache location in an idle state, comprising:

the control module is configured to:

when a first cache unit in an idle state exists in the first cache module currently, writing the access request into the first cache unit in the idle state;

when a first cache unit in an idle state does not exist in the first cache module currently and a first cache unit with a ready state being effective does not exist in the first cache module, the ready state of the first cache unit which is maintained in the first cache module and is in a non-idle state for the longest time is switched to be effective, and after the first cache unit is switched to the idle state, the access request is written into the first cache unit which is restored to the idle state.

6. The request buffer of claim 4, wherein the information field of a first cache unit in a non-idle state includes a request identifier of an access request cached in the first cache unit;

the control module is configured to determine, when receiving an access request of the master device, the corresponding first addressing identifier and the second addressing identifier according to an access address in the access request, and determine whether an access request with a request identifier identical to the access request exists in the first cache module, if yes, write the access request into the first cache unit where the access request with the same request identifier as the access request exists in the first cache module, where the access unit includes:

The control module is further configured to determine, when receiving an access request of the master device, the corresponding first addressing identifier and the second addressing identifier according to an access address in the access request, and determine whether a first cache unit with a request identifier in an information domain identical to a request identifier of the access request exists in the first cache module, if so, write the access request into the first cache unit.

7. The request buffer of claim 1, the first buffer module comprising a read request buffer and a write request buffer for buffering read access requests and write access requests, respectively, the write request buffer and the read request buffer each comprising a plurality of the first buffer units.

8. The request buffer of claim 1, the request identification further comprising an access type.

9. The request buffer of claim 1, further comprising: a second cache module;

the control module is further configured to, when sending a write access request in a first cache unit to the memory controller, read write data corresponding to the write access request from the second cache module according to the data write position information corresponding to the write access request cached in the first cache unit, and send the write data to the memory controller.

10. The request buffer of claim 9, the control module further configured to return corresponding response information to the master issuing a write access request when writing write data corresponding to the write access request to a corresponding location in the second cache module.

11. The request buffer of claim 9, the control module is further configured to, when receiving a read access request of the master device, determine whether a write access request with a matching access address exists in the first cache module according to an access address of the read access request, if so, read corresponding write data from the second cache module according to the data write location information corresponding to the write access request with the matching access address in the first cache module, send the write data to the master device that sends the read access request, and return corresponding response information to the master device.

12. The request buffer of claim 1, the first buffer module includes at least one first buffer area, the at least one first buffer area is respectively used for buffering access requests sent by different master devices, and each first buffer area includes a plurality of first buffer units.

13. The request buffer of claim 1, further comprising: the output buffer module is connected with the output end of the control module;

the control module is configured to send all access requests in a first cache unit to the memory controller according to the sequence of writing positions in the first cache unit when the ready state of the first cache unit in the first cache module is valid, and includes:

The control module is configured to send all access requests in a first cache unit to the output buffer module for caching according to the sequence of writing positions in the first cache unit when the ready state of the first cache unit in the first cache module is valid; the output buffer module is a first-in first-out buffer module.

14. The request buffer of claim 1, further comprising: the input buffer module is connected with the input end of the control module;

the input buffer module is configured to:

caching an access request sent by the main equipment;

15. The request buffer of claim 1, the information field of the first cache unit comprising a status bit comprising a ready status bit and an idle status bit.

16. A system on chip comprising a master, a memory controller, a memory to be accessed and a request buffer as claimed in any of claims 1 to 15.

17. An electronic assembly comprising the system-on-chip of claim 16.

18. An electronic device comprising the electronic assembly of claim 17.

19. A method of request transmission, the method comprising:

when an access request of a main device is received, writing the access request into a corresponding position in a corresponding first cache unit in a first cache module according to an access address and a request identifier in the access request, wherein two access requests with adjacent writing positions in the first cache unit have the same request identifier and continuous access addresses; the request identification at least comprises a main equipment identification;

and when the ready state of one first cache unit in the first cache module is valid, sending all access requests in the first cache unit to a memory controller according to the writing position sequence in the first cache unit, and switching the first cache unit into an idle state.