CN116257479B

CN116257479B - Reorder buffer, system, device, equipment and transmission method

Info

Publication number: CN116257479B
Application number: CN202310546003.4A
Authority: CN
Inventors: 冯小成; 刘义
Original assignee: Beijing Xiangdixian Computing Technology Co Ltd
Current assignee: Beijing Xiangdixian Computing Technology Co Ltd
Priority date: 2023-05-16
Filing date: 2023-05-16
Publication date: 2023-08-15
Anticipated expiration: 2043-05-16
Also published as: CN116257479A

Abstract

The present disclosure provides a reorder buffer, system, apparatus, device, and transmission method. The reordering buffer comprises an ordering module and a first buffer module; the ordering module receives the transaction request of the main module, reads the first identifier of the transaction request and replaces the first identifier with the corresponding second identifier; forwarding the transaction request with the second identifier to the slave module through the bus, and recording the mapping relation between the first identifier and the second identifier of the transaction request in the first cache module; wherein the second identifier of the transaction request is different from the second identifiers in other mapping relations recorded in the first cache module; and receiving the transaction response fed back by the slave module through the bus, replacing the second identifier of the transaction response with the corresponding first identifier according to the mapping relation recorded in the first cache module, and returning the transaction response with the first identifier to the master module. The occurrence of deadlock is avoided to a certain extent, and the advanced transmission performance of the system is not lost.

Description

Reorder buffer, system, device, equipment and transmission method

Technical Field

The present disclosure relates to the field of bus technologies, and in particular, to a reorder buffer, a system, a device, an apparatus, and a transmission method.

Background

The interconnection protocol of the System On Chip (SOC) internal bus has a high-level extensible interface (Advanced eXtensible Interface, AXI) protocol, and the like. The transaction request sent by the master module is judged by the interconnection bus (interconnection) through an address control signal, the response returned by the slave module identifies the master module sending the corresponding transaction request according to the identifier, and the mechanism causes the problem of deadlock caused by the fact that the AXI bus needs to keep order between the transaction requests with the same identifier (or the transaction responses with the same identifier) in the using process. At present, a common method for preventing bus deadlock is to add a checking module to a port where an interconnection bus is connected to each main module, each transaction sent by the main module needs to pass through the checking module, the checking module checks whether the main module sends the same identifier before but accesses the transactions of different slave modules, if so, the checking module temporarily blocks the transaction, and initiates a request for improving priority by the interconnection bus, so that the slave modules can accelerate the processing of the transaction corresponding to the received identifier. However, there is still some degree of blockage in this scheme, which also results in a loss of advanced transmission (delivery) performance of the system.

Disclosure of Invention

The disclosure aims to provide a reorder buffer, a system, a device, equipment and a transmission method, which solve the technical problem that a scheme for preventing bus deadlock can lose the advanced transmission (outbound) performance of a system in the prior art.

According to one aspect of the present disclosure, there is provided a reorder buffer applied to a bus system, including: the device comprises a sequencing module and a first cache module;

the ordering module is configured to receive the transaction request of the main module, read the first identifier of the transaction request and replace the first identifier with the corresponding second identifier;

forwarding the transaction request with the second identifier to the slave module through the bus, and recording the mapping relation between the first identifier and the second identifier of the transaction request in the first cache module; wherein the second identifier of the transaction request is different from the second identifiers in other mapping relations recorded in the first cache module;

receiving a transaction response fed back by the slave module through the bus, and reading a second identification of the transaction response; wherein the transaction response has the same second identity as the transaction request for which it is intended;

and replacing the second identifier of the transaction response with the corresponding first identifier according to the mapping relation recorded in the first cache module, and returning the transaction response with the first identifier to the main module.

In some embodiments, the reorder buffer further includes a second buffer module;

the ordering module is specifically configured to:

forwarding the transaction request with the second identifier to the slave module through the bus, confirming the number of the mapping relationships of the same first identifier corresponding to the transaction request in the mapping relationships currently recorded in the first cache module, and adding a preset threshold value to the number to serve as a third identifier of the transaction request;

recording the mapping relation among the first identifier, the second identifier and the third identifier of the transaction request in a first cache module;

receiving a transaction response fed back by the slave module through the bus, reading a second identifier of the transaction response, and confirming a first identifier and a third identifier corresponding to the second identifier of the transaction response according to the mapping relation recorded in the first cache module;

replacing the second identifier of the transaction response with the corresponding first identifier, and writing the transaction response with the first identifier into the corresponding position of the second cache module by taking the second identifier corresponding to the transaction response as a write pointer;

and according to the third identifiers and the second identifiers in the mapping relations corresponding to the same first identifier recorded in the first cache module, reading out the transaction response cached at the corresponding position from the second cache module and returning the transaction response to the main module according to the sequence from the smaller third identifier to the larger third identifier, wherein the sequence is recorded in the first cache module and corresponds to the same first identifier.

In some embodiments, in the reorder buffer, the ordering module is further configured to:

and each time a transaction response is returned to the main module, clearing the mapping relation of the same second identification corresponding to the transaction response, which is recorded in the first cache module.

In some embodiments, in the reorder buffer, the ordering module is configured to, according to the third identifier and the second identifier in each mapping relationship corresponding to the same first identifier recorded in the first buffer module, sequentially take the corresponding second identifier as a read pointer from the second buffer module in order from the third identifier with a value equal to a preset threshold value from the third identifier to the large, and read the transaction response buffered at the corresponding position from the second buffer module and return the transaction response to the master module, where the transaction response includes:

the ordering module is configured to subtract 1 from the value of a third identifier in the mapping relation of the same first identifier corresponding to the transaction response, which is recorded in the first cache module, after returning the transaction response to the main module;

and monitoring the value of a third identifier in each mapping relation recorded in the first cache module, and when the value of the third identifier in one mapping relation recorded in the first cache module is a preset threshold value, reading out the transaction response cached at the corresponding position from the second cache module by taking the second identifier in the mapping relation as a read pointer, and returning the transaction response to the main module.

after a transaction response is returned to the main module, before subtracting 1 from the value of a third identifier in the mapping relationship of the same first identifier corresponding to the transaction response, which is recorded in the first cache module, the mapping relationship of the same first identifier corresponding to the transaction response and the value of the third identifier being a preset threshold value, which is recorded in the first cache module, is cleared; or alternatively, the first and second heat exchangers may be,

and after the transaction response is returned to the main module, subtracting 1 from the value of the third identifier in the mapping relation of the same first identifier corresponding to the transaction response recorded in the first cache module, and clearing the mapping relation of the same first identifier corresponding to the transaction response and the value of the third identifier smaller than a preset threshold value recorded in the first cache module.

In some embodiments, in the reorder buffer, the ordering module is configured to replace the second identifier of the transaction response with the corresponding first identifier, and write the transaction response with the first identifier at a corresponding location of the second buffer module with the corresponding second identifier of the transaction response as a write pointer, including:

the ordering module is configured to judge whether the value of the third identifier corresponding to the second identifier of the transaction response is larger than a preset threshold value, if so, replace the second identifier of the transaction response with the corresponding first identifier, write the transaction response with the first identifier into the corresponding position of the second cache module by taking the second identifier corresponding to the transaction response as a write pointer, otherwise replace the second identifier of the transaction response with the corresponding first identifier, and directly return the transaction response with the first identifier to the main module.

In some embodiments, the reorder buffer further includes:

and the multiplexing selection module is configured to receive the transaction response output by the ordering module and the transaction response output by the second caching module and select one of the transaction responses to return to the main module.

In some embodiments, in the reorder buffer, the ordering module is configured to record a mapping relationship of the first identifier, the second identifier, and the third identifier of the transaction request in the first buffer module, and includes:

the ordering module is configured to write the mapping relation of the first identifier, the second identifier and the third identifier of the transaction request into the corresponding position of the first cache module by taking the second identifier of the transaction request as a write pointer;

the ordering module is configured to receive the transaction response fed back by the slave module through the bus, read the second identifier of the transaction response, and confirm the first identifier and the third identifier corresponding to the second identifier of the transaction response according to the mapping relation recorded in the first buffer module, and comprises:

the ordering module is configured to receive the transaction response fed back by the slave module through the bus and read a second identification of the transaction response;

and reading the mapping relation among the first identifier, the second identifier and the third identifier cached at the corresponding position from the first cache module by taking the second identifier of the transaction response as a read pointer so as to obtain the first identifier and the third identifier corresponding to the second identifier of the transaction response.

the ordering module is configured to write the first identifier and the third identifier of the transaction request into the corresponding positions of the first cache module by taking the second identifier of the transaction request as a write pointer;

and reading the first identifier and the third identifier cached at the corresponding positions from the first cache module by taking the second identifier of the transaction response as a read pointer.

In some embodiments, in the reorder buffer, the ordering module is specifically configured to:

forwarding the transaction request with the second identifier to the slave module through the bus, and writing the mapping relation between the first identifier and the second identifier of the transaction request into the corresponding position of the first cache module by taking the second identifier of the transaction request as a write pointer;

Receiving a transaction response fed back by the slave module through the bus, and reading a second identification of the transaction response;

and reading the mapping relation between the first identifier and the second identifier cached at the corresponding position from the first cache module by taking the second identifier of the transaction response as a read pointer so as to replace the second identifier of the transaction response with the corresponding first identifier.

forwarding the transaction request with the second identifier to the slave module through the bus, and writing the first identifier of the transaction request into a corresponding position of the first cache module by taking the second identifier of the transaction request as a write pointer;

and reading the first identifier cached at the corresponding position from the first cache module by taking the second identifier of the transaction response as a read pointer so as to replace the second identifier of the transaction response with the corresponding first identifier.

In some embodiments, in the reorder buffer, the ordering module is configured to receive a transaction request of the master module, read a first identifier of the transaction request and replace the first identifier with a corresponding second identifier, and includes:

And the ordering module is configured to receive the transaction request of the main module, read the first identifier of the transaction request, confirm whether the first cache module has a storage space, and if so, take the value of the write pointer corresponding to any storage space as the second identifier of the transaction request and replace the first identifier of the transaction request.

In some embodiments, in the reorder buffer, the first buffer module includes a plurality of registers, and the second identifier is an identifier of a register;

the ordering module is specifically configured to:

receiving a transaction request of a main module, reading a first identifier of the transaction request, and confirming whether an empty register exists in a first cache module, if so, taking the identifier of any empty register as a second identifier of the transaction request, and replacing the first identifier of the transaction request;

and forwarding the transaction request with the second identifier to the slave module through the bus, and caching the mapping relation between the first identifier and the second identifier of the transaction request into a register corresponding to the second identifier of the transaction request, or caching the first identifier of the transaction request into a register corresponding to the second identifier of the transaction request.

According to another aspect of the present disclosure, there is provided a bus system comprising a bus, a master module, a slave module, and a reorder buffer of any of the above embodiments.

According to another aspect of the present disclosure, there is provided an electronic device comprising the bus system of any of the above embodiments.

According to another aspect of the present disclosure, there is provided an electronic apparatus including the electronic device of any one of the above embodiments.

According to another aspect of the present disclosure, there is provided a data transmission method of a bus system, including:

receiving a transaction request of a main module, reading a first identifier of the transaction request and replacing the first identifier with a corresponding second identifier;

In some embodiments, in the data transmission method of the bus system, forwarding the transaction request with the second identifier to the slave module through the bus, and recording a mapping relationship between the first identifier and the second identifier of the transaction request in the first cache module, where the method includes:

receiving the transaction response fed back by the slave module through the bus, reading a second identifier of the transaction response, replacing the second identifier of the transaction response with a corresponding first identifier according to the mapping relation recorded in the first cache module, and returning the transaction response with the first identifier to the master module, wherein the transaction response comprises the following steps:

In some embodiments, the data transmission method of the bus system further includes:

In some embodiments, in the data transmission method of the bus system, according to the third identifier and the second identifier in each mapping relationship corresponding to the same first identifier recorded in the first cache module, the transaction response cached at the corresponding position is read from the second cache module and returned to the main module sequentially from the third identifier with the value of the preset threshold value according to the order from the third identifier to the large, with the corresponding second identifier as a read pointer, where the method includes:

Each time after a transaction response is returned to the main module, subtracting 1 from the value of a third identifier in the mapping relation of the same first identifier corresponding to the transaction response, which is recorded in the first cache module;

In some embodiments, in the data transmission method of the bus system, replacing the second identifier of the transaction response with the corresponding first identifier, and writing the transaction response with the first identifier at the corresponding position of the second buffer module with the second identifier corresponding to the transaction response as a write pointer, including:

judging whether the value of a third identifier corresponding to the second identifier of the transaction response is larger than a preset threshold value, if so, replacing the second identifier of the transaction response with a corresponding first identifier, taking the second identifier corresponding to the transaction response as a write pointer, writing the transaction response with the first identifier into a corresponding position of a second cache module, otherwise, replacing the second identifier of the transaction response with a corresponding first identifier, and directly returning the transaction response with the first identifier to a main module.

In some embodiments, in the data transmission method of the bus system, a mapping relationship between the first identifier, the second identifier, and the third identifier of the transaction request is recorded in a first buffer module, including:

writing the mapping relation among the first identifier, the second identifier and the third identifier of the transaction request into the corresponding position of the first cache module by taking the second identifier of the transaction request as a write pointer;

Receiving a transaction response fed back by the slave module through the bus, reading a second identifier of the transaction response, and confirming a first identifier and a third identifier corresponding to the second identifier of the transaction response according to the mapping relation recorded in the first cache module, wherein the method comprises the following steps:

writing the first identifier and the third identifier of the transaction request into the corresponding positions of the first cache module by taking the second identifier of the transaction request as a write pointer;

receiving a transaction response fed back by the slave module through the bus, reading a second identifier of the transaction response, and replacing the second identifier of the transaction response with a corresponding first identifier according to the mapping relation recorded in the first cache module, wherein the method comprises the following steps:

In some embodiments, in the data transmission method of the bus system, receiving a transaction request of a master module, reading a first identifier of the transaction request and replacing the first identifier with a corresponding second identifier, including:

And receiving the transaction request of the main module, reading the first identifier of the transaction request, confirming whether a storage space exists in the first cache module, if so, taking the value of the write pointer corresponding to any storage space as the second identifier of the transaction request, and replacing the first identifier of the transaction request.

In some embodiments, in the data transmission method of the bus system, the first buffer module includes a plurality of registers, and the second identifier is an identifier of the register;

receiving a transaction request of a master module, reading a first identifier of the transaction request and replacing the first identifier with a corresponding second identifier, forwarding the transaction request with the second identifier to a slave module through a bus, and recording a mapping relation between the first identifier and the second identifier of the transaction request in a first cache module, wherein the method comprises the following steps:

Drawings

FIG. 1 is a schematic diagram of a connection structure of a reorder buffer according to one embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a connection structure of a bus system according to an embodiment of the present disclosure;

fig. 3 is a flow chart illustrating a data transmission method of a bus system according to an embodiment of the disclosure.

Detailed Description

Before describing embodiments of the present disclosure, it should be noted that:

some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.

The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.

The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.

It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

The object of the present disclosure is to provide a reorder buffer, a system, a device, an apparatus, and a transmission method, where the reorder buffer includes an ordering module and a first buffer module; the ordering module receives the transaction request of the main module, reads the first identifier of the transaction request and replaces the first identifier with the corresponding second identifier; forwarding the transaction request with the second identifier to the slave module through the bus, and recording the mapping relation between the first identifier and the second identifier of the transaction request in the first cache module; wherein the second identifier of the transaction request is different from the second identifiers in other mapping relations recorded in the first cache module; and receiving the transaction response fed back by the slave module through the bus, replacing the second identifier of the transaction response with the corresponding first identifier according to the mapping relation recorded in the first cache module, and returning the transaction response with the first identifier to the master module.

In the reordering scheme, the fact that the identification carried by the bus and the transaction request received from the module is unique is achieved to a certain extent, the occurrence of deadlock is avoided, and the advanced transmission (outtiming) performance of the system is not lost.

One embodiment of the present disclosure provides a reorder buffer for use in a bus system, as shown in FIG. 1, comprising: the device comprises a sequencing module and a first cache module;

After the bus sends the transaction request to the slave module, the slave module generates a transaction response corresponding to the transaction request according to the received transaction request and assigns a corresponding identifier. In some cases, the identifier of the transaction request sent by the main module is a request mark a plus a first identifier, after the first identifier is replaced by a corresponding second identifier through the ordering module, the identifier of the transaction request received by the slave module is the request mark a plus a second identifier, the identifier of the transaction response corresponding to the received transaction request and fed back by the slave module is a response mark R plus a second identifier, wherein the second identifier of the transaction response is the same as the second identifier of the transaction request for which the slave module is corresponding to.

The first identifier of the transaction request refers to an original identifier of the transaction request, which may be a bus ID.

In some embodiments, the BUS may be an AXI BUS, a BUS, or the like. When the bus is an AXI bus, the first identification of the transaction request is an AXI-ID.

When multiple transaction requests issued by the master module within a time period have identical identifiers (i.e., the first identifiers are identical), in order to achieve the distinction of the transaction requests with identical identifiers from each other, the multiple transaction requests need to be kept in a certain order (i.e., order preservation is needed) from each other, that is, responses need to be returned in the order in which the transaction requests are sent by the master module.

In the proposal, the transaction request sent by the main module is replaced by the corresponding second identifier in the reorder buffer, and the ordering module gives the second identifier which is different from the second identifiers in other mapping relations recorded in the first buffer module to the received transaction request (namely, the first buffer module keeps the second identifiers which are different corresponding to the mapping relations recorded in the first buffer module), so that all the transaction requests can be distinguished from each other in the process of being transmitted to the slave module through the bus, and the transaction responses which are fed back corresponding to the slave module also have the second identifiers which are different from each other, thereby ensuring that the transaction requests are transmitted to the slave module through the bus, the transaction responses which are fed back corresponding to the slave module and the transaction responses which are fed back through the bus are not deadlock problems caused by the need of order keeping. And the second identifier of the transaction response is restored to the first identifier in the reorder buffer and returned to the main module, and the normal operation of the main module is not affected.

In some embodiments, the second identifier may be any identifier, so that when the ordering module receives the transaction request of the main module, the second identifier given to the currently received transaction request is different from the second identifier in each mapping relationship currently recorded in the first cache module, so that after the mapping relationship between the first identifier and the second identifier of the transaction request is recorded in the first cache module, each mapping relationship recorded in the first cache module still corresponds to a different second identifier.

In some embodiments, the second identifier given by the ordering module to the currently received transaction request is the current value of the write pointer of the first buffer module (after each writing of data, the value of the write pointer is updated), or may be the value of the write pointer corresponding to any storage space in the first buffer module, and the corresponding ordering module is configured to receive the transaction request of the master module, read the first identifier of the transaction request and replace it with the corresponding second identifier, and includes:

In some embodiments, in the context of the second corresponding value identified as the write pointer of the first cache module, the ordering module is specifically configured to:

It can be understood that the mapping relationship between the corresponding first identifier and the second identifier is cached in the storage location pointed by the second identifier in the first cache module, so that the second identifier carried by the transaction response currently received by the ordering module is taken as a read pointer, the mapping relationship between the first identifier and the second identifier cached in the corresponding location can be read from the first cache module, and the second identifier carried by the transaction response currently received can be mapped into the corresponding first identifier.

In other embodiments, the ranking module is specifically configured to:

It can be understood that, because the second identifier of the transaction request is used as a write pointer, the first identifier of the transaction request is written into the corresponding position of the first buffer module, so that the mapping relationship between each second identifier and the first identifier cached in the storage position pointed by each second identifier is naturally formed in the first buffer module, the corresponding first identifier can be found according to the corresponding second identifier, and the purpose of recording the mapping relationship between the first identifier and the second identifier of the transaction request in the first buffer module can be achieved. And taking the second identifier carried by the transaction response currently received by the ordering module as a read pointer, reading the first identifier cached at the corresponding position from the first caching module, and replacing the second identifier carried by the transaction response currently received with the corresponding first identifier.

In some embodiments, the first buffer module includes a plurality of registers, and the second identifier is an identifier of a register, that is, one second identifier corresponds to one register.

In some embodiments, the identification of the register may be a sequence number of the register. For example, when the first cache module includes 256 registers, the identifiers of the 256 registers are respectively 0 to 255, that is, the second identifier corresponding to the 0 th register is 0, the second identifier corresponding to the 1 st register is 1, and so on.

In the case of the second identifier being the identifier of the register, the ordering module is specifically configured to:

In some embodiments, when a corresponding second identifier is given to the currently received transaction request, the manner of searching for the empty register may be to poll, starting from the register corresponding to the second identifier of the last received transaction request, in the direction in which the sequence number of the register increases, the identifier of the first empty register that is polled being the second identifier of the current transaction request.

In some embodiments, when a corresponding second identifier is given to the currently received transaction request, the manner of searching for the empty register may be to poll each time starting from the 0 th register in the direction in which the sequence number of the register increases, where the identifier of the first empty register that is polled is the second identifier of the current transaction request.

In some embodiments, whether a register is empty is indicated by a status identifier, and the validity and invalidity of the status identifier of a register indicates whether the register is empty, respectively. When the status flag is 1-bit, 1 indicates valid (i.e., null) and 0 indicates invalid (i.e., not null).

Correspondingly, when confirming whether a register is empty, whether the register is empty can be confirmed by confirming whether the status identifier of the register is valid.

The status identifiers of the respective registers in the first cache module are cached by a flag register. The status identifiers for the 256 registers may be cached by a 256 bits flag register.

It can be understood that in the scenario that the first identifier of the transaction request is cached in the register corresponding to the second identifier of the transaction request, each first identifier is cached in the register corresponding to the corresponding second identifier, so that the mapping relationship between each second identifier and the first identifier cached in the register corresponding to each second identifier is naturally formed in the first cache module, the corresponding first identifier can be found according to the corresponding second identifier, and the purpose of recording the mapping relationship between the first identifier and the second identifier of the transaction request in the first cache module can be achieved.

Under the circumstance that the mapping relation between the first identifier and the second identifier of the transaction request is cached in the register corresponding to the second identifier of the transaction request, the reading process of the first cache module is that the ordering module is configured to receive the transaction response fed back by the slave module through the bus and read the second identifier of the transaction response, and the replacing the second identifier of the transaction response with the corresponding first identifier according to the mapping relation recorded in the first cache module comprises the following steps:

the ordering module is configured to receive the transaction response fed back by the slave module through the bus, read the second identifier of the transaction response, and read the mapping relation between the first identifier and the second identifier cached in the register corresponding to the second identifier of the transaction response from the first caching module so as to replace the second identifier of the transaction response with the corresponding first identifier.

In a scenario of caching the first identifier of the transaction request in a register corresponding to the second identifier of the transaction request, a reading process of the first cache module is that the ordering module is configured to receive a transaction response fed back by the slave module through a bus, and read the second identifier of the transaction response, and replace the second identifier of the transaction response with the corresponding first identifier according to a mapping relationship recorded in the first cache module, where the reading process includes:

And the ordering module is configured to receive the transaction response fed back by the slave module through the bus, read the second identifier of the transaction response, and read the first identifier cached in the register corresponding to the second identifier of the transaction response from the first caching module so as to replace the second identifier of the transaction response with the corresponding first identifier.

To further achieve order preservation during the return of the transaction responses from the reorder buffer to the master module, that is, to further achieve the return of the transaction responses with the same identifier (same first identifier) to the master module in the order in which the master module issues the corresponding transaction requests, to further avoid the occurrence of deadlock problems in the response channel, in some embodiments, the reorder buffer further includes a second buffer module configured to buffer the transaction responses received by the ordering module, and to return the transaction responses to the master module in the order.

The specific order-preserving implementation scheme is that the ordering module is configured to forward the transaction request with the second identifier to the slave module through the bus, and record the mapping relationship between the first identifier and the second identifier of the transaction request in the first cache module, and the ordering module comprises:

the ordering module is configured to forward the transaction request with the second identifier to the slave module through the bus, confirm the number of the mapping relationship of the same first identifier corresponding to the transaction request in the mapping relationship currently recorded in the first cache module, and add a preset threshold to the number as a third identifier of the transaction request;

And recording the mapping relation among the first identifier, the second identifier and the third identifier of the transaction request in the first cache module.

The preset threshold may be any value, for example, 0, 1, etc.

The number of mapping relationships of the same first identifier corresponding to the transaction request in the mapping relationship currently recorded in the first cache module indicates the number of requests with the same first identifier, that is, the number of in-transit (pending) transaction requests (represented by the second request) with the same first identifier, in the transaction requests in which the ordering module has received the requests but has not returned the responses to the master module, except for the transaction request currently received (represented by the first request). When the number is 0, it is stated that, except for the currently received transaction request (represented by a first request), there is no transaction request (represented by a second request) which has the same first identifier as the currently received transaction request and is in transit (pending), and in a next period of time, the first request is the transaction request which is ranked first among the transaction requests having the same first identifier, and the corresponding transaction response needs to be preferentially returned to the master module; when the number is 1, it is stated that in addition to the currently received transaction request (represented by the first request), there are 1 transaction requests (represented by the second request) having the same first identifier as the currently received transaction request and being in transit (pending), and in a next period of time, among the transaction requests having the same first identifier, the transaction request ranked first is required to be returned preferentially to the master module by the corresponding transaction response, followed by the transaction response of the first request, and so on.

In the foregoing scenario of recording the third identifier, the ordering module is configured to receive the transaction response fed back by the slave module through the bus, read the second identifier of the transaction response, replace the second identifier of the transaction response with the corresponding first identifier according to the mapping relationship recorded in the first buffer module, and return the transaction response with the first identifier to the master module, where the method includes:

the ordering module is configured to receive the transaction response fed back by the slave module through the bus, read the second identifier of the transaction response, and confirm the first identifier and the third identifier corresponding to the second identifier of the transaction response according to the mapping relation recorded in the first cache module;

Specifically, one way to return responses in order (response order preservation) is:

1) When a mapping relation that a value of a third identifier is a preset threshold value appears in the first cache module, the corresponding second identifier can be used as a read pointer to confirm whether the transaction response is cached at a corresponding position in the second cache module, if yes, the transaction response is directly read and returned to the main module, otherwise, after the transaction response is cached at the position, the transaction response is read and returned to the main module;

2) After a transaction response with the value of the third identifier being a preset threshold value is returned, searching a third identifier with the value of the first identifier being the preset threshold value plus 1 in the mapping relation of the first identifier corresponding to the transaction response in the first cache module, and using the corresponding second identifier as a read pointer to confirm whether the transaction response is cached in the corresponding position in the second cache module, if yes, directly reading the transaction response and returning the transaction response to the main module, otherwise, waiting for the transaction response cached in the position and then reading the transaction response and returning the transaction response to the main module;

3) And after returning the transaction response with the value of the third identifier being the preset threshold value plus 1, continuing to search the third identifier with the value of the mapping relation of the transaction response corresponding to the same first identifier being the preset threshold value plus 2 in the first cache module, and so on.

Another way to return responses in order (response order preservation) is that the ordering module is configured to subtract 1 from the value of the third identifier in the mapping relationship of the same first identifier corresponding to a transaction response recorded in the first cache module every time a transaction response is returned to the main module; and monitoring the value of a third identifier in each mapping relation recorded in the first cache module, and when the value of the third identifier in one mapping relation recorded in the first cache module is a preset threshold value, reading out the transaction response cached at the corresponding position from the second cache module by taking the second identifier in the mapping relation as a read pointer, and returning the transaction response to the main module.

That is, this way of response order preservation is: 1) When a mapping relation that a value of a third identifier is a preset threshold value appears in the first cache module, the corresponding second identifier can be used as a read pointer to confirm whether the transaction response is cached at a corresponding position in the second cache module, if yes, the transaction response is directly read and returned to the main module, otherwise, after the transaction response is cached at the position, the transaction response is read and returned to the main module; 2) After the transaction response is returned, the value of the third identifier in the mapping relation of the first identifier corresponding to the transaction response in the first buffer module is reduced by 1, and then the step 1) is repeated.

In the two response order keeping modes, the response order keeping can be realized through the third identifier, namely, the order return of the transaction response is realized at a lower resource cost.

In some embodiments, in a scenario in which the value of the third identifier in the mapping relationship recorded in the first cache module corresponding to the same first identifier as the transaction response is subtracted by 1 each time a transaction response is returned to the master module, the ordering module is further configured to:

That is, after the transaction response is returned to the main module, the transaction response which has been returned to the main module is found from the first cache module according to the first identifier and the third identifier, and is cleared from the first cache module, so that the occupation of resources of the first cache module is avoided.

In other embodiments, the transaction response that has returned to the master module may be further found from the first cache module according to the second identifier, and cleared from the first cache module, and the corresponding ordering module is further configured to:

That is, after the transaction response is returned to the master module, the mapping relationship recorded in the first cache module and corresponding to the same second identifier as the transaction response may be cleared.

In some embodiments, to enable immediate return of the response to the master module when the ordering module receives the transaction response with the third identifier as the preset threshold, the response time is shortened, the ordering module is configured to replace the second identifier of the transaction response with the corresponding first identifier, and write the transaction response with the first identifier at the corresponding position of the second cache module with the second identifier corresponding to the transaction response as the write pointer, including:

That is, the ordering module indicates that, for a transaction response that receives feedback from the slave module through the bus, when the value of the third identifier corresponding to the second identifier of the transaction response is greater than a preset threshold, the transaction response is not currently the most prioritized (top-ordered) transaction response among the transaction responses having the same first identifier, so that the transaction response having the first identifier needs to be written into the corresponding location of the second buffer module. And when the value of the third identifier corresponding to the second identifier of the transaction response is not greater than the preset threshold (equal to the preset threshold), it is indicated that, in the transaction responses with the same first identifier, the transaction response is currently the most preferred (most top ordered) transaction response, and the master module can be immediately returned.

In the above scenario where the response may be immediately returned to the master module, the transaction response may be output through the ordering module or may be output through the first buffer module, so in this scenario, the reorder buffer, as shown in fig. 1, further includes: a multiplexing selection module (Mux) configured to receive the transaction response output by the ordering module and the transaction response output by the second buffer module and select one of them to return to the master module.

In a scenario of recording the third identifier, the ordering module is configured to record, in the first cache module, a mapping relationship of the first identifier, the second identifier, and the third identifier of the transaction request, where the ordering module includes:

and the ordering module is configured to write the mapping relation of the first identifier, the second identifier and the third identifier of the transaction request into the corresponding position of the first cache module by taking the second identifier of the transaction request as a write pointer.

The ordering module, corresponding to the writing process of the first cache module, is configured to confirm the first identifier and the third identifier corresponding to the second identifier of the transaction response according to the mapping relationship recorded in the first cache module, and includes:

and the ordering module is configured to read the mapping relation among the first identifier, the second identifier and the third identifier cached at the corresponding position from the first cache module by taking the second identifier of the transaction response as a read pointer so as to obtain the first identifier and the third identifier corresponding to the second identifier of the transaction response.

It can be understood that the mapping relation of the corresponding first identifier, the second identifier and the third identifier is cached in the storage position pointed by the second identifier in the first cache module, so that the second identifier carried by the transaction response currently received by the ordering module is taken as a read pointer, the mapping relation of the first identifier, the second identifier and the third identifier cached in the corresponding position can be read from the first cache module, and the second identifier carried by the transaction response currently received can be mapped into the corresponding first identifier and the third indicator.

The mapping relation between the first identifier, the second identifier and the third identifier can be split into a mapping relation between the first identifier and the second identifier and a corresponding third identifier, the third identifier can be recorded in a tag (tag) area of a register corresponding to the second identifier under the condition that the first cache module comprises a plurality of registers, and the mapping relation between the first identifier and the second identifier can be recorded in a data (data) area of the register corresponding to the second identifier.

In other embodiments, the ordering module configured to record, in the first cache module, a mapping relationship of the first identifier, the second identifier, and the third identifier of the transaction request includes:

And the ordering module is configured to write the first identifier and the third identifier of the transaction request into the corresponding positions of the first cache module by taking the second identifier of the transaction request as a write pointer.

It can be understood that, because the second identifier of the transaction request is used as a write pointer, the first identifier and the third identifier of the transaction request are written into the corresponding positions of the first cache module, so that the mapping relationship between each second identifier and the first identifier and the third identifier cached in the storage position pointed by each second identifier is naturally formed in the first cache module, the corresponding first identifier and third identifier can be found according to the corresponding second identifier, and the purpose of recording the mapping relationship between the first identifier, the second identifier and the third identifier of the transaction request in the first cache module can be achieved.

and the ordering module is configured to read the first identifier and the third identifier cached at the corresponding positions from the first cache module by taking the second identifier of the transaction response as a read pointer.

It can be understood that the corresponding first identifier and the third identifier are cached in the storage location pointed by the second identifier in the first cache module, so that the second identifier carried by the transaction response currently received by the ordering module is taken as a read pointer, and the first identifier and the third identifier cached in the corresponding locations can be read from the first cache module.

In the scenario where the first cache module includes a plurality of registers, the third identifier may be recorded in a tag (tag) area of a register corresponding to the second identifier, and the first identifier may be recorded in a data (data) area of the register corresponding to the second identifier.

Correspondingly, in the scenario that the first cache module includes a plurality of registers, the ordering module is configured to forward the transaction request with the second identifier to the slave module through the bus, and confirm the number of the mapping relationships corresponding to the same first identifier as the transaction request in the mapping relationships currently recorded in the first cache module, and add a preset threshold to the number, as a third identifier of the transaction request, where the third identifier includes:

the ordering module is configured to forward the transaction request with the second identifier to the slave module through the bus, confirm the number of registers in the first buffer module, which currently records the mapping relation of the first identifier corresponding to the transaction request, and add a preset threshold to the number as a third identifier of the transaction request.

In some embodiments, in a scenario where the first buffer module and the second buffer module use the second identifier as the write pointer and the read pointer at the same time, the storage locations of the first buffer module and the second buffer module may be in one-to-one correspondence, for example, the mapping relationship between the first identifier and the second identifier of one transaction request is recorded in the nth storage location of the first buffer module, and then the ordering module may buffer the transaction response in the nth storage location of the second buffer module when receiving the corresponding transaction response.

Based on the same inventive concept, the embodiments of the present disclosure also provide a bus system, as shown in fig. 2, including a bus, a master module, a slave module, and the reorder buffer of any of the above embodiments.

The bus System is a processing chip or a System-on-a-chip (SOC) chip that needs to implement read-write operations through a bus.

In some embodiments, the reorder buffer may be provided on the master module. Correspondingly, the first cache module and the second cache module can be realized by using the existing cache area (cache space) in the main module, so that the consumption of storage resources can be reduced.

In some embodiments, a reorder buffer may be provided between the master and the bus.

In some embodiments, a reorder buffer may be provided on the bus.

Based on the same inventive concept, the embodiments of the present disclosure also provide an electronic device including the bus system of any of the above embodiments.

In some use cases, the product form of the electronic device is embodied as a graphics card; in other use scenarios, the product form of the electronic device is embodied as a CPU motherboard.

Based on the same inventive concept, the embodiment of the disclosure also provides an electronic device, which includes the electronic apparatus. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, a game console, or the like.

Based on the same inventive concept, the embodiments of the present disclosure further provide a data transmission method of a bus system, as shown in fig. 3, including:

step S110: receiving a transaction request of a main module, reading a first identifier of the transaction request and replacing the first identifier with a corresponding second identifier;

step S120: forwarding the transaction request with the second identifier to the slave module through the bus, and recording the mapping relation between the first identifier and the second identifier of the transaction request in the first cache module; wherein the second identifier of the transaction request is different from the second identifiers in other mapping relations recorded in the first cache module;

Step S130: receiving a transaction response fed back by the slave module through the bus, and reading a second identification of the transaction response; wherein the transaction response has the same second identity as the transaction request for which it is intended;

step S140: and replacing the second identifier of the transaction response with the corresponding first identifier according to the mapping relation recorded in the first cache module, and returning the transaction response with the first identifier to the main module.

The specific implementation process of the data transmission method of the bus system can be referred to the reorder buffer of any of the above embodiments, and will not be described herein again.

While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A reorder buffer for use in a bus system, comprising: the device comprises a sequencing module, a first cache module and a second cache module;

forwarding the transaction request with the second identifier to a slave module through a bus, confirming the number of the mapping relationships of the same first identifier corresponding to the transaction request in the mapping relationships currently recorded in the first cache module, and adding a preset threshold value to the number to serve as a third identifier of the transaction request; recording the mapping relation among the first identifier, the second identifier and the third identifier of the transaction request in the first cache module; wherein the second identifier of the transaction request is different from the second identifiers in other mapping relationships recorded in the first cache module;

Receiving a transaction response fed back by the slave module through the bus, and reading a second identification of the transaction response; wherein the transaction response has the same second identification as the transaction request for which it was intended;

according to the mapping relation recorded in the first cache module, confirming a first identifier and a third identifier corresponding to the second identifier of the transaction response; replacing the second identifier of the transaction response with the corresponding first identifier, and writing the transaction response with the first identifier into the corresponding position of the second cache module by taking the second identifier corresponding to the transaction response as a write pointer;

and according to the third identifiers and the second identifiers in the mapping relations corresponding to the same first identifier recorded in the first cache module, reading out the transaction response cached at the corresponding position from the second cache module and returning the transaction response to the main module according to the sequence from the third identifier with the value of the preset threshold value from the third identifier to the larger one by sequentially taking the corresponding second identifier as a read pointer.

2. The reorder buffer of claim 1, the ordering module further configured to:

and each time a transaction response is returned to the main module, clearing the mapping relation of the same second identification recorded in the first cache module and corresponding to the transaction response.

3. The reorder buffer according to claim 1, the ordering module configured to read out transaction responses buffered at corresponding locations from the second buffer module according to third identifiers and second identifiers in respective mapping relationships corresponding to the same first identifier recorded in the first buffer module, in order from the third identifier with the value of the preset threshold value from the third identifier to the larger, sequentially with the corresponding second identifier as a read pointer, and return the transaction responses buffered at corresponding locations from the second buffer module to the master module, including:

the ordering module is configured to subtract 1 from a value of a third identifier in a mapping relationship recorded in the first buffer module and corresponding to the same first identifier as the transaction response after returning the transaction response to the main module;

and monitoring the value of a third identifier in each mapping relation recorded in the first cache module, and when the value of the third identifier in one mapping relation recorded in the first cache module is the preset threshold value, reading out the transaction response cached at the corresponding position from the second cache module and returning the transaction response to the main module by taking the second identifier in the mapping relation as a read pointer.

4. The reorder buffer of claim 3, the ordering module further configured to:

After a transaction response is returned to the main module, before subtracting 1 from the value of a third identifier in the mapping relationship which is recorded in the first cache module and corresponds to the same first identifier, clearing the mapping relationship which is recorded in the first cache module, corresponds to the same first identifier as the transaction response and has the value of the third identifier as the preset threshold; or alternatively, the first and second heat exchangers may be,

and after a transaction response is returned to the main module, subtracting 1 from the value of a third identifier in the mapping relationship which is recorded in the first cache module and corresponds to the same first identifier, and clearing the mapping relationship which is recorded in the first cache module, corresponds to the same first identifier as the transaction response and has the value of the third identifier smaller than the preset threshold.

5. The reorder buffer of claim 1, said ordering module configured to replace a second identification of the transaction response with a corresponding first identification and to write the transaction response with the corresponding second identification of the transaction response as a write pointer at a corresponding location of said second cache module, comprising:

the ordering module is configured to determine whether a value of a third identifier corresponding to the second identifier of the transaction response is greater than the preset threshold, if yes, replace the second identifier of the transaction response with the corresponding first identifier, write the transaction response with the first identifier into a corresponding position of the second cache module by using the second identifier corresponding to the transaction response as a write pointer, otherwise replace the second identifier of the transaction response with the corresponding first identifier, and directly return the transaction response with the first identifier to the main module.

6. The reorder buffer of claim 5, further comprising:

and the multiplexing module is configured to receive the transaction response output by the ordering module and the transaction response output by the second caching module and select one of the transaction responses to return to the main module.

7. The reorder buffer of claim 1, the ordering module configured to record a mapping of the first, second, and third identifications of the transaction request to the first cache module, comprising:

the ordering module is configured to receive the transaction response fed back by the slave module through the bus, read the second identifier of the transaction response, and confirm the first identifier and the third identifier corresponding to the second identifier of the transaction response according to the mapping relationship recorded in the first buffer module, and includes:

8. The reorder buffer of claim 1, the ordering module configured to record a mapping of the first, second, and third identifications of the transaction request to the first cache module, comprising:

9. The reorder buffer of claim 7 or 8, the ordering module configured to receive a transaction request of a master module, read a first identification of the transaction request and replace it with a corresponding second identification, comprising:

the ordering module is configured to receive the transaction request of the main module, read the first identifier of the transaction request, confirm whether the first buffer module has a storage space, if so, take the value of the write pointer corresponding to any storage space as the second identifier of the transaction request, and replace the first identifier of the transaction request.

10. The reorder buffer of claim 1, said first buffer module comprising a plurality of registers, said second identification being an identification of said registers;

the ordering module is specifically configured to:

receiving a transaction request of a main module, reading a first identifier of the transaction request, and confirming whether an empty register exists in the first cache module, if yes, taking the identifier of any empty register as a second identifier of the transaction request, and replacing the first identifier of the transaction request;

11. A bus system comprising a bus, a master module, a slave module and the reorder buffer of any one of claims 1 to 10.

12. An electronic device comprising the bus system of claim 11.

13. An electronic device comprising the electronic apparatus of claim 12.

14. A data transmission method of a bus system, comprising:

forwarding the transaction request with the second identifier to the slave module through the bus, confirming the number of the mapping relationships of the same first identifier corresponding to the transaction request in the mapping relationships currently recorded in the first cache module, and adding a preset threshold value to the number to serve as a third identifier of the transaction request; recording the mapping relation among the first identifier, the second identifier and the third identifier of the transaction request in the first cache module; wherein the second identifier of the transaction request is different from the second identifiers in other mapping relationships recorded in the first cache module;

according to the mapping relation recorded in the first cache module, confirming a first identifier and a third identifier corresponding to the second identifier of the transaction response;

15. The method according to claim 14, according to the third identifier and the second identifier in each mapping relationship corresponding to the same first identifier recorded in the first cache module, starting from the third identifier with the value of the preset threshold value, sequentially taking the corresponding second identifier as a read pointer in order from the third identifier to the large, reading out the transaction response cached at the corresponding position from the second cache module, and returning the transaction response to the main module, including:

Each time a transaction response is returned to the main module, subtracting 1 from the value of a third identifier in the mapping relation of the same first identifier corresponding to the transaction response, which is recorded in the first cache module;

16. The method of claim 14, replacing the second identifier of the transaction response with the corresponding first identifier, and writing the transaction response with the first identifier at the corresponding location of the second cache module with the corresponding second identifier of the transaction response as a write pointer, comprising:

judging whether the value of a third identifier corresponding to the second identifier of the transaction response is larger than the preset threshold value, if so, replacing the second identifier of the transaction response with a corresponding first identifier, taking the second identifier corresponding to the transaction response as a write pointer, writing the transaction response with the first identifier into a corresponding position of a second cache module, otherwise, replacing the second identifier of the transaction response with a corresponding first identifier, and directly returning the transaction response with the first identifier to the main module.