CN118034638A

CN118034638A - Reorder buffer, system, component, apparatus and transmission method

Info

Publication number: CN118034638A
Application number: CN202410446029.6A
Authority: CN
Inventors: 李虹莹; 杨尚罡
Original assignee: Beijing Xiangdixian Computing Technology Co Ltd
Current assignee: Beijing Xiangdixian Computing Technology Co Ltd
Priority date: 2024-04-12
Filing date: 2024-04-12
Publication date: 2024-05-14

Abstract

The present disclosure provides a reorder buffer, system, component, apparatus, and transmission method. The reordering buffer comprises a FIFO, a control module and a buffer memory module; the cache module comprises a plurality of cache areas respectively corresponding to different request identifications; the control module is configured to write a request identification of a transaction request into the FIFO; the system is also configured to sequentially write response data into the buffer area corresponding to the corresponding request identifier; or the control module is configured to write the request identification of the transaction request and the allocated cache address into the FIFO; and the response data is written into the buffer address arranged in the top-most table item in the table item which is buffered with the corresponding request identification in the FIFO. The method not only meets the order-preserving requirement of the downstream module (IP), but also reduces delay, fully utilizes the bandwidth of the interconnection network and improves the performance.

Description

Reorder buffer, system, component, apparatus and transmission method

Technical Field

The present disclosure relates to the field of reorder buffers, and more particularly, to a reorder buffer, system, component, apparatus, and transmission method.

Background

A System On Chip (SOC) typically includes a plurality of intellectual property cores (Intellectual Property, IP) including, but not limited to, a central processing unit (Central Processing Unit, CPU), direct memory access units (Direct Memory Access, DMA), double Data Rate (DDR) and some dedicated Data processing modules. The various IPs are connected via an interconnection network, often supporting similar protocols, such as the interconnection protocol has the advanced extensible interface (Advanced eXtensible Interface, AXI) protocol, etc. But the protocols also define different specifications, some IPs may support advanced (outstanding) and out of order (out of order) transmissions, some IPs support advanced (outstanding) but not out of order (out of order) transmissions, and some IPs do not. These several cases are often problems faced by SoC chip designs.

Chip designers need to address the performance issues presented by interconnects and balance performance versus area and power consumption. If the connection is simple, since the downstream IP does not support disorder, advanced transmission (outstanding) transmission cannot be realized, and only if one request is sent out, the data corresponding to the request is waited for to return and then the next request is sent, so that the data and the request cannot be misplaced. As shown in FIG. 1, the upstream module may send out a transaction request 1 after the response data 0 of the transaction request 0 is returned, and may send out a transaction request 2 after the response data 1 of the transaction request 1 is returned, so that the bandwidth of the interconnection network cannot be fully utilized.

Disclosure of Invention

The present disclosure aims to provide a reorder buffer, a system, a component, a device, and a transmission method, which solve the technical problem that in the prior art, in order to realize downstream IP order preservation, advanced transmission (outstanding) transmission cannot be realized, resulting in insufficient utilization of an interconnection network bandwidth.

According to one aspect of the present disclosure, there is provided a reorder buffer, an parsing module, a FIFO, a control module, and a buffering module;

the cache module comprises a plurality of cache areas respectively corresponding to different request identifications; a control module configured to, upon receipt of a transaction request of an upstream module, write a request identification of the transaction request into the FIFO, and send the transaction request to the memory; the system is also configured to sequentially write the response data into a buffer area corresponding to a corresponding request identifier when the response data returned by the memory for a transaction request is received; the system is also configured to read response data sequentially from a buffer area corresponding to the request identifier arranged at the forefront in the FIFO from the buffer module and return the response data to the downstream module; or alternatively, the first and second heat exchangers may be,

The control module is configured to receive a transaction request of an upstream module, allocate a corresponding cache address of the transaction request in the cache module, write a request identification of the transaction request and the allocated cache address into the FIFO, and send the transaction request to the memory; the system is further configured to write the response data into a cache address in a forefront table item among table items cached with corresponding request identifications in the FIFO when the response data returned by the memory for a transaction request is received; and is further configured to read response data buffered at a buffer address in the FIFO queued in the foremost entry from the buffer module and return it to the downstream module.

In some embodiments, in the reorder buffer, the pointers of the FIFO include a first write pointer, a first read pointer, a plurality of second write pointers, and a plurality of second read pointers, where the plurality of second write pointers respectively correspond to different request identifiers, and the plurality of second read pointers respectively correspond to different request identifiers;

A control module configured to, upon receipt of a transaction request of an upstream module, write a request identification of the transaction request into the FIFO, and send the transaction request to the memory; the system is also configured to sequentially write the response data into a buffer area corresponding to a corresponding request identifier when the response data returned by the memory for a transaction request is received; the method is also configured to read response data sequentially read from a buffer area corresponding to the request identifier arranged at the forefront in the FIFO from the buffer module and return the response data to the downstream module, and comprises the following steps:

The control module is configured to write a request identifier of the transaction request into an item currently pointed by the first write pointer when receiving the transaction request of the upstream module, send the transaction request to the memory, and write the item identifier of the item currently pointed by the first write pointer into the item currently pointed by the corresponding second write pointer when the second write pointer corresponding to the request identifier is valid, wherein the second write pointer is updated to point to the item currently pointed by the first write pointer, and the first write pointer is updated to point to the next item of the item currently pointed by the first write pointer; the method comprises the steps of receiving response data returned by a memory for a transaction request, sequentially writing the response data into a buffer area corresponding to a request identifier corresponding to the response data, and switching a first flag bit in a table item currently pointed by a second read pointer corresponding to the request identifier corresponding to the response data to be valid, wherein the second read pointer is updated to point to a table item corresponding to a cached table item identifier in the table item currently pointed by the second read pointer; the method comprises the steps of receiving a request identifier of a first reading pointer from a cache module, and reading response data from the cache area corresponding to the request identifier in the currently pointed table of the first reading pointer, returning the response data to a downstream module, and updating the first reading pointer to point to the next table of the currently pointed table when a first flag bit in the currently pointed table of the first reading pointer is valid; or alternatively, the first and second heat exchangers may be,

The control module is configured to receive a transaction request of an upstream module, allocate a corresponding cache address of the transaction request in the cache module, write a request identification of the transaction request and the allocated cache address into the FIFO, and send the transaction request to the memory; the system is further configured to write the response data into a cache address in a forefront table item among table items cached with corresponding request identifications in the FIFO when the response data returned by the memory for a transaction request is received; and is further configured to read response data buffered at a buffer address of a first-front-most entry in the FIFO from the buffer module and return the response data to the downstream module, comprising:

The control module is configured to receive a transaction request of an upstream module, allocate a corresponding cache address of the transaction request in the cache module, write a request identification of the transaction request and the allocated cache address into an item currently pointed by a first write pointer, send the transaction request to the memory, and write an item identification of the item currently pointed by the first write pointer into the item currently pointed by the corresponding second write pointer when the second write pointer corresponding to the request identification is valid, wherein the second write pointer is updated to point to the item currently pointed by the first write pointer, and the first write pointer is updated to point to the next item of the item currently pointed by the first write pointer; the method comprises the steps of receiving response data returned by a memory for a transaction request, writing the response data into a cache address in an item currently pointed to by a second read pointer corresponding to a request identifier corresponding to the response data, and switching a first flag bit in the item currently pointed to by the second read pointer to be valid, wherein the second read pointer is updated to point to the item corresponding to the cached item identifier in the item currently pointed to by the second read pointer; the method further comprises the step of reading response data cached at a cache address in an item currently pointed to by the first reading pointer from the cache module, returning the response data to the downstream module, and updating the first reading pointer to point to the next item of the item currently pointed to by the first reading pointer when a first flag bit in the item currently pointed to by the first reading pointer is valid.

In some embodiments, in the reorder buffer, the control module is configured to, when receiving a transaction request of the upstream module, write a request identifier of the transaction request into an entry currently pointed to by the first write pointer, send the transaction request to the memory, and when a second write pointer corresponding to the request identifier is valid, write an entry identifier of the entry currently pointed to by the first write pointer into an entry currently pointed to by the corresponding second write pointer; and the method is further configured to switch the first flag bit in the table item currently pointed to by the second read pointer corresponding to the request identifier corresponding to the response data to be valid, wherein the second read pointer is updated to point to the table item corresponding to the cached table item identifier in the table item currently pointed to by the second read pointer, and comprises the following steps:

the control module is configured to write a request identifier of the transaction request into an item currently pointed by the first write pointer when receiving the transaction request of the upstream module, send the transaction request to the memory, write the item identifier of the item currently pointed by the first write pointer into the item currently pointed by the corresponding second write pointer when the second write pointer corresponding to the request identifier is valid, and switch the second flag bit in the item currently pointed by the second write pointer to be valid; the method comprises the steps of receiving response data from a user, wherein the response data corresponds to a request identifier, and is further configured to switch a first flag bit in a table item currently pointed by a second read pointer corresponding to the request identifier to be valid, and updating the second read pointer to point to a table item corresponding to a cached table item identifier in the table item currently pointed by the second read pointer when the second flag bit in the table item currently pointed by the second read pointer is valid; or alternatively, the first and second heat exchangers may be,

The control module is configured to receive a transaction request of an upstream module, allocate a corresponding cache address of the transaction request in the cache module, write a request identifier of the transaction request and the allocated cache address into an item currently pointed by a first write pointer, send the transaction request to the memory, and write an item identifier of the item currently pointed by the first write pointer into an item currently pointed by the corresponding second write pointer when the second write pointer corresponding to the request identifier is valid; and the second read pointer is further configured to switch the first flag bit in the currently pointed table entry of the second read pointer to be valid, and the second read pointer is updated to point to the table entry corresponding to the cached table entry identifier in the currently pointed table entry, and the method comprises the following steps:

The control module is configured to receive a transaction request of an upstream module, allocate a corresponding cache address of the transaction request in the cache module, write a request identifier of the transaction request and the allocated cache address into a table item currently pointed by a first write pointer, wherein a second flag bit in the table item currently pointed by the first write pointer is invalid, send the transaction request to the memory, write the table item identifier of the table item currently pointed by the first write pointer into the table item currently pointed by the corresponding second write pointer when the second write pointer corresponding to the request identifier is valid, and switch the second flag bit in the table item currently pointed by the second write pointer to be valid; and the second read pointer is updated to point to the table item corresponding to the cached table item identifier in the table item pointed at currently when the second flag bit in the table item pointed at currently by the second read pointer is valid.

In some embodiments, in the reorder buffer, the FIFO pointer further comprises a third read pointer;

The FIFO is configured to send a request identifier in the table item pointed at by the third read pointer to the downstream module, so that the downstream module requests corresponding response data from the control module through the request identifier, and the third read pointer is updated to point to the next table item of the table item pointed at by the third read pointer;

the control module is configured to read response data sequentially read from a buffer area corresponding to a request identifier in an item currently pointed to by the first read pointer from the buffer module, and return the response data to the downstream module, and comprises the following steps:

The control module is configured to sequentially read response data from a cache area corresponding to the request identifier in the table item currently pointed by the first reading pointer to return to the downstream module when a request identifier sent by the downstream module is received and the request identifier is the same as the request identifier in the table item currently pointed by the first reading pointer; or alternatively, the first and second heat exchangers may be,

The control module is configured to read response data cached at a cache address in an item currently pointed to by the first read pointer from the cache module and return the response data to the downstream module, and comprises:

And the control module is configured to read response data cached on a cache address in the table item currently pointed by the first read pointer from the cache module and return the response data to the downstream module when a request identifier sent by the downstream module is received and the request identifier is the same as the request identifier in the table item currently pointed by the first read pointer.

The FIFO is configured to send a request identifier and a cache address in the table item pointed at by the third read pointer to the downstream module, so that the downstream module requests corresponding response data from the control module through the request identifier and the corresponding cache address, and the third read pointer is updated to point to the next table item of the table item pointed at by the third read pointer;

The control module is configured to read response data cached in the cache address from the cache module according to the received cache address when a request identifier and a corresponding cache address sent by the downstream module are received and the received request identifier and the received cache address are respectively the same as the request identifier and the cache address in the table item currently pointed by the first read pointer, and return the response data cached in the cache address to the downstream module.

In some embodiments, in the reorder buffer, the entry pointed to before the first read pointer is released when the first read pointer is updated.

In some embodiments, in the reorder buffer, the control module is configured to, when receiving a transaction request of an upstream module, write a request identifier of the transaction request into the FIFO, and includes:

A control module configured to write a request identification of a transaction request of an upstream module into the FIFO when the FIFO is in a non-full state and the transaction request is received; or alternatively, the first and second heat exchangers may be,

A control module configured to write the request identification of the transaction request and the allocated cache address into the FIFO, comprising:

And the control module is configured to write the request identification of the transaction request and the allocated cache address into the FIFO when the FIFO is in a non-full state.

In some embodiments, in the reorder buffer, the control module includes an parsing module, a writing control module, and a reading control module;

A parsing module configured to, upon receipt of a transaction request of an upstream module, write a request identification of the transaction request into a FIFO, and send the transaction request to a memory; the write control module is configured to sequentially write the response data into a buffer area corresponding to a corresponding request identifier when receiving the response data returned by the memory for a transaction request; the read control module is configured to read response data sequentially from a buffer area corresponding to the forefront request identifier in the FIFO and return the response data to the downstream module; or alternatively, the first and second heat exchangers may be,

The analysis module is configured to receive the transaction request of the upstream module, apply for the corresponding cache address of the transaction request in the cache module from the read control module, write the request identification of the transaction request and the allocated cache address into the FIFO, and send the transaction request to the memory; the write control module is configured to write response data returned by the memory for a transaction request into a cache address in a forefront table item in the table item cached with the corresponding request identifier in the FIFO when the response data is received; and the read control module is configured to read response data cached at the cache address arranged in the forefront table item in the FIFO from the cache module and return the response data to the downstream module.

In some embodiments, the reorder buffer further includes a first arbitration module configured to:

when receiving a transaction request of an upstream module, sending a handshake request to the analysis module, and when receiving response information returned by the analysis module for the handshake request, selecting the transaction request from the received transaction request and sending the transaction request to the analysis module.

In some embodiments, in the reorder buffer, the parsing module is further configured to:

When a handshake request of the first arbitration module is received, a cache address corresponding to a transaction request corresponding to the handshake request in the cache module is applied to the read control module, and response information for the handshake request is returned to the first arbitration module after the cache address is applied.

receiving a transaction request of an upstream module;

And sending the received transaction requests to the control module one by one.

In some embodiments, the reorder buffer further includes a second arbitration module configured to:

And receiving response data returned by the downstream module and returning the response data to the corresponding upstream module.

According to another aspect of the present disclosure, a system on a chip is provided, including an upstream module, a downstream module, and a reorder buffer of any of the above embodiments.

According to another aspect of the present disclosure, there is provided an electronic assembly comprising the system-on-chip of any of the above embodiments.

According to another aspect of the present disclosure, there is provided an electronic device comprising the electronic assembly of any of the above embodiments.

According to another aspect of the present disclosure, there is provided a data transmission method of a system on a chip, including:

When a transaction request of an upstream module is received, writing a request identification of the transaction request into a FIFO, and sending the transaction request to a memory; when response data returned by the memory aiming at a transaction request is received, the response data is written into a buffer area corresponding to a corresponding request identifier in the buffer module; sequentially reading response data from a buffer area corresponding to the forefront request identifier in the read FIFO (first in first out) of the buffer module, and returning the response data to the downstream module; the cache module comprises a plurality of cache areas respectively corresponding to different request identifications; or alternatively, the first and second heat exchangers may be,

Receiving a transaction request of an upstream module, distributing a corresponding cache address of the transaction request in a cache module, writing a request identification of the transaction request and the distributed cache address into a FIFO, and sending the transaction request to a memory; when response data returned by a memory aiming at a transaction request is received, writing the response data into a cache address which is arranged in the forefront table item in the table item cached with the corresponding request identifier in the FIFO; and the response data cached at the cache address arranged in the forefront table item in the reading FIFO from the cache module is returned to the downstream module.

In some embodiments, in the data transmission method, the pointers of the FIFO include a first write pointer, a first read pointer, a plurality of second write pointers, and a plurality of second read pointers, where the plurality of second write pointers respectively correspond to different request identifiers, and the plurality of second read pointers respectively correspond to different request identifiers;

When a transaction request of an upstream module is received, writing a request identification of the transaction request into a FIFO, and sending the transaction request to a memory; when response data returned by the memory aiming at a transaction request is received, the response data is written into a buffer area corresponding to a corresponding request identifier in the buffer module; sequentially reading response data from a buffer area corresponding to the forefront request identifier in the read FIFO (first in first out) of the buffer module, and returning the response data to the downstream module; the cache module comprises a plurality of cache areas respectively corresponding to different request identifications, and comprises:

When a transaction request of an upstream module is received, a request identifier of the transaction request is written into an item currently pointed by a first write pointer, the transaction request is sent to a memory, and when a second write pointer corresponding to the request identifier is valid, the item identifier of the item currently pointed by the first write pointer is written into an item currently pointed by a corresponding second write pointer, the second write pointer is updated to point to the item currently pointed by the first write pointer, and the first write pointer is updated to point to the next item of the item currently pointed by the first write pointer; when response data returned by a memory aiming at a transaction request is received, sequentially writing the response data into a buffer area corresponding to a corresponding request identifier, and switching a first zone bit in a table item currently pointed by a second read pointer corresponding to the request identifier corresponding to the response data to be valid, wherein the second read pointer is updated to point to the table item corresponding to the cached table item identifier in the table item currently pointed by the second read pointer; reading the response data sequentially read from the buffer area corresponding to the request identifier in the table item pointed at by the first reading pointer from the buffer module, and returning to the downstream module, wherein when the first flag bit in the table item pointed at by the first reading pointer is valid, the first reading pointer is updated to point to the next table item of the table item pointed at by the first reading pointer; or alternatively, the first and second heat exchangers may be,

Receiving a transaction request of an upstream module, distributing a corresponding cache address of the transaction request in a cache module, writing a request identification of the transaction request and the distributed cache address into a FIFO, and sending the transaction request to a memory; when response data returned by a memory aiming at a transaction request is received, writing the response data into a cache address which is arranged in the forefront table item in the table item cached with the corresponding request identifier in the FIFO; reading response data buffered at a buffer address in a first-front table entry in the FIFO from the buffer module and returning the response data to the downstream module, including:

Receiving a transaction request of an upstream module, distributing a corresponding cache address of the transaction request in a cache module, writing a request identifier of the transaction request and the distributed cache address into an item currently pointed by a first write pointer, sending the transaction request to a memory, writing an item identifier of the item currently pointed by the first write pointer into an item currently pointed by the corresponding second write pointer when a second write pointer corresponding to the request identifier is valid, updating the second write pointer to point to the item currently pointed by the first write pointer, and updating the first write pointer to point to the next item of the item currently pointed by the first write pointer; when response data returned by a memory aiming at a transaction request is received, writing the response data into a cache address in a table item currently pointed by a second read pointer corresponding to a corresponding request identifier, and switching a first zone bit in the table item currently pointed by the second read pointer to be valid, wherein the second read pointer is updated to point to the table item corresponding to the cached table item identifier in the table item currently pointed by the second read pointer; and reading response data cached at a cache address in the table item pointed at by the first reading pointer from the cache module, returning to the downstream module, and updating the first reading pointer to point to the next table item of the table item pointed at by the first reading pointer when the first flag bit in the table item pointed at by the first reading pointer is valid.

Drawings

FIG. 1 is a timing diagram of transaction request and response data in a scenario where the downstream module does not support out-of-order and does not prefetch;

FIG. 2 is a timing diagram of transaction request and response data corresponding to a reorder buffer provided by one embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a connection structure of a system-on-chip including a reorder buffer according to one embodiment of the present disclosure;

FIG. 4 is a schematic diagram of an arrangement of information fields of entries of a FIFO according to one embodiment of the disclosure;

Fig. 5 is a schematic diagram of an interaction flow between a parsing module and a first arbiter according to an embodiment of the disclosure.

Detailed Description

Before describing embodiments of the present disclosure, it should be noted that:

Some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.

The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.

The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.

It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

The object of the present disclosure is to provide a reorder buffer, a system, a component, a device and a transmission method, the reorder buffer comprising a FIFO, a control module and a buffer module; the cache module comprises a plurality of cache areas respectively corresponding to different request identifications; a control module configured to, upon receipt of a transaction request of an upstream module, write a request identification of the transaction request into the FIFO, and send the transaction request to the memory; the system is also configured to sequentially write the response data into a buffer area corresponding to a corresponding request identifier when the response data returned by the memory for a transaction request is received; the system is also configured to read response data sequentially from a buffer area corresponding to the request identifier arranged at the forefront in the FIFO from the buffer module and return the response data to the downstream module; or, the control module is configured to receive a transaction request of the upstream module, allocate a corresponding cache address of the transaction request in the cache module, write a request identifier of the transaction request and the allocated cache address into the FIFO, and send the transaction request to the memory; the system is further configured to write the response data into a cache address in a forefront table item among table items cached with corresponding request identifications in the FIFO when the response data returned by the memory for a transaction request is received; and is further configured to read response data buffered at a buffer address in the FIFO queued in the foremost entry from the buffer module and return it to the downstream module.

In the reordering scheme, a pre-fetching mechanism of response data is realized through the FIFO and the cache module, outstanding transmission of an upstream module is realized, and the response data in the cache module can be returned to a downstream module in sequence (the sequence in which the control module receives the transaction request) to a certain extent. Therefore, the method not only meets the order-preserving requirement of a downstream module (IP) to a certain extent, but also fully utilizes the bandwidth of the interconnection network and improves the performance. As shown in FIG. 2, the upstream module may issue transaction request 0, transaction request 1, transaction request 2, transaction request 3, and transaction request 4 continuously and sequentially, adjacent requests may not be issued with a certain delay, and response data 0, response data 1, response data 2, response data 3, and response data 4 corresponding to transaction request 0, transaction request 1, transaction request 2, transaction request 3, and transaction request 4, respectively, may be returned to the downstream module continuously and sequentially.

One embodiment of the present disclosure provides a reorder buffer, as shown in fig. 3, comprising: FIFO, control module and buffer module;

a) The cache module comprises a plurality of cache areas respectively corresponding to different request identifications; a control module configured to, upon receipt of a transaction request of an upstream module, write a request identification of the transaction request into the FIFO, and send the transaction request to the memory; the system is also configured to sequentially write the response data into a buffer area corresponding to a corresponding request identifier when the response data returned by the memory for a transaction request is received; the system is also configured to read response data sequentially from a buffer area corresponding to the request identifier arranged at the forefront in the FIFO from the buffer module and return the response data to the downstream module; or alternatively, the first and second heat exchangers may be,

B) The control module is configured to receive a transaction request of an upstream module, allocate a corresponding cache address of the transaction request in the cache module, write a request identification of the transaction request and the allocated cache address into the FIFO, and send the transaction request to the memory; the system is further configured to write the response data into a cache address in a forefront table item among table items cached with corresponding request identifications in the FIFO when the response data returned by the memory for a transaction request is received; and is further configured to read response data buffered at a buffer address in the FIFO queued in the foremost entry from the buffer module and return it to the downstream module.

Wherein the reorder buffer is interconnected with the upstream module and the downstream module through an interconnection network. In some embodiments, the interconnection Network may be an AXI BUS, a BUS, or a Network on Chip (NoC), etc.

The transaction request comprises a write transaction request or a read transaction request, and when the transaction request is the write transaction request, the response data is a write response; when the transaction request is a read transaction request, the response data comprises a read response and/or read data (the data requested by the read transaction request from the memory), and the upstream module sends the transaction request to the control module through a read address channel (axiar), the control module sends the transaction request to the memory through the read address channel (axiar), and the response data (the read response and/or the read data) returned by the memory is returned to the control module through the read data channel (axir).

The request identifier of the transaction request written into the table entry of the FIFO refers to the original identifier of the transaction request, which may be the identifier of the upstream module (Master ID) that initiates the transaction request, or may be a combination of the transaction identifier and the identifier of the upstream module, for example, the request identifier corresponding to the write transaction request may be an AWID or a WID, and the request identifier corresponding to the read transaction request may be an ARID (ID is the identifier of the upstream module).

The response data returned by the memory for the transaction request has a corresponding identifier, and the identifier and the request identifier are in a corresponding relationship, for example, the identifier corresponding to the response data (read response and/or read data) of the read transaction request can be RID (ID is the identifier of the upstream module), so that the control module can find the response data corresponding to the request identifier arranged at the forefront in the FIFO from the cache module, read and return to the downstream module.

In some embodiments, the cache module may be a Static Random-Access Memory (SRAM).

receiving a transaction request of an upstream module;

And sending the received transaction requests to the control module one by one.

Multiple upstream modules may issue transaction requests simultaneously, and at most one transaction request may be selected for transmission to the control module by the first arbitration module per beat. In some embodiments, primary Round-Robin polling arbitration may be used, arbitration may be performed according to a certain priority order according to a user requirement, or a multi-level arbitration scheme may be used according to a requirement.

In some embodiments, the downstream module processes the response data read from the cache module, and returns (rtn) to the corresponding upstream module via the second arbitration module after processing. The second arbitration module returns the response data to the corresponding upstream module (Master) according to the request identifier (such as Master ID) corresponding to the received response data.

In some embodiments, the second arbitration module is a demultiplexer (demux).

In the above manner a), in the scenario that multiple upstream modules (specific different request identifiers) correspond to the same downstream module, by fixing the manner of allocating the area of the shared cache to each upstream module (master), the order of transaction request and response data with the same request identifier (corresponding to the same upstream module) can be implemented in one FIFO and one cache module, thereby saving hardware resources. Although the response data corresponding to different request identifications (Master IDs) share the cache modules, the cache modules are statically shared, that is, the area of the shared cache is allocated for each upstream module (Master) fixedly.

It can be understood that in the above mode a), each buffer zone of the buffer module cooperates with the control module to realize the function of first-in first-out, that is, in the buffer zone corresponding to a request identifier, the response data is sequentially read out and returned to the downstream module according to the sequence of writing into the buffer zone. Wherein the response data in the buffer area and the request identifier in the FIFO are in one-to-one relationship (i.e. the response data of one transaction request in the buffer area corresponds to one request identifier in the FIFO), i.e. the control module is configured to sequentially read the response data of one transaction request from the buffer module in the buffer area corresponding to the first one request identifier in the FIFO each time, and return the response data to the downstream module.

In some embodiments, in the scenario of the static shared buffer module (mode a) above, the pointers of the FIFO include a first write pointer, a first read pointer, a plurality of second write pointers, and a plurality of second read pointers, where the plurality of second write pointers respectively correspond to different request identifiers, and the plurality of second read pointers respectively correspond to different request identifiers;

The control module is configured to write a request identifier of the transaction request into an item currently pointed by the first write pointer when receiving the transaction request of the upstream module, send the transaction request to the memory, and write the item identifier of the item currently pointed by the first write pointer into the item currently pointed by the corresponding second write pointer when the second write pointer corresponding to the request identifier is valid, wherein the second write pointer is updated to point to the item currently pointed by the first write pointer, and the first write pointer is updated to point to the next item of the item currently pointed by the first write pointer; the method comprises the steps of receiving response data returned by a memory for a transaction request, sequentially writing the response data into a buffer area corresponding to a request identifier corresponding to the response data, and switching a first flag bit in a table item currently pointed by a second read pointer corresponding to the request identifier corresponding to the response data to be valid, wherein the second read pointer is updated to point to a table item corresponding to a cached table item identifier in the table item currently pointed by the second read pointer; and the buffer module is further configured to read the response data sequentially read from the buffer area corresponding to the request identifier in the table item currently pointed by the first reading pointer, return the response data to the downstream module, and update the first reading pointer to point to the next table item of the table item currently pointed by the first reading pointer when the first flag bit in the table item currently pointed by the first reading pointer is valid.

When the first flag bit in the table item pointed at by the first read pointer is valid, the first read pointer is updated to point to the next table item of the table item pointed at by the first read pointer, so that it is ensured that after the response data corresponding to the transaction request corresponding to the table item pointed at by the first read pointer is written into the corresponding buffer area, that is, after the response data in the corresponding buffer area can be returned to the downstream module, the first read pointer is updated. The method ensures that null data cannot be returned to the downstream module, and meets the order-preserving requirement of the downstream module (IP).

In this way, the table item identifier of the table item currently pointed by the first write pointer is written into the corresponding table item currently pointed by the second write pointer, and the table item currently pointed by the first write pointer is used as the new table item currently pointed by the second write pointer corresponding to the request identifier, the table items where the transaction requests with the same request identifier are located and cached in the FIFO are linked to form a linked list, so that under the condition that a plurality of upstream modules correspond to the same downstream module, the order of the transaction requests and response data with the same request identifier (corresponding to the same upstream module) can be realized in one FIFO, and hardware resources are saved.

The plurality of second write pointers corresponding to different request identifiers respectively means that each request identifier corresponds to one second write pointer. The second write pointer corresponding to a request identifier in the FIFO is valid only when the request identifier exists in the FIFO, that is, if the control module receives a transaction request with a request identifier of an upstream module, the FIFO does not currently exist the request identifier, that is, the second write pointer corresponding to the request identifier is invalid, and when the request identifier of the transaction request is written into the table entry currently pointed to by the first write pointer, the second write pointer corresponding to the request identifier is automatically switched to be valid and points to the table entry (that is, the table entry currently pointed to by the first write pointer) written by the request identifier of the transaction request.

Therefore, when the control module receives a transaction request, whether the second write pointer corresponding to the request identifier of the transaction request is valid or not, the operation of writing the request identifier into the FIFO triggers the second write pointer corresponding to the request identifier to update to point to the entry currently pointed to by the first write pointer (the entry written by the request identifier). It may be appreciated that the control module may determine whether to end the update operation of the second write pointer triggered by writing the request identifier into the FIFO according to whether the second write pointer corresponding to the transaction request points to the entry written by the request identifier.

If the control module receives a transaction request, the second write pointer corresponding to the request identifier of the transaction request is valid, and then the last transaction request with the specific same request identifier received by the control module is stored in the table item currently pointed by the second write pointer, the table item identifier of the table item currently pointed by the first write pointer is written into the table item currently pointed by the corresponding second write pointer, and the table item currently pointed by the second write pointer and the table item currently pointed by the first write pointer can be linked to form a linked list.

When a transaction request is received according to the control module, whether a second write pointer corresponding to a request identifier of the transaction request is valid or not is determined, and the update operation of the second write pointer triggered by the request identifier written in the FIFO can be divided into an update operation of an invalid second write pointer (including switching the second write pointer from invalid to valid and pointing to an entry currently pointed to by the first write pointer) and an update operation of the valid second write pointer (writing an entry identifier of an entry written in the request identifier into an entry currently pointed to by the corresponding second write pointer, where the second write pointer is updated to an entry currently pointed to by the first write pointer). A request to identify an operation to write to the FIFO triggers an update operation of an invalid second write pointer or an update operation of a valid second write pointer.

It should be noted that, the update operation of the first write pointer triggered by the request identifier written in the FIFO and the update operation of the second write pointer (the update operation of the invalid second write pointer or the update operation of the valid second write pointer) do not have strict sequence, and the foregoing "the entry pointed to by the first write pointer currently" refers to the entry pointed to by the first write pointer when the control module performs the operation of writing the request identifier in the FIFO, that is, the entry pointed to by the request identifier.

In some embodiments, in order to avoid that a request identifier is written into an invalid second write pointer triggered by the FIFO, the control module immediately executes the update operation of the valid second write pointer corresponding to the same request identifier, and a criterion may be added in the control module, that is, before executing the update operation of the valid second write pointer, the control module determines whether the second write pointer corresponding to the request identifier currently points to the entry written by the request identifier, if yes, the update operation of the valid second write pointer is not performed, and if not, the update operation of the valid second write pointer is performed.

The plurality of second read pointers respectively corresponding to different request identifiers means that each request identifier corresponds to one second read pointer. In the FIFO, a second read pointer corresponding to a request identifier exists only when the request identifier exists in the FIFO, that is, if the FIFO does not currently exist (i.e., the corresponding second read pointer is invalid) when a transaction request of an upstream module is received, when the request identifier of the transaction request is written into an entry currently pointed to by the first write pointer, the second read pointer corresponding to the request identifier is automatically switched to be valid and point to the entry (i.e., the entry currently pointed to by the first write pointer) written by the request identifier of the transaction request. After the second read pointer is valid, the updating mode of the second read pointer is to update the second read pointer to point to the table entry corresponding to the cached table entry identifier in the table entry pointed to by the corresponding second read pointer after the first mark position in the table entry pointed to by the corresponding second read pointer is valid. It should be noted that, if at this time, the entry currently pointed to by the second read pointer has no cached entry identifier, that is, there is no linked next entry, that is, the transaction request corresponding to the entry currently pointed to by the second read pointer is the last transaction request currently cached by the FIFO and having the same request identifier, at this time, the corresponding second read pointer will not be updated, and if the corresponding second read pointer is not updated until the entry is released, the second read pointer will be set to be invalid.

It will be appreciated that the first write pointer and the first read pointer are updated in the same manner as the read-write pointer of a conventional FIFO, for example: after each request identifier of a transaction request is written into an item (an item currently pointed to by the first write pointer) pointed to by the first write pointer, the first write pointer is added with 1 (when the first write pointer is currently at the maximum value, the first write pointer is reset to the minimum value after the current writing). When the first flag bit in the entry pointed to by the first read pointer is valid, the first read pointer is incremented by 1 (when the first read pointer is currently at a maximum value, the first read pointer is reset to a minimum value when updated this time).

In some embodiments, upon the first read pointer update, the entry pointed to before the first read pointer update is released. The first read pointer may be understood as an entry release pointer.

In some embodiments, the Entry identification (Entry ID) of an Entry may be the sequence number of the Entry.

In some embodiments, the request identification, the entry identification, and the first flag bit written into the entry are located in corresponding locations of the information field of the entry, as shown in FIG. 4.

In some embodiments, during the process of updating the second read pointer, the control module may determine whether the table entry is linked to other table entries by determining whether the table entry currently pointed to by the second read pointer is cached in the table entry, and if the table entry currently pointed to by the second read pointer is not cached in the table entry (i.e., the table entry is not linked to other table entries), the table entry currently pointed to by the second read pointer will not be updated, i.e., the corresponding second read pointer will not be updated.

In some embodiments, to facilitate determining whether the second read pointer may be updated, a second flag bit may be added in the information field of the table entry of the FIFO to indicate whether the table entry links other table entries, where the second flag bit is inactive when no link exists, and is active when other table entries are linked. When a second read pointer needs to be updated, it is first determined whether a second flag bit in an entry pointed by the second read pointer is valid, so as to determine whether the second read pointer can be updated, and when the second flag bit in the entry pointed by the second read pointer is valid, the second read pointer can be updated. If the second flag bit in the entry is not toggled active (i.e., inactive) until the entry to which the second read pointer is currently directed is released, then the second read pointer will be set inactive.

Correspondingly, in the scenario of the static shared cache module (the above-mentioned mode a), the control module is configured to, when receiving a transaction request of an upstream module, write a request identifier of the transaction request into an entry currently pointed to by the first write pointer, send the transaction request to the memory, and when a second write pointer corresponding to the request identifier is valid, write an entry identifier of the entry currently pointed to by the first write pointer into an entry currently pointed to by the corresponding second write pointer; and the method is further configured to switch the first flag bit in the table item currently pointed to by the second read pointer corresponding to the request identifier corresponding to the response data to be valid, wherein the second read pointer is updated to point to the table item corresponding to the cached table item identifier in the table item currently pointed to by the second read pointer, and comprises the following steps:

The control module is configured to write a request identifier of the transaction request into an item currently pointed by the first write pointer when receiving the transaction request of the upstream module, send the transaction request to the memory, write the item identifier of the item currently pointed by the first write pointer into the item currently pointed by the corresponding second write pointer when the second write pointer corresponding to the request identifier is valid, and switch the second flag bit in the item currently pointed by the second write pointer to be valid; and the second read pointer is updated to point to the table item corresponding to the cached table item identifier in the table item currently pointed by the second read pointer when the second flag bit in the table item currently pointed by the second read pointer is valid.

In some embodiments, in the context of the static shared buffer module (mode a above), the FIFO pointer further comprises a third read pointer;

and the control module is configured to sequentially read response data from the cache module and return the response data to the downstream module when a request identifier sent by the downstream module is received and is identical to the request identifier in the table item currently pointed by the first read pointer.

When the downstream module needs response data corresponding to a transaction request, the received request identifier is sent to the control module, so as to meet the requirement that the downstream module does not support outstanding transmission. Specifically, a handshake mechanism may be adopted between the FIFO and the downstream module, and when the downstream module ready, the FIFO sends the request identifier in the table entry pointed by the third read pointer to the downstream module, so as to achieve that the downstream module obtains the request identifier from the FIFO, so as to meet the requirement that the downstream module does not support outstanding transmission.

It will be appreciated that the third read pointer is updated to point to the next entry after the corresponding module performs the corresponding operation on the entry to which it points. Specifically, after the FIFO sends the request identifier in the entry currently pointed to by the third read pointer to the downstream module, the third read pointer is increased by 1 (when the third read pointer is currently at the maximum value, the third read pointer is reset to the minimum value after this reading).

In some embodiments, in the scenario of the static shared buffer module (the above manner a), when the control module is configured to receive a transaction request of the upstream module, when writing a request identifier of the transaction request into the FIFO, information (indicating information for indicating that the downstream module performs corresponding processing on corresponding response data) carried in the transaction request user field is written together into a corresponding table entry, such as operation type (including decompression, decryption, etc.), so that when the FIFO sends the request identifier in the table entry currently pointed by the third read pointer to the downstream module, other information (indicating information for indicating that the downstream module performs corresponding processing on corresponding response data) in the table entry is sent together to the downstream module, so that after the downstream module requests corresponding response data from the control module through the request identifier, and performs corresponding processing on the requested response data according to the corresponding indicating information.

In some embodiments, in the context of the static shared cache module (mode a above), the control module being configured to, upon receipt of a transaction request by an upstream module, write a request identification of the transaction request into the FIFO, comprises:

And a control module configured to write a request identification of the transaction request into the FIFO when the transaction request of the upstream module is received and the FIFO is in a non-full state.

When the FIFO is full, it is indicated that there are no free entries in the FIFO to store the information of the transaction request.

The full state signal of the FIFO may be written into the corresponding register by the first read pointer and the first write pointer after a certain combination logic, where the combination logic may be:

In response to the update of the write pointer, determining whether the current value of the first write pointer is equal to the current value of the first read pointer;

in response to the current value of the first write pointer being equal to the current value of the first read pointer, it is indicated that the FIFO is currently full.

In some embodiments, in the context of a static shared cache module (mode a above), the control module includes an parsing module, a write control module, and a read control module;

A parsing module configured to, upon receipt of a transaction request of an upstream module, write a request identification of the transaction request into a FIFO, and send the transaction request to a memory; the write control module is configured to sequentially write the response data into a buffer area corresponding to a corresponding request identifier when receiving the response data returned by the memory for a transaction request; and the read control module is configured to read response data sequentially from the buffer area corresponding to the forefront request identifier in the FIFO and return the response data to the downstream module.

In the above mode b), by writing the request identifier of the transaction request and the allocated buffer address into the FIFO, when the response data needs to be written into the buffer module, the response data is written into the buffer address of the table item in the FIFO, which is arranged in the forefront table item and is buffered with the corresponding request identifier, and when the response data corresponding to the request identifier needs to be read from the buffer module and returned to the downstream module, the response data buffered in the buffer address of the table item in the forefront and is read from the buffer module and returned to the downstream module, so that the transaction request and the order of the response data with the same request identifier (corresponding to the same upstream module) can be realized in one FIFO and one buffer module, and the hardware resources are saved. And multiple upstream modules (masters) dynamically share the cache module, i.e., the cache address in the cache module for each transaction request is not fixed.

Compared with the mode of fixedly allocating the area of the shared cache for each upstream module (master), the dynamic cache sharing mode saves one-half of the bandwidth of N (N is the total number of the upstream modules connected with the same downstream module), and the cache can be fully utilized, and the interface and the interconnection network reach full bandwidth no matter a single upstream module (master) works independently or a plurality of or all the upstream modules (masters) work together.

In the case of the dynamic sharing buffer module (the above-mentioned mode b), when the response data needs to be written into the FIFO and the buffer address of the table item that is arranged in the forefront table item and is buffered with the corresponding request identifier, if the FIFO and the buffer address of the table item that is arranged in the forefront table item and is buffered with the corresponding request identifier already have data, the response data may be written into the updated FIFO and the buffer address of the table item that is arranged in the forefront table item and is buffered with the corresponding request identifier after the release of the table item.

In some embodiments, in the context of the dynamic shared buffer module (above-described mode b), the pointers of the FIFO include a first write pointer, a first read pointer, a plurality of second write pointers, and a plurality of second read pointers, where the plurality of second write pointers respectively correspond to different request identifiers, and the plurality of second read pointers respectively correspond to different request identifiers;

It can be understood that, by writing the request identifier of the transaction request and the allocated buffer address into the table item currently pointed by the first write pointer, and writing the table item identifier of the table item currently pointed by the first write pointer into the table item currently pointed by the corresponding second write pointer, and taking the table item currently pointed by the first write pointer as the new table item currently pointed by the second write pointer corresponding to the request identifier, when the response data needs to be written into the buffer module, the corresponding table item (the table item currently pointed by the second read pointer) is found by the corresponding second read pointer, then the response data is written into the buffer address in the table item, when the response data corresponding to the request identifier needs to be read from the buffer module and returned to the downstream module, the corresponding table item (the table item currently pointed by the first read pointer) is found according to the first read pointer, and then the response data is read from the buffer address in the table item and returned to the downstream module. A plurality of upstream modules (masters) are implemented to dynamically share the cache module.

The functions and updating manners of the first write pointer, the first read pointer and the second write pointer are similar to those of the static shared buffer module (the above manner a), and are not repeated here. In the scenario of the dynamic shared buffer module (the above mode b), the second read pointer is used for switching the first flag bit, and is also used for writing the response data to the buffer address in the table item currently pointed to by the second read pointer corresponding to the corresponding request identifier when the control module receives the response data returned by the memory for a transaction request, so that the step of writing the response data to the buffer address in the table item arranged at the forefront in the table item buffered with the corresponding request identifier in the FIFO is conveniently realized, and the order-preserving requirement of the downstream module (IP) is met.

In some embodiments, when a control module receives a transaction request, according to information carried in the transaction request (such as a burst size corresponding to a read transaction request), a buffer size required by response data of the transaction request may be determined, so that whether there is enough free buffer space (i.e., whether there is free buffer space greater than or equal to the required buffer size) in the buffer module may be determined according to the buffer size required by the response data of the transaction request, and if so, address information (i.e., an applied buffer address) of the corresponding free buffer space (whose size is equal to the required buffer size) is allocated to the transaction request.

The control module controls the writing and reading of the buffer module, so that the used buffer space and the idle buffer space in the buffer module are monitored at the same time, and whether the buffer module has enough idle buffer space can be judged.

In some embodiments, the cache address includes a cache start address and a required cache size (i.e., a size of response data corresponding to the read transaction request).

In some embodiments, when the transaction request is a read transaction request, the cache address includes a cache start address and a burst size (corresponding to the size of data that the read transaction request is to read back from memory).

In some embodiments, the cache address, when written into an entry, is written into the information field of the entry, as shown in FIG. 4.

In some embodiments, the control module may determine whether the entry is linked to other entries by determining whether an entry id is cached in the entry currently pointed to by the second read pointer during the updating of the entry currently pointed to by the second read pointer (i.e., during the updating of the second read pointer), and if the entry id is not cached in the entry currently pointed to by the second read pointer (i.e., the entry is not linked to other entries), the second read pointer will not be updated.

In some embodiments, to facilitate determining whether the second read pointer may be updated, a second flag bit may be added in the information field of the table entry of the FIFO to indicate whether the table entry links other table entries, where the second flag bit is inactive when no link exists, and is active when other table entries are linked. When a second read pointer needs to be updated, it is first determined whether a second flag bit in an entry pointed by the second read pointer is valid, so as to determine whether the second read pointer can be updated, and when the second flag bit in the entry pointed by the second read pointer is valid, the second read pointer can be updated. If the second flag bit in the entry is not toggled active (i.e., is inactive) until the entry to which the second read pointer is currently directed is released, then the second read pointer will be set to null.

Correspondingly, in the scenario of the dynamic sharing cache module (the above mode b), the control module is configured to receive a transaction request of an upstream module, allocate a corresponding cache address of the transaction request in the cache module, write a request identifier of the transaction request and the allocated cache address into an entry currently pointed by the first write pointer, send the transaction request to the memory, and write an entry identifier of the entry currently pointed by the first write pointer into an entry currently pointed by the corresponding second write pointer when the second write pointer corresponding to the request identifier is valid; and the second read pointer is further configured to switch the first flag bit in the currently pointed table entry of the second read pointer to be valid, and the second read pointer is updated to point to the table entry corresponding to the cached table entry identifier in the currently pointed table entry, and the method comprises the following steps:

In some embodiments, in the context of the dynamic shared cache module (mode b above), the FIFO pointer further comprises a third read pointer;

The third read pointer functions and updates in a manner similar to that in the case of the static shared buffer module (the above-described manner a), and will not be described here again.

In other embodiments, in the context of the dynamic shared cache module (mode b above), the FIFO pointer further comprises a third read pointer;

It may be understood that, because the updating manners of the first read pointer and the third read pointer are the same, a request identifier sent by the downstream module and a request identifier in an entry currently pointed to by the first read pointer received by the control module can be in one-to-one correspondence, when a request identifier sent by the downstream module is received and the request identifier is the same as the request identifier in the entry currently pointed to by the first read pointer, the control module may directly return to the downstream module according to the response data cached at the cache address in the entry currently pointed to by the first read pointer read from the cache module, or may return to the downstream module according to the corresponding cache address received together when the request identifier sent by the downstream module is received, and read the response data cached at the cache address from the cache module.

In some embodiments, in the context of the dynamic shared cache module (the foregoing manner b), when the request identifier of the transaction request is written into the FIFO, the control module simultaneously writes information (indicating information for indicating that the downstream module performs corresponding processing on the corresponding response data, such as operation type (including decompression, decryption, etc.)) carried in the transaction request user domain into the corresponding table entry, so when the FIFO sends the request identifier in the table entry currently pointed to by the third read pointer to the downstream module, other information (indicating information for indicating that the downstream module performs corresponding processing on the corresponding response data) in the table entry is sent to the downstream module together, so that the downstream module requests the corresponding response data from the control module through the request identifier, and performs corresponding processing on the requested response data according to the corresponding indicating information.

In some embodiments, in the context of the dynamic shared cache module (manner b above), the control module configured to write the request identification of the transaction request and the allocated cache address into the FIFO comprises:

The judging manner of the full state of the FIFO is similar to that in the case of the static shared buffer module (the above-mentioned manner a), and will not be repeated here.

In some embodiments, in the context of a dynamic shared cache module (mode b above), the control module includes an parsing module, a write control module, and a read control module; the analysis module is configured to receive the transaction request of the upstream module, apply for the corresponding cache address of the transaction request in the cache module from the read control module, write the request identification of the transaction request and the allocated cache address into the FIFO, and send the transaction request to the memory; the write control module is configured to write response data returned by the memory for a transaction request into a cache address in a forefront table item in the table item cached with the corresponding request identifier in the FIFO when the response data is received; and the read control module is configured to read response data cached at the cache address arranged in the forefront table item in the FIFO from the cache module and return the response data to the downstream module.

Correspondingly, in a scenario where the reorder buffer further includes a first arbitration module, the first arbitration module is configured to:

That is, the first arbitration module sends a handshake request to the parsing module, when receiving response information returned by the parsing module for the handshake request, selects one of the received transaction requests to send to the parsing module, and if no response information returned by the parsing module for the handshake request is received, the first arbitration module does not send the transaction request to the parsing module. In other words, the decompression module will back-pressure the first arbitration module, and the first arbitration module will keep (hold) the received transaction request, and each upstream module (master) cannot continuously send the transaction request to the first arbitration module, which is equivalent to the back-pressure of the first arbitration module to each upstream module (master), thereby realizing data flow control.

Further, as shown in fig. 5, the parsing module is further configured to: when a handshake request of the first arbitration module is received, a cache address corresponding to a transaction request corresponding to the handshake request in the cache module is applied to the read control module, and response information for the handshake request is returned to the first arbitration module after the cache address is applied.

That is, the first arbitration module triggers the analysis module to apply for the buffer address to the read control module through a handshake request, and if the buffer address is applied, the first arbitration module selects one of the received transaction requests to send to the analysis module, so as to complete handshake. If not (the buffer module does not have enough free buffer space), the first arbitration module will not send a transaction request to the resolution module.

In some embodiments, a plurality of mutually independent upstream modules (upstream IPs) that do not support out-of-order are interconnected with a downstream module (downstream IPs) that does not support out-of-order. For example, the upstream module (upstream IP) is a display controller, and the downstream module (downstream IP) is a display decompression module. The display controller typically includes a plurality of layers (layers) that support data out-of-order returns between layers, with data order returns being guaranteed within the same layer. Each layer opens an API interface to an application program, and the layers can work independently by a layer, such as playing video in full screen; or a plurality of layers can work simultaneously, such as superposition display, and a small window plays video when browsing the webpage. Under the scene, each layer is used as an upstream module and connected to the decompression module at the same downstream, and the scheme of the dynamic shared buffer module of the reordering buffer is adopted (the mode b), so that the order-preserving requirement under the scene can be realized, the bandwidth can be fully utilized when a single layer works and a plurality of layers work, and the highest performance is achieved (under the scheme of a static shared buffer module when a certain layer works independently, the buffer module cannot be fully utilized). Specifically, the control module receives a transaction request of any layer, allocates a corresponding cache address of the transaction request in the cache module, writes a request identifier of the transaction request and the allocated cache address into the FIFO, and sends the transaction request to the memory; when receiving response data returned by a memory aiming at a transaction request, a control module writes the response data into a cache address arranged in a forefront table item in the table item cached with a corresponding request identifier in the FIFO; the control module reads response data cached at a cache address arranged in the forefront table item in the FIFO from the cache module and returns the response data to the decompression module.

In some embodiments, a plurality of mutually independent upstream modules (upstream IP) are interconnected with one downstream module (downstream IP) that does not support outstanding transmissions. For example, the data read from the memory by the upstream module (upstream IP) needs to be decrypted before it can be used, and the downstream module (downstream IP) is a decryption engine that can only execute commands serially (neither supporting out-of-order nor multiple outstanding transfers). The multiple upstream modules (upstream IPs) may work simultaneously, or several of the multiple upstream modules may work together or one of the multiple upstream modules may work separately, and the scheme of combining the dynamic shared buffer module (the above manner b) of the reordering buffer with the third read pointer not only meets the requirement that the decryption engine does not support outstanding transmission, but also can ensure that the decryption engine can reach the maximum performance under the above various working scenarios (when one of the upstream IPs works alone, the buffer module cannot be fully utilized under the scheme of the static shared buffer module). Specifically, the control module receives a transaction request of any upstream module, allocates a corresponding cache address of the transaction request in the cache module, writes a request identifier of the transaction request and the allocated cache address into the FIFO, and sends the transaction request to the memory; when receiving response data returned by a memory aiming at a transaction request, a control module writes the response data into a cache address arranged in a forefront table item in the table item cached with a corresponding request identifier in the FIFO; the FIFO sends the request identification in the table item pointed by the third read pointer to the downstream module (decryption engine) so that the downstream module (decryption engine) requests corresponding response data from the control module through the request identification; when a request identifier sent by a downstream module (decryption engine) is received by the control module and is identical to the request identifier in the table item currently pointed to by the first read pointer, response data cached on a cache address in the table item currently pointed to by the first read pointer is read from the cache module and returned to the downstream module (decryption engine).

In some embodiments, if there is no scenario of separate operation for each upstream module (upstream IP), or the maximum bandwidth that each upstream module (upstream IP) can send is limited and smaller than the maximum bandwidth of the downstream module (downstream IP), the above static shared buffer scheme may be adopted, so that the area of the shared buffer is allocated to each upstream module (upstream IP) fixedly, and part of hardware resources are reduced.

Based on the same inventive concept, the embodiments of the present disclosure also provide a System-on-a-chip (SOC) including at least one upstream module, a downstream module, and the reorder buffer of any of the above embodiments.

In some embodiments, the reorder buffer may be disposed on an interconnect network of a system-on-chip.

Based on the same inventive concept, the embodiments of the present disclosure also provide an electronic assembly comprising the system-on-chip of any of the embodiments described above.

In some use scenarios, the product form of the electronic assembly is embodied as a graphics card; in other use cases, the product form of the electronic assembly is embodied as a CPU motherboard.

Based on the same inventive concept, the embodiments of the present disclosure also provide an electronic device including the above-described electronic component. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, a game console, or the like.

Based on the same inventive concept, the embodiments of the present disclosure further provide a data transmission method of a system on a chip, including:

In some embodiments, in the data transmission method of the system on chip, the pointers of the FIFO include a first write pointer, a first read pointer, a plurality of second write pointers and a plurality of second read pointers, where the plurality of second write pointers respectively correspond to different request identifiers, and the plurality of second read pointers respectively correspond to different request identifiers;

The specific implementation process of the data transmission method of the system-on-chip can be referred to the reorder buffer in any of the above embodiments, and will not be described herein again.

While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A reorder buffer comprising: FIFO, control module and buffer module;

The cache module comprises a plurality of cache areas respectively corresponding to different request identifications; the control module is configured to write a request identification of a transaction request into the FIFO and send the transaction request to the memory when the transaction request of the upstream module is received; the system is further configured to sequentially write response data returned by the memory for a transaction request into a cache region corresponding to a corresponding request identifier when the response data is received; the system is also configured to read response data sequentially from the buffer module from a buffer area corresponding to the request identifier arranged at the forefront in the FIFO and return the response data to a downstream module; or alternatively, the first and second heat exchangers may be,

The control module is configured to receive a transaction request of an upstream module, allocate a corresponding cache address of the transaction request in the cache module, write a request identifier of the transaction request and the allocated cache address into the FIFO, and send the transaction request to the memory; the system is further configured to write response data returned by the memory for a transaction request into a cache address in a forefront table item among table items cached with corresponding request identifications in the FIFO when the response data is received; and the response data buffered at the buffer address arranged in the forefront table item in the FIFO is read from the buffer module and returned to the downstream module.

2. The reorder buffer of claim 1, the pointers of the FIFO comprising a first write pointer, a first read pointer, a plurality of second write pointers, and a plurality of second read pointers, the plurality of second write pointers corresponding respectively to different request identifications, the plurality of second read pointers corresponding respectively to different request identifications;

The control module is configured to write a request identification of a transaction request into the FIFO and send the transaction request to the memory when the transaction request of the upstream module is received; the system is further configured to sequentially write response data returned by the memory for a transaction request into a cache region corresponding to a corresponding request identifier when the response data is received; the method is also configured to read response data sequentially read from a buffer area corresponding to the request identifier arranged at the forefront in the FIFO from the buffer module and return the response data to a downstream module, and comprises the following steps:

The control module is configured to write a request identifier of the transaction request into an item currently pointed by the first write pointer when receiving the transaction request of the upstream module, send the transaction request to the memory, and write the item identifier of the item currently pointed by the first write pointer into the item currently pointed by the corresponding second write pointer when the second write pointer corresponding to the request identifier is valid, wherein the second write pointer is updated to point to the item currently pointed by the first write pointer, and the first write pointer is updated to point to the next item of the item currently pointed by the first write pointer; the method comprises the steps of receiving response data returned by a memory for a transaction request, sequentially writing the response data into a buffer area corresponding to a corresponding request identifier, and switching a first flag bit in a table item currently pointed by a second read pointer corresponding to the request identifier corresponding to the response data to be valid, wherein the second read pointer is updated to point to a table item corresponding to a cached table item identifier in the table item currently pointed by the second read pointer; the method comprises the steps of receiving a request identifier of a first read pointer from a cache module, and reading response data from the cache area corresponding to the request identifier in the currently pointed table item of the first read pointer, wherein the request identifier is used for indicating the current pointed table item of the first read pointer; or alternatively, the first and second heat exchangers may be,

The control module is configured to receive a transaction request of an upstream module, allocate a corresponding cache address of the transaction request in the cache module, write a request identifier of the transaction request and the allocated cache address into the FIFO, and send the transaction request to the memory; the system is further configured to write response data returned by the memory for a transaction request into a cache address in a forefront table item among table items cached with corresponding request identifications in the FIFO when the response data is received; and is further configured to read response data buffered at a buffer address in the FIFO that is arranged in the foremost entry from the buffer module and return the response data to the downstream module, including:

The control module is configured to receive a transaction request of an upstream module, allocate a corresponding cache address of the transaction request in the cache module, write a request identifier of the transaction request and the allocated cache address into an item currently pointed by the first write pointer, send the transaction request to the memory, and write an item identifier of the item currently pointed by the first write pointer into an item currently pointed by the corresponding second write pointer when the second write pointer corresponding to the request identifier is valid, wherein the second write pointer is updated to point to the item currently pointed by the first write pointer, and the first write pointer is updated to point to a next item of the item currently pointed by the first write pointer; the method comprises the steps of receiving response data returned by a memory for a transaction request, writing the response data into a cache address in an item currently pointed to by a second read pointer corresponding to a request identifier corresponding to the response data, and switching a first flag bit in the item currently pointed to by the second read pointer to be valid, wherein the second read pointer is updated to point to an item corresponding to an item identifier cached in the item currently pointed to by the second read pointer; and the buffer module is further configured to read response data buffered at a buffer address in the table item currently pointed to by the first read pointer from the buffer module, return the response data to the downstream module, and update the first read pointer to point to the next table item of the table item currently pointed to by the first read pointer when the first flag bit in the table item currently pointed to by the first read pointer is valid.

3. The reorder buffer according to claim 2, the control module being configured to, upon receipt of a transaction request of an upstream module, write a request identification of the transaction request into an entry currently pointed to by the first write pointer, and send the transaction request to memory, and when a second write pointer corresponding to the request identification is valid, write an entry identification of the entry currently pointed to by the first write pointer into an entry currently pointed to by the corresponding second write pointer; and the method is further configured to switch the first flag bit in the table item currently pointed to by the second read pointer corresponding to the request identifier corresponding to the response data to be valid, wherein the second read pointer is updated to point to the table item corresponding to the cached table item identifier in the table item currently pointed to by the second read pointer, and comprises the following steps:

The control module is configured to write a request identifier of the transaction request into an item currently pointed by the first write pointer when receiving the transaction request of the upstream module, wherein a second flag bit in the item currently pointed by the first write pointer is invalid, send the transaction request to the memory, write the item identifier of the item currently pointed by the first write pointer into the item currently pointed by the corresponding second write pointer when the second write pointer corresponding to the request identifier is valid, and switch the second flag bit in the item currently pointed by the second write pointer to be valid; the method comprises the steps of receiving response data from a user, wherein the response data corresponds to a request identifier, and is further configured to switch a first flag bit in a table item currently pointed by a second read pointer corresponding to the request identifier to be valid, and updating the second read pointer to point to a table item corresponding to a cached table item identifier in the table item currently pointed by the second read pointer when the second flag bit in the table item currently pointed by the second read pointer is valid; or alternatively, the first and second heat exchangers may be,

The control module is configured to receive a transaction request of an upstream module, allocate a corresponding cache address of the transaction request in the cache module, write a request identifier of the transaction request and the allocated cache address into an item currently pointed by the first write pointer, send the transaction request to the memory, and write an item identifier of the item currently pointed by the first write pointer into an item currently pointed by the corresponding second write pointer when the second write pointer corresponding to the request identifier is valid; and the second read pointer is further configured to switch the first flag bit in the currently pointed table entry of the second read pointer to be valid, and the second read pointer is updated to point to the table entry corresponding to the cached table entry identifier in the currently pointed table entry, and the method comprises the following steps:

The control module is configured to receive a transaction request of an upstream module, allocate a corresponding cache address of the transaction request in the cache module, write a request identifier of the transaction request and the allocated cache address into an item currently pointed by the first write pointer, wherein a second flag bit in the item currently pointed by the first write pointer is invalid, send the transaction request to the memory, and write an item identifier of the item currently pointed by the first write pointer into the item currently pointed by the corresponding second write pointer when the second write pointer corresponding to the request identifier is valid, and switch the second flag bit in the item currently pointed by the second write pointer to be valid; and the second read pointer is updated to point to the table item corresponding to the cached table item identifier in the table item pointed at currently when the second flag bit in the table item pointed at currently by the second read pointer is valid.

4. The reorder buffer of claim 2, said FIFO pointer further comprising a third read pointer;

The control module is configured to read response data sequentially read from a buffer area corresponding to a request identifier in an item currently pointed to by the first read pointer from the buffer module, and return the response data to a downstream module, and includes:

the control module is configured to read response data from the cache module and sequentially read the response data from the cache area corresponding to the request identifier in the table item currently pointed by the first reading pointer to return to the downstream module when a request identifier sent by the downstream module is received and the request identifier is the same as the request identifier in the table item currently pointed by the first reading pointer; or alternatively, the first and second heat exchangers may be,

The control module is configured to read response data cached at a cache address in an entry currently pointed to by the first read pointer from the cache module, and return the response data to a downstream module, and includes:

The control module is configured to read response data cached at a cache address in an item currently pointed to by the first read pointer from the cache module and return the response data to the downstream module when a request identifier sent by the downstream module is received and the request identifier is the same as a request identifier in the item currently pointed to by the first read pointer.

5. The reorder buffer of claim 2, said FIFO pointer further comprising a third read pointer;

The FIFO is configured to send a request identifier and a cache address in the table item currently pointed to by the third read pointer to the downstream module, so that the downstream module requests corresponding response data from the control module through the request identifier and the cache address corresponding to the request identifier, and the third read pointer is updated to point to the next table item of the table item currently pointed to by the third read pointer;

The control module is configured to read response data cached at the cache address from the cache module according to the received cache address when a request identifier and a cache address corresponding to the request identifier sent by the downstream module are received and the received request identifier and the received cache address are respectively identical to the request identifier and the cache address in the table item currently pointed by the first read pointer, and return the response data cached at the cache address to the downstream module.

6. The reorder buffer of claim 2, wherein upon the first read pointer update, an entry pointed to prior to the first read pointer update is released.

7. The reorder buffer of claim 1, the control module configured to, upon receiving a transaction request of an upstream module, write a request identification of the transaction request into the FIFO, comprising:

The control module is configured to write a request identifier of a transaction request of an upstream module into the FIFO when the request is received and the FIFO is in a non-full state; or alternatively, the first and second heat exchangers may be,

The control module is configured to write the request identification of the transaction request and the allocated cache address into the FIFO, and includes:

The control module is configured to write the request identification of the transaction request and the allocated cache address into the FIFO when the FIFO is in a non-full state.

8. The reorder buffer of claim 1, said control module comprising an parse module, a write control module, and a read control module;

The parsing module is configured to write a request identifier of the transaction request into the FIFO and send the transaction request to the memory when the transaction request of the upstream module is received; the write control module is configured to sequentially write response data returned by the memory for a transaction request into a buffer area corresponding to a corresponding request identifier when the response data is received; the read control module is configured to read response data sequentially read from a buffer area corresponding to the forefront request identifier in the FIFO from the buffer module and return the response data to the downstream module; or alternatively, the first and second heat exchangers may be,

The analysis module is configured to receive a transaction request of an upstream module, apply for a cache address corresponding to the transaction request in the cache module from the read control module, write a request identifier of the transaction request and the allocated cache address into the FIFO, and send the transaction request to a memory; the write control module is configured to write response data returned by the memory for a transaction request into a cache address arranged in a forefront table item in the table item cached with a corresponding request identifier in the FIFO when the response data is received; the read control module is configured to read response data cached at a cache address in the forefront table item in the FIFO from the cache module and return the response data to the downstream module.

9. The reorder buffer of claim 8, further comprising a first arbitration module configured to:

And when receiving the transaction request of the upstream module, sending a handshake request to the analysis module, and when receiving response information returned by the analysis module for the handshake request, selecting the transaction request from the received transaction request to send the transaction request to the analysis module.

10. The reorder buffer of claim 9, the parse module further configured to:

When a handshake request of the first arbitration module is received, applying for a buffer address corresponding to a transaction request corresponding to the handshake request in the buffer module from the read control module, and after applying for the buffer address, returning response information aiming at the handshake request to the first arbitration module.

11. The reorder buffer of claim 1, further comprising a first arbitration module configured to:

receiving a transaction request of the upstream module;

And sending the received transaction requests to the control module one by one.

12. The reorder buffer of claim 1, further comprising a second arbitration module configured to:

13. A system on a chip comprising at least one upstream module, a downstream module and the reorder buffer of any one of claims 1 to 12.

14. An electronic assembly comprising the system-on-chip of claim 13.

15. An electronic device comprising the electronic assembly of claim 14.

16. A method for data transmission of a system on a chip, comprising:

When a transaction request of an upstream module is received, writing a request identification of the transaction request into a FIFO, and sending the transaction request to a memory; when response data returned by the memory aiming at a transaction request is received, writing the response data into a buffer area corresponding to a corresponding request identifier in a buffer module; reading response data sequentially read from a buffer area corresponding to the forefront request identifier in the FIFO from the buffer module, and returning the response data to a downstream module; the cache module comprises a plurality of cache areas respectively corresponding to different request identifications; or alternatively, the first and second heat exchangers may be,

Receiving a transaction request of an upstream module, distributing a corresponding cache address of the transaction request in a cache module, writing a request identification of the transaction request and the distributed cache address into a FIFO, and sending the transaction request to a memory; when response data returned by the memory aiming at a transaction request is received, writing the response data into a cache address arranged in the forefront table item in the table item cached with the corresponding request identifier in the FIFO; and reading response data cached at a cache address arranged in the forefront table item in the FIFO from the cache module, and returning the response data to the downstream module.

17. The method of claim 16, the pointers of the FIFO comprising a first write pointer, a first read pointer, a plurality of second write pointers, and a plurality of second read pointers, the plurality of second write pointers corresponding respectively to different request identifications, the plurality of second read pointers corresponding respectively to different request identifications;

When a transaction request of an upstream module is received, writing a request identification of the transaction request into a FIFO, and sending the transaction request to a memory; when response data returned by the memory aiming at a transaction request is received, writing the response data into a buffer area corresponding to a corresponding request identifier in a buffer module; reading response data sequentially read from a buffer area corresponding to the forefront request identifier in the FIFO from the buffer module, and returning the response data to a downstream module; the buffer memory module comprises a plurality of buffer memory areas corresponding to different request identifications respectively, and the buffer memory module comprises:

when a transaction request of an upstream module is received, writing a request identifier of the transaction request into an item currently pointed by the first write pointer, sending the transaction request to a memory, and when a second write pointer corresponding to the request identifier is valid, writing an item identifier of the item currently pointed by the first write pointer into an item currently pointed by the second write pointer corresponding to the second write pointer, wherein the second write pointer is updated to point to the item currently pointed by the first write pointer, and the first write pointer is updated to point to the next item of the item currently pointed by the first write pointer; when response data returned by the memory aiming at a transaction request is received, sequentially writing the response data into a buffer area corresponding to a corresponding request identifier of the response data, and switching a first zone bit in a table item currently pointed by a second read pointer corresponding to the request identifier corresponding to the response data to be valid, wherein the second read pointer is updated to point to the table item corresponding to the cached table item identifier in the table item currently pointed by the second read pointer; reading response data sequentially read from a buffer area corresponding to a request identifier in the table item currently pointed by the first reading pointer from the buffer module, and returning the response data to a downstream module, wherein when a first flag bit in the table item currently pointed by the first reading pointer is valid, the first reading pointer is updated to point to the next table item of the table item currently pointed by the first reading pointer; or alternatively, the first and second heat exchangers may be,

Receiving a transaction request of an upstream module, distributing a corresponding cache address of the transaction request in a cache module, writing a request identification of the transaction request and the distributed cache address into a FIFO, and sending the transaction request to a memory; when response data returned by the memory aiming at a transaction request is received, writing the response data into a cache address arranged in the forefront table item in the table item cached with the corresponding request identifier in the FIFO; reading response data buffered at a buffer address of a foremost entry in the FIFO from the buffer module and returning the response data to a downstream module, comprising:

Receiving a transaction request of an upstream module, distributing a corresponding cache address of the transaction request in the cache module, writing a request identification of the transaction request and the distributed cache address into an item currently pointed by the first write pointer, sending the transaction request to a memory, and writing an item identification of the item currently pointed by the first write pointer into an item currently pointed by the corresponding second write pointer when a second write pointer corresponding to the request identification is valid, wherein the second write pointer is updated to point to the item currently pointed by the first write pointer, and the first write pointer is updated to point to a next item of the item currently pointed by the first write pointer; when response data returned by the memory aiming at a transaction request is received, writing the response data into a cache address in a table item currently pointed by a second read pointer corresponding to a corresponding request identifier, and switching a first flag bit in the table item currently pointed by the second read pointer to be valid, wherein the second read pointer is updated to point to the table item corresponding to the cached table item identifier in the table item currently pointed by the second read pointer; and reading response data cached on a cache address in the table item currently pointed by the first reading pointer from the cache module, returning the response data to a downstream module, and updating the first reading pointer to point to the next table item of the table item currently pointed by the first reading pointer when a first flag bit in the table item currently pointed by the first reading pointer is valid.