CN117707875B - Method for generating test hardware circuit connection - Google Patents
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Abstract
The invention relates to the technical field of test hardware circuit generation, in particular to a method for generating test hardware circuit connection, which is based on test protocol standards, replaces manual realization of test circuit generation, provides components required by test hardware circuit connection and hierarchical relations among the components through a standard description file according to test requirements, matches port information of the components according to names of the components, and accordingly can determine a port description database connected between each input port and ports of other components according to the hierarchical relations among the components and the port information of the components, and finally can generate a corresponding test hardware circuit description file through the obtained port description database, thereby ensuring that the test hardware circuit description file is accurate and reliable, meanwhile, the connection of the test hardware circuit is not required to be performed through manual comparison with the test protocol standards, the operation is more efficient and quick, and the consistency and the test quality of the test hardware circuit are ensured.
Description
Technical Field
The invention relates to the technical field of test hardware circuit generation, in particular to a method for generating test hardware circuit connection.
Background
IJTAG (Internal Joint Test Action Group) is a standardized interface protocol for integrated circuit testing, which has importance in chip-level and circuit board-level testing, and not only can realize interoperability between chip-level and circuit board-level testing tools, so that the testing process is more efficient, but also has the advantages of providing access to internal testing resources of the chip, including internal registers, testing modes, fault injection and the like, and therefore, the use of iJTAG circuits for testing the chip becomes the current mainstream.
IJTAG relates to various equipment interfaces including BIST Access Port (BAP), boundary SCAN REGISTER (BSR) and the like, which have different protocols and signal transmission modes, if the test hardware circuit is designed manually according to a test standard protocol, the test hardware circuit is optimized by relying on professional judgment of a designer in the manual design process, and particularly when complex designs or test conditions are processed, the problems that connection does not meet the test standard protocol or connection is inaccurate in the drawing process exist, and the requirements of actual test hardware circuit connection cannot be met.
Disclosure of Invention
The invention aims to provide a generation method of test hardware circuit connection, which solves the problems of high difficulty and low efficiency of the conventional test hardware circuit connection through manual design.
The invention solves the technical problems as follows:
a method of generating a test hardware circuit connection, comprising the steps of:
s1, acquiring a specification description file containing component names and component hierarchical relations according to a test protocol standard;
S2, matching port information of each component in the specification description file according to the test protocol standard to obtain a mapping database;
s3, according to port information of each component in the mapping database, matching connection description of input ports of each component to obtain a port description database;
s4, obtaining a test hardware circuit description file according to the port description database.
Further defined, the step S1 includes:
s11, acquiring required component names and hierarchical relations among components according to test requirements; the hierarchical relationship comprises network hierarchies, and components of the same network hierarchy are homogeneous components;
S12, recording names of all components according to hierarchical relations among the components to obtain description files, determining layers of the components according to control levels of the components, and determining front and rear positions of the components in corresponding layers according to data flow directions among the same layers of the components;
s13, judging whether names of all components in the description file and the hierarchical relationship among all components meet the test protocol standard, if so, obtaining the standard description file, and if not, adjusting the names of the components and/or adjusting the hierarchical relationship among all components to re-execute the steps S11-S13.
Further defined, the step S2 includes:
s21, extracting names of all components in the specification description file;
s22, determining the functions of all the components according to the names of the components;
s23, carrying out function label identification on each component according to the functions of each component to obtain a preliminary database, wherein the function labels comprise STI function labels and TAP function labels;
And S24, according to the test protocol standard, port information of each component in the preliminary database is matched to obtain a mapping database.
Further defined, the step S3 includes:
S31, determining the hierarchical attribute of each component in the mapping database according to the hierarchical relationship among the components;
s32, determining an input port and an input port name of a corresponding component according to port information of each component;
s33, acquiring connection description of the corresponding input port according to the name of the input port of each component;
s34, obtaining a port description database according to the names of the components, the hierarchical properties of the components and the connection description of the input ports of the components.
Further defined, the step S33 includes the steps of:
acquiring a connection description of a from_so input port;
acquiring connection description of an SI input port;
Acquiring a connection description of a select input port;
Acquiring connection description of a CSU input port;
A connection description of the tck input port is obtained.
Further defined, the obtaining the connection description of the from_so input port includes the steps of:
sa1, selecting a component from the mapping database obtained in the step S31;
Step Sa2, judging whether the component is selected to be the first layer in step Sa1, if so, executing step Sa3, and if not, executing step Sa5;
sa3, judging whether a component exists in the next layer of the current component, if SO, connecting a from_so input port of the current component with an SO port of the last component in the next layer of the current component; if not, executing step Sa4;
Sa4, judging whether the current component is the first of the first layers, if so, connecting a from_so input port of the current component with a TDI port of a HostScanInterface interface; if not, the from_so input port of the current component is connected with the SO port of one component on the same layer;
Sa5, judging whether components of the STI function label exist in the same family of the current component, if so, connecting a from_so input port of the current component with a to_ ijtag _so port of the STI function label component; if not, executing step Sa6;
Sa6, judging whether a component exists in the next layer of the current component, if SO, connecting a from_so input port of the current component with an SO port of the last component in the next layer of the current component; if not, executing step Sa7;
Sa7, judging whether the current component is the first component of the layer where the current component is located, if SO, connecting a from_so input port of the current component with an SO port of a previous component of the same group of components on the current component; if not, the from_so input port of the current component is connected with the SO port of the last component on the same layer as the current component;
Sa8, re-selecting a component from step S31, and executing steps Sa2-Sa 8 until the connection description of the input port of each component from_so in the mapping database is completed.
Further defined, the obtaining the connection description of the SI input port includes the steps of:
sb1, selecting a component from the mapping database obtained in the step S31;
Sb2, judging whether the current component is the first component of the layer where the current component is located, if yes, executing a step Sb3, and if not, connecting an SI input port of the current component with an SO port of the previous component of the current component;
Sb3, judging whether the current component is in the first layer, if so, connecting an SI input port of the current component with a TDI port of a HostScanInterface interface; if not, executing a step Sb4;
And Sb4, selecting one component of a same group of components on the current component from the mapping database obtained in the step S31, and re-executing the step Sb2 until the connection description of the SI input port of each component in the mapping database is completed.
Further defined, obtaining a connection description of the select input port includes the steps of:
sc1, selecting a component from the mapping database obtained in the step S31;
Sc2, judging whether the current component is in the first layer, if so, executing step Sc3; if not, the select input port of the current component is connected with the ijtag _select port of the component of the first layer on the current component;
sc3, judging whether a component of the TAP function label exists in the mapping database, and if so, connecting a select input port of the current component with a to_ hostijtag port of the TAP function label component; if not, the select input port of the current component is connected with the HostScanInterface interface;
And step S4, re-selecting one component from the mapping database obtained in the step S31, and executing the steps Sc 2-Sc 4 until the connection description of the select input port of each component in the mapping database is completed.
Further defined, the obtaining the connection description of the CSU input port includes the steps of:
sd1, selecting a component from the mapping database obtained in the step S31;
sd2, judging whether the current component is the first layer, if so, executing a step Sd3; if not, executing the step Sd4;
sd3, judging whether a component of the TAP function label exists in the mapping database, if so, connecting a CSU input port of the current component with a CSU port of the TAP function label component; if not, the CSU input port of the current component is connected with the CSU port of the HostScanInterface interface;
Sd4, judging whether the same group component of the current component has the component of the STI function label, if so, connecting the CSU input port of the current component with the to_ ijtag _csu port of the STI function label component; if not, executing the step Sd3;
Sd5, re-selecting a component from the mapping database obtained in the step S31, and executing the steps Sd 2-Sd 5 until the connection description of the CSU input port of each component in the mapping database is completed.
Further defined, obtaining the connection description of the tck input port includes the steps of:
se1, selecting a component from the mapping database obtained in the step S31;
Se2, judging whether the current component is the first layer, if so, connecting a tck input port of the current component with a tck port of a HostScanInterface interface; if not, executing step Se3;
Se3, judging whether the same group component of the current component has the component of the STI function label, if so, connecting a tck input port of the current component with a to_ ijtag _tck port of the STI function label component; if not, the tck input port of the current component is connected with the tck port of the HostScanInterface interface;
And Se4, reselecting a component from the mapping database obtained in the step S31, and executing the steps Se 2-Se 4 until the connection description of the tck input port of each component in the mapping database is completed.
The invention has the beneficial effects that:
the invention is based on the test protocol standard, replaces manual realization of the generation of the test circuit, provides components required by the connection of the test hardware circuit and hierarchical relations among the components through the standard description file according to the test requirement, and matches the port information of each component according to the names of each component, so that the port description database connected between each input port and ports of other components can be determined according to the hierarchical relations among each component and the port information of each component, and finally the corresponding test hardware circuit description file can be generated through the obtained port description database.
Drawings
FIG. 1 is a diagram showing steps of a method for generating test hardware circuit connections according to the present invention;
FIG. 2 is a schematic diagram of a test hardware circuit according to the test requirements of embodiment 1 of the present invention;
FIG. 3 is a flow chart of a determination component from_so input port connection description of the present invention;
FIG. 4 is a flow chart of the determination component SI input port connection description of the present invention;
FIG. 5 is a flow chart of the determination component select input port connection description of the present invention;
Fig. 6 is a flow chart of a connection description of the input ports of the determining component CSU according to the present invention.
Detailed Description
Example 1
Referring to fig. 1, the present embodiment provides a method for generating test hardware circuit connection, including the following steps:
s1, acquiring a specification description file containing component names and component hierarchical relations according to a test protocol standard;
S2, matching port information of each component in the specification description file according to the test protocol standard to obtain a mapping database;
s3, according to the information of each port in the mapping database, matching connection description among ports of each component to obtain a port description database;
And S4, obtaining a test hardware circuit description file according to the port description database, and completing the generation of test hardware circuit connection.
Further illustratively, step S1 includes:
s11, acquiring required component names and hierarchical relations among components according to test requirements; the hierarchical relationship comprises network hierarchies, and components of the same network hierarchy are homogeneous components.
Before the test hardware circuit is ready to be generated, the functions and the functional logic related to the test hardware circuit are determined according to the test requirements, so that components required by the test hardware circuit can be determined, and a plurality of components are usually required, and therefore the hierarchical relationship among the components can be determined according to the test requirements, and the subsequent description is convenient.
The hierarchical relationship between components includes a network hierarchy (host-client) and also includes a logical hierarchy (parent-child), and components of the same network hierarchy are referred to as sibling components.
Referring to fig. 2, for example, the test requirements are that the component a to be tested, the component B to be tested and the component C to be tested need to be tested, that the component a to be tested and the component B to be tested need to be tested, that the component B to be tested, that the component a to be tested and the component B to be tested need to be tested, or that the component a to be tested, the component B to be tested and the component C to be tested need to be tested, so that the required SIB component and TDR component are determined according to the test requirements.
When the test of the component A to be tested is required, selecting a first SIB (Special Instruction Block, special instruction component) component to be connected with the component A to be tested through a first TDR (TEST DATA REGISTER ) component; when the component A to be tested and the component B to be tested are required to be tested, a second SIB component is selected to be connected with the first SIB component, and the second SIB component is connected with the component B to be tested through a second TDR component, so that whether the component B to be tested is controlled according to the second SIB component; when the component B to be tested is required to be tested, a third SIB component is selected to be connected with the component C to be tested through a third TDR component, so that the test requirement is met, at the moment, the first SIB component, the second TDR component, the second SIB component and the second TDR component are the same-family components, and the third SIB component and the third TDR component are the same-family components.
S12, recording names of the components according to the hierarchical relation among the components to obtain description files, determining layers of the components according to control levels of the components, and determining front and rear positions of the components in corresponding layers according to data flow directions among the same layers of the components.
The description file is a blank file before writing, the blank file is a description template file, namely after determining the hierarchical relationship among the components, names of the components are filled into the blank file according to the hierarchical relationship among the components, so that the description file can be obtained, and the hierarchical relationship among the components can be obtained when the description file is read, so that the efficiency of describing and reading the hierarchical relationship among the components is improved.
Referring to fig. 2, the first SIB component and the third SIB component control their subsequent components, respectively, so both the first SIB component and the third SIB component are described as a first layer; the first SIB component will send the data stream to the third SIB, so the first SIB component is described as a first layer first and the third SIB component is described as a first layer second; thus, a first TDR component is described as a second layer first, a second SIB component is described as a second layer second, and a third TDR component is described as a second layer third; the second TDR component is described as the third layer first.
S13, judging whether names of all components in the description file and the hierarchical relationship among all components meet the test protocol standard, if so, obtaining the standard description file, and if not, adjusting the names of the components and/or adjusting the hierarchical relationship among all components to re-execute the steps S11-S13.
In order to avoid the problem of input errors and the like of the obtained description file, all names of components and hierarchical relationships of the components in the description file need to meet the test protocol standard, for example, the IEEE1149.1 and the IEEE1687 protocol standard, if not, the names of the components need to be readjusted and/or the hierarchical relationships among the components need to be adjusted to re-execute step S11 until the description file meets the test protocol standard.
Further describing, step S2 includes:
s21, extracting names of all components in the specification description file.
S22, determining the functions of the components according to the names of the components.
S23, carrying out function label identification on each component according to the functions of each component to obtain a preliminary database, wherein the function labels comprise STI function labels and TAP function labels.
The names of the components, such as an SIB (mbist) component, an SIB (logic_test) component and a TDR (logic_test) component, are extracted from the specification description file, and according to the test protocol standard, the SIB (segment insertion bit) component can be used as a switch to access the TDR (test data register) component to the network of TAP (TAP controller) or remove the TDR from the TAP network, and the TDR component can control and configure the access network, or can control and observe the module through an embedded module interface, so that the SIB component is identified as an SIB function tag, the TDR component is identified as a TDR function tag, and a preliminary database containing the component function tag is obtained, and meanwhile, the specification description file is also contained in the preliminary database.
And S24, according to the test protocol standard, port information of each component in the preliminary database is matched to obtain a mapping database.
And matching port information of each component through a test protocol standard according to the name of each component.
For example, an internal database conforming to the IEEE1149.1 and IEEE1687 protocol standards is constructed, where the internal database includes component names conforming to the protocol standards and information of ports in corresponding components, so that the names of components in the preliminary database can be matched to the components with the same names and the port information corresponding to the current component in the internal database according to the names of the components in the preliminary database, so as to implement matching of port information of each component in the preliminary database, and obtain a mapping database including component names, component function labels, and component port information.
Further describing, step S3 includes:
S31, determining the hierarchical attribute of each component in the mapping database according to the hierarchical relationship among the components.
According to the specification description file in the mapping database, the name of each component is obtained, and a hierarchical attribute, namely a Label attribute, is added for the current component according to the hierarchical relationship of the current component, wherein the hierarchical relationship of each component is represented by the Label attribute, for example, the ith component of the nth layer is marked as Label: i-1_n-1", n and i are positive integers, label: i-1_n-1 is the hierarchy attribute of the ith component of the nth layer.
The component add hierarchy attribute of the first layer of the second layer is "Label:0_1", the 0 and lower horizontal lines representing the first layer may be omitted for the" Label "attribute of the first layer, i.e., the component addition hierarchy attribute of the second of the first layer is" Label:1", the component add hierarchy attribute of the first layer is" Label:0 "so that its hierarchical relationship can be determined from the" Label "attribute of the component.
S32, determining the input port and the input port name of the corresponding component according to the port information of each component.
S33, obtaining connection description of the corresponding input port according to the name of the input port of each component.
According to the test standard protocol, which of a plurality of ports in each component is an input port can be obtained through the mapping database, meanwhile, the name of the input port is determined, and the description of how the input ports of each component are connected can be conveniently confirmed according to the hierarchical relationship of each component and the input port function of each component.
S34, obtaining a port description database according to the names of the components, the hierarchical properties of the components and the connection description of the input ports of the components.
Example 2
In step S33, in the method for generating test hardware circuit connection provided in the present embodiment, the connection description of the input port includes: connection description of from_so input port, connection description of SI input port, connection description of select input port, connection description of CSU input port, and connection description of tck input port:
further illustratively, referring to FIG. 3, obtaining a connection description of the from_so input port includes the steps of:
sa1, selecting a component from the mapping database obtained in the step S31;
Step Sa2, judging whether the component is selected to be the first layer in step Sa1, if so, executing step Sa3, and if not, executing step Sa5;
Sa3, judging whether a component exists in the next layer of the current component, if so, connecting a from_so input port of the current component with a SO (Serial Out) port of the last component in the next layer of the current component; if not, executing step Sa4;
Sa4, judging whether the current component is the first of the first layers, if so, connecting a from_so input port of the current component with a TDI port of a HostScanInterface interface; if not, the from_so input port of the current component is connected with the SO port of one component on the same layer;
Sa5, judging whether components of the STI function label exist in the same family of the current component, if so, connecting a from_so input port of the current component with a to_ ijtag _so port of the STI function label component; if not, executing step Sa6;
Sa6, judging whether a component exists in the next layer of the current component, if SO, connecting a from_so input port of the current component with an SO port of the last component in the next layer of the current component; if not, executing step Sa7;
Sa7, judging whether the current component is the first component of the layer where the current component is located, if SO, connecting a from_so input port of the current component with an SO port of a previous component of the same group of components on the current component; if not, the from_so input port of the current component is connected with the SO port of the last component on the same layer as the current component;
Sa8, re-selecting a component from step S31, and executing steps Sa2-Sa 8 until the connection description of the input port of each component from_so in the mapping database is completed.
Further illustratively, referring to FIG. 4, obtaining a connection description of an SI input port includes the steps of:
sb1, selecting a component from the mapping database obtained in the step S31;
Sb2, judging whether the current component is the first component of the layer where the current component is located, if yes, executing a step Sb3, and if not, connecting an SI input port of the current component with an SO port of the previous component of the current component;
Sb3, judging whether the current component is in the first layer, if so, connecting an SI input port of the current component with a TDI port of a HostScanInterface interface; if not, executing a step Sb4;
And Sb4, selecting one component of a same group of components on the current component from the mapping database obtained in the step S31, and re-executing the step Sb2 until the connection description of the SI input port of each component in the mapping database is completed.
Further illustratively, referring to FIG. 5, obtaining a connection description of a select input port includes the steps of:
sc1, selecting a component from the mapping database obtained in the step S31;
Sc2, judging whether the current component is in the first layer, if so, executing step Sc3; if not, the select input port of the current component is connected with the ijtag _select port of the component of the first layer on the current component;
sc3, judging whether a component of the TAP function label exists in the mapping database, and if so, connecting a select input port of the current component with a to_ hostijtag port of the TAP function label component; if not, the select input port of the current component is connected with the HostScanInterface interface;
And step S4, re-selecting one component from the mapping database obtained in the step S31, and executing the steps Sc 2-Sc 4 until the connection description of the select input port of each component in the mapping database is completed.
Further illustratively, referring to FIG. 6, obtaining a connection description of a CSU input port includes the steps of:
sd1, selecting a component from the mapping database obtained in the step S31;
sd2, judging whether the current component is the first layer, if so, executing a step Sd3; if not, executing the step Sd4;
sd3, judging whether a component of the TAP function label exists in the mapping database, if so, connecting a CSU input port of the current component with a CSU port of the TAP function label component; if not, the CSU input port of the current component is connected with the CSU port of the HostScanInterface interface;
Sd4, judging whether the same group component of the current component has the component of the STI function label, if so, connecting the CSU input port of the current component with the to_ ijtag _csu port of the STI function label component; if not, executing the step Sd3;
Sd5, re-selecting a component from the mapping database obtained in the step S31, and executing the steps Sd 2-Sd 5 until the connection description of the CSU input port of each component in the mapping database is completed.
Further illustratively, obtaining a connection description of a tck input port includes the steps of:
se1, selecting a component from the mapping database obtained in the step S31;
Se2, judging whether the current component is the first layer, if so, connecting the tck input end of the current component with a tck port of a HostScanInterface interface; if not, executing step Se3;
Se3, judging whether the same group component of the current component has the component of the STI function label, if so, connecting a tck input port of the current component with a to_ ijtag _tck port of the STI function label component; if not, the tck input port of the current component is connected with the tck port of the HostScanInterface interface;
And Se4, reselecting a component from the mapping database obtained in the step S31, and executing the steps Se 2-Se 4 until the connection description of the tck input port of each component in the mapping database is completed.
Wherein, step S33 further comprises the steps of:
A connection description of the Reset input port is obtained.
Wherein, step Sf is the same as step Sd, and obtaining the connection description of the Reset input port includes the following steps:
sf1, selecting a component from the mapping database obtained in the step S31;
Sf2, judging whether the current component is a first layer, if so, executing a step Sf3; if not, executing a step Sf4;
sf3, judging whether a component of the TAP function label exists in the mapping database, and if so, connecting a Reset input port of the current component with a Reset port of the TAP function label component; if not, the Reset input port of the current component is connected with the Reset port of the HostScanInterface interface;
Sf4, judging whether the same group component of the current component has the component of the STI function label, if so, connecting a Reset input port of the current component with a to_ ijtag _reset port of the STI function label component; if not, executing a step Sf3;
And S5, re-selecting one component from the mapping database obtained in the step S31, and executing the steps Sf 2-Sf 5 until the connection description of the Reset input port of each component in the mapping database is completed.
Example 3
The present embodiment also provides an electronic device including a memory for storing a computer program and a processor that runs the computer program to cause the electronic device to execute the method of generating a test hardware circuit connection according to embodiment 2.
The present embodiment also provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the method of generating test hardware circuit connections of embodiment 2.
The present embodiment also provides a computer program product comprising a computer program which, when executed by a processor, implements the method of generating a test hardware circuit connection of embodiment 2.
The above is an embodiment of the present application. The foregoing embodiments and the specific parameters in the embodiments are only for clarity of the verification process of the application, and are not intended to limit the scope of the application, which is defined by the claims, and all equivalent structural changes made by the application of the specification and drawings of the application are included in the scope of the application.
Claims (9)
1. A method of generating a test hardware circuit connection, comprising the steps of:
s1, acquiring a specification description file containing component names and component hierarchical relations according to a test protocol standard;
S2, matching port information of each component in the specification description file according to the test protocol standard to obtain a mapping database;
s3, according to port information of each component in the mapping database, matching connection description of input ports of each component to obtain a port description database;
S4, obtaining a test hardware circuit description file according to the port description database;
The step S3 includes:
S31, determining the hierarchical attribute of each component in the mapping database according to the hierarchical relationship among the components;
s32, determining an input port and an input port name of a corresponding component according to port information of each component;
s33, acquiring connection description of the corresponding input port according to the name of the input port of each component;
s34, obtaining a port description database according to the names of the components, the hierarchical properties of the components and the connection description of the input ports of the components.
2. The method for generating test hardware circuit connections according to claim 1, wherein the step S1 comprises:
s11, acquiring required component names and hierarchical relations among components according to test requirements; the hierarchical relationship comprises network hierarchies, and components of the same network hierarchy are homogeneous components;
S12, recording names of all components according to hierarchical relations among the components to obtain description files, determining layers of the components according to control levels of the components, and determining front and rear positions of the components in corresponding layers according to data flow directions among the same layers of the components;
s13, judging whether names of all components in the description file and the hierarchical relationship among all components meet the test protocol standard, if so, obtaining the standard description file, and if not, adjusting the names of the components and/or adjusting the hierarchical relationship among all components to re-execute the steps S11-S13.
3. The method for generating test hardware circuit connections according to claim 2, wherein the step S2 comprises:
s21, extracting names of all components in the specification description file;
s22, determining the functions of all the components according to the names of the components;
s23, carrying out function label identification on each component according to the functions of each component to obtain a preliminary database, wherein the function labels comprise STI function labels and TAP function labels;
And S24, according to the test protocol standard, port information of each component in the preliminary database is matched to obtain a mapping database.
4. A method of generating test hardware circuit connections according to claim 3, wherein the connection description of the input port comprises: connection description of from_so input port, connection description of SI input port, connection description of select input port, connection description of CSU input port, and connection description of tck input port.
5. The method of generating test hardware circuit connections according to claim 4, wherein obtaining a connection description of the from_so input port comprises the steps of:
sa1, selecting a component from the mapping database obtained in the step S31;
Step Sa2, judging whether the component is selected to be the first layer in step Sa1, if so, executing step Sa3, and if not, executing step Sa5;
sa3, judging whether a component exists in the next layer of the current component, if SO, connecting a from_so input port of the current component with an SO port of the last component in the next layer of the current component; if not, executing step Sa4;
Sa4, judging whether the current component is the first of the first layers, if so, connecting a from_so input port of the current component with a TDI port of a HostScanInterface interface; if not, the from_so input port of the current component is connected with the SO port of one component on the same layer;
Sa5, judging whether components of the STI function label exist in the same family of the current component, if so, connecting a from_so input port of the current component with a to_ ijtag _so port of the STI function label component; if not, executing step Sa6;
Sa6, judging whether a component exists in the next layer of the current component, if SO, connecting a from_so input port of the current component with an SO port of the last component in the next layer of the current component; if not, executing step Sa7;
Sa7, judging whether the current component is the first component of the layer where the current component is located, if SO, connecting a from_so input port of the current component with an SO port of a previous component of the same group of components on the current component; if not, the from_so input port of the current component is connected with the SO port of the last component on the same layer as the current component;
Sa8, re-selecting a component from step S31, and executing steps Sa2-Sa 8 until the connection description of the input port of each component from_so in the mapping database is completed.
6. The method of generating test hardware circuit connections of claim 4, wherein obtaining a connection description of the SI input port comprises:
sb1, selecting a component from the mapping database obtained in the step S31;
Sb2, judging whether the current component is the first component of the layer where the current component is located, if yes, executing a step Sb3, and if not, connecting an SI input port of the current component with an SO port of the previous component of the current component;
Sb3, judging whether the current component is in the first layer, if so, connecting an SI input port of the current component with a TDI port of a HostScanInterface interface; if not, executing a step Sb4;
And Sb4, selecting one component of a same group of components on the current component from the mapping database obtained in the step S31, and re-executing the step Sb2 until the connection description of the SI input port of each component in the mapping database is completed.
7. The method of generating test hardware circuit connections of claim 4, wherein obtaining a connection description of the select input port comprises the steps of:
sc1, selecting a component from the mapping database obtained in the step S31;
Sc2, judging whether the current component is in the first layer, if so, executing step Sc3; if not, the select input port of the current component is connected with the ijtag _select port of the component of the first layer on the current component;
sc3, judging whether a component of the TAP function label exists in the mapping database, and if so, connecting a select input port of the current component with a to_ hostijtag port of the TAP function label component; if not, the select input port of the current component is connected with the HostScanInterface interface;
And step S4, re-selecting one component from the mapping database obtained in the step S31, and executing the steps Sc 2-Sc 4 until the connection description of the select input port of each component in the mapping database is completed.
8. The method of generating test hardware circuit connections of claim 4, wherein obtaining a connection description of the CSU input ports comprises:
sd1, selecting a component from the mapping database obtained in the step S31;
sd2, judging whether the current component is the first layer, if so, executing a step Sd3; if not, executing the step Sd4;
sd3, judging whether a component of the TAP function label exists in the mapping database, if so, connecting a CSU input port of the current component with a CSU port of the TAP function label component; if not, the CSU input port of the current component is connected with the CSU port of the HostScanInterface interface;
Sd4, judging whether the same group component of the current component has the component of the STI function label, if so, connecting the CSU input port of the current component with the to_ ijtag _csu port of the STI function label component; if not, executing the step Sd3;
Sd5, re-selecting a component from the mapping database obtained in the step S31, and executing the steps Sd 2-Sd 5 until the connection description of the CSU input port of each component in the mapping database is completed.
9. The method of generating test hardware circuit connections according to claim 4, wherein obtaining a connection description of the tck input port comprises the steps of:
se1, selecting a component from the mapping database obtained in the step S31;
Se2, judging whether the current component is the first layer, if so, connecting a tck input port of the current component with a tck port of a HostScanInterface interface; if not, executing step Se3;
Se3, judging whether the same group component of the current component has the component of the STI function label, if so, connecting a tck input port of the current component with a to_ ijtag _tck port of the STI function label component; if not, the tck input port of the current component is connected with the tck port of the HostScanInterface interface;
And Se4, reselecting a component from the mapping database obtained in the step S31, and executing the steps Se 2-Se 4 until the connection description of the tck input port of each component in the mapping database is completed.
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