CN117706409B - Battery cell charge and discharge test circuit and control method thereof - Google Patents
Battery cell charge and discharge test circuit and control method thereof Download PDFInfo
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- CN117706409B CN117706409B CN202410166516.7A CN202410166516A CN117706409B CN 117706409 B CN117706409 B CN 117706409B CN 202410166516 A CN202410166516 A CN 202410166516A CN 117706409 B CN117706409 B CN 117706409B
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- 238000012360 testing method Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000007599 discharging Methods 0.000 claims description 19
- 238000005070 sampling Methods 0.000 claims description 18
- 239000003990 capacitor Substances 0.000 claims description 13
- 238000004590 computer program Methods 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims description 9
- 238000004891 communication Methods 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 7
- 230000006399 behavior Effects 0.000 claims description 6
- 230000000295 complement effect Effects 0.000 claims description 6
- 230000003750 conditioning effect Effects 0.000 claims description 3
- 238000012544 monitoring process Methods 0.000 claims description 2
- 238000012546 transfer Methods 0.000 abstract description 5
- 238000005265 energy consumption Methods 0.000 abstract description 2
- 238000011084 recovery Methods 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 description 4
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052744 lithium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 230000007613 environmental effect Effects 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
- G01R31/396—Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
- G01R31/385—Arrangements for measuring battery or accumulator variables
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
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- Charge And Discharge Circuits For Batteries Or The Like (AREA)
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Abstract
The invention provides a battery cell charge and discharge test circuit and a control method thereof, wherein the circuit comprises: and the battery core terminals of the N power modules are respectively connected with N tested battery cores and are used for collecting the voltage and the current of the tested battery cores and determining the capacity of the auxiliary battery cores at the same time, so that the energy transfer between the auxiliary battery cores and the tested battery cores is realized, and the charge and discharge test of the N tested battery cores is realized under the condition of not connecting a power supply. The invention can realize energy transfer between the battery cores without power supply of an external power supply, can realize energy recovery and reutilization, saves energy sources and reduces the energy consumption and the operation cost of the system.
Description
Technical Field
The invention belongs to the technical field of battery testing, and particularly relates to a battery cell charge and discharge testing circuit.
Background
The lithium battery is widely applied in the energy storage field due to the advantages of high energy density, long cycle life, environmental protection, cleanness and the like. However, safety accidents of the lithium battery also occur sometimes, and the battery core needs to be subjected to charge and discharge tests when leaving a factory and in subsequent use so as to accurately evaluate the performance of the battery core and improve the safety of the battery. The battery cell charge and discharge test is important, capacity division and formation before delivery and regrouping during echelon utilization are all required to accurately obtain data such as battery capacity, charge and discharge characteristics and the like under specific charge and discharge conditions, and therefore an efficient and accurate charge and discharge tester is required. When the battery cell is subjected to charge and discharge test, the energy of the battery cell discharge needs to be effectively utilized, and the charge and discharge tester has the function of energy feedback.
The current energy feedback type charge and discharge tester connects the battery core in parallel to a direct current bus through a bidirectional DC/DC converter, charges and discharges the battery core, and the direct current bus is connected to a three-phase power supply through a bidirectional AC/DC converter, so that energy exchange with an external power supply is realized. However, the above solution has some problems: (1) is bulky; (2) High-power energy transfer with an external power supply is needed, and the loss is high.
Disclosure of Invention
In order to solve the above problems, an objective of the present invention is to provide a battery cell charge/discharge test circuit and a control method thereof.
In order to achieve the above purpose, the invention adopts the following technical scheme:
a cell charge-discharge test circuit comprising:
And the bus terminals of the 1+N power modules are connected with the direct current buses, the battery core terminal of the first power module is connected with the auxiliary battery core, and the battery core terminals of the N power modules are respectively connected with N tested battery cores and are used for controlling the charge and discharge voltage and current of the tested battery cores.
Preferably, the power module comprises a bus terminal, a communication terminal, a power unit and a singlechip; bus terminals of each power module are connected in parallel; the communication terminals of each power module are connected in parallel, the power module connected with the auxiliary battery cell is taken as a host, and the power module connected with the battery cell to be tested is taken as a slave.
Preferably, the power unit is a half-bridge inverter circuit, a half bridge arm is formed by connecting two MOS tubes in series, the drain electrode of the upper MOS tube is connected with the bus fuse and then is connected with the bus anode, the source electrode of the lower MOS tube is connected with the bus cathode and the cathode of the battery cell current sampling chip, and the connection point of the two MOS tubes is connected with the power inductor; the MOS transistor is connected with the Schottky diode in anti-parallel between the drain electrode and the source electrode, the MOS gate electrode adopts complementary driving signals, the switching frequency is 100 kHz-200 kHz, and the driving signals are provided with dead areas of 100 ns-200 ns.
Preferably, the power inductance value is 220 mu H-2200 mu H, and the power inductance is connected with the battery cell fuse and then connected with the battery cell anode; an indirect bus filter electrolytic capacitor between the drain electrode of the upper MOS and the source electrode of the lower MOS; the contact point of the power inductor and the fuse is connected with the positive electrode of the cell filter electrolytic capacitor, and the source electrode of the lower MOS is connected with the negative electrode of the cell filter electrolytic capacitor; the battery cell fuse is connected with the positive electrode of the battery cell, and the positive electrode of the battery cell current sampling chip is connected with the negative electrode of the battery cell.
Preferably, the voltage of the bus filter electrolytic capacitor is subjected to analog sampling and conversion by a singlechip after passing through an operational amplifier differential circuit, and is used as bus voltage; the voltage between the positive electrode and the negative electrode of the battery cell is subjected to analog sampling and conversion by a singlechip after passing through an operational amplifier differential circuit, and is used as the voltage of the battery cell; the battery cell current sampling chip is a CC6900SO current sensor, the output is connected with an RC low-pass filter, and the output is subjected to analog sampling and conversion by a singlechip after passing through an operational amplifier conditioning circuit to be used as battery cell current; the singlechip adjusts the duty ratio of an original driving signal according to the bus voltage, the cell voltage and the cell current; the original driving signal is generated by a singlechip, and a complementary driving signal with dead zone is formed after passing through a driver chip and is applied to the grid electrodes of the upper MOS tube and the lower MOS tube.
The invention also provides a control method of the battery cell charge-discharge test circuit, which comprises the following steps:
Step 1: starting all power modules, and monitoring bus voltage, cell voltage and cell current in real time;
Step 2: the power module host adjusts the bus voltage of the power module to 5V, and keeps constant, and the deviation is within +/-5%;
Step 3: the power module host computer sends the real-time power set value of each slave computer to the slave computer, and the slave computer calculates the real-time current set value according to the cell voltage;
step 4: if the real-time current set value of the slave is zero, the slave driver chip is in a stop state; if the real-time current set value of the slave is not zero, entering a step 5;
Step 5: the singlechip of the slave machine sets a driving signal according to the duty ratio of (bus voltage-cell voltage)/100% of bus voltage, and enables the slave machine driver chip to be in an operating state;
Step 6: the duty ratio of the driving signal is adjusted according to the current of the battery core, and if the battery core is in a charging state and the current of the battery core is smaller than a real-time current set value, the duty ratio is reduced; if the battery cell is in a charging state and the battery cell current is larger than the real-time current set value, the duty ratio is increased; if the battery cell is in a discharging state and the battery cell current is smaller than the real-time current set value, the duty ratio is increased; if the battery cell is in a discharging state and the battery cell current is larger than the real-time current set value, the duty ratio is reduced;
Step 7: in the test process, if the voltage of the host battery is higher than the upper limit protection value, the power module slave which is discharging the battery is stopped, and if the voltage of the host battery is lower than the lower limit protection value, the power module slave which is charging the battery is stopped. If the voltage of the slave battery is higher than the upper limit protection value, the charging behavior of the slave is stopped, and if the voltage of the slave battery is lower than the lower limit protection value, the discharging behavior of the slave is stopped.
The invention also provides an electronic device comprising a bus, a transceiver, a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the transceiver, the memory and the processor are connected through the bus, and the electronic device is characterized in that the computer program realizes the steps in the battery cell charge and discharge test circuit when being executed by the processor.
The invention also provides a computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when executed by a processor, implements the steps in a cell charge-discharge test circuit described above.
The battery cell charge and discharge test circuit and the control method thereof have the beneficial effects that: compared with the prior art, the invention can realize energy transfer between the battery cores without external power supply, can realize energy recovery and reutilization, saves energy sources and reduces the energy consumption and the running cost of the system.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a circuit diagram of a battery cell charge-discharge test according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a power module circuit according to an embodiment of the present invention;
FIG. 3 is a flow chart of a process step of setting the charge and discharge of the battery cell according to an embodiment of the present invention;
Fig. 4 is a control flow chart of a battery cell charging and discharging process according to an embodiment of the present invention.
Detailed Description
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1-4, a battery cell charge-discharge test circuit includes:
The battery cell charge and discharge test circuit comprises N+1 power modules and 1 auxiliary battery cell.
The power module comprises a bus terminal, a battery cell terminal, a communication terminal, a power unit and a singlechip.
And the N+1 power modules are connected in parallel, wherein the battery core terminals of the 1 power modules are connected with the auxiliary battery cores, and the battery core terminals of the N power modules are respectively connected with N tested battery cores.
The communication terminals are in an RS485 communication mode, all the communication terminals are connected in parallel, the power module connected with the auxiliary battery cell is taken as a host, and the power module connected with the battery cell to be tested is taken as a slave.
The power unit is a half-bridge inverter circuit, a half bridge arm is formed by connecting two MOS tubes in series, the drain electrode of the upper MOS tube is connected with the bus fuse and then is connected with the bus anode, the source electrode of the lower MOS tube is connected with the bus cathode and the cathode of the cell current sampling chip, and the connection point of the two MOS tubes is connected with the power inductor.
The MOS transistor is connected with the Schottky diode in anti-parallel between the drain electrode and the source electrode, the MOS gate electrode adopts complementary driving signals, the switching frequency is 100 kHz-200 kHz, and the driving signals are provided with dead areas of 100 ns-200 ns.
The power inductance value is 220 mu H-2200 mu H, and the power inductance is connected with the battery cell fuse and then connected with the battery cell anode.
And the value of the bus filter electrolytic capacitor is selected to be 100 mu F/A-200 mu F/A.
The contact point of the power inductor and the fuse is connected with the positive electrode of the cell filter electrolytic capacitor, the source electrode of the lower MOS is connected with the negative electrode of the cell filter electrolytic capacitor, and the cell filter electrolytic capacitor is selected to be 100 uF/A-200 uF/A.
The battery cell fuse is connected with the positive electrode of the battery cell, and the positive electrode of the battery cell current sampling chip is connected with the negative electrode of the battery cell.
The rated current of the bus fuse cannot be smaller than the maximum bus current, and the rated current of the cell fuse cannot be smaller than the maximum cell current.
The voltage of the bus filter electrolytic capacitor is subjected to analog sampling and conversion by the singlechip after passing through the operational amplifier differential circuit, and is used as the bus voltage.
The voltage between the positive electrode and the negative electrode of the battery cell is subjected to analog sampling and conversion by the singlechip after passing through the operational amplifier differential circuit, and is used as the voltage of the battery cell.
The battery cell current sampling chip is a CC6900SO current sensor, the output is connected with an RC low-pass filter, and the output is subjected to analog sampling and conversion by a singlechip after passing through an operational amplifier conditioning circuit to be used as the battery cell current.
The singlechip adjusts the duty ratio of the original driving signal according to the bus voltage, the cell voltage and the cell current.
The original driving signal is generated by a singlechip, and a complementary driving signal with dead zone is formed after passing through a driver chip and is applied to the grid electrodes of the upper MOS tube and the lower MOS tube. The driver chip is EG2104.
The invention also provides a method for setting the battery cell charging and discharging process and a method for controlling the battery cell charging and discharging process.
1. Control method of battery cell charge and discharge test circuit
(1) According to the charge-discharge cycle steps of the battery cell, a time-power curve is derived;
(2) According to the charging efficiency and the discharging efficiency of the battery cell charging and discharging test circuit, a converted time-power curve is obtained, wherein the new power of the charging process step = the original charging power/the charging efficiency, and the new power of the discharging process step = the original discharging power;
(3) Setting the time of the standing step in the curve as an adjustable parameter and restricting the adjustable range;
(4) Determining the number of the battery cells to be simultaneously involved in the test;
(5) Performing time shift on the converted time-power curve which is the same as the number (N) of the test circuit cores and superposing the power to obtain a superposed time-total power curve;
And (3) calculating the calculation time-power curve of each test cell according to the step (2), obtaining N curves in total, shifting the N curves on a time axis, aligning the N curves on the time axis, and superposing the corresponding powers of the N curves on the same time point to obtain a time-total power curve.
(6) Optimizing the time shift value of each curve and the time of the standing step by taking the minimum absolute value of the maximum power in the time-total power curve as a target;
(7) Calculating the total energy change value (energy loss value in the transfer process) of all the battery cells for one charge and discharge cycle according to a time-total power curve;
(8) And determining the capacity of the auxiliary battery cell according to the maximum power absolute value and the total energy change value.
(9) And downloading the charge-discharge cycle steps and the time shift value to the power module host.
2. Battery cell charge and discharge process control
(1) All power modules are started, and bus voltage, cell voltage and cell current are monitored in real time.
(2) The power module host regulates the bus voltage of the self module to 5V and keeps constant, and the deviation is within +/-5%.
(3) The power module host computer sends the real-time power set value of each slave computer to the slave computer, and the slave computer calculates the real-time current set value according to the cell voltage.
(4) If the real-time current set value of the slave is zero, the slave driver chip is in a stop state; if the real-time current set value of the slave is not zero, the step (5) is entered.
(5) The single chip microcomputer of the slave machine sets a driving signal according to the duty ratio of (bus voltage-cell voltage)/100% of the bus voltage, and enables the slave machine driver chip to be in an operation state.
(6) The duty ratio of the driving signal is adjusted according to the current of the battery core, and if the battery core is in a charging state and the current of the battery core is smaller than a real-time current set value, the duty ratio is reduced; if the battery cell is in a charging state and the battery cell current is larger than the real-time current set value, the duty ratio is increased; if the battery cell is in a discharging state and the battery cell current is smaller than the real-time current set value, the duty ratio is increased; and if the battery cell is in a discharging state and the battery cell current is larger than the real-time current set value, reducing the duty ratio.
(7) In the test process, if the voltage of the host battery is higher than the upper limit protection value, the power module slave which is discharging the battery is stopped, and if the voltage of the host battery is lower than the lower limit protection value, the power module slave which is charging the battery is stopped. If the voltage of the slave battery is higher than the upper limit protection value, the charging behavior of the slave is stopped, and if the voltage of the slave battery is lower than the lower limit protection value, the discharging behavior of the slave is stopped.
The invention also provides an electronic device comprising a bus, a transceiver, a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the transceiver, the memory and the processor are connected through the bus, and the electronic device is characterized in that the computer program realizes the steps in the battery cell charge and discharge test circuit when being executed by the processor.
Compared with the prior art, the beneficial effects of the electronic equipment provided by the invention are the same as those of the battery cell charge and discharge test circuit described in the technical scheme, and the description is omitted herein.
The invention also provides a computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when executed by a processor, implements the steps in a cell charge-discharge test circuit described above.
Compared with the prior art, the beneficial effects of the computer readable storage medium provided by the invention are the same as those of the battery cell charge and discharge test circuit described in the technical scheme, and the description is omitted here.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (4)
1. A battery cell charge-discharge test circuit, comprising:
1+N power modules, wherein bus terminals of all the power modules are connected with a direct current bus, a battery core terminal of a first power module is connected with an auxiliary battery core, and battery core terminals of N power modules are respectively connected with N tested battery cores and used for controlling charging and discharging voltages and currents of the tested battery cores;
The power module comprises a bus terminal, a battery cell terminal, a communication terminal, a power unit and a singlechip; bus terminals of each power module are connected in parallel; the communication terminals of each power module are connected in parallel, the power module connected with the auxiliary battery cell is taken as a host, and the power module connected with the battery cell to be tested is taken as a slave;
The power unit is a half-bridge inverter circuit, a half bridge arm is formed by connecting two MOS tubes in series, the drain electrode of the upper MOS tube is connected with the bus fuse and then is connected with the bus anode, the source electrode of the lower MOS tube is connected with the bus cathode and the cathode of the cell current sampling chip, and the connection point of the two MOS tubes is connected with the power inductor; the MOS transistor is connected with the Schottky diode in anti-parallel between the drain electrode and the source electrode, the MOS gate electrode adopts a complementary driving signal, the switching frequency is 100 kHz-200 kHz, and the driving signal is provided with a dead zone of 100 ns-200 ns;
The power inductance value is 220 mu H-2200 mu H, and the power inductance is connected with the battery cell fuse and then connected with the battery cell anode; an indirect bus filter electrolytic capacitor between the drain electrode of the upper MOS and the source electrode of the lower MOS; the contact point of the power inductor and the fuse is connected with the positive electrode of the cell filter electrolytic capacitor, and the source electrode of the lower MOS is connected with the negative electrode of the cell filter electrolytic capacitor; the battery cell fuse is connected with the positive electrode of the battery cell, and the positive electrode of the battery cell current sampling chip is connected with the negative electrode of the battery cell;
The voltage of the bus filter electrolytic capacitor is subjected to analog sampling and conversion by a singlechip after passing through an operational amplifier differential circuit, and is used as bus voltage; the voltage between the positive electrode and the negative electrode of the battery cell is subjected to analog sampling and conversion by a singlechip after passing through an operational amplifier differential circuit, and is used as the voltage of the battery cell; the battery cell current sampling chip is a CC6900SO current sensor, the output is connected with an RC low-pass filter, and the output is subjected to analog sampling and conversion by a singlechip after passing through an operational amplifier conditioning circuit to be used as battery cell current; the singlechip adjusts the duty ratio of an original driving signal according to the bus voltage, the cell voltage and the cell current; the original driving signal is generated by a singlechip, and a complementary driving signal with dead zone is formed after passing through a driver chip and is applied to the grid electrodes of the upper MOS tube and the lower MOS tube.
2. The control method of the battery cell charge and discharge test circuit is characterized by comprising the following steps of:
Step 1: starting all power modules, and monitoring bus voltage, cell voltage and cell current in real time;
Step 2: the power module host adjusts the bus voltage of the power module to 5V, and keeps constant, and the deviation is within +/-5%;
Step 3: the power module host computer sends the real-time power set value of each slave computer to the slave computer, and the slave computer calculates the real-time current set value according to the cell voltage;
step 4: if the real-time current set value of the slave is zero, the slave driver chip is in a stop state; if the real-time current set value of the slave is not zero, entering a step 5;
step 5: the singlechip of the slave machine sets a driving signal according to the duty ratio of (bus voltage-cell voltage)/100% of bus voltage, and enables the slave machine driver chip to be in an operating state;
Step 6: the duty ratio of the driving signal is adjusted according to the current of the battery core, and if the battery core is in a charging state and the current of the battery core is smaller than a real-time current set value, the duty ratio is reduced; if the battery cell is in a charging state and the battery cell current is larger than the real-time current set value, the duty ratio is increased; if the battery cell is in a discharging state and the battery cell current is smaller than the real-time current set value, the duty ratio is increased; if the battery cell is in a discharging state and the battery cell current is larger than the real-time current set value, the duty ratio is reduced;
Step 7: in the test process, if the voltage of the host battery is higher than an upper limit protection value, stopping the power module slave which discharges the battery, and if the voltage of the host battery is lower than a lower limit protection value, stopping the power module slave which charges the battery; if the voltage of the slave battery is higher than the upper limit protection value, the charging behavior of the slave is stopped, and if the voltage of the slave battery is lower than the lower limit protection value, the discharging behavior of the slave is stopped.
3. An electronic device comprising a bus, a transceiver, a memory, a processor and a computer program stored on the memory and operable on the processor, the transceiver, the memory and the processor being connected by the bus, characterized in that the computer program when executed by the processor implements the steps of a cell charge and discharge test circuit as claimed in claim 2.
4. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps in a cell charge and discharge test circuit as claimed in claim 2.
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| CN111572408A (en) * | 2020-05-29 | 2020-08-25 | 上海威迈斯新能源有限公司 | Method for heating power battery by using electric drive system and electric automobile |
| CN115836460A (en) * | 2021-06-04 | 2023-03-21 | 东洋系统株式会社 | Battery testing device and battery charging testing method |
| WO2023273301A1 (en) * | 2021-06-30 | 2023-01-05 | 易事特集团股份有限公司 | Buck-boost charge-discharge seamless switching control method and system |
| CN117134450A (en) * | 2023-08-10 | 2023-11-28 | 深圳市正浩创新科技股份有限公司 | SOC balance control method for parallel battery packs and related equipment |
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