CN117706178A

CN117706178A - Voltage monitoring circuit

Info

Publication number: CN117706178A
Application number: CN202410160241.6A
Authority: CN
Inventors: 赵鑫; 邓超
Original assignee: Shenzhen Chip Hope Micro-Electronics Ltd
Current assignee: Shenzhen Chip Hope Micro-Electronics Ltd
Priority date: 2024-02-05
Filing date: 2024-02-05
Publication date: 2024-03-15
Anticipated expiration: 2044-02-05
Also published as: CN117706178B

Abstract

The application discloses voltage monitoring circuit belongs to power electronics technical field, in this circuit, the positive input of comparator links to each other with the second end of first hysteresis module and the second end of first switch respectively, the first end of first switch links to each other with the first end of first hysteresis module, the first end of first hysteresis module is used for receiving target signal, the first end of first hysteresis module links to each other with the first end of signal holding module, the second end of signal holding module links to each other with the first end of second hysteresis module and the first end of second switch respectively, the second end of second hysteresis module and the second end of second switch all link to each other with the negative input of comparator, the control end of first switch and the control end of second switch all are used for receiving the output signal of comparator. The circuit can remarkably reduce the structural complexity and the logic complexity when monitoring the upward change condition and the downward change condition of the target signal.

Description

Voltage monitoring circuit

Technical Field

The invention relates to the technical field of power electronics, in particular to a voltage monitoring circuit.

Background

Currently, many chips need to monitor the change of the target signal to trigger some logic functions. Such as: the chip sets a preset threshold in the system, and monitors the upward change condition and the downward change condition of the target signal periodically. That is, if the target signal increases by more than a preset threshold value in the current monitoring period with respect to the output signal of the previous monitoring period, the chip outputs a high level signal. If the target signal is reduced by more than a preset threshold value in the current monitoring period relative to the output signal of the last monitoring period, the chip outputs a low-level signal. If the increased variation or the decreased variation of the target signal is smaller than the preset threshold value in the current monitoring period relative to the previous monitoring period, the chip keeps the output signal of the previous monitoring period unchanged, so that upward monitoring and downward monitoring of the target signal are realized.

In the prior art, a very complex circuit structure is usually designed on a chip to realize the logic function. Referring to fig. 1, fig. 1 is a block diagram of a prior art method for monitoring up and down a target signal. In the structure shown in fig. 1, two comparators M, a signal holding block 101, a latch 102, and a logic judging block 103 are provided. In this circuit, two comparators are used to monitor the upward and downward changes of the target signal Vin, respectively. In the application scene of high-precision quick response, the requirement on the response speed of the two comparators is high, and when the two comparators work simultaneously, not only large quiescent current is needed, but also a large space volume is needed to be occupied. Meanwhile, the output signals of the two comparators also need to be subjected to signal retention by a signal retention module, and a latch and logic judgment module is needed to carry out latch refreshing and logic judgment on the output signals of the two comparators, so that the logic complexity and the structural complexity of the monitoring circuit are higher. Currently, there is no more effective solution to this technical problem.

Therefore, how to reduce the logic complexity and the structural complexity of the voltage monitoring circuit when the up-change condition and the down-change condition of the target signal are monitored cycle by cycle is a technical problem to be solved by those skilled in the art.

Disclosure of Invention

In view of the above, the present invention is directed to a voltage monitoring circuit, which solves the technical problems of high logic complexity and high structural complexity of the voltage monitoring circuit when monitoring the upward change condition and the downward change condition of a target signal cycle by cycle. The specific scheme is as follows:

in order to solve the above technical problems, the present invention provides a voltage monitoring circuit, including: the device comprises a comparator, a first hysteresis module for generating a first hysteresis voltage, a second hysteresis module for generating a second hysteresis voltage, a first switch, a second switch and a signal holding module for sampling and holding an output signal of the comparator;

the positive input end of the comparator is respectively connected with the second end of the first hysteresis module and the second end of the first switch, the first end of the first switch is connected with the first end of the first hysteresis module, the first end of the first hysteresis module is used for receiving a target signal, the first end of the first hysteresis module is connected with the first end of the signal holding module, the second end of the signal holding module is respectively connected with the first end of the second hysteresis module and the first end of the second switch, the second end of the second hysteresis module and the second end of the second switch are both connected with the negative input end of the comparator, and the control end of the first switch and the control end of the second switch are both used for receiving an output signal of the comparator.

Preferably, the first hysteresis module and the second hysteresis module have the same structure.

Preferably, the first hysteresis module specifically includes: a first resistor; the second hysteresis module specifically comprises: a second resistor; the currents flowing through the first resistor and the second resistor are respectively a first preset current and a second preset current.

Preferably, the method further comprises: and the current generation module is used for generating the first preset current and the second preset current.

Preferably, the current generation module includes: the operational amplifier, the first PMOS tube, the second PMOS tube, the third PMOS tube, the first NMOS tube and the third resistor;

the positive input end of the operational amplifier is used for receiving a target voltage signal, the negative input end of the operational amplifier is respectively connected with the first end of the third resistor and the source electrode of the first NMOS tube, the second end of the third resistor is connected with the gate electrode of the first NMOS tube and the output end of the operational amplifier, the drain electrode of the first NMOS tube is respectively connected with the gate electrode of the first PMOS tube, the gate electrode of the second PMOS tube, the gate electrode of the third PMOS tube and the drain electrode of the first PMOS tube, the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are respectively connected with a VCC power supply, and the drain electrode of the second PMOS tube and the drain electrode of the third PMOS tube are respectively used for outputting the first preset current and the second preset current.

Preferably, the method further comprises: a fourth PMOS tube and a fifth PMOS tube;

the drain electrode of the fourth PMOS tube is connected with the first end of the first resistor, the grid electrode of the fourth PMOS tube is used for receiving the target signal, the drain electrode of the fifth PMOS tube is connected with the first end of the second resistor, the grid electrode of the fifth PMOS tube is connected with the second end of the signal holding module, and the source electrodes of the fourth PMOS tube and the fifth PMOS tube are grounded.

Preferably, the method further comprises: a first parasitic diode and a second parasitic diode;

the positive electrode of the first parasitic diode is connected with the source electrode of the fourth PMOS tube, the negative electrode of the first parasitic diode is connected with the drain electrode of the fourth PMOS tube, the positive electrode of the second parasitic diode is connected with the source electrode of the fifth PMOS tube, and the negative electrode of the second parasitic diode is connected with the drain electrode of the fifth PMOS tube.

Preferably, the signal holding module includes: the first buffer, the second buffer, the first capacitor, the second capacitor, the third switch and the fourth switch;

the input end of the first buffer is used for receiving the target signal, the output end of the first buffer is connected with the first end of the third switch, the second end of the third switch is connected with the first end of the first capacitor and the input end of the second buffer respectively, the second end of the first capacitor is grounded, the output end of the second buffer is connected with the first end of the fourth switch, the second end of the fourth switch is connected with the first end of the second capacitor, the second end of the second capacitor is grounded, the control end of the third switch is used for receiving a first control signal for sampling the target signal, and the control end of the fourth switch is used for receiving a second control signal for maintaining the target signal.

Preferably, the signal holding module includes: a third buffer, a third capacitor and a fifth switch;

the input end of the third buffer is used for receiving the target signal, the output end of the third buffer is connected with the first end of the fifth switch, the second end of the fifth switch is connected with the first end of the third capacitor, the second end of the third capacitor is grounded, and the control end of the fifth switch is used for receiving a third control signal for maintaining the target signal.

Preferably, the method further comprises: an inverter;

the input end of the inverter is connected with the output end of the comparator, the control end of the first switch is used for receiving the output signal of the comparator, and the control end of the second switch is used for receiving the output signal of the inverter.

Therefore, in the invention, because the signal holding module can sample and hold the output result of the comparator to obtain the sample and hold signal, when the comparator monitors the upward change condition of the target signal, the first hysteresis module is turned off through the first switch, and the second hysteresis module is turned on through the second switch, and at the moment, only the target signal is larger than the sample and hold signal by a second hysteresis voltage in the current monitoring period, the comparator outputs a high-level signal. If the target signal is smaller than the sample-and-hold signal by a second hysteresis voltage in the current monitoring period, the comparator will keep the current output result unchanged. When the comparator monitors the downward change condition of the target signal, the first hysteresis module is conducted through the first switch, the second hysteresis module is turned off through the second switch, and at the moment, only the sampling hold signal is larger than the signal of the target signal in the current monitoring period by a first hysteresis voltage, then the comparator outputs a low-level signal. If the sample-and-hold signal is less than the target signal by a first hysteresis voltage during the current monitoring period, the comparator will maintain the current output result unchanged. Compared with the prior art, in the voltage monitoring circuit, the logic judgment module, the latch and the comparator in the original voltage monitoring circuit are replaced by the hysteresis module and the switch which are simpler in circuit structure, and in the voltage monitoring circuit, the target signal can be monitored upwards and downwards only by executing corresponding logic judgment by the comparator, and the logic judgment module and the latch are not required to be used for logic judgment and signal latching, so that the structural complexity and the logic complexity in monitoring the upwards and downwards changing conditions of the target signal can be obviously reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

FIG. 1 is a diagram showing the structure of the prior art for up and down monitoring of a target signal;

FIG. 2 is a block diagram of a voltage monitoring circuit according to an embodiment of the present invention;

FIG. 3 is a block diagram of a second hysteresis module provided at the negative input of the comparator;

FIG. 4 is a block diagram of a first hysteresis module provided at the positive input of the comparator;

FIG. 5 is a block diagram of a comparator with a first hysteresis module, a second hysteresis module, and a switch at two inputs;

FIG. 6 is a block diagram of the voltage monitoring circuit of FIG. 2 with the first and second hysteresis modules set as resistors;

FIG. 7 is a block diagram of a current generation module according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of another voltage monitoring circuit according to an embodiment of the present invention;

fig. 9 is a block diagram of a signal holding module according to an embodiment of the present invention;

fig. 10 is a block diagram of another signal holding module according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 2, fig. 2 is a block diagram of a voltage monitoring circuit according to an embodiment of the present invention, where the circuit includes: the device comprises a comparator M, a first hysteresis module 11 for generating a first hysteresis voltage, a second hysteresis module 12 for generating a second hysteresis voltage, a first switch K1, a second switch K2 and a signal holding module SH for sampling and holding an output signal of the comparator M;

the positive input end of the comparator M is connected to the second end of the first hysteresis module 11 and the second end of the first switch K1, the first end of the first switch K1 is connected to the first end of the first hysteresis module 11, the first end of the first hysteresis module 11 is configured to receive the target signal Vin, the first end of the first hysteresis module 11 is connected to the first end of the signal holding module SH, the second end of the signal holding module SH is connected to the first end of the second hysteresis module 12 and the first end of the second switch K2, the second end of the second hysteresis module 12 and the second end of the second switch K2 are both connected to the negative input end of the comparator M, and the control end of the first switch K1 and the control end of the second switch K2 are both configured to receive the output signal of the comparator M.

The voltage monitoring circuit provided by the embodiment can remarkably reduce the structural complexity and the logic complexity when monitoring the upward change condition and the downward change condition of the target signal Vin. In this voltage monitoring circuit, it is necessary to set a bidirectional hysteresis voltage in advance at the positive input terminal and the negative input terminal of the comparator M.

Referring to fig. 3 and 4, fig. 3 is a structural diagram when a second hysteresis module is disposed at a negative input end of the comparator, and fig. 4 is a structural diagram when a first hysteresis module is disposed at a positive input end of the comparator. In fig. 3, the second hysteresis module 12 generates a second hysteresis voltage at the negative input of the comparator M. In fig. 4, the first hysteresis module 11 generates a first hysteresis voltage at the positive input of the comparator M.

Let the first hysteresis voltage generated by the first hysteresis module 11 be V1 and the second hysteresis voltage generated by the second hysteresis module 12 be V2. If the voltage value of the positive input terminal of the comparator M in FIG. 3 is Vin1 and the voltage value of the negative input terminal of the comparator M is a fixed value Vref, the comparator M will output a high level signal only if Vin1 is greater than or equal to Vref+V2. If the voltage value of the positive input end of the comparator M in FIG. 4 is Vin2 and the voltage value of the negative input end of the comparator M is a fixed value Vrerf, the comparator M outputs a low level signal only if Vin2 is not less than Vref-V1.

In practical applications, in order to enable the voltage monitoring circuit to monitor the upward and downward functions of the target signal Vin, a switch may be further provided in the circuits shown in fig. 3 and 4 to control the inversion point of the output signal of the comparator M. Referring to fig. 5 specifically, fig. 5 is a block diagram illustrating a case where a first hysteresis module, a second hysteresis module, and a switch are provided at two input terminals of a comparator.

In fig. 5, it is assumed that the voltage value of the positive input terminal of the comparator M is Vin, and the voltage value of the negative input terminal of the comparator M is Vref. When the first switch K1 is turned off and the second switch K2 is turned on, the structure diagram of fig. 5 at this time is equivalent to the structure diagram shown in fig. 4. In this case, if Vin is not less than Vref-V1, the comparator M outputs a low level signal; if Vin < Vref-V1, the comparator M will keep the original output state unchanged.

When the first switch K1 is turned on and the second switch K2 is turned off, the structure diagram of fig. 5 at this time is equivalent to that shown in fig. 3. In this case, if Vin1 is greater than or equal to Vref+V2, the comparator M will output a high level signal; if Vin1 < Vref+V2, the comparator M will keep the original output state unchanged.

In this embodiment, in order to realize the cycle-by-cycle monitoring function of the target signal Vin, a signal holding module SH may be added on the basis of fig. 5, and the signal holding module SH may sample and hold the output signal of the comparator M in the last monitoring cycle. Referring to fig. 2 specifically, the positive input end of the comparator M may be set as a signal of the target signal Vin in the current monitoring period, and the negative input end of the comparator M may be set as an output signal of the comparator M in the last monitoring period, that is, the signal holding module SH is used to sample and Hold the output signal of the comparator M in the last monitoring period, so as to obtain the sample and Hold signal vin_hold.

In fig. 2, a certain time may be selected for the comparator M to compare, and after the comparator M finishes the comparison, the output signal of the current monitoring period is transmitted to the sample-hold module SH. After the comparator M compares the signals at the two input ends, since the sample-Hold signal vin_hold in the sample-Hold module SH is refreshed by the signal of the target signal Vin in the current monitoring period, the signals at the two input ends of the comparator M are both the signals of the target signal Vin in the current monitoring period, and are equal to each other. Whether the output level of the comparator M is high or low before the sample-and-Hold signal vin_hold is refreshed, the current output state of the comparator M is maintained after the sample-and-Hold signal vin_hold is refreshed, because the voltage difference between the two input terminals of the comparator M is zero.

In this case, when the comparator M monitors the upward variation of the target signal Vin, only the first hysteresis module 11 is turned off by the first switch K1 and the second hysteresis module 12 is turned on by the second switch K2, and only the target signal Vin is larger than the sample-Hold signal vin_hold by the second hysteresis voltage V2 in the current monitoring period, the comparator M outputs a high-level signal in the upward direction. If the target signal Vin is smaller than the sample-Hold signal vin_hold by the second hysteresis voltage V2 in the current monitoring period, the comparator M keeps the current output result unchanged.

Similarly, when the comparator M monitors the downward change condition of the target signal Vin, only the first hysteresis module 11 is turned on by the first switch K1, and the second hysteresis module 12 is turned off by the second switch K2, and only the sample-Hold signal vin_hold is larger than the signal of the target signal Vin in the current monitoring period by the first hysteresis voltage V1, the comparator M outputs a low-level signal in the downward direction. If the sample-Hold signal vin_hold is smaller than the target signal Vin by the first hysteresis voltage V1 in the current monitoring period, the comparator M will keep the current output result unchanged.

In practical application, the first hysteresis voltage V1 and the second hysteresis voltage V2 may be set to the same voltage value, or the first hysteresis voltage V1 and the second hysteresis voltage V2 may be set to different voltage values, which is not particularly limited herein.

Compared with the prior art, in the voltage monitoring circuit, the logic judgment module, the latch and the comparator in the original voltage monitoring circuit are replaced by the hysteresis module and the switch which are simpler in circuit structure, and in the voltage monitoring circuit, the target signal can be monitored upwards or downwards only by executing corresponding logic judgment by the comparator, and the logic judgment module and the latch are not required to be used for logic judgment and signal latching, so that the structural complexity and the logic complexity in monitoring the upwards and downwards changing conditions of the target signal can be obviously reduced.

It can be seen that, in this embodiment, since the signal holding module can sample and hold the output result of the comparator, a sample and hold signal is obtained. When the comparator monitors the upward change condition of the target signal, the first hysteresis module is turned off through the first switch, the second hysteresis module is turned on through the second switch, and at the moment, only the target signal is larger than the sampling hold signal by a second hysteresis voltage in the current monitoring period, the comparator outputs a high-level signal. If the target signal is smaller than the sample-and-hold signal by a second hysteresis voltage in the current monitoring period, the comparator will keep the current output result unchanged. When the comparator monitors the downward change condition of the target signal, the first hysteresis module is conducted through the first switch, the second hysteresis module is turned off through the second switch, and at the moment, only the sampling hold signal is larger than the signal of the target signal in the current monitoring period by a first hysteresis voltage, then the comparator outputs a low-level signal. If the sample-and-hold signal is less than the target signal by a first hysteresis voltage during the current monitoring period, the comparator will maintain the current output result unchanged. Compared with the prior art, in the voltage monitoring circuit, the logic judgment module, the latch and the comparator in the original voltage monitoring circuit are replaced by the hysteresis module and the switch which are simpler in circuit structure, and in the voltage monitoring circuit, the target signal can be monitored upwards and downwards only by executing corresponding logic judgment by the comparator, and the logic judgment module and the latch are not required to be used for logic judgment and signal latching, so that the structural complexity and the logic complexity in monitoring the upwards and downwards changing conditions of the target signal can be obviously reduced.

Based on the above embodiment, this embodiment further describes and optimizes the technical solution, and as a preferred embodiment, the first hysteresis module 11 and the second hysteresis module 12 have the same structure.

In the present embodiment, the first hysteresis module 11 and the second hysteresis module 12 may also be provided as circuit modules having the same structure. It is conceivable that when the first hysteresis module 11 and the second hysteresis module 12 are provided as circuit modules having the same structure, not only is it convenient for the worker to build the voltage monitoring circuit, but also the structural layout of the voltage monitoring circuit can be made more neat.

Referring to fig. 6, fig. 6 is a block diagram illustrating a case where a first hysteresis module and a second hysteresis module in the voltage monitoring circuit shown in fig. 2 are set as resistors. As a preferred embodiment, the first hysteresis module 11 specifically comprises: a first resistor R1; the second hysteresis module 12 is specifically: a second resistor R2; the currents flowing through the first resistor R1 and the second resistor R2 are a first preset current I1 and a second preset current I2, respectively.

In this embodiment, in order to make the structures of the first hysteresis module 11 and the second hysteresis module 12 simpler and reduce the occupation amount of the voltage monitoring circuit to the space volume, the first hysteresis module 11 may be set to be the first resistor R1, and the first preset current I1 flows through the first resistor R1 to generate the first hysteresis voltage V1. Similarly, the second hysteresis module 12 may be further configured as a second resistor R2, and the second preset current I2 flows through the second resistor R2 to generate the second hysteresis voltage V2.

As a preferred embodiment, the voltage monitoring circuit further includes: and the current generation module is used for generating a first preset current I1 and a second preset current I2.

In order to make the first preset current I1 flowing through the first resistor R1 and the second preset current I2 flowing through the second resistor R2 more accurate and reliable, a current generating module for generating the first preset current I1 and the second preset current I2 may be further provided in the voltage monitoring circuit.

Specifically, in practical applications, the current generation module may be set as a constant current source circuit. The configuration of the constant current source circuit is not particularly limited, as long as the constant current source circuit can output the first preset current I1 and the second preset current I2.

Referring to fig. 7, fig. 7 is a block diagram of a current generating module according to an embodiment of the invention. As a preferred embodiment, the current generation module includes: the operational amplifier A, the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3, the first NMOS tube N1 and the third resistor R3;

the positive input end of the operational amplifier a is used for receiving a target voltage signal V0, the negative input end of the operational amplifier a is respectively connected with a first end of a third resistor R3 and a source electrode of a first NMOS tube N1, a second end of the third resistor R3 is grounded, a grid electrode of the first NMOS tube N1 is connected with an output end of the operational amplifier a, a drain electrode of the first NMOS tube N1 is respectively connected with a grid electrode of a first PMOS tube P1, a grid electrode of a second PMOS tube P2, a grid electrode of a third PMOS tube P3 and a drain electrode of the first PMOS tube P1, a source electrode of the second PMOS tube P2 and a source electrode of the third PMOS tube P3 are respectively connected with a VCC power supply, and a drain electrode of the second PMOS tube P2 and a drain electrode of the third PMOS tube P3 are respectively used for outputting a first preset current I1 and a second preset current I2.

In this embodiment, the current generating module may be configured as a current mirror, and thus the current generating module may be enabled to output and generate the first preset current I1 and the second preset current I2. In the current generation module shown in fig. 7, the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3 are mirror circuits. If the drain electrode of the first PMOS transistor P1 can output the current I0, the first preset current I1 output by the drain electrode of the second PMOS transistor P2 and the third preset current output by the third PMOS transistor P3 are both I0. Wherein i0=v0/R3, V0 is the voltage value of the target voltage signal V0, and R3 is the resistance value of the third resistor R3.

It should be noted that in the circuit diagram shown in fig. 1 in the prior art, two comparators are used to monitor the target signal up and down, and because of the mismatch of each comparator, it is difficult to test and repair the turning point of the output signal set in the voltage monitoring circuit in a high-precision application scenario. In the application, if the first hysteresis voltage V1 or the second hysteresis voltage V2 needs to be adjusted, the purpose of adjusting the first hysteresis voltage V1 and the second hysteresis voltage V2 can be achieved by directly adjusting the voltage value of V0 or the resistance value of the third resistor R3, so that the purpose of testing and adjusting the turning point of the output signal of the comparator can be achieved.

Obviously, through the technical scheme provided by the embodiment, the test and the adjustment of the turning point of the output signal of the comparator are more convenient for a worker to test and adjust when the voltage monitoring circuit is used.

Referring to fig. 8, fig. 8 is a block diagram of another voltage monitoring circuit according to an embodiment of the invention. As a preferred embodiment, the voltage monitoring circuit further includes: a fourth PMOS tube P4 and a fifth PMOS tube P5;

the drain electrode of the fourth PMOS transistor P4 is connected to the first end of the first resistor R1, the gate electrode of the fourth PMOS transistor P4 is configured to receive the target signal Vin, the drain electrode of the fifth PMOS transistor P5 is connected to the first end of the second resistor R2, the gate electrode of the fifth PMOS transistor P5 is connected to the second end of the signal holding module, and the source electrodes of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are both grounded.

It will be appreciated that if the target signal Vin and the sample-and-Hold signal vin_hold are not directly coupled into the circuit via the buffer, the current that generates the hysteresis voltage will have an effect on the target signal Vin and the sample-and-Hold signal vin_hold. Such as: the target signal Vin and the sample-Hold signal vin_hold are directly connected to the circuit through the capacitor terminals, and the capacitor is inevitably charged by the current generating hysteresis voltage, which affects the target signal Vin and the sample-Hold signal vin_hold, which is absolutely not allowed in high-precision application. In this embodiment, in order to avoid the above problem, a fourth PMOS transistor P4 and a fifth PMOS transistor P5 may be further disposed in the voltage monitoring circuit.

After the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are arranged in the voltage monitoring circuit, the fourth PMOS transistor P4 and the fifth PMOS transistor P5 can be regarded as two buffers with reliable performance and simple structure, so that the sampling precision when the target signal Vin and the sample Hold signal vin_hold are sampled can be ensured.

As a preferred embodiment, the voltage monitoring circuit further includes: a first parasitic diode D1 and a second parasitic diode D2;

the positive electrode of the first parasitic diode D1 is connected to the source electrode of the fourth PMOS transistor P4, the negative electrode of the first parasitic diode D1 is connected to the drain electrode of the fourth PMOS transistor P4, the positive electrode of the second parasitic diode D2 is connected to the source electrode of the fifth PMOS transistor P5, and the negative electrode of the second parasitic diode D2 is connected to the drain electrode of the fifth PMOS transistor P5.

As a preferred embodiment, the voltage monitoring circuit further includes: an inverter N;

the input end of the inverter N is connected to the output end of the comparator M, the control end of the first switch K1 is configured to receive the output signal u of the comparator M, and the control end of the second switch K2 is configured to receive the output signal nu of the inverter N.

In this embodiment, in order to enable the voltage monitoring circuit to perform better up-monitoring and down-monitoring on the target signal Vin, an inverter N may also be provided at the output end of the comparator M. Assuming that the output signal of the comparator M is u, the inverter N outputs a signal nu opposite to the output signal u of the comparator M. In this case, the output signal u of the comparator M can be used to control the on and off states of the first switch K1, and the output signal nu of the inverter N can be used to control the on and off states of the second switch K2.

Note that, the circuit diagram shown in fig. 8 is connected to the circuit diagram shown in fig. 7 through VCC, and in fig. 8, the sample-Hold signal vin_hold sent by the signal holding module SH is received through the gate of the fifth PMOS transistor P5.

Obviously, through the technical scheme provided by the embodiment, the convenience of staff in monitoring the target signal cycle by utilizing the voltage monitoring circuit can be further improved.

Based on the above embodiments, the technical solution is further described and optimized in this embodiment, please refer to fig. 9, and fig. 9 is a block diagram of a signal holding module provided in the embodiment of the present invention. As a preferred embodiment, the signal holding module SH includes: a first buffer B1, a second buffer B2, a first capacitor C1, a second capacitor C2, a third switch K3, and a fourth switch K4;

the input end of the first buffer B1 is configured to receive the target signal Vin, the output end of the first buffer B1 is connected to a first end of the third switch K3, a second end of the third switch K3 is respectively connected to a first end of the first capacitor C1 and an input end of the second buffer B2, a second end of the first capacitor C1 is grounded, the output end of the second buffer B2 is connected to a first end of the fourth switch K4, a second end of the fourth switch K4 is connected to a first end of the second capacitor C2, a second end of the second capacitor C2 is grounded, a control end of the third switch K3 is configured to receive a first control signal CT1 for sampling the target signal Vin, and a control end of the fourth switch K4 is configured to receive a second control signal CT2 for holding the target signal Vin.

In the present embodiment, the signal holding module SH is specifically described. In practical applications, if the change condition of the target signal Vin needs to be monitored at a specific time point, two buffers may be set in the signal holding module.

That is, the first control signal CT1 controls the on and off time of the third switch K3, so as to achieve the purpose of sampling the target signal Vin at a specific time point. Then, the second control signal CT2 controls the on and off time of the fourth switch K4, so as to achieve the purpose of maintaining and outputting the target signal Vin at a specific time point and obtaining the sample-Hold signal vin_hold.

Referring to fig. 10, fig. 10 is a block diagram of another signal holding module according to an embodiment of the invention. As a preferred embodiment, the signal holding module SH includes: a third buffer B3, a third capacitor C3 and a fifth switch K5;

the input end of the third buffer B3 is configured to receive the target signal Vin, the output end of the third buffer B3 is connected to the first end of the fifth switch K5, the second end of the fifth switch K5 is connected to the first end of the third capacitor C3, the second end of the third capacitor C3 is grounded, and the control end of the fifth switch K5 is configured to receive the third control signal CT3 for holding the target signal Vin.

In practical applications, if there is no special requirement or limitation on the sampling time point of the target signal Vin, in this case, only one buffer may be set in the signal holding module SH to sample and Hold the target signal Vin, so as to obtain the sample and Hold signal vin_hold.

Obviously, by the technical scheme provided by the embodiment, the signal holding module can be suitable for different application scenes.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing has outlined a detailed description of a voltage monitoring circuit in accordance with the present invention, wherein specific examples are presented herein to illustrate the principles and embodiments of the present invention, and the above examples are intended only to facilitate an understanding of the method of the present invention and the core concepts thereof; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims

1. A voltage monitoring circuit, comprising: the device comprises a comparator, a first hysteresis module for generating a first hysteresis voltage, a second hysteresis module for generating a second hysteresis voltage, a first switch, a second switch and a signal holding module for sampling and holding an output signal of the comparator;

2. The voltage monitoring circuit of claim 1, wherein the first hysteresis module and the second hysteresis module are identical in structure.

3. The voltage monitoring circuit of claim 2, wherein the first hysteresis module is specifically: a first resistor; the second hysteresis module specifically comprises: a second resistor; the currents flowing through the first resistor and the second resistor are respectively a first preset current and a second preset current.

4. A voltage monitoring circuit according to claim 3, further comprising: and the current generation module is used for generating the first preset current and the second preset current.

5. The voltage monitoring circuit of claim 4, wherein the current generation module comprises: the operational amplifier, the first PMOS tube, the second PMOS tube, the third PMOS tube, the first NMOS tube and the third resistor;

6. The voltage monitoring circuit of claim 5, further comprising: a fourth PMOS tube and a fifth PMOS tube;

7. The voltage monitoring circuit of claim 6, further comprising: a first parasitic diode and a second parasitic diode;

8. The voltage monitoring circuit of claim 1, wherein the signal holding module comprises: the first buffer, the second buffer, the first capacitor, the second capacitor, the third switch and the fourth switch;

9. The voltage monitoring circuit of claim 1, wherein the signal holding module comprises: a third buffer, a third capacitor and a fifth switch;

10. A voltage monitoring circuit according to any one of claims 1 to 9, further comprising: an inverter;