CN114156852A - Surge current control circuit of LDO linear voltage regulator - Google Patents
Surge current control circuit of LDO linear voltage regulator Download PDFInfo
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- CN114156852A CN114156852A CN202111442588.2A CN202111442588A CN114156852A CN 114156852 A CN114156852 A CN 114156852A CN 202111442588 A CN202111442588 A CN 202111442588A CN 114156852 A CN114156852 A CN 114156852A
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- 239000003990 capacitor Substances 0.000 claims description 27
- 238000001514 detection method Methods 0.000 claims description 6
- 238000005070 sampling Methods 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 239000003381 stabilizer Substances 0.000 claims 2
- 229910044991 metal oxide Inorganic materials 0.000 claims 1
- 150000004706 metal oxides Chemical class 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000013643 reference control Substances 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/025—Current limitation using field effect transistors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
The invention relates to the technical field of LDO (low dropout regulator) linear regulators, and discloses an inrush current control circuit of an LDO linear regulator. The invention controls the current of the output end at the starting moment by adding the surge current control circuit, prevents the damage of the power gauge and the output system caused by overhigh starting current, does not influence the current limiting value of the current limiting circuit during normal work, effectively improves the reliability of LDO application and prevents the damage of the LDO power supply to the power supply system.
Description
Technical Field
The invention relates to the technical field of LDO (low dropout regulator) linear regulators, in particular to a surge current control circuit of an LDO linear regulator.
Background
The LDO linear voltage regulator has the outstanding advantages of simple structure, low cost, low noise, low power consumption and small packaging size, and is widely applied to portable electronic equipment.
As shown in fig. 1, a conventional LDO includes peripheral components including an input capacitor CIN, an output capacitor COUT, and a load resistor RL, and an enable control circuit EN, a reference voltage VR generation circuit, an error amplifier EA, a Current limiting circuit Current Limit, feedback resistors RF1, and RF2 are included inside a chip. The working principle of the LDO is as follows: the input enable EN signal controls whether the whole circuit works or not, the output voltage is divided by feedback resistors RF1 and RF2, sampled and input to the reverse end of an error amplifier EA, compared with the reference voltage VR of the same-phase end of the error amplifier EA, the output is subjected to error amplification and Current Limit output of a Current limiting circuit, the grid potential of a power PMOS tube MP is controlled and adjusted at the same time, the FB potential is equal to the reference VR through adjustment and control, meanwhile, the output Current is controlled not to exceed a Limit value, the PMOS power tube is prevented from being damaged, and meanwhile, the output voltage VOUT is controlled.
At the moment of starting a traditional LDO (low dropout regulator), a power tube MP is conducted to charge an output capacitor COUT (capacitor COUT), the COUT generally adopts a ceramic capacitor, the ESR is small, the impedance between input and ground is low, a large surge current is generated, the current has great harmfulness, and if the problem is not solved, the power rail can be out of control, so that the system enters an undesirable state.
Disclosure of Invention
In order to solve the problem of starting surge of the traditional LDO, the invention provides the surge current control circuit of the LDO linear voltage regulator, which improves the application reliability of the LDO and prevents the damage of a power supply system caused by a power supply of the LDO.
In order to achieve the purpose, the invention provides the following technical scheme: the utility model provides a LDO linear regulator's inrush current control circuit, includes LDO linear regulator, still includes inrush current control circuit, inrush current control circuit is connected with LDO linear regulator for the control starts inrush current in the twinkling of an eye, prevents the too high damage that causes power rule and output system of starting current.
As a preferred embodiment of the present invention, the LDO linear regulator includes a peripheral component input capacitor CIN, an output capacitor COUT, and a load resistor RL, the chip includes an enable control circuit EN, a reference voltage VR, an error amplifier EA, a current limiting circuit, a power PMOS transistor MP, and feedback resistors RF1 and RF2, an output VOUT of the LDO linear regulator is divided by the feedback resistors RF1 and RF2 to obtain a sampling voltage FB, which is connected to an inverting input terminal of the error amplifier EA, a non-inverting input terminal of the error amplifier EA is connected to the reference voltage VR, an output pg of the error amplifier EA is connected to a gate of the power PMOS transistor MP, and an output terminal of the surge current limiting control circuit is connected to a negative terminal of the current limiting circuit.
As a preferred embodiment of the present invention, the surge current control circuit includes a VOUT voltage detection comparator, a time delay circuit, resistors R2, R3, R4, switches S1, S2; the VOUT voltage detection comparison circuit is a comparator, VOUT voltage is input to a positive end, reference voltage is input to a negative end, and a Dout signal is output to control an S1 switch and a time delay circuit.
In a preferred embodiment of the present invention, the reference voltage is 0.7V.
As a preferred embodiment of the present invention, the PMOS transistors MP1 and MP1 sample the mirror MP power transistor, the proportional mirror iout outputs Current, the i _ SENSE is output to the irrush Current Control circuit, the irrush Current Control circuit outputs V _ SENSE voltage to the negative terminal of the Current, the V _ SENSE voltage is compared with the reference voltage VR at the positive terminal for output, and when V _ SENSE is increased to VR, the output Current pg is made constant and does not increase any more by controlling the potential of the output Current pg
Compared with the prior art, the invention provides an inrush current control circuit of an LDO linear voltage regulator, which has the following beneficial effects:
according to the surge current control circuit of the LDO linear voltage regulator, the surge current control circuit is controlled by increasing the surge current, the instantaneous output end current is controlled and started, the damage to a power supply gauge and an output system caused by overhigh starting current is prevented, the current limiting value of the current limiting circuit in normal working is not influenced, the reliability of LDO application is effectively improved, and the damage to a power supply system caused by an LDO power supply is prevented.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a prior art LDO linear regulator;
FIG. 2 is an LDO linear regulator with an inrush current control circuit according to the present invention;
fig. 3 is an equivalent diagram of the inrush current control circuit of fig. 2;
fig. 4 is a circuit diagram of an embodiment of the inrush current control circuit of fig. 3.
Fig. 5 is a waveform diagram of the operation of fig. 2.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further described with the specific embodiments.
As shown in fig. 1 to 5, the present invention provides a technical solution: the utility model provides a LDO linear regulator's inrush current control circuit, includes LDO linear regulator, still includes inrush current control circuit, inrush current control circuit is connected with LDO linear regulator for the control starts inrush current in the twinkling of an eye, prevents the too high damage that causes power rule and output system of starting current.
In this embodiment (please refer to fig. 2), the LDO linear regulator includes a peripheral component input capacitor CIN, an output capacitor COUT and a load resistor RL, the chip includes an enable Control circuit EN, a reference voltage VR, an error amplifier EA, a Current limiting circuit, a power PMOS transistor MP, feedback resistors RF1 and RF2, an output VOUT of the LDO linear regulator is divided by the feedback resistors RF1 and RF2 to obtain a sampling voltage FB connected to a reverse input end of the error amplifier EA, a non-inverting input end of the error amplifier EA is connected to the reference voltage VR, an output pg of the error amplifier EA is connected to a gate of the power PMOS transistor MP, and an output end of the Inrush Current Control circuit is connected to a negative end of the Current limiting circuit, based on the prior art (please refer to fig. 1), a surge reference Control circuit Inrush is added; when the LDO is started and the set VOUT value is not reached, the internal EA and the Current Ilimit control MP are started to charge the output capacitor and the load by a Current limiting value; the charging Current reaches the surge Control circuit Inrush Current Control by adding the surge Control circuit Inrush Current Control and the Current Ilimit Control and combining the Control and the Control when starting.
In this embodiment (see fig. 3), the Inrush Current Control circuit includes a VOUT voltage detection comparator VOUT, a Time Delay circuit Time Delay, resistors R2, R3, R4, and switches S1 and S2; the VOUT voltage detection comparison circuit Detect VOUT is a comparator, VOUT voltage is input at a positive end, 0.7V reference voltage is input at a negative end, a Dout signal is output to control an S1 switch and a Time Delay circuit Time Delay, when VOUT is lower than 0.7V, Dout outputs a low signal, a switch S1 is controlled to be OFF, the Time Delay is controlled to be turned OFF, the Time Delay outputs a low signal at the moment, and S2 is controlled to be OFF; when VOUT is higher than 0.7V, Dout outputs a high signal, control S1 is ON, Time Delay is started, Time Delay output DTout2 controls S2 to be changed from OFF to ON after 200us of Delay, and equivalent resistance R (V _ SENSE-GND) between V _ SENSE and GND is R2// R3// R4; the ON/OFF state of the switches S1 and S2 controls whether the resistors R3 and R4 are connected between the V _ SENSE and the GND in parallel with the R2 or not, equivalently controls the resistance value of the resistors between the V _ SENSE and the GND, realizes different current limiting values in starting and normal working states, and achieves the control of the surge current at the starting moment;
the inrush current and the current limiting value of normal operation in the starting process are calculated as follows:
i_inrsh1＝KxVR/(R2) (VOUT<0.7V)
i_inrush2＝KxVR/(R2//R3) (0.7≤VOUT，Time Delay<200us)
i _ Limit ═ KxVR/(R2// R3// R4) (after start-up is complete)
In this embodiment, the power supply further includes a PMOS transistor MP1, an MP1 sampling mirror MP power transistor, a proportional mirror iout outputting a Current, an i _ SENSE outputting a voltage to an irrush Current Control circuit, the irrush Current Control circuit outputting a V _ SENSE voltage to a negative terminal of a Current Ilimit, comparing the V _ SENSE voltage with a reference voltage VR at the positive terminal, and outputting the V _ SENSE voltage and the reference voltage VR, wherein when the V _ SENSE voltage rises to VR, the output Current is constant and does not increase any more by controlling a pg potential.
Fig. 4 is an example of one circuit implementation of fig. 3, an inrush current control circuit, as follows: the surge current control circuit comprises I1, I1 is a comparator, and NMOS tubes N1, N2, N3 and N4; PMOS tubes MP1, MP 2; capacitances C1, CD, C2; current bias sources ib1, ibd; the positive input end of the I1 comparator is connected with VOUT, the negative input end of the I1 comparator is connected with 0.7V reference voltage, the output Dout is connected with the grid of an NMOS tube N1 and the grid of an NMOS tube N3, the grid of an NMOS tube N1 is connected with the output of the comparator I1, the source of the NMOS tube N1 is connected with the substrate GND, the drain of the NMOS tube is connected with the negative end of a current bias source ib1 and the positive end of a capacitor C1 and the grid of an NMOS tube N2 and the grid of a PMOS tube MP2, the grid of the NMOS tube N2 is connected with the positive end of C1, the grid of the PMOS tube MP2, the drain of the NMOS tube N1 and the negative end of a current source bias source ibd, the source of the NMOS tube N2 and the substrate are connected with GND, the drain of the NMOS tube N2 is connected with the positive end of a capacitor CD, the grid of the NMOS tube N869 and the drain of the current bias source 86d, the NMOS tube N8672 is connected with the output of the comparator I1 and the drain of the substrate R867, the drain of the NMOS tube N3, and the drain of the NMOS tube N867 is connected with the substrate R3, The drain electrode of the PMOS tube MP1, the drain electrode of the NMOS tube N4 and the positive end of the capacitor C2, the gate electrode of the NMOS tube N4 is connected with the drain electrode of the NMOS tube N2, the negative end of the current bias source ibd and the positive end of the capacitor CD, the source electrode of the NMOS tube N4 is connected with the positive end of the resistor R4, the substrate of the NMOS tube N4 is connected with GND, the drain electrode of the NMOS tube N4 is connected with the positive end of the resistor R2, the drain electrode of the PMOS tube MP1, the drain electrode of the NMOS tube N3 and the positive end of the capacitor C2, the gate electrode of the PMOS tube MP2 is connected with the negative end of the current bias source ibd 1 and the positive end of the capacitor C1, the gate electrode of the NMOS tube N2 and the drain electrode of the NMOS tube N1, the source electrode and the substrate of the PMOS tube MP2 are connected, the drain electrode of the PMOS tube MP2 is connected with the drain electrode of the current bias source ibd, the drain electrode of the PMOS tube MP2 and the drain electrode of the PMOS tube MP2 are connected with the drain electrode of the NMOS tube N2 and the drain electrode of the PMOS tube 2; the positive end of the current bias source ib1 is connected with VIN, and the negative end is connected with the drain of the NMOS transistor N1, the positive end of the capacitor C1, the gate of the NMOS transistor N2 and the gate of the PMOS transistor MP 2; the positive end of the current bias source ibd is connected with the drain electrode of the PMOS tube MP2, and the negative end of the current bias source ibd is connected with the drain electrode of the N2 of the NMOS tube, the positive end of the capacitor CD and the grid electrode of the NMOS tube N4; the negative end of the capacitor C1 is connected with GND, and the positive end of the capacitor C1 is connected with the negative end of a current bias source ib1, the drain electrode of an NMOS tube N1, the grid electrode of the NMOS tube N2 and the grid electrode of a PMOS tube MP 2; the negative end of the capacitor CD is connected with GND, and the positive end of the capacitor CD is connected with the negative end of the current bias source ibd, the drain electrode of the NMOS tube N2 and the gate electrode of the NMOS tube N4; the negative end of the capacitor C2 is connected with GND, the positive end of the capacitor C2 is connected with the drain electrode of the PMOS tube MP1, the drain electrode of the NMOS tube N4, the positive end of the resistor R2 and the drain electrode of the NMOS tube N3; the negative end of the resistor R2 is connected with GND, the positive end of the resistor R2 is connected with the positive end of the capacitor C2, the drain electrode of the PMOS tube MP1, the drain electrode of the NMOS tube N4 and the drain electrode of the NMOS tube N3; the negative end of the resistor R3 is connected with GND, and the positive end of the resistor R3 is connected with the source electrode of the NMOS transistor N3; the negative end of the resistor R4 is connected with GND, and the positive end of the resistor R4 is connected with the source electrode of the NMOS transistor N4;
dout is the output of the comparator Detect VOUT, when VOUT is lower than 0.7V, the Dout output is low, NMOS tubes N1 and N3 are controlled to be closed, meanwhile, the drain output of an N1 tube is high, the output is low through a reverse output DTout2, a grid of N4 is also controlled to be low, and at the moment, the V _ SENSE voltage value is the product of the resistance values of i _ SENSE and R2; when VOUT voltage rises to 0.7V, Dout is turned from low to high, NMOS tube N3 is controlled to be opened, meanwhile, the grid of NMOS tube N1 is controlled to be high, the potential of the drain of NMOS tube N1 and the grid of NMOS tube N2 are turned down, current bias source ibd starts to charge CD for the capacitor, when the charging delay time reaches CD VTHN/ibd, the delay time can be set to 200us through ibd and CD value adjustment, and NMOS tube N4 is opened; before the NMOS transistor N4 is turned on, the V _ SENSE voltage value is the product of the resistance values of i _ SENSE and R2// R3, and after the NMOS transistor N4 is turned on, the V _ SENSE voltage value is the product of the resistance values of i _ SENSE and R2// R3// R4
While there have been shown and described what are at present considered the fundamental principles and essential features of the invention and its advantages, it will be apparent to those skilled in the art that the invention is not limited to the details of the foregoing exemplary embodiments, but is capable of other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (5)
1. The utility model provides an inrush current control circuit of LDO linear regulator, includes LDO linear regulator, its characterized in that: still include the inrush current control circuit, the inrush current control circuit is connected with LDO linear voltage regulator for the control starts inrush current in the twinkling of an eye, prevents the too high damage that causes power rule and output system of starting current.
2. The inrush current control circuit of an LDO linear regulator according to claim 1, wherein: the LDO linear voltage stabilizer comprises a peripheral component input capacitor CIN, an output capacitor COUT and a load resistor RL, an enable control circuit EN, a reference voltage VR, an error amplifier EA, a current limiting circuit, a power PMOS tube MP, feedback resistors RF1 and RF2 are arranged inside a chip, a sampling voltage FB obtained after the output VOUT of the LDO linear voltage stabilizer is subjected to voltage division through the feedback resistors RF1 and RF2 is connected to the reverse input end of the error amplifier EA, the non-inverting input end of the error amplifier EA is connected with the reference voltage VR, the output pg of the error amplifier EA is connected with the grid electrode of the power PMOS tube MP, and the output end of the surge current control circuit is connected with the reverse end of the current limiting circuit.
3. The inrush current control circuit of an LDO linear regulator according to claim 2, wherein: the surge current control circuit comprises a VOUT voltage detection comparison circuit, a time delay circuit, resistors R2, R3 and R4 and switches S1 and S2; the VOUT voltage detection comparison circuit is a comparator, VOUT voltage is input to a positive end, reference voltage is input to a negative end, and a Dout signal is output to control an S1 switch and a time delay circuit.
4. The inrush current control circuit of an LDO linear regulator according to claim 3, wherein: the reference voltage is 0.7V.
5. The inrush current control circuit of an LDO linear regulator according to claim 3, wherein: the amplifier also comprises a PMOS (P-channel metal oxide semiconductor) tube MP1, an MP1 sampling mirror image MP power tube, a proportional mirror image iout output Current, an output i _ SENSE is input into an Inrush Current Control circuit, the Inrush Current Control circuit outputs V _ SENSE voltage to be input into the negative end of the Current Ilimit, the V _ SENSE voltage is compared with reference voltage VR of the positive end for output, and when the V _ SENSE voltage is increased to VR, the output Current is constant and does not increase any more by controlling pg potential.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111442588.2A CN114156852B (en) | 2021-11-30 | 2021-11-30 | Surge current control circuit of LDO linear voltage stabilizer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111442588.2A CN114156852B (en) | 2021-11-30 | 2021-11-30 | Surge current control circuit of LDO linear voltage stabilizer |
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| CN114156852A true CN114156852A (en) | 2022-03-08 |
| CN114156852B CN114156852B (en) | 2024-06-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115963882A (en) * | 2022-12-30 | 2023-04-14 | 南京微盟电子有限公司 | Current-limiting control circuit of linear voltage stabilizer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055311A (en) * | 2009-10-29 | 2011-05-11 | 炬力集成电路设计有限公司 | Linear voltage-stabilized power supply device and soft start method thereof |
| US20120249104A1 (en) * | 2011-03-30 | 2012-10-04 | Socheat Heng | Voltage regulator |
| CN103677038A (en) * | 2012-09-18 | 2014-03-26 | 株式会社理光 | Low-dropout regulator |
| US20160218613A1 (en) * | 2015-01-26 | 2016-07-28 | Vidatronic, Inc. | Inrush current controller for voltage regulators |
| CN113110694A (en) * | 2021-04-30 | 2021-07-13 | 南京邮电大学 | Low dropout regulator circuit with current surge suppression |
-
2021
- 2021-11-30 CN CN202111442588.2A patent/CN114156852B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055311A (en) * | 2009-10-29 | 2011-05-11 | 炬力集成电路设计有限公司 | Linear voltage-stabilized power supply device and soft start method thereof |
| US20120249104A1 (en) * | 2011-03-30 | 2012-10-04 | Socheat Heng | Voltage regulator |
| CN103677038A (en) * | 2012-09-18 | 2014-03-26 | 株式会社理光 | Low-dropout regulator |
| US20160218613A1 (en) * | 2015-01-26 | 2016-07-28 | Vidatronic, Inc. | Inrush current controller for voltage regulators |
| CN113110694A (en) * | 2021-04-30 | 2021-07-13 | 南京邮电大学 | Low dropout regulator circuit with current surge suppression |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115963882A (en) * | 2022-12-30 | 2023-04-14 | 南京微盟电子有限公司 | Current-limiting control circuit of linear voltage stabilizer |
| CN115963882B (en) * | 2022-12-30 | 2024-01-26 | 南京微盟电子有限公司 | Current-limiting control circuit of linear voltage stabilizer |
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| Publication number | Publication date |
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| CN114156852B (en) | 2024-06-21 |
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