CN117539309A - LDO circuit - Google Patents
LDO circuit Download PDFInfo
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- CN117539309A CN117539309A CN202311478752.4A CN202311478752A CN117539309A CN 117539309 A CN117539309 A CN 117539309A CN 202311478752 A CN202311478752 A CN 202311478752A CN 117539309 A CN117539309 A CN 117539309A
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- 239000003990 capacitor Substances 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
Abstract
The embodiment of the invention relates to the field of integrated circuits and discloses an LDO circuit, which comprises: LDO main body circuit and overshoot clamp circuit. The LDO main circuit comprises an operational amplifier, a first NMOS tube, a first PMOS tube, a second PMOS tube, a first capacitor, a second capacitor, a first resistor, a second resistor and a third resistor; the overshoot clamp circuit comprises a second NMOS tube; the source electrode of the second NMOS tube is connected with a second reference voltage, the grid electrode and the drain electrode are respectively connected with two sides of the second resistor, and the drain electrode is connected with a connecting node between the second capacitor and the second resistor; the maximum voltage of the output end of the operational amplifier is larger than the sum of the second reference voltage and the threshold voltage of the second NMOS tube. The LDO circuit can greatly reduce the overshoot voltage generated by the circuit and protect circuit elements while meeting the low-power consumption design of the operational amplifier.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to an LDO circuit.
Background
LDO (low dropout regulator, low dropout linear voltage regulator) has the outstanding advantages of low cost, low noise, small quiescent current, etc. In addition, the external components required by the LDO are few, and only one or two bypass capacitors are usually required, so that the LDO is widely applied to the field of integrated circuits.
However, since a larger capacitor is required in the LDO architecture to provide the capacitance required by the dominant pole, the capacitor is also continuously charged during the power-up of the LDO to reach the target voltage. After the output voltage reaches the target voltage without continuous boosting, the continuously charged capacitor can continuously output excessive current to the output end due to the fact that the capacitor cannot fall back to the normal working voltage quickly, so that the output of the LDO circuit is large in overshoot voltage.
Disclosure of Invention
The embodiment of the invention aims to provide an LDO circuit which can meet the low power consumption design of an operational amplifier, greatly reduce the overshoot voltage generated by the circuit and protect circuit elements.
In order to solve the technical problems, the embodiment of the invention provides an LDO circuit, an LDO main body circuit and an overshoot clamp circuit;
the LDO main body circuit comprises an operational amplifier, a first NMOS tube, a first PMOS tube, a second PMOS tube, a first capacitor, a second capacitor, a first resistor, a second resistor and a third resistor;
the output end of the operational amplifier is connected with the grid electrode of the first NMOS tube, and the second resistor and the second capacitor are sequentially connected in series between the output end of the operational amplifier and the ground; the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube; the source electrode of the first PMOS tube is connected with a power supply voltage, and the grid electrode of the first PMOS tube is connected with the drain electrode; the source electrode of the second PMOS tube is connected with a power supply voltage, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the second PMOS tube is connected with the first capacitor in series as one connecting passage between the output end of the LDO circuit and the ground, and the first resistor and the third resistor are connected with the other connecting passage between the drain electrode of the second PMOS tube and the ground in series in sequence; the inverting input end of the operational amplifier is connected with a connecting node between the first resistor and the third resistor, and the non-inverting input end of the operational amplifier is connected with a first reference voltage;
the overshoot clamp circuit comprises a second NMOS tube; the source electrode of the second NMOS tube is connected with a second reference voltage, the grid electrode and the drain electrode are respectively connected to two sides of the second resistor, and the drain electrode is connected to a connection node between the second capacitor and the second resistor;
and the maximum voltage of the output end of the operational amplifier is larger than the sum of the second reference voltage and the threshold voltage of the second NMOS tube.
In the LDO circuit described above, the second reference voltage is a fixed voltage generated by a current flowing from the power supply through the current mirror and the fourth resistor to ground on the fourth resistor.
In the LDO circuit described above, the second reference voltage is a fixed voltage generated by a current flowing from the power supply through the current mirror and the third NMOS transistor to ground at the drain of the third NMOS transistor.
In the LDO circuit described above, the second reference voltage is a fixed voltage generated by the current flowing from the power supply through the current mirror and the third PMOS to the ground at the source of the third PMOS.
Compared with the prior art, the embodiment of the invention clamps the voltage of the second capacitor to the second reference voltage by the overshoot clamp circuit before the output voltage of the LDO circuit reaches the target voltage, so that the second capacitor with higher voltage can not continuously supply power to the second capacitor with higher voltage after the output voltage reaches the target voltage to generate larger overshoot voltage, namely the LDO circuit in the embodiment has simple structure, and can achieve the effects of greatly shortening the establishment time of a large signal and reducing the output overshoot voltage while keeping the low power consumption of the amplifier.
Drawings
FIG. 1 is a schematic diagram of an LDO circuit according to an embodiment of the present invention;
fig. 2 is a circuit diagram of the generation of a second reference voltage Vclamp according to an embodiment of the present invention;
fig. 3 is a circuit diagram of the generation of the second reference voltage Vclamp according to an embodiment of the present invention;
fig. 4 is a circuit diagram of the generation of the second reference voltage Vclamp according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the following detailed description of the embodiments of the present invention will be given with reference to the accompanying drawings. However, those of ordinary skill in the art will understand that in various embodiments of the present invention, numerous technical details have been set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and with various changes and modifications based on the following embodiments.
An embodiment of the present invention relates to an LDO circuit, as shown in fig. 1, where the LDO circuit provided in this embodiment includes: an LDO main body circuit and an overshoot clamp circuit;
the LDO main body circuit comprises an operational amplifier A0, a first NMOS tube M0, a first PMOS tube M1, a second PMOS tube M2, a first capacitor C1, a second capacitor C0, a first resistor R1, a second resistor R2 and a third resistor R0;
the output end of the operational amplifier A0 is connected with the grid electrode of the first NMOS tube M0, and a second resistor R2 and a second capacitor C0 are sequentially connected in series between the output end of the operational amplifier A0 and the ground; the source electrode of the first NMOS tube M0 is grounded, and the drain electrode is connected with the drain electrode of the first PMOS tube M1; the source electrode of the first PMOS tube M1 is connected with the power supply voltage VDD, and the grid electrode is connected with the drain electrode; the source electrode of the second PMOS tube M2 is connected with the power supply voltage VDD, the grid electrode is connected with the grid electrode of the first PMOS tube M1, the drain electrode is connected with a first capacitor C1 in series on one connecting path between the output end of the LDO circuit and the ground, and a first resistor R1 and a third resistor R0 are connected in series on the other connecting path between the drain electrode of the second PMOS tube M2 and the ground in sequence; the reverse input end of the operational amplifier A0 is connected with a connecting node between the first resistor R1 and the third resistor R0, and the positive input end of the operational amplifier A0 is connected with a first reference voltage Vref;
the overshoot clamp circuit comprises a second NMOS tube M3; the source electrode of the second NMOS tube M3 is connected with a second reference voltage Vclamp, the grid electrode and the drain electrode are respectively connected with two sides of a second resistor R2, and the drain electrode is connected with a connecting node between a second capacitor C0 and the second resistor R2;
the maximum voltage at the output end of the operational amplifier A0 is greater than the sum of the second reference voltage Vclamp and the threshold voltage of the second NMOS transistor M3.
Specifically, the second capacitance C0 provides the capacitance required for the dominant pole, and the capacitance is large. Meanwhile, the second resistor R2 and the second capacitor C0 form a compensation zero point. Before starting to power up, the output voltage V0 at the output end of the operational amplifier A0 and the output voltage Vout at the output end of the LDO circuit (the drain electrode of the second PMOS transistor M2) are both 0. The process of LDO circuit operation can be seen as a process of raising the output voltage Vout to a target voltage and stabilizing the output power supply.
Specifically, the selection of the target voltage value of the output voltage Vout may be determined according to the actual requirement, but it should be noted that the selection of the first reference voltage Vref may be performed only after the determination of the target voltage value. Since the following relationship is satisfied between the reference voltage (first reference voltage Vref) connected to the positive input terminal of the operational amplifier A0 and the target voltage value of the output voltage Vout of the LDO circuit in which the operational amplifier A0 is located:
wherein, R0 is the resistance of the third resistor R0, R1 is the resistance of the first resistor R1, V1 is the target voltage value of the output voltage of the LDO circuit, and Vref is the first reference voltage value.
Specifically, in the above scheme, an amplifying relationship is formed between the first PMOS transistor M1 and the second PMOS transistor M2, where the first PMOS transistor M1 provides gate driving for the second PMOS transistor M2, and the first PMOS transistor M1 may be replaced by a resistor, which is not specifically limited in this application.
The following describes the operation of the LDO circuit of the present embodiment.
After starting to power up, the LDO circuit needs to charge the load first capacitor C1 by outputting current through the output end of the operational amplifier A0, and the operational amplifier A0 outputs current through the output end by comparing the voltage between the forward input end and the reverse input end. Along with the output current of the operational amplifier A0, the loop gradually raises the gate voltage of the first NMOS transistor M0 very high, far higher than the normal operating voltage, so as to provide enough pull-down capability to fully open the second PMOS transistor M2 to charge the first capacitor C1, thereby increasing the voltage on the first capacitor C1 (i.e., the output voltage Vout of the LDO circuit up to the target voltage. In the process of charging the first capacitor C1 to increase the output voltage Vout to the target voltage, the second capacitor C0 is also charged continuously, the voltage on the second capacitor C0 is also increased continuously, the voltage V0 at the output end of the operational amplifier A0 is also increased continuously, and the voltage on the second capacitor C0 is gradually close to V0.
In the above process, the change relationship between the voltage V0 at the output end of the operational amplifier A0 and the output voltage Vout of the LDO circuit basically satisfies the following formula (2): deltaV out ＝G·ΔV 0 3 ；
Wherein DeltaV out As the variation of the output voltage Vout of the LDO circuit, G is the gain of the entire LDO circuit loop, and is specifically determined by the capacitance of the first capacitor C1 and the second capacitor C0 and the maximum output current capability of the operational amplifier A0, and can be regarded as a constant, and the specific value of G is not limited in this application.
In the process that the voltage V0 at the output end of the operational amplifier A0 continuously increases, the voltage value of V0 is related to the first reference voltage Vref, the output voltage Vout and the amplification factor of the operational amplifier A0, and specifically satisfies the following relationship:
wherein A is the amplification factor of the operational amplifier A0, R0 is the resistance value of the third resistor R0, R1 is the resistance value of the first resistor R1, vout is the output voltage value of the LDO circuit, and Vref is the first reference voltage value. Vgs0 is VrefWhen the voltages are equal, the normal starting voltage of the first NMOS tube M0 can be ensured. Vgs0The magnitude of the overdrive voltage is the sum of the threshold voltage of the first NMOS transistor M0 and the overdrive voltage of the first NMOS transistor M0, and the magnitude of the overdrive voltage is related to the magnitude of the current passing through the first NMOS transistor M0.
When the voltage V0 at the output end of the operational amplifier A0 rises to be greater than the sum of the second reference voltage Vclamp and the threshold voltage of the second NMOS transistor M3, the second NMOS transistor M3 in the overshoot clamp is turned on, and the voltage of the second capacitor C0 is immediately pulled to the second reference voltage Vclamp after the second NMOS transistor M3 is turned on.
In time sequence, the operation of increasing the voltage V0 at the output terminal of the operational amplifier A0 to be greater than the sum of the second reference voltage Vclamp and the threshold voltage of the second NMOS transistor M3 to turn on the second NMOS transistor M3 should occur before the output voltage Vout reaches the target voltage. Therefore, at least the output voltage Vout is guaranteed to reach the target voltage, and the loop turns on the second NMOS transistor M3 before the gate voltage of the first NMOS transistor M0 drops back to the normal operating voltage. Since the output voltage Vout is fed back to the operational amplifier A0 after reaching the target voltage, the current and voltage at the output terminal of the operational amplifier A0 will immediately change to pull down V0. That is, once the voltage V0 at the output end of the operational amplifier A0 can make the output voltage Vout reach the target voltage, the voltage V0 at the output end of the operational amplifier A0 is pulled down immediately, and the maximum voltage V0 at the output end of the operational amplifier A0 is the voltage that can make the output voltage Vout reach the target voltage and trigger the feedback moment. In order to ensure that the voltage of the second capacitor C0 is pulled down before the output voltage Vout reaches the target voltage, it is necessary to set the maximum voltage at the output terminal of the operational amplifier A0 to be greater than the sum of the second reference voltage Vclamp and the threshold voltage of the second NMOS transistor M3. The maximum value of the voltage V0 at the output end of the operational amplifier A0 can reach the power supply voltage VDD, when the LDO is turned on, the LDO outputs to charge the load large capacitor C1, the gate voltage of the loop will be raised very high by the first NMOS transistor M0, which is far higher than the normal operating voltage, so that sufficient pull-down capability is provided to fully open the second PMOS transistor M2 to charge the first capacitor C1. (at the time of large signal establishment, due to V0 becomes very large during the process of charging the first capacitor C1, which is much larger than the sum of the second reference voltage Vclamp and the threshold voltage of the second NMOS transistor M3. ).
After the second NMOS M3 is turned on, the voltage on the second capacitor C0 becomes the second reference voltage Vclamp and remains stable, and after the output voltage Vout reaches the target voltage to trigger feedback so as to be pulled down, the voltage on the second capacitor C0 is discharged outwards in the magnitude of Vclamp and quickly drops to the working voltage. The overshoot voltage generated by the output of the LDO circuit during the voltage drop of Vclamp on the second capacitor C0 to the operating voltage is much smaller than the overshoot voltage of the output of the LDO circuit before clamping the second capacitor C0.
Compared with the related art, in the embodiment of the application, the voltage of the second capacitor is clamped to the second reference voltage by the overshoot clamping circuit before the output voltage of the LDO circuit reaches the target voltage, so that the second capacitor with higher voltage can not continuously supply power to the second capacitor after the output voltage reaches the target voltage, and the overshoot voltage can be reduced to about 1/27 of the original overshoot voltage by reasonable design. That is, the LDO circuit in this embodiment has a simple structure, and can achieve the effect of greatly shortening the setup time of a large signal and reducing the overshoot voltage output by the circuit while maintaining the low power consumption of the amplifier.
Another embodiment of the present invention relates to an LDO circuit, which is complementary to the foregoing embodiment, and specifically relates to the following:
in one example, in the above embodiment, the generating circuit of the second reference voltage Vclamp may be as shown in fig. 2, and the second reference voltage Vclamp may be: the current flowing from the power supply through the current mirror CM1 and the fourth resistor R4 to ground generates a fixed voltage across the fourth resistor R4.
In another example, in the above embodiment, the generating circuit of the second reference voltage Vclamp may be as shown in fig. 3, and the second reference voltage Vclamp may be: the current flowing from the power source through the current mirror CM1 and the third NMOS transistor M4 to ground generates a fixed voltage at the drain of the third NMOS transistor M4.
The drain electrode of the third NMOS transistor M4 is connected to the current mirror, the source electrode is grounded, the gate electrode is connected to the drain electrode, and the second reference voltage Vclamp may be a fixed voltage generated at the drain electrode of the third NMOS transistor M4.
In another example, in the above embodiment, the generating circuit of the second reference voltage Vclamp may be as shown in fig. 4, and the second reference voltage Vclamp may be: the current flowing through the current mirror CM1 and the third PMOS transistor M5 from the power supply generates a fixed voltage at the source of the third PMOS transistor M5.
The source electrode of the third PMOS transistor M5 is connected to the current mirror, the drain electrode is grounded, the gate electrode is connected to the drain electrode, and the second reference voltage Vclamp may be a fixed voltage generated at the source electrode of the third PMOS transistor M5.
Compared with the related art, the embodiment of the application provides multiple generation modes for the second reference voltage Vclamp, so that the second reference voltage Vclamp can be selected in multiple ways, accurate control of the value of the second reference voltage Vclamp is facilitated, and overshoot voltage reduction is better achieved.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of carrying out the invention and that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
Claims (4)
1. An LDO circuit, comprising: an LDO main body circuit and an overshoot clamp circuit;
the LDO main body circuit comprises an operational amplifier, a first NMOS tube, a first PMOS tube, a second PMOS tube, a first capacitor, a second capacitor, a first resistor, a second resistor and a third resistor;
the output end of the operational amplifier is connected with the grid electrode of the first NMOS tube, and the second resistor and the second capacitor are sequentially connected in series between the output end of the operational amplifier and the ground; the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube; the source electrode of the first PMOS tube is connected with a power supply voltage, and the grid electrode of the first PMOS tube is connected with the drain electrode; the source electrode of the second PMOS tube is connected with a power supply voltage, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the second PMOS tube is connected with the first capacitor in series as one connecting passage between the output end of the LDO circuit and the ground, and the first resistor and the third resistor are connected with the other connecting passage between the drain electrode of the second PMOS tube and the ground in series in sequence; the inverting input end of the operational amplifier is connected with a connecting node between the first resistor and the third resistor, and the non-inverting input end of the operational amplifier is connected with a first reference voltage;
the overshoot clamp circuit comprises a second NMOS tube; the source electrode of the second NMOS tube is connected with a second reference voltage, the grid electrode and the drain electrode are respectively connected to two sides of the second resistor, and the drain electrode is connected to a connection node between the second capacitor and the second resistor;
and the maximum voltage of the output end of the operational amplifier is larger than the sum of the second reference voltage and the threshold voltage of the second NMOS tube.
2. The circuit of claim 1, wherein the second reference voltage is a fixed voltage developed across the fourth resistor by a current from a power source through a current mirror and the fourth resistor to ground.
3. The circuit of claim 1, wherein the second reference voltage is a fixed voltage generated by a current from a power supply through a current mirror and a third NMOS transistor to ground at a drain of the third NMOS transistor.
4. The circuit of claim 1, wherein the second reference voltage is a fixed voltage generated by a current from a power supply through a current mirror and a third PMOS transistor to ground at a source of the third PMOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311478752.4A CN117539309A (en) | 2023-11-07 | 2023-11-07 | LDO circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311478752.4A CN117539309A (en) | 2023-11-07 | 2023-11-07 | LDO circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117539309A true CN117539309A (en) | 2024-02-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311478752.4A Pending CN117539309A (en) | 2023-11-07 | 2023-11-07 | LDO circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117539309A (en) |
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2023
- 2023-11-07 CN CN202311478752.4A patent/CN117539309A/en active Pending
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