CN117693189A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN117693189A CN117693189A CN202211041612.6A CN202211041612A CN117693189A CN 117693189 A CN117693189 A CN 117693189A CN 202211041612 A CN202211041612 A CN 202211041612A CN 117693189 A CN117693189 A CN 117693189A
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- semiconductor device
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- metal oxide
- oxide semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims description 40
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 42
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000007789 gas Substances 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 170
- 230000002093 peripheral effect Effects 0.000 description 36
- 239000003990 capacitor Substances 0.000 description 18
- 101150099798 GSK1 gene Proteins 0.000 description 15
- 238000005530 etching Methods 0.000 description 11
- JESCETIFNOFKEU-SJORKVTESA-N (2s,5r)-5-[4-[(2-fluorophenyl)methoxy]phenyl]pyrrolidine-2-carboxamide Chemical compound N1[C@H](C(=O)N)CC[C@@H]1C(C=C1)=CC=C1OCC1=CC=CC=C1F JESCETIFNOFKEU-SJORKVTESA-N 0.000 description 6
- 101100230208 Oryza sativa subsp. japonica GSK2 gene Proteins 0.000 description 6
- 239000004020 conductor Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000005245 sintering Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000006731 degradation reaction Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- Semiconductor Memories (AREA)
Abstract
The present invention provides a semiconductor device and a method of manufacturing the same, the semiconductor device including: the semiconductor device comprises a first metal oxide semiconductor device, a second metal oxide semiconductor device, a first dielectric layer, a stop layer and a second dielectric layer. The first metal oxide semiconductor device and the second metal oxide semiconductor device are located on the substrate. The first dielectric layer is beside the first metal oxide semiconductor device and the second metal oxide semiconductor device. A stop layer is on the first dielectric layer. And a second dielectric layer covering the stop layer. The thickness of the second dielectric layer over the first metal oxide semiconductor device is greater than the thickness of the second dielectric layer over the second metal oxide semiconductor device.
Description
Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a dynamic random access memory and a method of manufacturing the same.
Background
Currently, stacked Dynamic Random Access Memory (DRAM) with capacitors stacked over transistors can achieve the goal of high memory density. However, the material layers of the stacked dram may form dangling bonds during fabrication, resulting in NMOS device reliability issues.
Disclosure of Invention
The present invention is directed to a semiconductor device and a method of manufacturing the same, which can improve reliability of a first device (e.g., NMOS) and can prevent degradation of a member of a memory cell region and a second device (e.g., PMOS) of a peripheral circuit region.
According to an embodiment of the present invention, a semiconductor device according to an embodiment of the present invention includes: the first metal oxide semiconductor device is positioned on the substrate. And the second metal oxide semiconductor device is positioned on the substrate. And the first dielectric layer is beside the first metal oxide semiconductor device and the second metal oxide semiconductor device. A stop layer on the first dielectric layer. And a second dielectric layer covering the stop layer, wherein the thickness of the second dielectric layer above the first metal oxide semiconductor device is greater than the thickness of the second dielectric layer above the second metal oxide semiconductor device.
A semiconductor device according to an embodiment of the present invention includes: the first metal oxide semiconductor device is positioned on the substrate. And the second metal oxide semiconductor device is positioned on the substrate. And the first dielectric layer is beside the first metal oxide semiconductor device and the second metal oxide semiconductor device. A first stop layer on the first dielectric layer. And a second stop layer on the first stop layer, wherein a thickness of the second stop layer over the first metal oxide semiconductor device is greater than a thickness of the second stop layer over the second metal oxide semiconductor device.
A method for manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a first metal oxide semiconductor device and a second metal oxide semiconductor device on the substrate. And forming a first dielectric layer beside the first metal oxide semiconductor device and the second metal oxide semiconductor device. A first stop layer is formed on the first dielectric layer. At least a portion of the first stop layer is removed to form an opening in the first stop layer, the opening corresponding to the first metal oxide semiconductor device. And (5) performing a treatment process. A second dielectric layer is formed overlying the stop layer.
The semiconductor device and the manufacturing method thereof can improve the reliability of the first device (such as NMOS) and avoid the degradation of the components of the memory cell area and the second device (such as PMOS) of the peripheral circuit area.
Drawings
FIG. 1 is a schematic top view of a DRAM according to an embodiment of the present invention;
FIGS. 2A-2G are schematic cross-sectional views of a manufacturing process of a DRAM according to an embodiment of the present invention along the line I-I' of FIG. 1;
FIGS. 3A-3G are schematic cross-sectional views of a manufacturing process of a DRAM according to an embodiment of the present invention along the line II-II' of FIG. 1;
FIGS. 4A-4D are schematic cross-sectional views of a manufacturing process of a DRAM according to another embodiment of the present invention along the line I-I' of FIG. 1;
FIGS. 5A-5D are schematic cross-sectional views of a manufacturing process of a DRAM according to another embodiment of the present invention along the line II-II' of FIG. 1;
FIGS. 6A-6D are schematic cross-sectional views of a manufacturing process of a DRAM according to a further embodiment of the present invention along the line I-I' of FIG. 1;
fig. 7A to 7D are schematic cross-sectional views illustrating a manufacturing process of a dynamic random access memory according to still another embodiment of the present invention along the line II-II' of fig. 1.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Referring to fig. 1, 2A and 3A, a substrate 100 is provided. The substrate 100 is, for example, a semiconductor substrate, such as a silicon substrate. The substrate 100 includes a memory cell region MR and a peripheral circuit region PR. Isolation structures 102 are formed in the substrate 100 to define a plurality of active areas AA. Next, a buried word line WL is formed in the substrate 100. An insulating layer 104 is also formed between the buried word line WL and the substrate 100 to electrically isolate the buried word line WL from the substrate 100. Thereafter, a first device T1 and a second device T2 are formed on the substrate 100 of the peripheral circuit region PR. The first device T1 and the second device T2 may be metal oxide semiconductor devices. The first device T1 is, for example, an N-channel mosfet. The second device T2 is, for example, a pmos. A bit line structure BL is also formed on the substrate 100. The embedded word line WL and bit line structure BL comprise a conductive material, such as tungsten.
Next, a dielectric layer 106 is formed on the substrate 100 of the peripheral circuit region PR. The dielectric layer 106 is, for example, silicon oxide. The dielectric layer 106 may be planarized via a chemical mechanical planarization process.
Thereafter, the dielectric layer 106 is patterned to form openings (not shown) in the dielectric layer 106 of the memory cell region MR. Next, a dielectric layer 108 is formed in the opening and on the dielectric layer 106, and the dielectric layer 108 is planarized to expose the dielectric layer 108 of the memory cell region MR.
Then, the dielectric layer 106 exposed by the memory cell region MR is removed to form an opening, and a contact 110 is formed in the opening, wherein the material of the contact 110 is, for example, polysilicon.
Thereafter, the dielectric layers 106 and 108 are patterned to form contact openings (not shown) in the dielectric layers 106 and 108 of the peripheral circuit region PR.
Then, a conductor layer, such as tungsten, is formed on the substrate 100. The conductor layer also fills the contact opening. Thereafter, the conductive layer is patterned to form a plurality of contacts 111A and a plurality of conductive lines 111B in the peripheral circuit region PR, and a plurality of conductive pads 111C in the memory cell region MR. The conductive line 111B is electrically connected to the first device T1 or the second device T2 via the contact 111A. The conductive pad 111C is electrically connected to the contact 110.
Thereafter, stop layers 112, 114 are formed on the substrate 100. The stop layers 112, 114 are, for example, silicon nitride. The stop layer 112 is a conformal layer formed, for example, by atomic layer deposition. The stop layer 114 is formed by a planarization layer deposited by chemical vapor deposition, such as by back etching or chemical mechanical planarization. The step coverage of the stop layer 112 is good and the quality is better than that of the stop layer 114. The etch selectivity of stop layer 114 is superior to stop layer 112.
Next, a dielectric layer 116, a stop layer 118, a dielectric layer 120, and a stop layer 122 are formed on the stop layer 114. The material of the stop layers 118, 122 is different from the material of the dielectric layers 116, 122. The stop layers 118, 122 are, for example, silicon nitride. The dielectric layers 116, 122 are, for example, silicon oxide.
Referring to fig. 2B and 3B, a patterning process is performed to form a plurality of capacitor openings 124 in the stop layer 114, the dielectric layer 116, the stop layer 118, the dielectric layer 120 and the stop layer 122 of the memory cell region MR. Next, a plurality of lower electrodes 126 are formed in the plurality of capacitor openings 124. The material of the lower electrode 126 is, for example, titanium nitride or ruthenium. The plurality of lower electrodes 126 are electrically connected to the underlying conductive pad 111C. The method of forming the plurality of lower electrodes 126 includes, for example, the following steps. First, a conductive layer is formed on the stop layer 122 and the plurality of capacitor openings 124, and then the stop layer 122 is used as a polishing stop layer, and the redundant conductive layer covered on the stop layer 122 is removed through a chemical mechanical polishing process.
Referring to fig. 2B and 3B, a mask layer 128 is formed on the substrate 100, and the mask layer 128 is patterned to form a plurality of holes 130 and openings 132. The hole 130 exposes the stop layer 122 in the memory cell region MR, and the opening 132 exposes the stop layer 122 in the peripheral circuit region PR. Next, an etching process is performed using the mask layer 128 as a mask to remove the stop layer 122 and the dielectric layer 120 under the stop layer 122 exposed by the holes 130.
Referring to fig. 2C and 3C, using the mask layer 128 as a mask, the stop layer 118 is an etch stop layer to remove the stop layer 122 and the dielectric layer 120 not covered by the mask layer 128.
Referring to fig. 2D and 3D, a portion of the stop layer 118 is removed. Then, an etching process is performed to remove the dielectric layer 116 by using the stop layer 114 as an etching stop layer. Thus, the surface of the lower electrode 126 is exposed. In some embodiments, the lower electrode 126 has a cylindrical profile.
Referring to fig. 2E and 3E, a dielectric 134 is formed on the surfaces of the lower electrode 126 and the stop layer 114. Dielectric 134 is, for example, a high-k dielectric material. Next, an upper electrode 136 is formed on the dielectric 134. The material of the upper electrode 136 includes titanium nitride, tungsten, or germanium silicide. The dielectric 134 and the upper electrode 136 are formed, for example, by forming a dielectric material and a conductive material on the substrate 100, and then performing a photolithography and etching process to remove the conductive material and the dielectric material of the peripheral circuit region PR. The lower electrode 126, dielectric 134, and upper electrode 136 form a capacitor 140.
Referring to fig. 2E and 3E, a mask layer 142 is formed on the substrate 100. Mask layer 142 is, for example, a photoresist layer. Mask layer 142 is then patterned to form openings 143. The opening 143 exposes the stop layer 114 over the gate structure GSK1 of the first device T1 of the peripheral circuit region PR. The mask layer 142 covers the gate structure GSK2 of the second device T2 of the peripheral circuit region PR and the capacitor 140 of the memory cell region MR.
Referring to fig. 2F and 3F, an etching process is performed using the mask layer 142 as an etching mask to remove the stop layers 112 and 114 above the gate structure GSK1, thereby forming an opening 144. The opening 144 exposes the cap layer 16 on top of the gate structure GSK 1. Thereafter, a treatment process 146 is performed. The treatment process 146 is, for example, a hydrogen-fed sintering process (H 2 sintering process) to remove the dangling bonds in the cap layer 16 of the gate structure GSK1 and to improve the reliability of the first device T1. Since the capacitor 140 of the memory cell region MR and the second device T2 of the peripheral circuit region PR are covered with the mask layer 142, gas diffusion used in the processing 146 can be prevented or reduced, and thus degradation of the capacitor 140 of the memory cell region MR and the second device T2 of the peripheral circuit region PR can be avoided.
Referring to fig. 2G and 3G, the mask layer 142 is removed. Thereafter, an interconnect structure 150 is formed over the substrate 100. Interconnect structure 150 includes dielectric layer 152, contacts 154A, 154B, dielectric layer 156, conductive lines 158A, 158B, stop layer 160, dielectric layer 162, conductive features (including conductive lines and vias) 164A, 164B, stop layer 166, dielectric layer 168, vias 170A and 170B, conductive lines 172A, 172B, and protective layer 174. The dielectric layer 152 is, for example, silicon oxide formed by plasma enhanced chemical vapor deposition.
The contact 154A extends through the dielectric layer 152 and is electrically connected to the first device T1 or the second device T2 via the conductive line 111B and the contact 111A, respectively. Contact 154A is also electrically connected to subsequently formed conductive line 158A, conductive feature 164A, via 170A, and conductive line 172A. The contact 154B extends through the dielectric layer 152 and electrically connects the upper electrode 136 of the capacitor 140. Contact 154B is also electrically connected to subsequently formed conductive line 158B, conductive feature 164B, via 170B, and conductive line 172B. The interconnect structure 150 can be formed by any known method, and will not be described herein.
In the present embodiment, the dielectric layer 152 fills the opening 144 and contacts the capping layer 16 of the gate structure GSK1 of the first device T1 of the peripheral circuit region PR. The dielectric layer 152 is separated from the cap layer 16 of the gate structure GSK2 of the second device T2 of the peripheral circuit region PR by the stop layers 112, 114. Thus, the thickness H1 of the dielectric layer 152 over the first device T1 of the peripheral circuit region PR may be greater than the thickness H2 of the dielectric layer 152 over the second device T2 of the peripheral circuit region PR. The present embodiment is a capacitor-first process, which is performed after the capacitor is formed. However, the invention is not limited thereto. Embodiments of the present invention may also include post capacitor processing that is performed after the capacitor is formed.
Referring to fig. 4A and 5A, after the contact 111A, the wire 111B, and the conductor pad 111C are formed according to the above-described method, a stop layer 112 is formed over the substrate 100. And a mask layer 242 is formed on the substrate 100 before the stop layer 114 is formed. The mask layer 242 is, for example, a photoresist layer. Mask layer 242 is then patterned to form openings 243. The opening 243 exposes the stop layer 112 over the gate structure GSK1 of the first device T1 of the peripheral circuit region PR. The mask layer 242 covers the gate structure GSK2 of the second device T2 of the peripheral circuit region PR and the stop layer 112 of the memory cell region MR.
Referring to fig. 4B and 5B, an etching process is performed using the mask layer 242 as an etching mask to remove the stop layer 112 above the gate structure GSK1, thereby forming an opening 244. The opening 244 exposes the cap layer 16 of the gate structure GSK 1. Thereafter, a process 246 is performed. The processing process 246 is, for example, a hydrogen sintering process to remove dangling bonds in the top cap layer 16 of the gate structure GSK1, so as to improve the reliability of the first device T1. Since the capacitor 140 of the memory cell region MR and the second device T2 of the peripheral circuit region PR are covered by the mask layer 242 and the stop layer 112, the diffusion of the gas used in the processing 246 can be prevented or reduced, and thus the deterioration of the capacitor 140 of the memory cell region MR and the second device T2 of the peripheral circuit region PR can be prevented.
Referring to fig. 4C and 4C, the mask layer 242 is removed. Then, a stop layer 114 is formed on the substrate 100. The stop layer 114 fills the opening 244 and contacts the cap layer 16 of the gate structure GSK1 of the first device T1 of the peripheral circuit region PR. The stop layer 114 is separated from the cap layer 16 of the gate structure GSK2 of the second device T2 of the peripheral circuit region PR by the stop layer 112. Thus, the thickness H3 of the stop layer 114 over the first device T1 of the peripheral circuit region PR may be greater than the thickness H4 of the stop layer 114 over the second device T2 of the peripheral circuit region PR.
Referring to fig. 4D and 5D, a capacitor 140 and an interconnect structure 150 are formed according to the above method.
In the present embodiment, the stop layer 112 above the gate structure GSK1 of the first device T1 is completely removed, however, the present invention is not limited thereto, and the stop layer 112 above the gate structure GSK1 of the first device T1 may be partially removed, as shown in fig. 6A to 6D.
Referring to fig. 6A and 7A, a mask layer 342 is formed according to a method of forming the mask layer 242. The mask layer 342 has an opening 343 exposing the stop layer 112 over the gate structure GSK1 of the first device T1 of the peripheral circuit region PR. The mask layer 342 covers the gate structure GSK2 of the second device T2 of the peripheral circuit region PR and the stop layer 112 of the memory cell region MR.
Referring to fig. 6B and fig. 7B, an etching process is performed using the mask layer 342 as an etching mask to partially remove the stop layer 112 above the gate structure GSK1, thereby forming an opening 344. The opening 344 exposes the stop layer 112a remaining over the capping layer 16 of the gate structure GSK 1. Thereafter, a process 346 is performed. The treatment process 346 is, for example, a hydrogen-fed sintering process. Since the stop layer 112a of the capping layer 16 of the gate structure GSK1 is thin, the gas can still pass through the stop layer 112a to remove the dangling bonds in the capping layer 16 of the gate structure GSK1, thereby improving the reliability of the first device T1. Since the capacitor 140 of the memory cell region MR and the second device T2 of the peripheral circuit region PR are covered with the mask layer 342 and the thicker stop layer 112, the diffusion of the gas used in the processing process 346 can be prevented or reduced, and thus the deterioration of the capacitor 140 of the memory cell region MR and the second device T2 of the peripheral circuit region PR can be prevented.
Referring to fig. 6C and 7C, the mask layer 342 is removed. Then, a stop layer 114 is formed on the substrate 100. The stop layer 114 fills the opening 344 and is separated from the cap layer 16 of the gate structure GSK1 of the first device T1 of the peripheral circuit region PR by the thinner stop layer 112a. The stop layer 114 is separated from the cap layer 16 of the gate structure GSK2 of the second device T2 of the peripheral circuit region PR by a thicker stop layer 112. Thus, the thickness H5 of the stop layer 114 over the first device T1 of the peripheral circuit region PR may be greater than the thickness H6 of the stop layer 114 over the second device T2 of the peripheral circuit region PR.
Referring to fig. 6D and 7D, a capacitor 140 and an interconnect 150 are formed in accordance with the method described above.
The semiconductor device of the embodiment of the invention selectively removes the stop layer over the first device (such as NMOS) of the peripheral circuit region completely or partially through the formation of the mask layer, so that the treatment process (such as sintering process) can be performed for the first device (such as NMOS), thereby improving the reliability of the first device. Since the memory cell region and the second device (e.g., PMOS) of the peripheral circuit region are covered with the mask layer, gas diffusion used in the processing process can be prevented or reduced, and thus degradation of the components of the memory cell region and the second device (e.g., PMOS) of the peripheral circuit region can be avoided.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (12)
1. A semiconductor device, comprising:
the first metal oxide semiconductor device is positioned on the substrate;
a second MOS device on the substrate
A first dielectric layer beside the first MOS device and the second MOS device;
a stop layer on the first dielectric layer; and
and a second dielectric layer covering the stop layer, wherein the thickness of the second dielectric layer above the first metal oxide semiconductor device is greater than the thickness of the second dielectric layer above the second metal oxide semiconductor device.
2. The semiconductor device of claim 1, wherein the second dielectric layer extends through the stop layer and is in contact with the first metal oxide semiconductor device.
3. The semiconductor device of claim 2, wherein the first mos device comprises an N-channel mos device and the second mos device comprises a P-channel mos device.
4. A semiconductor device, comprising:
the first metal oxide semiconductor device is positioned on the substrate;
the second metal oxide semiconductor device is positioned on the substrate;
a first dielectric layer beside the first MOS device and the second MOS device;
a first stop layer on the first dielectric layer; and
and a second stop layer on the first stop layer, wherein a thickness of the second stop layer over the first metal oxide semiconductor device is greater than a thickness of the second stop layer over the second metal oxide semiconductor device.
5. The semiconductor device of claim 4, wherein the second stop layer is in contact with the first metal oxide semiconductor device.
6. The semiconductor device of claim 4, wherein a thickness of the first stop layer between the second stop layer and the first metal oxide semiconductor device is less than a thickness of the first stop layer between the second stop layer and the second metal oxide semiconductor device.
7. A method of manufacturing a semiconductor device, comprising:
forming a first metal oxide semiconductor device and a second metal oxide semiconductor device on a substrate;
forming a first dielectric layer beside the first metal oxide semiconductor device and the second metal oxide semiconductor device;
forming a first stop layer on the first dielectric layer;
removing at least a portion of the first stop layer to form an opening in the first stop layer, the opening corresponding to the first metal oxide semiconductor device;
performing a treatment process; and
a second dielectric layer is formed overlying the stop layer.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the gas used in the treatment process includes hydrogen.
9. The method for manufacturing a semiconductor device according to claim 7, wherein the forming a second dielectric layer further fills in the opening.
10. The method for manufacturing a semiconductor device according to claim 7, further comprising forming a second stop layer over the first stop layer and filling in the opening.
11. The method for manufacturing a semiconductor device according to claim 10, wherein at least part of the first stopper layer is removed, and a bottom of the opening exposes the first stopper layer.
12. The method for manufacturing a semiconductor device according to claim 7, wherein at least a part of the first stopper layer is removed, and a bottom of the opening exposes the first mos device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202211041612.6A CN117693189A (en) | 2022-08-29 | 2022-08-29 | Semiconductor device and method for manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211041612.6A CN117693189A (en) | 2022-08-29 | 2022-08-29 | Semiconductor device and method for manufacturing the same |
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| CN117693189A true CN117693189A (en) | 2024-03-12 |
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| CN202211041612.6A Pending CN117693189A (en) | 2022-08-29 | 2022-08-29 | Semiconductor device and method for manufacturing the same |
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