CN117691998A

CN117691998A - RC calibration circuit

Info

Publication number: CN117691998A
Application number: CN202311778809.2A
Authority: CN
Inventors: 房哲
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2023-12-21
Filing date: 2023-12-21
Publication date: 2024-03-12

Abstract

An RC calibration circuit comprising: the system comprises an integrating unit, a comparing unit, a control unit, a reference resistor and a capacitor array, wherein: the integration unit is suitable for outputting an integration result, and the integration result is related to the number of the conductive capacitor units in the capacitor array; the comparison unit is suitable for comparing the integration result with a first difference value and outputting a comparison result; the first difference is: a difference between the reference voltages over the different time periods; the control unit is suitable for outputting the control signal based on the comparison result, and when the level of the comparison result is turned over, the number of the conducted capacitors in the capacitor array is obtained and is used as a target calibration number to be output. The RC calibration circuit provided by the scheme has small error and can adapt to different continuous time systems.

Description

RC calibration circuit

Technical Field

The invention relates to the technical field of circuits, in particular to an RC calibration circuit.

Background

In continuous time systems, such as e.g. active filters, resistive-capacitive (RC) oscillators, continuous time sigma-delta analog-to-digital converters, the design of the circuit depends on the resistance and capacitance within the chip. The precise cut-off frequency and RC time constant have a large impact on the stability and accuracy of the system. To avoid the use of external passive devices, RC calibration circuits are typically provided on-chip.

In the prior art, the design of an RC calibration circuit depends on the charge-discharge strategy of the RC circuit. The discharge time constant of the RC circuit is continuously adjusted, so that the discharge time constant of the RC circuit under different process angles (corners) is a determined time, and the relatively accurate RC discharge time constant is obtained.

However, there are large systematic errors when applying existing RC calibration circuits.

Disclosure of Invention

The invention aims to provide an RC calibration circuit with small system error, which can adapt to different continuous time systems.

The invention provides an RC calibration circuit, comprising: the system comprises an integrating unit, a comparing unit, a control unit, a reference resistor and a capacitor array, wherein: the capacitor array comprises a plurality of capacitor units which are connected in parallel between the input end and the output end of the integration unit, and the control end of the capacitor array is coupled with the control unit, and the number of the turned-on capacitor units is controlled based on the adjustment signals output by the control unit; the first end of the reference resistor inputs reference voltage, and the second end of the reference resistor is coupled with the input end of the integration unit; the values of the reference voltages are different in adjacent different time periods; the integration unit is suitable for outputting an integration result, and the integration result is related to the number of the conductive capacitor units in the capacitor array; the comparison unit is suitable for comparing the integration result with a first difference value and outputting a comparison result; the first difference is: a difference between the reference voltages over the different time periods; the control unit is suitable for outputting the adjusting signal based on the comparison result, and acquiring the number of the conducted capacitors in the capacitor array as a target calibration number and outputting the target calibration number when the level of the comparison result is turned over.

Optionally, the integrating unit includes a single-input single-output integrating unit, where: the input end of the single-input single-output integration unit is coupled with the second end of the reference resistor, and the output end of the single-input single-output integration unit outputs the integration result; the first end of the reference resistor inputs a first reference voltage in a first time period and outputs a second reference voltage in a second time period; the first difference is a difference between the first reference voltage and the second reference voltage.

Optionally, the RC calibration circuit further comprises: the first end of the reset unit is coupled with the input end of the single-input single-output integration unit, the second end of the reset unit is coupled with the output end of the single-input single-output integration unit, and the control end of the reset unit inputs a clock reset signal; when the clock reset signal is at a high level, the single-input single-output integration unit is reset.

Optionally, the comparing unit includes a difference value obtaining module and a comparing module, where: the difference acquisition module is suitable for acquiring the first difference value, and the comparison module is suitable for comparing the integration result with the first difference value and outputting the comparison result.

Optionally, the integrating unit includes a dual-input dual-output integrating unit, wherein: the first input end of the double-input double-output integration unit inputs a first reference voltage in a first time period and inputs a second reference voltage in a second time period; the second input end of the first voltage source is used for inputting the first reference voltage in the first time period and inputting the third reference voltage in the second time period; a first integration result is output at a first output end; the second output end outputs a second integration result; the difference between the first integral result and the second integral result is the integral result.

Optionally, the RC calibration circuit may further include: further comprises: a first reset unit and a second reset unit; the capacitor array comprises a first capacitor array and a second capacitor array; wherein: the first capacitor array is connected in series between the first input end and the first output end of the dual-input dual-output integration unit, and the first reset unit is connected in parallel with the first capacitor array; the second capacitor array is connected in series between the second input end and the second output end of the dual-input dual-output integration unit, and the second reset unit is connected in parallel with the second capacitor array; and the control end of the first reset unit and the control end of the second reset unit are respectively input with a clock reset signal, and when the clock reset signal is in a high level, the dual-input dual-output integration unit is reset.

Optionally, the comparing unit includes: a dual-input dual-output pre-amplifier and a comparison module, wherein: the first input end of the dual-input dual-output preamplifier inputs the first integration result in a first time period and inputs the second reference voltage in a second time period; the second input end of the first voltage source inputs the second integration result in the first time period, and the third reference voltage is input in the second time period; the first output end outputs the difference value between the first integration result and the second reference voltage; the second output end outputs the difference value between the second integration result and the third reference voltage; the first input end of the comparison module is coupled with the first output end of the dual-input dual-output pre-amplifier, the second input end of the comparison module is coupled with the second output end of the dual-input dual-output pre-amplifier, and the output end of the comparison module is coupled with the input end of the control unit.

Optionally, in the second period, the first input end of the dual-input dual-output pre-amplifier is connected with the first output end in a conducting manner, and the second input end of the dual-input dual-output pre-amplifier is connected with the second output end in a conducting manner.

Optionally, the comparing module includes: a four-input comparator, wherein: the four-input comparator has a first positive input end for inputting the first integration result, a second positive input end for inputting the third reference voltage, a first negative input end for inputting the second integration result, a second negative input end for inputting the second reference voltage, and an output end coupled with the input end of the control unit.

Optionally, the first reference voltage is smaller than the second reference voltage, and the third reference voltage is smaller than the first reference voltage.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

a capacitor array is connected in series between the input end and the output end of the integration unit, and the integration result output by the integration unit is related to the number of the turned-on capacitor units in the capacitor array. The comparison unit compares the integration result with the first difference value and outputs a comparison result. The control unit adjusts the number of the conductive capacitor units in the capacitor array based on the comparison result. When the number of the turned-on capacitor units in the capacitor array is changed, the integration result of the integration unit is influenced. Thus, dynamic RC calibration can be accurately achieved, and different continuous time systems can be adapted.

Drawings

FIG. 1 is a schematic diagram of a prior art RC calibration circuit;

FIG. 2 is a schematic diagram of an RC calibration circuit in an embodiment of the present invention;

FIG. 3 is a timing diagram of an RC calibration circuit in an embodiment of the present invention;

FIG. 4 is a schematic diagram of another RC calibration circuit in an embodiment of the present invention;

fig. 5 is a timing diagram of another RC calibration circuit in an embodiment of the invention.

Detailed Description

Referring to fig. 1, a schematic diagram of a conventional RC calibration circuit is shown. In fig. 1, when Zhong Fuwei signal clk_rst is high, the voltage across capacitor array CBANK is reset to supply voltage AVDD. After the reset is finished, when the CLK_INT is at a high level, the CBANK and the reference resistor Rref branch start to discharge, the discharge period is the high level time of the CLK_INT, and the discharge current is Iref=V1/Rref.

During a certain clk_int high period, the voltage vin=avdd-v1×t/(rref×c) at the positive input terminal of the comparator comp, and C is the equivalent capacitance value of the capacitor array CBANK. The capacitor array CBANK includes a plurality of capacitor units, and the number of the capacitor units conducted in the capacitor array CBANK is different, so that the corresponding equivalent capacitance values C are different. The reverse input terminal voltage vref=avdd× (R ₁ +R ₃ )/(2R ₁ +R ₃ ) Wherein R is ₁ Is the resistance value of the resistor R1, R ₃ Is the resistance of the resistor R3. Comparator comp is atThe rising edge of the clock signal clk_clk performs a comparison operation, and the output result of the comparator comp is output to the digital calibration module. The digital calibration module outputs a calibration signal DATA_CTRL according to a calibration result to adjust the number of the turned-on capacitor units in the capacitor array CBANK so as to adjust the equivalent capacitance value of the capacitor array CBANK, thereby realizing the adjustment of VIN. V1 is the voltage at the first end of the reference resistor Rref and is input to the "-" input end of the pre-amplifier amp; the "+" input of the preamplifier acquires the voltage at one end of the resistor R3. The second terminal of the reference resistor Rref is grounded AVSS.

The number of the turned-on capacitor units in the capacitor array CBANK is adjusted, so that VIN and VREF are gradually close. When the output result of the comparator comp is inverted, calibration is completed. At this time, the digital calibration module outputs a calibration complete signal lock_done. The number stored in the digital calibration module is the number of the conducted capacitor units in the calibrated capacitor array CBANK.

However, in the RC calibration circuit provided in fig. 1, the capacitor involved in discharging is composed of the upper and lower plate capacitors at both ends of the capacitor and the end-to-ground capacitor. In some applications, such as sigma-delta analog-to-digital converters, the capacitance across the integrator input and output is simply the coupling capacitance of the upper and lower plates. Therefore, the RC calibration circuit has certain systematic errors and mismatch when applied to a sigma-delta analog-to-digital converter.

In the embodiment of the invention, a capacitor array is connected in series between the input end and the output end of the integration unit, and the integration result output by the integration unit is related to the number of the turned-on capacitor units in the capacitor array. The comparison unit compares the integration result with the first difference value and outputs a comparison result. The control unit adjusts the number of the conductive capacitor units in the capacitor array based on the comparison result. When the number of the turned-on capacitor units in the capacitor array is changed, the integration result of the integration unit is influenced, and RC calibration is achieved.

Because the scheme in the embodiment of the invention carries out RC calibration based on the equivalent capacitance value of the capacitor array, dynamic RC calibration can be accurately realized, and different continuous time systems can be adapted.

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

The invention provides an RC calibration circuit, comprising: the device comprises an integrating unit, a comparing unit, a control unit, a reference resistor and a capacitor array.

In an embodiment of the present invention, the capacitor array may include N capacitor units, where the N capacitor units are connected in parallel. The specific structure of the capacitor array may refer to CBANK in fig. 1. The capacitor array further comprises a reset switch, and when the reset switch inputs a high-level reset signal, the equivalent capacitance value of the capacitor array is reset to 0.

The control terminal of the capacitor array may be coupled to the output terminal of the control unit. Under the action of the adjusting signal output by the control unit, the number of the conducted capacitor units in the capacitor array is changed, so that the equivalent capacitance value of the capacitor array is adjusted.

In some embodiments, the capacitance values of N capacitive cells in the capacitive array are all equal. Setting the capacitance value of any capacitor unit as C ₁ When the number of the conductive capacitor units in the capacitor array is 1, the equivalent capacitance of the capacitor array is C ₁ The method comprises the steps of carrying out a first treatment on the surface of the When the number of the turned-on capacitor units in the capacitor array is 2, the equivalent capacitance of the capacitor array is 2×C ₁ The method comprises the steps of carrying out a first treatment on the surface of the And so on.

In an embodiment of the present invention, a first end of the reference resistor may be input with a reference voltage, and a second end of the reference resistor may be coupled with an input end of the integration unit. That is, the reference voltage is input to the input terminal of the integration unit through the reference resistor.

In a specific implementation, the values of the reference voltages input by the first ends of the reference resistors are different in different time periods. That is, the reference voltages input at the input terminals of the integration units are different in different periods.

In some embodiments, a first end of the reference voltage inputs a first reference voltage during a first period of time. The first end of the reference voltage inputs a second reference voltage in a second period. The first reference voltage is not equal to the second reference voltage.

The capacitive array is connected in series between the input end and the output end of the integration unit, so that the integration result output by the integration unit can be related to the equivalent capacitance value of the capacitive array, namely, the number of the conductive capacitive units in the capacitive array.

In the embodiment of the invention, the integration result can be inversely related to the number of the conductive capacitor units in the capacitor array. That is, the larger the number of the turned-on capacitor units in the capacitor array, the larger the equivalent capacitance value of the capacitor array, and the smaller the integration result.

In the embodiment of the invention, the comparison unit may input the integration result and the first difference value, compare the integration result and the first difference value, and output the comparison result. The first difference may be a difference between the reference voltages over different time periods.

In a specific implementation, when the integration result is greater than the first difference value, the comparison unit may output a high level; the comparison unit may output a low level when the integration result is not greater than the first difference value.

In some embodiments, the reference voltage in the first period is a first reference voltage, and the reference voltage in the second period is a second reference voltage, and the first difference may be a difference between the second reference voltage and the first reference voltage. The second reference voltage is greater than the first reference voltage.

In the embodiment of the present invention, the control unit may output the adjustment signal based on the comparison result output by the comparison unit. When the comparison result output by the comparison unit is at a high level, the control unit can control the adjustment signal to the capacitor array so as to control the number of the turned-on capacitor units in the capacitor array to be increased by one. Since the equivalent capacitance of the capacitor array is inversely related to the integration result, the integration result is reduced when the number of capacitors turned on in the capacitor array is increased. The integration result gradually decreases as the number of conductive capacitor cells in the capacitor array increases. When the number of the conducted capacitors in the capacitor array is increased to M, the integration result is not larger than the first difference value, so that the output result of the comparison unit is turned from high level to low level, and at the moment, the control unit can calibrate and output M as the target number. M is a positive integer, and M is more than or equal to 1 and less than or equal to N.

The RC calibration circuit provided in the above embodiments of the present invention will be described in detail.

In an embodiment of the present invention, the integrating unit may include a single-input single-output integrating unit. That is, the integrating unit includes one input terminal and one output terminal.

Referring to fig. 2, a schematic diagram of an RC calibration circuit in an embodiment of the present invention is shown. In fig. 2, the integrating unit is a single-input single-output integrating unit. Referring to fig. 3, a timing diagram of an RC calibration circuit in an embodiment of the invention is shown. The following is a description with reference to fig. 2 and 3.

The input end of the single-input single-output integration unit INT is coupled with the second end of the reference resistor R, and the output end of the single-input single-output integration unit INT outputs an integration result. A capacitor array Cbank is connected in series between the input and output terminals of the single-input single-output integration unit INT.

In the first time period, the reference voltage input by the first end of the reference resistor R is a first reference voltage VCM; in the second period, the reference voltage input at the first end of the reference resistor R is the second reference voltage VREFP.

As shown in fig. 2, a switching unit S1 is disposed between the first reference voltage VCM and the first terminal of the reference resistor R, and a control terminal of the switching unit S1 inputs a first control signal PH1; a switching unit S2 is disposed between the second reference voltage VREFP and the first end of the reference resistor R, and a control end of the switching unit S2 inputs a second control signal PH2. When the first control signal PH1 is at a high level, the switch unit S1 is turned on, and the first end of the reference resistor R inputs the first reference voltage VCM; when the second control signal PH2 is at a high level, the switch unit S2 is turned on, and the first terminal of the reference resistor R inputs the second reference voltage VREFP. Since the first control signal PH1 and the second control signal PH2 are not at the high level, the first end of the reference resistor R inputs the first reference voltage VCM and the second reference voltage VREFP in different time periods.

It will be appreciated that the first terminal of the reference resistor R may be controlled to input different reference voltages for different time periods in other ways.

For example, the first end of the reference resistor R is connected to a power source. The power supply generates a first reference voltage VCM during a first period and generates a second reference voltage VREFP during a second period.

The integration result output by the single-input single-output integration unit INT is: vout= [ (VREFP-VCM) ×t]/(R _ref X C), wherein T is the high level duration of the second reference voltage VREFP, R _ref And C is the equivalent capacitance value of the capacitor array Cbank for the resistance value of the reference resistor R.

It can be seen that the integration result is related to the number of turned-on capacitor units in the capacitor array, and as the equivalent capacitance C of the capacitor array increases, the integration result VOUT decreases.

A reset unit S3 may also be provided between the input and output of the single input single output integration unit INT. The first end of the reset unit S3 is coupled to the input end of the single-input single-output integration unit INT, the second end of the reset unit S3 is coupled to the output end of the single-input single-output integration unit INT, and the control end of the reset unit S3 inputs the clock reset signal clk_rst. When the clock reset signal clk_rst is at a high level, the single input single output integration unit INT is reset.

That is, when the clock reset signal is at a high level, the reset unit S3 is turned on, and the single input single output integration unit INT is reset.

The comparison unit may include a difference acquisition module and a comparison module comp, wherein: the integration result may be input to the first input terminal of the comparison module comp; the difference module may obtain a difference between the second reference voltage VREFP and the first reference voltage VCM, and output the difference to the second input terminal of the comparison module comp. The comparison module comp compares the first difference value with the integration result, and when the integration result is larger than the first difference value, the comparison result output by the comparison module comp is high level; when the integration result is not greater than the first difference value, the comparison result output by the comparison module comp is at a low level.

The control unit outputs an adjusting signal based on the comparison result output by the comparison unit so as to adjust the number of the conducted capacitors in the capacitor array. When the comparison result output by the comparison module comp is inverted, the control unit may output a lock_done signal, which characterizes the end of calibration.

In an implementation, the first reference voltage VCM and the second reference voltage VREFP are preset reference voltages, and the first reference voltage VCM may be smaller than the second reference voltage VREFP.

In an embodiment of the present invention, the integrating unit may include a dual input dual output integrating unit. That is, the integrating unit includes two input terminals and two output terminals.

In a specific implementation, the first input end of the dual-input dual-output integration unit can input a first reference voltage in a first time period and input a second reference voltage in a second time period; the second input end of the dual-input dual-output integration unit can input a first reference voltage in a first time period and a third reference voltage in a second time period; the first output end of the dual-input dual-output integration unit can output a first integration result; the second input end of the double-input double-output integration unit can output a second integration result, and the difference value between the first integration result and the second integration result is the integration result.

In a specific implementation, the RC calibration circuit may further include a first reset unit and a second reset unit. The capacitor array may include a first capacitor array and a second capacitor array, and the reference resistor may include a first reference resistor and a second reference resistor, where the resistance values of the first reference resistor and the second reference resistor are equal.

The first capacitor array is connected in series between the first input end and the first output end of the dual-input dual-output integration unit, and the first reset unit is connected in parallel with the first capacitor array; the second capacitor array is connected in series between the second input end and the second output end of the dual-input dual-output integration unit, and the second reset unit is connected in parallel with the second capacitor array.

The control end of the first reset unit and the control end of the second reset unit are respectively input with a clock reset signal. When the clock reset signal is at a high level, the dual-input dual-output integration unit is reset.

In some embodiments, the comparison unit may include a dual input dual output pre-amplifier and a comparison module, wherein:

the first input end of the dual-input dual-output preamplifier inputs a first integration result in a first time period and inputs a second reference voltage in a second time period; the second input end of the dual-input dual-output pre-amplifier inputs a second integration result in a first time period and inputs a third reference voltage in a second time period; the first output end of the dual-input dual-output preamplifier outputs a difference value between a first integration result and a second reference voltage; the second output end of the dual-input dual-output pre-amplifier outputs a difference value between the second integration result and the third reference voltage.

The first input end of the comparison module is coupled with the first output end of the dual-input dual-output pre-amplifier, the second input end of the comparison module is coupled with the second output end of the dual-input dual-output pre-amplifier, and the output end of the comparison module is coupled with the input end of the control unit.

In a second time period, the first input end of the dual-input dual-output pre-amplifier is connected with the first output end in a conducting way, and the second input end of the dual-input dual-output pre-amplifier is connected with the second output end in a conducting way.

In some embodiments, the first reference voltage is less than the third reference voltage, and the third reference voltage is less than the second reference voltage.

In an embodiment, the first control signal and the second control signal are not high at the same time. That is, when the rising edge of the first control signal comes, the second control signal is at a low level. When the rising edge of the second control signal comes, the first control signal is low.

Referring to fig. 4, another RC calibration circuit in an embodiment of the invention is shown. Referring to fig. 5, a timing diagram of another RC calibration circuit in an embodiment of the invention is shown. The following describes the case with reference to fig. 4 and 5.

The first input terminal of the dual input dual output integration unit INT is an inverting input terminal (i.e., the "-" input terminal in fig. 4), and the second input terminal of the dual input dual output integration unit INT is a "+" terminal (i.e., the "+" input terminal in fig. 4). The first output terminal of the dual input dual output integration unit INT is a forward output terminal (i.e., the "+" output terminal in fig. 4), and the second output terminal of the dual input dual output integration unit INT is a reverse output terminal (i.e., the "-" output terminal in fig. 4).

The first input terminal of the dual input dual output integration unit INT inputs the first reference voltage VCM during a first period of time, and the first input terminal of the dual input dual output integration unit INT inputs the second reference voltage VREFP during a second period of time. The second input terminal of the dual input dual output integration unit INT inputs the first reference voltage VCM during a first period of time, and the second input terminal of the dual input dual output integration unit INT inputs the third reference voltage VREFN during a second period of time. VREFP > VCM > VREFN.

The first input end of the dual-input dual-output integration unit INT is connected with a first reference resistor R1, the second input end is connected with a second reference resistor R2, and the resistance value of the first reference resistor R1 and the resistance value of the second reference resistor R2 are both R _ref . A first capacitor array Cbank1 is connected in series between the first input end and the first output end of the dual-input dual-output integration unit INT, a second capacitor array Cbank2 is connected in series between the second input end and the second output end of the dual-input dual-output integration unit INT, the structures of the first capacitor array Cbank1 and the second capacitor array Cbank2 are the same, and the number of the conducted capacitor units in the two capacitor arrays Cbank1 and Cbank2 is equal. That is, the equivalent capacitance values of the first capacitor array Cbank1 and the second capacitor array Cbank2 are equal.

The two ends of the first capacitor array Cbank1 are connected with a first reset unit in parallel, and the two ends of the second capacitor array Cbank2 are connected with a second reset unit in parallel. The first reset unit and the second reset unit are conducted when the clock reset signal is in a high level, and the dual-input dual-output integration unit INT enters a reset state.

As shown in fig. 4, in some embodiments, the first input terminal of the dual input dual output integration unit INT may be controlled to input the first reference voltage VCM for a first period of time and the second reference voltage VREFP for a second period of time by controlling the switching unit by the first control signal PH1 and the switching unit by the second control signal PH 2; and controlling the second input terminal of the dual input dual output integration unit INT to input the first reference voltage VCM during the first period and the third reference voltage VREFN during the second period.

It will be appreciated that different voltage inputs over different time periods may also be achieved by means of voltage switching. For example, the control voltage source inputs the first reference voltage VCM for a first period of time and the second reference voltage VREFP for a second period of time.

In fig. 4, the first integration result output by the first output terminal of the dual-input dual-output integration unit INT is: voutp= (VREFP-VCM) T/(R) _ref * C) The method comprises the steps of carrying out a first treatment on the surface of the C is the equivalent capacitance of the first capacitor array Cbank1, and T is the high duration of the second reference voltage VREFP.

The second integration result output by the second output end of the dual-input dual-output integration unit INT is: voutn= (VCM-VREFP) T/(R) _ref * C) The method comprises the steps of carrying out a first treatment on the surface of the C is the equivalent capacitance of the second capacitor array Cbank2, and T is the high duration of the third reference voltage VREFN.

Since the second reference voltage VREFP and the third reference voltage VREFN are controlled by the second control signal PH2, the high duration of the second reference voltage VREFP and the high duration of the third reference voltage VREFN are both T.

Thus, the integration result output by the dual-input dual-output integration unit INT is: VOUTP-voutn= (VREFP-VREFN) ×t/(R) _ref *Cbank)。

The first input terminal (i.e., the "-" input terminal in fig. 4) of the dual-input dual-output pre-amplifier amp inputs the first integration result VOUTP for a first period of time and inputs the second reference voltage VREFP for a second period of time; the second input terminal (i.e., the "+" input terminal in fig. 4) of the dual-input dual-output pre-amplifier amp inputs the second integration result VOUTN during the first period of time, and inputs the third reference voltage VREFN during the second period of time; the output result of the first output terminal (i.e., the "+" output terminal in fig. 4) of the dual-input dual-output pre-amplifier amp is: VOUTP-VREFP; the output of the second output terminal of the dual-input dual-output pre-amplifier amp (i.e., "-" output terminal in fig. 4) is: VOUTN-VREFN.

The first input of the comparison module comp inputs VOUTP-VREFP and the second input of the comparison module comp inputs VOUTN-VREFN. Thus, the comparison result output by the output end of the comparison module comp is: (VOUTP-VOUTN) - (VREFP-VREFN).

The control unit may output the adjustment signal based on the comparison results (VOUTP-VOUTN) - (VREFP-VREFN) output by the comparison unit. When the comparison result output by the comparison unit is at a high level, the control unit may control the adjustment signal to the capacitor arrays (the first capacitor array Cbank1 and the second capacitor array Cbank 2) to control the number of the capacitor units conducted in the capacitor arrays to be increased by one, that is: the number of the turned-on capacitor units in the first capacitor array Cbank1 and the second capacitor array Cbank2 is increased by one.

As the number of capacitor cells turned on in the capacitor arrays (the first capacitor array Cbank1 and the second capacitor array Cbank 2) increases, the integration result (VOUTP-VOUTN) gradually decreases. When the number of the turned-on capacitors in the capacitor arrays (the first capacitor array Cbank1 and the second capacitor array Cbank 2) is increased to M, the integration result (VOUTP-VOUTN) is not greater than the first difference (VREFP-VREFN), so the output result of the comparing unit is inverted from high level to low level, and at this time, the control unit can calibrate and output M as the target calibration number. M is a positive integer, and M is more than or equal to 1 and less than or equal to N.

The integration result output by the dual-input dual-output integration unit INT is: VOUTP-voutn= (VREFP-VREFN) ×t/(R) _ref X C). The RC calibration circuit aims at realizing T/(R) _ref X C) =1. As can be seen from the above, when the integration result is equal to VREFP-VREFN, it means T/(R) _ref X C) =1. At this time, the output result of the comparison module comp is inverted from the high level to the low level.

In a specific implementation, the first period is a period when the first control signal is at a high level, and the second period is a period when the second control signal is at a high level. The falling edge of the reset clock signal may be the same as the falling edge of the first control signal. I.e. when the falling edge of the reset clock signal comes in, the falling edge of the first control signal also comes in at the same time.

In other embodiments, the comparison module may also include: a four-input comparator, wherein:

the first positive input end of the four-input comparator inputs a first integration result VOUTP, the second positive input end of the four-input comparator inputs a third reference voltage VREFN, the first negative input end of the four-input comparator inputs a second integration result VOUTN, and the second negative input end of the four-input comparator inputs a second reference voltage VREFP; the output end of the four-input comparator is coupled with the input end of the control unit.

In combination with the above embodiments, for a four-input comparator, the comparison result output by the output terminal is: voutp+vrefn- (voutn+vrefp). The above formula is converted, and the comparison result is converted into (VOUTP-VOUTN) - (VREFP-VREFN).

The integration result output by the dual-input dual-output integration unit is as follows: VOUTP-voutn= (VREFP-VREFN) ×t/(R) _ref X C). The RC calibration circuit aims at realizing T/(R) _ref X C) =1. As can be seen from the above, when the integration result is equal to VREFP-VREFN, it means T/(R) _ref X C) =1. At this time, the output result of the four-input comparator is inverted from a high level to a low level.

The control unit can record the number M of the conductive capacitor units in the capacitor array when the output result of the four-input comparator is turned from high level to low level, namely the target calibration number.

It should be noted that the specific circuit structures of the integrating unit and the comparing unit are not limited to the description in the foregoing embodiments, and in specific applications, the corresponding integrating unit and comparing unit may be selected according to the specific application requirements.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. An RC calibration circuit comprising: the system comprises an integrating unit, a comparing unit, a control unit, a reference resistor and a capacitor array, wherein:

the capacitor array comprises a plurality of capacitor units which are connected in parallel between the input end and the output end of the integration unit, and the control end of the capacitor array is coupled with the control unit, and the number of the turned-on capacitor units is controlled based on the adjustment signals output by the control unit;

the first end of the reference resistor inputs reference voltage, and the second end of the reference resistor is coupled with the input end of the integration unit; the values of the reference voltages are different in adjacent different time periods;

the integration unit is suitable for outputting an integration result, and the integration result is related to the number of the conductive capacitor units in the capacitor array;

the comparison unit is suitable for comparing the integration result with a first difference value and outputting a comparison result; the first difference is: a difference between the reference voltages over the different time periods;

the control unit is suitable for outputting the adjusting signal based on the comparison result, and acquiring the number of the conducted capacitors in the capacitor array as a target calibration number and outputting the target calibration number when the level of the comparison result is turned over.

2. The RC calibration circuit of claim 1, wherein the integration unit comprises a single-input single-output integration unit, wherein:

the input end of the single-input single-output integration unit is coupled with the second end of the reference resistor, and the output end of the single-input single-output integration unit outputs the integration result; the first end of the reference resistor inputs a first reference voltage in a first time period and outputs a second reference voltage in a second time period; the first difference is a difference between the first reference voltage and the second reference voltage.

3. The RC calibration circuit of claim 2, further comprising: the first end of the reset unit is coupled with the input end of the single-input single-output integration unit, the second end of the reset unit is coupled with the output end of the single-input single-output integration unit, and the control end of the reset unit inputs a clock reset signal; when the clock reset signal is at a high level, the single-input single-output integration unit is reset.

4. The RC calibration circuit of claim 2, wherein the comparison unit comprises a difference acquisition module and a comparison module, wherein: the difference acquisition module is suitable for acquiring the first difference value, and the comparison module is suitable for comparing the integration result with the first difference value and outputting the comparison result.

5. The RC calibration circuit of claim 1, wherein the integration unit comprises a dual-input dual-output integration unit, wherein:

the first input end of the double-input double-output integration unit inputs a first reference voltage in a first time period and inputs a second reference voltage in a second time period; the second input end of the first voltage source is used for inputting the first reference voltage in the first time period and inputting the third reference voltage in the second time period; a first integration result is output at a first output end; the second output end outputs a second integration result; the difference between the first integral result and the second integral result is the integral result.

6. The RC calibration circuit of claim 5, further comprising: a first reset unit and a second reset unit; the capacitor array comprises a first capacitor array and a second capacitor array; wherein:

the first capacitor array is connected in series between the first input end and the first output end of the dual-input dual-output integration unit, and the first reset unit is connected in parallel with the first capacitor array;

the second capacitor array is connected in series between the second input end and the second output end of the dual-input dual-output integration unit, and the second reset unit is connected in parallel with the second capacitor array;

and the control end of the first reset unit and the control end of the second reset unit are respectively input with a clock reset signal, and when the clock reset signal is in a high level, the dual-input dual-output integration unit is reset.

7. The RC calibration circuit of claim 5, wherein the comparison unit comprises: a dual-input dual-output pre-amplifier and a comparison module, wherein:

the first input end of the dual-input dual-output preamplifier inputs the first integration result in a first time period and inputs the second reference voltage in a second time period; the second input end of the first voltage source inputs the second integration result in the first time period, and the third reference voltage is input in the second time period; the first output end outputs the difference value between the first integration result and the second reference voltage; the second output end outputs the difference value between the second integration result and the third reference voltage;

8. The RC calibration circuit of claim 7, wherein a first input of the dual-input dual-output pre-amplifier is in conductive connection with a first output and a second input of the dual-input dual-output pre-amplifier is in conductive connection with a second output during a second time period.

9. The RC calibration circuit of claim 5, wherein the comparison module comprises: a four-input comparator, wherein:

the four-input comparator has a first positive input end for inputting the first integration result, a second positive input end for inputting the third reference voltage, a first negative input end for inputting the second integration result, a second negative input end for inputting the second reference voltage, and an output end coupled with the input end of the control unit.

10. The RC calibration circuit of any one of claims 5-9, wherein the first reference voltage is less than the second reference voltage and the third reference voltage is less than the first reference voltage.