CN117690804A - Wafer level packaging method - Google Patents

Abstract

The embodiment of the disclosure provides a wafer level packaging method, which comprises the following steps: providing a wafer; forming an electric connection structure in the wafer, wherein the bottom of the electric connection structure is positioned in the wafer, and the top of the electric connection structure is exposed out of the top surface of the wafer; forming a chip on the wafer, the chip being in electrical contact with the top of the electrical connection structure; forming a packaging structure on a wafer, wherein a chip is positioned in the packaging structure; performing a first back grinding process on the bottom surface of the wafer to expose the bottom of the electric connection structure; and forming a conductive structure, wherein the conductive structure is contacted with the bottom of the electric connection structure. The embodiment of the disclosure is at least beneficial to improving the yield of wafer packaging.

Description

Wafer level packaging method

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a wafer level packaging method.

Background

Currently, in a wafer level packaging process, the chip needs to be packaged before dicing to seal the chip. When packaging a chip, the back surface of the chip is usually adhered to a temporary carrier disc, and then the chip and the carrier disc are sealed by filling molding, and are pressed for molding, so that the plastic packaging process is completed.

However, in the current process of packaging the chip, the problem of low packaging yield is easily caused.

Disclosure of Invention

The embodiment of the disclosure provides a wafer level packaging method, which is at least beneficial to improving the yield of wafer packaging.

The embodiment of the disclosure provides a preparation method of a semiconductor structure, which comprises the following steps: providing a wafer; forming an electric connection structure in the wafer, wherein the bottom of the electric connection structure is positioned in the wafer, and the top of the electric connection structure is exposed out of the top of the wafer; forming a chip on the wafer, the chip being in electrical contact with the top of the electrical connection structure; forming a packaging structure on the wafer, wherein the chip is positioned in the packaging structure; performing a first back grinding process on the bottom surface of the wafer to expose the bottom of the electric connection structure; and forming a conductive structure, wherein the conductive structure is contacted with the bottom of the electric connection structure.

In some embodiments, the wafer includes a first central region and a first peripheral region, the electrical connection structure is located in the wafer of the first central region, and the first backgrinding process includes: and grinding the bottom of the wafer in the first central area to remove part of the thickness of the wafer until the bottom of the electric connection structure is exposed, reserving the wafer in the first peripheral area, and forming a first annular protruding structure at the bottom of the wafer in the first peripheral area.

In some embodiments, the first annular projection structure has a width of 1mm to 5mm in a direction parallel to the top surface of the wafer.

In some embodiments, the first backgrinding process comprises: and grinding the whole bottom surface of the wafer to remove part of the thickness of the wafer until the bottom of the electric connection structure is exposed.

In some embodiments, a method of forming the package structure includes: forming an initial packaging structure on the wafer top surface by adopting a plastic packaging process, wherein the initial packaging structure packages the chip; and carrying out a second back grinding process on the top surface of the initial packaging structure, removing part of the initial packaging structure until the top surface of the chip is exposed, and forming the packaging structure by the rest part of the initial packaging structure.

In some embodiments, the initial package structure includes: the chip is located in the initial packaging structure of the second central area, and the second back grinding process comprises the following steps: and grinding the top surface of the initial packaging structure of part of the second central area until the top surface of the chip is exposed, so as to remove part of the thickness of the initial packaging structure, reserving the initial packaging structure of the second peripheral area, and forming a second annular protruding structure at the top of the packaging structure of the second peripheral area.

In some embodiments, the second annular bump structure has a width of 5 μm to 20 μm in a direction parallel to the top surface of the wafer.

In some embodiments, the second backgrinding process comprises: and carrying out a second back grinding process on the whole top surface of the initial packaging structure to remove part of the thickness of the initial packaging structure.

In some embodiments, the conductive structure comprises: a wiring board and a connector, the method of forming the conductive structure comprising: forming a wiring board at the bottom of the electric connection structure by adopting an electroplating process, wherein the wiring board is in electric contact with the bottom of the electric connection structure; the connection member is formed on a surface of the wiring board remote from the electrical connection structure.

In some embodiments, after the step of the first backgrinding process and before the step of forming the conductive structure, further comprising: forming a dielectric layer at the bottom of the wafer, wherein the conductive structure is positioned in the dielectric layer, and the dielectric layer exposes the conductive structure far away from the end face of the electric connection structure.

In some embodiments, the electrical connection structure includes a through silicon via interconnect structure and a first pad, the method of forming the electrical connection structure comprising: providing an initial wafer; forming a first through hole in the initial wafer, wherein part of the initial wafer is exposed out of the bottom of the first through hole, and the opening of the first through hole is exposed out of the top surface of the initial wafer; forming a conductive part in the first through hole, wherein the conductive part fills the first through hole so as to form the silicon through hole interconnection structure; and forming the first bonding pad on the top surface of the through silicon via interconnection structure, which is far away from the wafer, wherein the wafer exposes the top surface of the first bonding pad.

In some embodiments, the wafer has a first thickness and the package structure has a second thickness, the first thickness being not less than the second thickness.

In some embodiments, after the step of forming the conductive structure, further comprising: and performing a first cutting process on the wafer to remove the first annular protruding structure.

In some embodiments, after the step of forming the conductive structure, further comprising: and performing a second cutting process on the packaging structure to remove the second annular protruding structure.

In some embodiments, the plurality of chips are arranged at intervals along a direction parallel to the top surface of the wafer, and the wafer, the electrical connection structure, the chips, the electrical connection structure and the conductive structure form a package, and the package further includes: and performing a third cutting process on the packaging piece to form a plurality of mutually separated sub-packaging pieces, wherein each sub-packaging piece at least comprises one chip.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages:

in the above technical scheme, the electric connection structure is formed in the wafer, and the bottom of the electric connection structure is positioned in the wafer, so that the wafer can be used as a supporting structure, and the wafer can not damage the bottom of the electric connection structure while playing a supporting role. The top surface of the wafer exposes the top of the electrical connection structure so that the top of the electrical connection structure can be in electrical contact with the chip. After the chip is packaged to form a package structure, a first back grinding process is performed on the wafer top surface to expose the bottom of the electrical connection structure and form a conductive structure so that the chip can be bonded into a system board or other conductive element through the conductive structure. It is not difficult to find that, because the electrical connection structure is directly formed in the wafer, and the bottom of the electrical connection structure is located in the wafer, the wafer can be used as a supporting structure, so that the use of a temporary carrier disc can be omitted, and the problem of chip offset caused by a pressing process is avoided.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 to 16 are schematic views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the disclosure.

Detailed Description

As known from the background art, in the current process of packaging a chip, the problem of low packaging yield exists.

Analysis has found that one of the reasons for the low package yield is that, at present, in the process of packaging a chip, a redistribution layer needs to be formed, the top surface of the redistribution layer is electrically connected to the chip, and the bottom surface of the redistribution layer is used for forming electrical connection with conductive structures such as solder balls. In order to provide supporting force for the chip and protect the bottom of the redistribution layer, the bottom of the redistribution layer is in direct contact with the temporary carrier plate, then the chip is sealed by filling molding, the plastic packaging process is completed, after the temporary carrier plate is removed, the redistribution layer is exposed, and then conductive structures such as solder balls are formed on the bottom of the redistribution layer. Based on the bonding mode of the chip and the temporary carrier disc, the chip may shift after the lamination forming, and the subsequent manufacturing process is adversely affected, so that the reliability of the semiconductor device is reduced.

The embodiment of the disclosure provides a wafer level packaging method, wherein an electrical connection structure is formed in a wafer, and the bottom of the electrical connection structure is positioned in the wafer, so that the wafer can be used as a supporting structure, the use of a temporary carrier disc is omitted, and the problem of chip offset caused by a pressing process is avoided. The top surface of the wafer exposes the top of the electrical connection structure so that the top of the electrical connection structure can be in electrical contact with the chip. After the chip is packaged to form a packaging structure, a first back grinding process is performed on the top surface of the wafer to expose the bottom of the electrical connection structure and form a conductive structure, so that the chip can be bonded into a system board or other conductive elements through the conductive structure, and the chip can work normally after packaging.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the embodiments of the present disclosure. However, the technical solutions claimed in the embodiments of the present disclosure can be implemented without these technical details and based on various changes and modifications of the following embodiments.

The wafer level packaging method comprises the following steps:

referring to fig. 1, a wafer 1 is provided, and in some embodiments, a wafer 100 may be a semiconductor wafer, and a silicon wafer has a greater hardness, so that the silicon wafer may protect the bottom of the electrical connection structure after the electrical connection structure is formed in the wafer 100. And because the hardness of the silicon wafer is relatively high, the wafer 100 can also have relatively good mechanical support capability for providing mechanical support for chip packaging during subsequent packaging of chips located on the top surface of the wafer 100.

In other embodiments, the material of wafer 100 may also be a silicon wafer, a germanium wafer, a silicon carbide wafer, or a silicon on insulator wafer.

In some embodiments, the wafer 100 may also include the device structure 1 therein, which may include, for example, a DRAM capacitor, a MOS device, and the like.

Referring to fig. 2 and 3, electrical connection structures 101 are formed in wafer 100, with the bottom of electrical connection structures 101 being located in wafer 100, and in some embodiments, the top surface of wafer 100 exposing the top of electrical connection structures 101. That is, the wafer 100 wraps the bottom of the electrical connection structure 101, so that the wafer 100 can protect the electrical connection structure 101, and thus, the packaging process will not cause process damage to the bottom of the electrical connection structure 101 when packaging chips, thereby ensuring that the electrical connection structure 101 has better electrical transmission performance, and ensuring that the subsequent process such as wiring has higher yield due to avoiding the process damage of the electrical connection structure 101. In addition, the top surface of the wafer 100 exposes the top of the electrical connection structure 101, which is beneficial for forming the electrical contact between the chip and the electrical connection structure 101 on the top surface of the wafer 100.

In some embodiments, the top of the electrical connection structure is not higher than the top surface of the wafer 100, so that the gap between the wafer 100 and the subsequently formed chip 102 can be reduced, thereby reducing the use of the package structure and improving the warpage caused by the stress mismatch between the wafer 100 and the package structure.

The electrical connection structure 101 is used to electrically connect a subsequently formed chip to other device structures, thereby extracting electrical signals from the chip.

In some embodiments, the top surface of the electrical connection structure 101 may be higher than the top surface of the wafer 100, so that the area of the electrical connection structure 101 exposed is larger, which is beneficial to form electrical contact with the chip. On the other hand, after the chip is electrically contacted with the top of the electrical connection structure 101, a gap is formed between the bottom of the chip and the top surface of the wafer 100, so that after the chip is packaged, the packaging material can be located in the gap, that is, the whole chip is completely covered, thereby enhancing the sealing effect on the chip. Specifically, in some embodiments, the electrical connection structure 101 is higher than the top surface of the wafer 100, and the electrical connection structure may include a first electrical connection structure in the substrate and a second electrical connection structure in the substrate

In some embodiments, the electrical connection structure 101 is a through-silicon via interconnection structure, the forming method of the through-silicon via interconnection structure is simple, the volume in the wafer 100 is smaller, and a multi-layer wafer stacked package structure with higher density can be formed, so that the size of the semiconductor structure is reduced, and the signal transmission speed is improved. The method of forming the electrical connection structure 101 includes:

an initial wafer 100 is provided, the material of the initial wafer 100 being the same as the material of the wafer 100.

A first via is formed in the initial wafer 100, a portion of the initial wafer 100 is exposed at the bottom of the first via, and an opening of the first via is exposed at the top surface of the initial wafer 100. That is, the first via does not penetrate through the wafer 100. In some embodiments, the process step of forming the first via may include: forming a patterned mask layer on the top surface of the initial wafer 100 to define an opening of the first via; etching the initial wafer 100 with the first through hole opening exposed until a first through hole with a preset depth is formed; and removing the patterned mask layer.

And forming a conductive part in the first through hole, wherein the conductive part is filled with the first through hole so as to form a through silicon via interconnection structure. Specifically, in some embodiments, the conductive portion may include: the barrier layer, seed crystal layer and electrically conductive main part, wherein, the seed crystal layer is located electrically conductive main part's lateral wall, and the barrier layer is located the lateral wall of seed crystal layer, and the inner wall of barrier layer cover first through-hole, and the barrier layer is used for preventing the problem of interdiffusion takes place between electrically conductive main part and the wafer 100, and the seed crystal layer is used for as electroplating seed layer for form electrically conductive main part.

Specifically, the method of forming the conductive portion may include: and forming a barrier layer on the side wall of the first through hole by adopting a deposition process, wherein the barrier layer is positioned on the side wall of the first through hole. In some embodiments, the material of the barrier layer may be a conductive material, for example, may be at least one of Ta, ti, taN or TiN.

And forming a seed crystal layer on the surface of the barrier layer, which is far away from the side wall of the first through hole, by adopting a deposition process, wherein the material of the seed crystal layer can be the same as that of a conductive main body part formed later so as to be used as an electroplating seed layer for forming the conductive main body part later.

A conductive body portion is formed in the first via, the conductive body portion being in contact with a surface of the seed layer remote from the barrier layer. The conductive body portion serves as an electrical connection. In some embodiments, the conductive body portion may be formed using an electroplating process, in particular, a dry electroplating process may be used, such as vacuum plating, vapor phase plating, and fusion plating using a molten metal. In some embodiments, the material of the conductive body portion may be: any of Cu, al, or W.

And forming the first bonding pad on the top surface of the through silicon via interconnection structure, which is far away from the wafer, wherein the wafer exposes the top surface of the first bonding pad. In some embodiments, a plating process may be used to form a first pad on the top surface of the through-silicon via interconnect structure principle wafer. The area of the first bonding pad is larger than that of the through silicon via interconnection structure, and the first bonding pad is arranged to be in electrical contact with the chip 102, so that contact resistance between the first bonding pad and the chip 102 is reduced, and the transmission rate of electric signals is improved.

Specifically, referring to fig. 2, in some embodiments, the top surface of the through-silicon via interconnect structure is flush with the top surface of the wafer, and the top surface of the first pad is higher than the top surface of the die. It should be noted that when the electrical connection structure is configured as described above, an insulating layer may be formed on the surface of the chip 102 facing the wafer 100, and a through-silicon via interconnection structure may be formed in the insulating layer, where the top surface of the through-silicon via interconnection structure is flush with the top surface of the insulating layer, and then a bonding pad is formed on the surface of the through-silicon via interconnection structure in the insulating layer, where the bonding pad is higher than the top surface of the insulating layer. That is, the structure in which the chip 102 is provided to make electrical contact with the electrical connection structure 101 corresponds to the electrical connection structure 101 in fig. 2.

Referring to fig. 3, in other embodiments, the through-silicon via interconnect structure and the first pad may both be located in the wafer 100, with the wafer top surface exposing the first pad away from the top surface of the through-silicon via interconnect structure. It will be appreciated that when the electrical connection structure is the structure of fig. 3, the structure of the chip 102 that makes electrical contact with the electrical connection structure 101 may also be provided in conformity with the electrical connection structure 101 of fig. 3.

In some embodiments, after the via surface is exposed on the top surface of the wafer 100, an insulating dielectric layer is deposited on the top surface of the wafer 100 covering the surface of the wafer 100 and the exposed surface of the via-silicon interconnect structure, and then the insulating dielectric layer and a portion of the via-silicon interconnect structure are removed such that the surface of the via-silicon interconnect structure is not higher than the top surface of the wafer 100, and then a metal pad is formed on the via-silicon interconnect structure.

It is understood that in other embodiments, the top surface of the initial wafer 100 may not be etched, and the initial wafer 100 may be the wafer 100, and the top surface of the wafer 100 is level with the top surface of the through-silicon via interconnect structure.

In other embodiments, the electrical connection structure 101 may be other conductive structures, for example, a metal interconnection structure or the like that may serve as an electrical connection element.

Referring to fig. 4, after the electrical connection structure 101 is formed, a chip 102 is formed on the wafer 100, and the chip 102 is electrically contacted with the top of the electrical connection structure 101. In some embodiments, a flip-chip bonding process may be used to bond the chip 102 to the top of the electrical connection structure 101, thereby making electrical contact of the chip 102 to the electrical connection structure 101. In some embodiments, the chip 102 and the electrical connection structure 101 are interconnected by a hybrid bonding process. In some embodiments, the chip 102 may be any of a DRAM chip 102, an SRAM chip 102, or an SDRAM chip 102. In some embodiments, the number of chips 102 may be plural, and the plural chips 102 may be arranged on the wafer 100 in an array, and the number of chips 102 corresponds to the number of electrical connection structures 101 one by one, that is, one chip 102 and one electrical connection structure 101 form electrical contact.

Referring to fig. 5 to 7, after the chips 102 are formed, a package structure 103 is formed on the wafer 100, and the chips 102 are located in the package structure 103. The packaging structure 103 wraps the chip 102 and is used for providing functions of electric connection, protection, support, assembly and the like for the chip 102, meanwhile, the packaging structure 103 can also protect the chip 102 from being damaged, and the problem that gas or water vapor is used for carrying out the inside of the chip 102 to cause the oxidation of the chip 102 is prevented. In some embodiments, the package structure 103 may be formed on the surface of the package substrate by using a plastic package process, and the material of the package structure 103 may be an encapsulation molding compound, for example, any one of epoxy molding compound, silicone rubber, or polyimide.

In the process of performing the plastic packaging process on the chip 102, the wafer 100 is used as a supporting structure to provide mechanical supporting force for the chip 102 and the plastic packaging process, and the bottom of the electrical connection structure 101 is covered by the wafer 100, so that the plastic packaging process does not damage the electrical connection structure 101 and the electrical connection structure 101 cannot deviate. In this way, after the wiring process is performed based on the electrical connection structure 101 to lead out the electrical signal of the chip 102 through the electrical connection structure 101, the problem of reduced yield of the wiring due to the offset of the electrical connection structure 101 can be avoided, and the reliability of the wafer package can be improved.

In some embodiments, the method of forming the package structure 103 includes:

referring to fig. 5, an initial package structure 2 is formed on the top surface of a wafer 100 by a plastic packaging process, the initial package structure 2 encapsulates a chip 102 therein, the top surface of the initial package structure 2 is higher than the top surface of the chip 102, and the chip 102 is encapsulated therein.

Referring to fig. 6 and 7, a second back grinding process is performed on the top surface of the initial package structure 2, and a portion of the initial package structure 2 is removed until the top surface of the chip 102 is exposed, and the remaining portion of the initial package structure 2 forms a package structure 103. In some embodiments, the top surface of the chip 102 is flush with the top surface of the package structure 103, so that, on the one hand, the chip 102 with the top surface exposed may form an electrical connection with the rest of the conductive elements or form a stacked structure with another packaged chip 102. On the other hand, since the wafer 100 needs to be turned over during the subsequent first back grinding process on the bottom surface of the wafer 100, so that the bottom surface of the wafer 100 faces upward, at this time, since the top surface of the package structure 103 is flush with the top surface of the chip 102, the package structure 103 can play a supporting role, so as to prevent the problem of damage to the chip 102 caused by stress concentration generated by the chip 102.

In some embodiments, the initial package structure 2 includes: a second central region and a second peripheral region, the chip 102 being located in the initial package structure 2 of the second central region, and in some embodiments, the second peripheral region may be an edge region of the initial package structure 2, and the second central region is a region of the initial package structure 2 other than the second peripheral region, and the second back grinding process includes:

referring to fig. 6, the top surface of the initial package structure 2 in a portion of the second central region is polished until the top surface of the chip 102 is exposed, so as to remove a portion of the thickness of the initial package structure 2, leave the initial package structure 2 in the second peripheral region, and form a second annular bump structure 20 on top of the package structure 103 in the second peripheral region. That is, the second annular protrusion structure 20 makes the edge of the package structure 103 have a larger thickness than the second central area of the center of the package structure 103, so that the edge of the package structure 103 can bear a larger strain force, and on one hand, the problem of warpage or deformation of the edge of the package structure 103 can be prevented. On the other hand, the second annular protrusion structure 20 may serve as a substitute for a temporary carrier to provide mechanical support for the wafer 100 during the subsequent polishing of the bottom surface of the wafer 100 to expose the bottom of the electrical connection structure 101. In addition, since the second annular protrusion structure 20 is disposed around the chip 102, and the top of the second annular protrusion structure 20 is higher than the top surface of the chip 102, when the second annular protrusion structure 20 plays a supporting role, the chip 102 is in a suspended state, so that the top surface of the chip 102 is not damaged, and the protection of the chip 102 is facilitated.

Considering that the width of the second annular protrusion structure 20 needs to be set larger, so that more edges in the second annular structure can have a larger thickness, the risk of warpage or peeling of the edges of the package structure 103 can be prevented. In addition, the width of the second annular protrusion structure 20 is not too large, so that after the second annular protrusion structure 20 and the package structure 103 corresponding to the second annular protrusion structure 20 are removed, more package structures 103 remain, and a good package effect is provided for the chip 102. Based on this, in some embodiments, the second annular bump structure 20 is provided with a width of 5 μm to 20 μm in a direction parallel to the top surface of the wafer 100. Within this range, the second annular bump structure 20 may serve to reduce the risk of peeling off the edge of the package structure 103, and may further provide more package structures 103 covering the chip 102, thereby providing a good protection effect for the chip 102.

Referring to fig. 7, in other embodiments, the second back grinding process may also include: a second back grinding process is performed on the entire top surfaces of the initial package structures 2 to remove a portion of the thickness of the initial package structures 2. That is, the top surface of the package structure 103 in the second central area is flush with the top surface of the package structure 103 in the second peripheral area, which is advantageous to simplify the second back grinding process, and to omit the subsequent process of cutting the formed second annular bump structure 20, thereby improving the package efficiency.

Because the thicknesses of the material and the packaging material of the wafer 100 are different, there is a problem that the thermal expansion coefficients of the wafer 100, the electrical connection structure 101 and the packaging structure 103 are different, and the wafer is warped due to the different thermal expansion coefficients of the packaging structure 103 and the wafer 100. Based on this, in some embodiments, the wafer 100 is provided with a first thickness, and the package structure 103 has a second thickness, the first thickness being not smaller than the second thickness. Thus, the thickness of the wafer 100 is larger, so that the wafer 100 has better deformation resistance, and the problem of warping of the wafer 100 caused by the difference between the thermal expansion coefficient of the wafer 100 and the thermal expansion coefficient of the packaging structure can be prevented.

In some embodiments, when the bottom surface of the die 102 is higher than the top surface of the wafer 100, a gap exists between the die 102 of the wafer and the top surface of the wafer 100. At this time, the material used for the package structure 103 may include various kinds. For example, the material of the package structure covering the top surface and the side surface of the chip 102 may be an encapsulation molding compound, for example, any one of epoxy molding compound, silicone rubber, and polyimide. The material of the package structure between the die 102 and the top surface of the wafer 100 may be either DAF (Die Attach Film) adhesive or NCF (non conductivity film) adhesive, which may improve the problem of excessive stress between the packaging film plastic and the wafer due to the packaging film plastic filling the die 102 between the wafer 100.

Referring to fig. 8 to 11, after forming the package structure 103, a first back grinding process is performed on the bottom surface of the wafer 100 to expose the bottom of the electrical connection structure 101. The bottom of the electrical connection structure 101 is used to form an electrical connection with a conductive structure, and the subsequent conductive structure is bonded with other conductive devices, for example, a system board, so that signal transmission between the chip 102 and the system board can be realized, and normal operation of the chip 102 can be realized.

In some embodiments, the wafer 100 includes a first central region and a first peripheral region, the electrical connection structure 101 is located in the wafer 100 of the first central region, and the first backgrinding process includes:

referring to fig. 8, the bottom surface of the wafer 100 in the first central region is polished to remove a portion of the thickness of the wafer 100 until the bottom of the electrical connection structure 101 is exposed, the wafer 100 in the first peripheral region is left, and the bottom of the wafer 100 in the first peripheral region forms the first annular bump structure 10. Wherein the first peripheral region refers to an edge region of the wafer 100, and the first center region refers to the wafer 100 except for the first peripheral region. That is, a portion of the wafer 100 covering the bottom of the electrical connection structure 101 is removed to expose the bottom of the electrical connection structure 101, and the bottom of the wafer 100 located at the periphery of the electrical connection structure 101 is left to form a first annular bump structure 10, where the first annular bump structure 10 surrounds the electrical connection structure 101.

It is not difficult to find that, due to the existence of the first annular protrusion structure 10, the thickness of the wafer 100 in the first peripheral area is greater than that of the wafer 100 in the first central area, so that the greater the deformation force and the peeling force that the wafer 100 in the first peripheral area can bear, the wafer 100 in the first peripheral area is not easy to crack, and the risk of peeling of the edge of the wafer 100 is reduced. In this way, in the subsequent process of forming the electrical contact between the conductive structure and the electrical connection structure 101 in the first central area, the probability of cracking or edge peeling of the bottom of the wafer 100 in the first peripheral area caused by the process damage of the wafer 100 in the first peripheral area caused by the process of forming the conductive structure can be reduced.

In some embodiments, the width of the first annular raised structure 10 is 1mm to 5mm in a direction parallel to the top surface of the wafer 100. In this range, on the one hand, the width of the first annular bump structure 10 is not too large, so that after the wafer 100 is cut along the sidewall of the first annular bump structure 10 to form the die, the problem that the die size is too small due to too many cut wafers 100 caused by too large width of the first annular bump structure 10 can be avoided. On the other hand, in this range, the width of the first annular protrusion structure 10 is not too small, so that the thickness of the edge portion with more bottom of the wafer 100 is thicker, the problem that the wafer 100 in the first peripheral area is easy to crack is further improved, and the risk of peeling the edge of the wafer 100 is reduced.

In other embodiments, a first back grinding process may also be performed on the bottom surface of the wafer 100 before forming the package structure 103, so as to form the first annular bump structure 10 in the first peripheral area. In this way, in the process of forming the package structure 103, the first annular protruding structure 10 may be used to replace the temporary carrier, so as to perform a mechanical supporting function, and thus the use of the temporary carrier may be omitted.

Referring to fig. 9, in further embodiments, the first backgrinding process may include: the entire bottom surface of the wafer 100 is polished to remove a portion of the thickness of the wafer 100 until the bottom of the electrical connection structure 101 is exposed. That is, the bottom surface of the wafer 100 in the first peripheral area is flush with the bottom surface of the wafer 100 in the first central area, that is, the first annular bump structure 10 is not formed, which is advantageous to simplify the first back grinding process on the one hand, and to omit the subsequent process of cutting the formed first annular bump structure 10 on the other hand, thereby improving the packaging efficiency.

Notably, referring to fig. 8, in some embodiments, the second annular raised structures 20 may be formed in a second back grinding process, where the entire bottom surface of the wafer 100 is ground; referring to fig. 9, in other embodiments, the entire top surface of the initial package structure 2 may be polished in a second back grinding process, and the back surface of the entire wafer 100 may be polished in a first back grinding process; referring to fig. 10, in still other embodiments, the entire top surface of the initial package structure 2 may be ground in a second back grinding process, forming a first annular bump structure 10 in a first back grinding process; referring to fig. 11, in still other embodiments, the second annular bump structure 20 may be formed in a second back grinding process and the first annular bump structure 10 may be formed in a first back grinding process.

In some embodiments, the first annular raised structure 10 may be any one of a circle or a rectangle, and the second annular raised structure 20 may be any one of a circle or a rectangle.

Referring to fig. 12 to 13, after exposing the bottom of the electrical connection structure 101, a conductive structure 106 is formed, and the conductive structure 106 is in contact with the bottom of the electrical connection structure 101. The conductive structure 106 is used for leading out an electrical signal of the electrical connection structure 101 located in the wafer 100, so as to realize signal transmission between the chip 102 and an external circuit. In some embodiments, the conductive structures 106 may be bonded to a system board, which may be a PCB board with metal lines thereon, to electrically connect the chips 102 to the system board, which may enable interconnection between the chips 102.

Referring to fig. 12, in some embodiments, after the step of the first backgrinding process and before the step of forming the conductive structure 106, further comprises: a dielectric layer 104 is formed on the bottom surface of the wafer 100, the conductive structure 106 is located in the dielectric layer 104, and the dielectric layer 104 exposes the end surface of the conductive structure 106 away from the electrical connection structure 101, so that the conductive structure 106 can lead out the electrical signal of the chip 102. In some embodiments, the dielectric layer 104 is located on the bottom surface of the wafer 100, which may protect the bottom surface of the wafer 100. In some embodiments, when the bottom surface of the wafer 100 has the first annular bump structure 10, the dielectric layer 104 may be located only on the bottom surface of the wafer 100 in the first central region, so that the process of forming the dielectric layer 104 may be simplified. In some embodiments, the dielectric layer 104 may be formed on the bottom surface of the wafer 100 by a deposition process, and the material of the dielectric layer 104 may be at least one of oxide and silicon nitride.

After forming the dielectric layer 104, a conductive structure is formed, and in some embodiments, the conductive structure 106 includes: the wiring board 3 and the connection member 4, the method of forming the conductive structure 106 includes:

the wiring board 3 is formed on the bottom of the electrical connection structure 101 using an electroplating process, and the wiring board 3 is in electrical contact with the bottom of the electrical connection structure 101, and in some embodiments, the wiring board 3 may be a second pad, and the second pad is formed on the bottom of the electrical connection structure 101, and the connector 4 is electrically connected to the electrical connection structure 101 through the second pad. Compared with the method of directly forming the connecting piece 4 at the bottom of the electrical connection structure 101, the process of forming the second bonding pad and then forming the connecting piece 4 is simpler, and the combination between the connecting piece 4 and the second bonding pad is firmer, which is beneficial to improving the electrical transmission performance.

In some embodiments, the material of the second pad may be any of copper, aluminum, tin, or gold.

In some embodiments, when the bottom surface of the wafer 100 has the dielectric layer 104, the process for forming the wiring board 3 includes: patterning the dielectric layer 104 to define an opening of the wiring board 3; etching the patterned dielectric layer 104 to form a first groove, wherein the first groove exposes the bottom of the electrical connection structure 101; the wiring board 3 is formed in the first groove using an electroplating process. In some embodiments, the top surface of the wiring board 3 may be higher than the top surface of the dielectric layer 104, thus facilitating subsequent formation of the connection 4 to the top surface of the wiring board 3.

The connection 4 is formed on the surface of the wiring board 3 remote from the electrical connection structure 101. In some embodiments, the connector 4 may be a micro bump, for example, a solder ball. The micro-bump has smaller size, so that the requirement of the miniaturized wafer packaging structure 103 can be met, the micro-bump is tightly combined with the wiring board, the contact resistance between the micro-bump and the wiring board can be reduced, and RC delay is reduced.

In some embodiments, the connector 4 may be formed using a micro-bump process, the process comprising: depositing solder on a surface of the wiring board 3 remote from the electrical connection structure 101, and in some embodiments, the solder may be deposited on the surface of the wiring board 3 by any one of electroplating, vapor deposition, electroless plating, or printing; the solder is subjected to a reflow process to form the connector 4.

In some embodiments, before the step of forming the connector 4, a solder mask layer 105 is formed on the top surface of the dielectric layer 104, where the solder mask layer 105 is used to prevent solder used during the process of forming the connector 4 from scattering to the surface of the dielectric layer 104, thereby polluting the surface of the dielectric layer 104. In addition, the solder mask layer 105 has a moisture-proof function and can protect the dielectric layer 104, so that the dielectric layer 104 can maintain good performance.

Referring to fig. 14, in some embodiments, after the step of forming the conductive structure 106, further comprises: a first cutting process is performed on the wafer 100 to remove the first annular bump structure 10. During the first cutting process, further comprising: the wafer 100 corresponding to the first annular bump structure 10 is diced, so that the sidewalls of the diced wafer 100 are flush with the sidewalls of the dielectric layer 104 and the sidewalls of the solder mask layer 105, and thus, the bottom surface of the wafer 100 which is not diced is covered with the dielectric layer 104, so that the bottom surface of the wafer 100 can be well protected. The first dicing process also makes the surface of the diced wafer 100 flat, which is beneficial to forming a stacked structure with another packaged chip 102. In some embodiments, the first cutting process may include any one of a grinding wheel cutting process or a laser cutting process.

Referring to fig. 15, in some embodiments, after the step of forming the conductive structure 106, further comprises: a second dicing process is performed on the package structure 103 to remove the second annular bump structure 20. During the second cutting process, further comprising: the package structure 103 corresponding to the second annular bump structure 20 is cut, so that the sidewalls of the package structure 103, the wafer 100, the dielectric layer 104 and the solder mask layer 105 after cutting are flush, and the surface of the package structure 103 after cutting is flat, which is beneficial to forming a stacked structure with another package chip 102. In some embodiments, the second cutting process may include any one of a grinding wheel cutting process or a laser cutting process.

Referring to fig. 16, in some embodiments, the plurality of chips 102 are arranged at intervals along a direction parallel to the top surface of the wafer 100, and the wafer 100, the electrical connection structure 101, the chips 102, the electrical connection structure 101, and the conductive structure 106 form a package, and further includes: a third dicing process is performed on the packages to form a plurality of mutually separated sub-packages 5, each sub-package 5 including at least one of the chips 102. In some embodiments, when the wafer 100 is a wafer, the sub-packages 5 formed are dies. Because the wafer 100 and the packaging structure 103 are arranged to replace the temporary carrier in the packaging process, the pressing process of the temporary carrier and the chip 102 is omitted, and the problem of chip 102 deviation caused by the pressing process is avoided. Therefore, in the formed package, each chip 102 is disposed opposite to the electrical connection structure 101 and the conductive structure 106, so that the problem that damage is caused to the electrical connection structure 101 or the conductive structure 106 corresponding to the adjacent chip 102 due to the offset of the chip 102 when one chip 102 is separated in the third cutting process can be prevented, and the yield of the formed sub-package structure 103 is improved.

In the wafer level packaging method provided in the above embodiment, the electrical connection structure 101 is formed in the wafer 100, and the bottom of the electrical connection structure 101 is located in the wafer 100, so that the wafer 100 can be used as a supporting structure, the use of temporary carrier is omitted, and the problem of chip 102 offset caused by the lamination process is avoided. The top surface of the wafer 100 exposes the top of the electrical connection structure 101 such that the top of the electrical connection structure 101 may be in electrical contact with the die 102. After the chip 102 is packaged to form the package structure 103, a first back grinding process is performed on the top surface of the wafer 100 to expose the bottom of the electrical connection structure 101 and form the conductive structure 106, so that the chip 102 may be bonded into a system board or other conductive element through the conductive structure 106, so that the chip 102 may work normally after packaging.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Variations and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should therefore be assessed only by that of the appended claims.

Claims (15)

1. A wafer level packaging method, comprising:

providing a wafer;

forming an electric connection structure in the wafer, wherein the bottom of the electric connection structure is positioned in the wafer, and the top of the electric connection structure is exposed out of the top of the wafer;

forming a chip on the wafer, the chip being in electrical contact with the top of the electrical connection structure;

forming a packaging structure on the wafer, wherein the chip is positioned in the packaging structure;

performing a first back grinding process on the bottom surface of the wafer to expose the bottom of the electric connection structure;

and forming a conductive structure, wherein the conductive structure is contacted with the bottom of the electric connection structure.

2. The wafer level packaging method of claim 1, wherein the wafer includes a first central region and a first peripheral region, the electrical connection structure is located in the wafer of the first central region, the first backgrinding process includes: and grinding the bottom of the wafer in the first central area to remove part of the thickness of the wafer until the bottom of the electric connection structure is exposed, reserving the wafer in the first peripheral area, and forming a first annular protruding structure at the bottom of the wafer in the first peripheral area.

3. The wafer level packaging method according to claim 2, wherein the width of the first annular bump structure is 1mm to 5mm in a direction parallel to the top surface of the wafer.

4. The wafer level packaging method of claim 1, wherein the first backgrinding process comprises: and grinding the whole bottom surface of the wafer to remove part of the thickness of the wafer until the bottom of the electric connection structure is exposed.

5. The wafer level packaging method of claim 1, wherein the method of forming the package structure comprises:

forming an initial packaging structure on the wafer top surface by adopting a plastic packaging process, wherein the initial packaging structure packages the chip;

and carrying out a second back grinding process on the top surface of the initial packaging structure, removing part of the initial packaging structure until the top surface of the chip is exposed, and forming the packaging structure by the rest part of the initial packaging structure.

6. The wafer level packaging method of claim 5, wherein the initial packaging structure comprises: the chip is located in the initial packaging structure of the second central area, and the second back grinding process comprises the following steps:

and grinding the top surface of the initial packaging structure of part of the second central area until the top surface of the chip is exposed, so as to remove part of the thickness of the initial packaging structure, reserving the initial packaging structure of the second peripheral area, and forming a second annular protruding structure at the top of the packaging structure of the second peripheral area.

7. The wafer level packaging method according to claim 6, wherein the width of the second annular bump structure is 5 μm to 20 μm in a direction parallel to the top surface of the wafer.

8. The wafer level packaging method of claim 5, wherein the second backgrinding process comprises: and carrying out a second back grinding process on the whole top surface of the initial packaging structure to remove part of the thickness of the initial packaging structure.

9. The wafer level packaging method of claim 1, wherein the conductive structure comprises: a wiring board and a connector, the method of forming the conductive structure comprising:

forming a wiring board at the bottom of the electric connection structure by adopting an electroplating process, wherein the wiring board is in electric contact with the bottom of the electric connection structure;

the connection member is formed on a surface of the wiring board remote from the electrical connection structure.

10. The wafer level packaging method of claim 9, further comprising, after the step of the first back grinding process and before the step of forming the conductive structure: forming a dielectric layer at the bottom of the wafer, wherein the conductive structure is positioned in the dielectric layer, and the dielectric layer exposes the conductive structure far away from the end face of the electric connection structure.

11. The wafer level packaging method of claim 1, wherein the electrical connection structure comprises a through silicon via interconnect structure and a first pad, the method of forming the electrical connection structure comprising:

providing an initial wafer;

forming a first through hole in the initial wafer, wherein part of the initial wafer is exposed out of the bottom of the first through hole, and the opening of the first through hole is exposed out of the top surface of the initial wafer;

forming a conductive part in the first through hole, wherein the conductive part fills the first through hole so as to form the silicon through hole interconnection structure;

and forming the first bonding pad on the top surface of the through silicon via interconnection structure, which is far away from the wafer, wherein the wafer exposes the top surface of the first bonding pad.

12. The wafer level packaging method of claim 1, wherein the wafer has a first thickness and the package structure has a second thickness, the first thickness being not less than the second thickness.

13. The wafer level packaging method of claim 2, further comprising, after the step of forming the conductive structure:

and performing a first cutting process on the wafer to remove the first annular protruding structure.

14. The wafer level packaging method of claim 6, further comprising, after the step of forming the conductive structure:

and performing a second cutting process on the packaging structure to remove the second annular protruding structure.

15. The method of claim 13 or 14, wherein the plurality of chips are arranged at intervals along a direction parallel to the top surface of the wafer, and the wafer, the electrical connection structure, the chips, the electrical connection structure, and the conductive structure form a package, and further comprising: and performing a third cutting process on the packaging piece to form a plurality of mutually separated sub-packaging pieces, wherein each sub-packaging piece at least comprises one chip.