WO2022161247A1

WO2022161247A1 - Wafer-level package system-in-package structure and packaging method

Info

Publication number: WO2022161247A1
Application number: PCT/CN2022/072997
Authority: WO
Inventors: 黄河; 刘孟彬; 向阳辉
Original assignee: 中芯集成电路（宁波）有限公司
Priority date: 2021-01-29
Filing date: 2022-01-20
Publication date: 2022-08-04

Abstract

Disclosed are a wafer-level package system-in-package structure and a packaging method. The packaging method comprises: providing a device wafer, which comprises a plurality of first chips, which are provided with first welding pads exposed from an upper surface of the device wafer; forming conductive bumps on the first welding pads by means of an electroplating process; providing at least one second chip after the conductive bumps are formed, with a lower surface of the second chip being provided with a second welding pad; and bonding the second chip onto the device wafer, and making the second welding pad of the second chip electrically connect to the conductive bumps. According to the present invention, the conductive bumps are formed by means of an electroplating process, and then a welding process is carried out to complete wafer-level system integration, wherein the conductive bumps on the entire wafer can be formed at the same time by means of the electroplating process, such that the efficiency can be improved; and the present invention is compatible with a front end process of a semiconductor, so that wafer-level system integration can be completed by means of the front end process, thereby greatly improving the efficiency of the whole system integration process and omitting the transfer between the front end process and a packaging process.

Description

A wafer-level system packaging structure and packaging method

technical field

The invention relates to the field of semiconductor device manufacturing, in particular to a wafer-level system packaging structure and a packaging method.

Background technique

With the development trend of VLSI, the feature size of integrated circuits continues to decrease, and people's requirements for the packaging technology of integrated circuits continue to increase accordingly. Existing packaging technologies include ball grid array (BGA), chip scale (chip scale) package, CSP), wafer level package (wafer level package, WLP), three-dimensional package (3D) and system package (system in package) package, SiP).

technical problem

At present, in order to meet the goals of lower cost, more reliability, faster and higher density of integrated circuit packaging, advanced packaging methods mainly adopt the three-dimensional stacking mode of wafer level system in package (WLPSIP) , Compared with the traditional system packaging, the wafer-level system packaging is to complete the packaging integration process on the wafer, which has the advantages of greatly reducing the area of the packaging structure, reducing the manufacturing cost, optimizing the electrical performance, and batch manufacturing. Reduce workload and equipment requirements.

In the wafer-level system packaging process, not only need to bond two bare chips together to achieve physical connection, but also need to connect their interconnecting leads to achieve electrical connection.

technical solutions

The purpose of the present invention is to provide a wafer-level system packaging method, which simplifies the packaging process. In order to achieve the above object, the present invention provides a wafer-level system packaging method, including: providing a device wafer, the device wafer includes a plurality of first chips, and the first chips have exposed surfaces on the device wafer. a first bonding pad on the surface; a conductive bump is formed on the first bonding pad by an electroplating process; after the conductive bump is formed, at least one second chip is provided, and the lower surface of the second chip has a second bonding pad ; Bond the second chip on the device wafer, and electrically connect the second pad of the second chip with the conductive bump.

The present invention also provides a wafer-level system packaging structure, comprising: a device wafer, the upper surface of the device wafer has a first pad, the first pad is electrically connected with a conductive bump, the conductive bump The block is formed by an electroplating process; the upper surface of the device wafer is provided with a photolithographic bonding material, and the photolithographic bonding material has a cavity; a second chip, the second chip passes through the A photolithographic bonding material is bonded on the device wafer and covers the cavity, and the cavity is used as a working cavity of the second chip; the lower surface of the second chip has a second pad , the second pad is electrically connected to the conductive bump.

beneficial effect

The beneficial effects of the present invention are that the conductive bumps are formed by the process, and the electroplating process can simultaneously form the conductive bumps on the entire wafer, which can improve the efficiency, and is compatible with the front-end process of the semiconductor, so that the wafer-level system can be completed by the front-end process. The integration greatly improves the process efficiency of the entire system integration and saves the transition between the front-end process and the packaging process.

Further, the second chip and the first chip and the interconnecting chip and the first chip are bonded by a dry film. On the one hand, the dry film is a photoresistable material, and a desired pattern can be formed by a semiconductor process. The process is simple and compatible with semiconductors. Process compatible, mass production is possible. Moreover, the elastic modulus of the dry film is relatively small, which can be easily deformed without being damaged when subjected to thermal stress, thereby reducing the bonding stress between the second chip/interconnect chip and the first chip. When photolithography dry film, the dry film of the wall structure can be reserved around the area where the external conductive bumps and conductive bumps are pre-formed, so that when the external conductive bumps and conductive bumps are formed, due to the blocking of the dry film, the expected formation can be achieved. Shaped external conductive bumps and conductive bumps to prevent lateral overflow of the external conductive bumps and conductive bumps. When a cavity needs to be formed under the second chip, by forming an opening in the adhesive layer, and the second chip covers the opening to form a cavity, process steps can be saved (otherwise, the cavity needs to be formed when the second chip is fabricated).

Further, when forming the photolithographic bonding material, its projection is centered on the center of the second chip, and the coverage area is greater than 10% of the area of the second chip, preferably covering the entire lower surface of the second chip (except the second pad). In this way, when the plastic encapsulation layer is formed in the subsequent process, it is ensured that there is no void under the second chip, the bonding strength is improved, and the yield is improved.

Further, due to the influence of the manufacturing process of the device wafer, the surface of the external electrode is usually lower than the surface of the first chip. Therefore, the electrical properties of the external electrode are drawn out by electroplating external conductive bumps, and the external conductive bumps protrude from the external surface. The surface of the electrode is easy to carry out the wire bonding process, and the connection performance between the bonding wire and the external conductive bump is higher, which is beneficial to improve the reliability of the package; when the conductive bump is formed, the external conductive bump is formed at the same time. , which is beneficial to improve the packaging efficiency; in addition, the second chip is bonded to the surface of the first chip, and the external conductive bumps are exposed, which can provide accommodation space for the bonding wires connecting the external electrodes, so that the bonding wires are compatible with three-dimensional stacked crystals. Round-level packaging does not lead to an increase in the height of the packaging structure, and has the advantages of simple wire bonding process and low cost.

Further, by interconnecting the chips, the leading end (for example, the I/O end) of the chip module composed of the first chip and the second chip is led to the side of the device wafer with the first bonding pad and the external electrode, and Compared with the solution of leading the terminal to the side of the device wafer facing away from the first pad and the external electrode, subsequent processing of the device wafer (for example, backside thinning or through-silicon via interconnection process) can be performed. Therefore, the damage to the device wafer is reduced, which is beneficial to improve the packaging reliability, and the packaging method is suitable for system integration of various wafers, and the packaging compatibility is correspondingly improved.

Further, by first bonding the plurality of second chips on the device wafer, the pre-alignment of the plurality of second chips is realized, so that the plurality of second chips and the conductive bumps can be thermally bonded at the same time. Compared with sequentially bonding each second chip and the conductive bump, the manufacturing efficiency is greatly improved. Further, a plurality of second chips and conductive bumps and/or a plurality of interconnecting chips and external conductive bumps can be thermally bonded at the same time, compared to single-point thermal pressing of each second chip or interconnecting chip. Bonding greatly improves manufacturing efficiency.

Further, the projection of the first bonding pad and the second bonding pad in the direction perpendicular to the surface of the device wafer has an overlapping area, and the area of the overlapping area is greater than half of the area of the first bonding pad or the second bonding pad, so as to improve the binding strength.

Further, when the adhesive layer is formed, its projection is centered on the center of the second chip/interconnect chip, and the coverage area is greater than 10% of the area of the second chip/interconnect chip, preferably covering the entire second chip/interconnect chip. The lower surface (except the area where the electrodes are located), in this way, when the plastic encapsulation layer is formed in the subsequent process, it is ensured that there is no gap under the second chip/interconnect chip, which improves the bonding strength and improves the yield.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

1 to 8 are schematic diagrams of structures corresponding to different steps in a wafer-level system packaging method according to Embodiment 1 of the present invention.

FIG. 9 to FIG. 13 show schematic structural diagrams corresponding to different steps in a wafer-level system packaging method according to Embodiment 2 of the present invention.

FIG. 14 to FIG. 18 show schematic structural diagrams corresponding to different steps in a wafer-level system packaging method according to Embodiment 3 of the present invention.

FIGS. 19 to 21 are schematic diagrams illustrating structures corresponding to the formation of openings in a wafer-level system packaging method according to Embodiment 4 of the present invention.

Description of reference numerals: 5-interconnect chip; 501-plug; 502-pad; 51-interconnect structure; 10-wafer; 110-first pad; 101-first chip; 12-dielectric layer; 13-through silicon via structure; 20-second chip; 21-second pad; 30-conductive bump; 31-external conductive bump; 111-external electrode; 40-photolithographic bonding material; 50- 41-opening; 60-covering substrate; 200-substrate; 61-electrical connection structure; 100-chip module; 2-circuit board; 210-circuit structure; 220-bonding wire; 230-adhesive layer; 240 - plastic sealing layer; 600 - plastic sealing layer; 610 - redistribution layer; 62 - solder balls; 70 - insulating layer; 80 - cover substrate; 81 - accommodation cavity; 82 - electrical lead-out structure.

Embodiments of the present invention

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and accompanying drawings. However, it should be noted that the concept of the technical solution of the present invention can be implemented in various forms, and is not limited to the specific implementation described here. example. The accompanying drawings are all in a very simplified form and in an inaccurate scale, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers Layers may be on, adjacent to, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. Spatial relational terms such as "under", "below", "below", "under", "above", "above", etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. If a method herein includes a series of steps, the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the steps may be omitted and/or some other steps not described herein may be added to this method. If the components in a certain drawing are the same as the components in other drawings, although these components can be easily identified in all the drawings, in order to make the description of the drawings clearer, this specification will not refer to all the same components. Numbers are attached to each figure.

实施例Example 11

An embodiment of the present invention provides a wafer-level system packaging method, including the following steps: S01 : providing a device wafer, the device wafer includes a first chip, and the first chip has a first solder joint exposing an upper surface of the device wafer pads; S02: forming conductive bumps on the first pads by an electroplating process S03: after forming the conductive bumps, at least one second chip is provided, and the lower surface of the second chip has a second bonding pad; S04: bonding the second chip The device is assembled on the device wafer, and the second bonding pad of the second chip is electrically connected with the conductive bump. It should be noted that the SON in this specification does not represent the order of the manufacturing processes. FIGS. 1 to 8 are schematic structural diagrams corresponding to different steps of the wafer-level system packaging method of the present embodiment. Please refer to FIGS. 1 to 8 for detailed description of each step.

Referring to FIG. 1 , a device wafer is provided. The device wafer includes a wafer 10 and a first chip 101 formed on the upper surface of the wafer 10 . The upper surface of the first chip 101 exposes first bonding pads 110 , and the first bonding pads 110 Can be a pad. In this embodiment, the wafer 10 is a silicon substrate. In other embodiments, the material of the wafer 10 can also be other semiconductor materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the semiconductor substrate can also be a silicon-on-insulator substrate or an on-insulator substrate germanium substrates and other types of substrates. The semiconductor material may be a material suitable for process requirements or ease of integration. According to actual process requirements, the thickness of the wafer 10 is 10 micrometers to 100 micrometers.

The first chip 101 may be formed on the wafer 10 through a semiconductor process. For example, the device wafer is a to-be-packaged wafer that has completed device fabrication. The plurality of first chips 101 formed in the wafer 10 may be of the same type or different types of chips. It should be noted that the device wafer can be fabricated by using an integrated circuit fabrication technology, for example, an N-type metal-oxide-semiconductor (N-Metal-Oxide-Semiconductor, NMOS) is formed on the first semiconductor substrate through processes such as deposition and etching. ) devices and P-Metal-Oxide-Semiconductor (PMOS) devices, etc., forming a dielectric layer, a metal interconnection structure, and a pad electrically connected to the metal interconnection junction on the device, so as to make the device At least one first chip 101 is integrated in the wafer. In another embodiment, the first chip 101 may be a fabricated chip, which is adhered to the upper surface of the device wafer. At this time, there is no micro-device inside the device wafer, and the device wafer may also be internally integrated with micro-devices such as MOS transistors, and the first chip 101 and the micro-devices are electrically connected through an interconnection structure. Continuing to refer to FIG. 1 , in this embodiment, a dielectric layer 12 exposing the first pads 110 is formed on the upper surface of the device wafer. The dielectric layer 12 has a certain thickness, which can provide space in the subsequent steps of forming conductive bumps.

Referring to FIG. 2, a photolithographic bonding material 40 is formed on the upper surface of the device wafer, and the photolithographic bonding material 40 is used to bond the second chip to the upper surface of the device wafer in a later process. In this embodiment, the photolithographic bonding material 40 includes a film-like dry film or a liquid dry film. In other embodiments, other photosensitive adhesive materials may also be selected. Film-like dry film is to coat the solvent-free photoresist on the polyester film base, and then cover the polyethylene film; when using, remove the polyethylene film, and press the solvent-free photoresist on the base plate , After exposure and development, graphics can be formed in the dry film. Liquid dry film means that the components in the film-like dry film exist in liquid form. Dry film is a permanently bonded film with high bond strength. The film-like dry film can be formed on the device wafer by means of film sticking, and the liquid dry film is coated on the device wafer by a spin coating process, and then the liquid dry film is cured. The second chip and the device wafer are bonded by dry film. On the one hand, the dry film is a photolithographic material, which can be used to form a desired pattern through a semiconductor process. The process is simple and compatible with the semiconductor process, and can be mass-produced. Moreover, the elastic modulus of the dry film is relatively small, which can be easily deformed without being damaged when subjected to thermal stress, thereby reducing the bonding stress between the second chip and the device wafer.

In an optional embodiment, after forming the photolithographic bonding material, the method further includes: patterning the photolithographic bonding material, and forming a surrounding wall structure around the area where the conductive bumps are pre-formed. The interior enclosed by the enclosure wall structure is an area where conductive bumps are formed, the enclosure wall structure is preferably a closed annular structure, and the enclosed space is cylindrical. During photolithography of the photolithographic bonding material, the photolithographic bonding material of the surrounding wall structure is retained around the area where the conductive bumps are pre-formed, so that when the conductive bumps are formed, due to the blocking of the surrounding walls, the desired shape can be formed. Conductive bumps to prevent lateral overflow of the conductive bumps. In this embodiment, the photolithographic bonding material 40 is formed on the surface of the device wafer. In another embodiment, the photolithographic bonding material 40 can also be formed on the surface of the second chip 20 .

In this embodiment, the thickness of the formed photolithographic bonding material 40 is 5-200 μm, such as 15 μm, 30 μm, 80 μm, 150 μm, and the like. In addition, the projection of the photolithographic bonding material 40 on the surface of the device wafer is centered on the center of the second chip 20 and covers at least 10% of the area of the second chip. Specifically, the thickness of the photolithographic bonding material 40 is related to the height of the conductive bumps formed in the later process. The correlation between the two will be described in detail later when the conductive bumps are formed. In this embodiment, the photolithographic bonding material 40 covers at least 10% of the area of the second chip, and covers the center of the second chip. It is preferable to cover the entire lower surface of the second chip (except the area where the second pad is located). When the plastic sealing layer is formed in the subsequent process, it is not easy to fill the plastic sealing layer to the middle position of the second chip (because it is far from the edge of the second chip), the photolithographic bonding material 40 of this solution not only serves as a bonding agent It also plays a role of sealing in advance. The photolithographic bonding material 40 and the plastic sealing layer in the subsequent process jointly play the role of sealing the second chip. In an alternative solution, the photolithographic bonding material 40 covers the entire lower surface of the second chip 20 (except for the area where the second pad is located), so that there is no gap under the second chip when the plastic encapsulation layer is formed in the subsequent process. , improve the bonding strength and improve the yield.

With continued reference to FIG. 2 , the conductive bumps 30 are formed on the first pads 110 through an electroplating process. The material of the conductive bump includes any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium. The height of the formed conductive bump 30 is related to the height of the dry film and the structure of the second chip. When the second pad of the second chip is equal to the lower surface of the second chip, the height of the conductive bump 30 is related to the height of the dry film. The heights of (including the height of the dielectric layer 12 in this embodiment) are approximately the same height, so that when the second chip and the dry film are adhered, the second pads 21 are just in contact with the conductive bumps 30 . When the second bonding pad 21 is recessed downward relative to the lower surface of the second chip 20 , the height of the conductive bump 30 is equal to the depth of the recess+dry film thickness+the thickness of the dielectric layer 12 . In an optional embodiment, the height of the conductive bump is 5-200 μm. Such as 10μm, 50μm, 100μm. The electroplating process includes electroless palladium immersion gold (ENEPIG) or electroless nickel gold (ENIG), wherein the process parameters of ENEPIG or ENIG can refer to Table 1.

Table 1

The conductive bumps are formed by the electroplating process, and then the soldering process is performed to complete the wafer-level system integration. The electroplating process can form the conductive bumps on the entire wafer at the same time, which can improve the efficiency. Moreover, it is compatible with the front-end process of the semiconductor, so that the front-end process can be used. The process completes the wafer-level system integration, which greatly improves the process efficiency of the entire system integration and saves the transition between the front-end process and the packaging process. Before electroless plating, in order to better complete the electroplating process, the surface of the pad can be cleaned first to remove the natural oxide layer on the surface of the pad and improve the surface wettability of the pad; after that, activation can be performed process to promote the nucleation and growth of the coating metal on the metal to be plated. In order to better realize electroplating and form relatively complete conductive bumps, the settings of the first pad and the second pad also need to meet certain requirements. For example, the exposed area of the first pad is 5-200 square microns. Within this range, the pads can be in sufficient contact with the plating solution to avoid insufficient contact between the pads and the plating solution, which will affect the contact between the conductive bumps and the pads. In addition, it can also ensure that the contact area will not be too large to reduce the plating efficiency and will not occupy too much surface. The cross-sectional area of the formed conductive bumps is greater than 10 square micrometers, which can not only ensure that the area occupied by the conductive bumps is not too large, but also ensure the bonding strength between the conductive bumps and the bonding pads. In an alternative solution, the material of the conductive bump is the same as the material of the first bonding pad, which makes it easier to form the conductive bump. Of course, the material of the first pad can be different from the material of the conductive bump. In order to form the conductive bump more easily, a material layer can be formed on the first pad first. The material of the material layer is the same as the material of the conductive bump. The method of forming the material layer may be a deposition process.

Referring to FIG. 3 , at least one second chip 20 is provided, and the lower surface of the second chip 20 has second pads 21 . The second chip 20 is used as a chip to be integrated in the wafer-level packaging, and the wafer-level packaging method in this embodiment can realize heterogeneous integration. Correspondingly, the second chip 20 may be a chip made of a silicon wafer, or a chip made of other materials. The second chip 20 is made by using an integrated circuit manufacturing technology, and can be a memory chip, a communication chip, a processor or a logic chip. The second chip 20 generally includes an NMOS device or a PMOS device or the like formed on a semiconductor substrate. The second bonding pads 21 are located on the lower surface of the second chip 20 and are used to realize electrical connection between the second chip 200 and other devices. Specifically, the second pad 21 may be a pad. In this embodiment, the material of the second pad 21 includes any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium. In a preferred solution, the second pad and the conductive bump The material combinations include gold-gold, copper-copper, copper-tin or gold-tin.

The plurality of second chips are chips with the same function; the plurality of second chips include at least two chips with different functions; and the first chips are passive devices or active devices. The second chip can be a sensor module chip, a MEMS chip, a filter chip, a logic chip, a memory chip, a capacitor, an inductor, etc., and the capacitor can be an MLCC capacitor. The sensor module chip includes a module chip for sensing at least one of radio frequency signals, infrared radiation signals, visible light signals, acoustic wave signals, and electromagnetic wave signals; the filter chip includes at least one of surface acoustic wave resonators and bulk acoustic wave resonators. The second chip may be an encapsulated chip, and a subsequent plastic encapsulation process is not required. The second chip may also be a bare chip, and the second chip may also be a chip with a shielding layer on the top surface.

In this embodiment, the materials of the second bonding pads 21 and the conductive bumps 30 are metal, and the second bonding pads 21 and the conductive bumps 30 are electrically connected through a thermocompression bonding process. Each second bonding pad 21 and each conductive bump 30 are thermocompression bonded one by one; or a plurality of second bonding pads 21 and a plurality of conductive bumps 30 are thermocompression bonded simultaneously. By first bonding the plurality of second chips 20 on the device wafer, the pre-alignment of the plurality of second chips 20 is realized, so that the plurality of second chips 20 and the conductive bumps 30 can be thermally bonded at the same time. Compared with bonding each of the second chips 20 and the conductive bumps 30 in sequence, the manufacturing efficiency is greatly improved. In this embodiment, the area of the first bonding pad 110 or the second bonding pad 21 is 5-200 square micrometers; the area of the overlapping area of the second bonding pad 21 and the conductive bump 30 in the direction perpendicular to the surface of the device wafer is larger than that of the second bonding pad 21 and the conductive bump 30 . Half of the area of the second pads 21 to improve the bonding strength of the two. In an alternative solution, the conductive bumps 30 and the second pads 21 are facing each other, that is, in the direction perpendicular to the surface of the device wafer, the two are to the greatest extent possible. overlap each other. In an optional solution, the cross-sectional area of the conductive bump is greater than 10 square micrometers to ensure structural strength.

In this embodiment, the plurality of second chips 20 are bonded to the surface of the wafer one by one. Referring to FIG. 4 , in another embodiment, the surface of the second chip 20 with the second pads 21 is the front side, and the side opposite to the front side is the back side. Before the second chip 20 is bonded to the device wafer, the second chip 20 is bonded to the device wafer. The backside of the chip 20 is temporarily bonded to the substrate 200 ; after the second chip 20 is bonded to the wafer, the substrate is debonded. The substrate 200 may be a carrier wafer for temporarily fixing a plurality of second chips 20, and the substrate 200 is also used for supporting the second chips 20 in the process of bonding the second chips 20 to the device wafer, thereby Improve the reliability of bonding. The second chip 20 is temporarily bonded to the substrate 200 through an adhesive layer or electrostatic bonding. Electrostatic bonding technology is a method to achieve bonding without any adhesive. During the bonding process, the second chip to be bonded and the substrate are connected to different electrodes respectively, and the surface of the second chip and the substrate are charged under the action of voltage, and the charges on the surface of the second chip and the substrate are electrically different, so that in the first During the bonding process of the two chips and the substrate, a large electrostatic attraction is generated to realize the physical connection between the two. Correspondingly, in the process of debonding, the substrate can be separated from the second chip 20 by a chemical method or a mechanical peeling method.

Referring to FIG. 5 , in this embodiment, after bonding the second chips 20 , the method further includes: forming a plastic sealing layer 50 , and the plastic sealing layer 50 is filled at least between adjacent second chips. In this embodiment, the encapsulation layer 50 covers the surface of the device wafer and the second chip 20, that is, the encapsulation layer 50 fills the gap between the second chips 20 and covers the second chip 20. The plastic encapsulation layer realizes the The sealing of the second chip can better isolate air and moisture, thereby improving the packaging effect. Specifically, the encapsulation layer 50 may be formed through an injection molding process. The filling performance of the injection molding process is good, and the injection molding agent can be well filled between the plurality of second chips 20 , so that the second chips 20 have a good encapsulation effect. In other embodiments, other processes may also be used to form the encapsulation layer. In addition, according to different properties of the second chip, the upper surface of the second chip may also be exposed outside the plastic encapsulation layer.

Referring to FIG. 6 , in this embodiment, the surface of the first chip 101 opposite to the first bonding pad (the lower surface of the first chip 101 in FIG. 5 ) has a third bonding pad. After the plastic sealing layer 50 is formed, the method further includes: The backside of the device wafer is thinned; and a through-silicon via structure 13 is formed from the backside of the thinned device wafer, and the through-silicon via structure 13 is connected to the third pad. By thinning the backside of the device wafer, the thickness of the device wafer is reduced, thereby improving the heat dissipation effect of the device wafer; in addition, reducing the thickness of the device wafer is also conducive to reducing the formation of a through-hole interconnection structure and reduce the overall thickness of the package structure after packaging, thereby improving the performance of the package structure. In this embodiment, the process used in the thinning process may be one or more of a back grinding process, a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process, and a wet etching process.

In order to effectively control the stop position of the thinning process, in the manufacturing process of the device wafer, a deep trench isolation structure for defining the stop position is usually formed in the semiconductor substrate of the device wafer, so that the thinning process stops at the deep Bottom of the trench isolation structure. In another embodiment, neutral dopant ions (eg, one or both of oxygen ions and nitrogen ions) may also be used to form stoppages in the semiconductor substrate of the device wafer during the fabrication process of the device wafer. zone so that the thinning process stops at the bottom of the stop zone. In other embodiments, when the semiconductor substrate of the device wafer is a silicon-on-insulator substrate or a germanium-on-insulator substrate, the bottom substrate layer of the semiconductor substrate may also be thinned, so as to better Stop at the bottom of the insulator layer.

It should be noted that, after the thinning process, the thickness of the device wafer should not be too small or too large. If the thickness of the device wafer is too small, the mechanical properties of the device wafer are correspondingly poor, and it is easy to have adverse effects on structures such as devices formed in the device wafer; if the thickness of the device wafer is too large, it is not conducive to improving the performance of the package structure. Therefore, in this embodiment, the thickness of the device wafer after thinning is 5 μm to 10 μm. After the thinning process of the device wafer, a through silicon via structure 13 electrically connected to the third pad is formed in the device wafer. The electrical connection with the third pad is realized through the through silicon via structure 13 . Since the second chip 20 and the first bonding pads 110 are electrically connected through the conductive bumps 30 , the second chip 20 is electrically connected to other circuits through the conductive bumps 20 , the first bonding pads 110 and the TSV structure 13 .

Referring to FIGS. 7 and 8 , in one embodiment, after bonding the second chip (after FIG. 3 ), the method further includes: providing a capping substrate 60 , the first surface of the capping substrate 60 includes a cavity, and the bonding seal The first surface of the substrate 60 is covered with the device wafer, and the cavity covers at least a part of the second chip. The material of the capping substrate 60 may be: semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, or a dielectric material. A cavity is formed in the cover substrate 60, and the cavity can be larger, and one cavity can accommodate a plurality of second chips 20 at the same time. Two chips 20. Referring to FIG. 8 , in an optional embodiment, the cavity may also only cover a part of a second chip 20 , for example, only cover the main body of the second chip. For example, for a bulk acoustic wave resonator or a surface acoustic wave resonator or an infrared thermopile sensor, the chip needs to be formed with a cavity structure, and the cavity structure corresponds to the functional area of the chip structure, rather than including the entire chip in the cavity. For example, the bulk acoustic wave resonator (BAW), the surface acoustic wave resonator (SAW) and the solidly mounted bulk acoustic wave resonator (SMR) are provided with an upper cavity above the main resonance region, the cavity in this embodiment can be used as the upper cavity, For the infrared thermopile sensor, a thermal insulation cavity for thermal insulation is provided under the functional area. The cavity formed in this embodiment can be used as a thermal insulation cavity. In order to receive ultrasonic waves, the lower surface covers the cavity, and the cavity in this embodiment can be used as the lower cavity of the ultrasonic sensor. In an optional embodiment, after the cover substrate is bonded to the device wafer, the formed cavity is a sealed cavity, which can prevent the contamination (moisture, dust, grease, etc.) of the device in the cavity from the external environment. Continuing to refer to FIG. 8 , in one embodiment, the second chip includes an interconnect structure, and the interconnect structure exposes the upper surface of the second chip, and the method further includes: forming an electrical connection structure 61 penetrating the capping substrate 60 , and the electrical connection structure One end of the 61 is connected to the interconnection structure of the second chip, and the other end is located on the upper surface of the cover substrate 60 . The electrical properties of the second chip 20 are led out through the electrical connection structure 61 .

实施例Example 22

Referring to FIGS. 9 to 13 , the first chip 101 of the present embodiment further has external electrodes 111 exposing the upper surface of the device wafer, and the method further includes: forming external conductive bumps 31 on the external electrodes 111 through an electroplating process; The bumps 31 and the conductive bumps 30 are formed in the same electroplating process step; or the external conductive bumps 31 and the conductive bumps 30 are formed in different electroplating process steps. The same steps as those in Embodiment 1 are not repeated here.

Specifically, the external electrodes 111 are provided at intervals between the interconnection lead pads (Pads) of the first chip 101 and the first bonding pads 110 . The minimum distance between the first pad 110 and the external electrode 111 should not be too small. If the minimum distance between the first pads 110 and the external electrodes 111 is too small, the conductive bumps 30 and the external conductive bumps 31 are easily bridged or merged, thereby adversely affecting package reliability. Therefore, in this embodiment, the minimum distance between the first pad 110 and the external electrode 111 is 3 micrometers. It should also be noted that, in other embodiments, according to the circuit design, the first pad may also be electrically connected to the external electrode.

In this embodiment, the second chip 20 is subsequently bonded on the first chip 101 , and the first bonding pad 110 is used to realize electrical connection with the second chip 20 . The external electrodes 111 are used to electrically lead out the chip module 100 formed by the first chip 101 and the corresponding second chip 20 , so as to realize the electrical connection between the chip module and other substrates with circuit structures. In this embodiment, a dielectric layer 12 is formed on the upper surface of the device wafer, and the exposed positions of the first pads 110 and the external electrodes 111 are protected by the dielectric layer 12 to prevent short circuits. The dielectric layer 12 is etched to expose the first pads 110 and the external electrodes 111. Therefore, the surfaces of the first pads 110 and the external electrodes 111 are lower than the first surface of the device wafer, that is, the first surface of the device wafer Grooves are formed to expose the first pads 110 and the external electrodes 111 respectively. In addition, the dielectric layer 12 has a certain thickness, which can provide space in the subsequent steps of forming the conductive bumps 30 and externally connecting the conductive bumps 31 . In this embodiment, the steps of bonding the second chip 20 on the first chip 101 are the same as those in the first embodiment, and are not repeated here. Similar to forming the surrounding wall structure on the outer periphery of the conductive bump, in this embodiment, the surrounding wall structure is formed on the outer periphery of the area where the external conductive bump is pre-formed.

Referring to FIG. 10 , the conductive bumps 30 are formed on the first pads 110 by an electroplating process, and the external conductive bumps 31 are formed on the external electrodes 111 . In this embodiment, the external conductive bumps 31 and the external conductive bumps 30 are formed in the same electroplating process step, that is, both are formed simultaneously. In another embodiment, the conductive bumps 30 and the external conductive bumps 31 are formed in different formed in the electroplating process step, that is, both are formed in steps. When the two are formed in steps, the same process parameters can be used or different process parameters can be used. It can be understood that forming the conductive bumps 30 and the external conductive bumps 31 at the same time is beneficial to simplify the process steps and improve the packaging efficiency.

Affected by the manufacturing process of the device wafer, the surface of the external electrode is usually lower than the surface of the first chip. Therefore, the electrical properties of the external electrode are drawn out by electroplating external conductive bumps, and the external conductive bumps protrude from the surface of the external electrode. , which is easy to carry out the wire bonding process, and the connection performance between the bonding wire and the external conductive bump is higher, which is beneficial to improve the reliability of the package; in addition, the second chip is bonded to the surface of the first chip and exposed The external conductive bumps can provide accommodation space for the bonding wires connected to the external electrodes, so that the bonding wires are compatible with three-dimensional stacked wafer-level packaging, which will not lead to an increase in the height of the package structure, and has the advantages of simple wire bonding process and low cost. Advantage.

11 , in this embodiment, after bonding the second chip 20 , the packaging method further includes: cutting the device wafer to form a chip module 100 , the chip module 100 includes the second chip 20 and the first chip 101 bonded together. After the device wafer is cut, the second chip 20 and the corresponding first chip 101 form an independent chip module, so as to prepare for the subsequent bonding of the chip module to other substrates.

The device wafer is usually provided with criss-cross scribe lines, and the scribe lines are arranged between any two adjacent first chips 101 on the device wafer. Therefore, the device wafer is scribed along the scribe lines. cut. In this embodiment, the device wafer between the first chips 101 is partially etched from the first surface of the device wafer to form grooves, and then the second surface of the device wafer is subjected to a backside thinning process to The trenches are exposed to separate the respective first chips 101 . Since the etching process has a wide process window, narrow scribe lines can be etched, which can reduce the probability of damage to the second chip 20, the conductive bumps 30 or the external conductive bumps 31, and can also improve the The chipping phenomenon of a chip 101 reduces the probability of damage to the effective circuit inside the first chip 101 , which is beneficial to obtain a complete independent stack, thereby improving the reliability of the package. Moreover, performing the backside thinning process on the second surface of the device wafer 10 can realize a lighter, thinner and smaller wafer-level chip package. In other embodiments, laser cutting or mechanical cutting may also be used for cutting.

Referring to FIG. 12 , after cutting the device wafer, the method further includes: adhering the side of the chip module 100 close to the first chip 101 to the circuit board 2 , and the circuit board 2 has a circuit structure 210 ; using a wire bonding process to form the bonding wire 220 , the bonding wire 220 is electrically connected to the external conductive bump 31 and the circuit structure 210 in the circuit board 2 . Specifically, by adhering the chip module 100 to the substrate 2 , preparations are made for the subsequent wire bonding process, so as to utilize the circuit structure 210 in the circuit board 2 to connect the chip composed of the first chip 101 and the second chip 20 to the chip The module provides circuit signals, or uses the circuit structure 210 in the circuit board 2 to realize the electrical connection between the chip module and other chips or other substrates.

In this embodiment, the circuit board 2 may be a printed circuit board (printed circuit board, printed circuit board). In other embodiments, the circuit board may also be an FPC board (flexible printed circuit board, flexible circuit board) or other types of substrates such as interposer boards. In this embodiment, the chip module 100 is adhered to the circuit board 2 through the adhesive layer 230 . As an example, the adhesive layer 230 may be an adhesive film. The bonding wires 220 are formed by a wire bonding process, and the bonding wires 220 are electrically connected to the external conductive bumps 31 and the circuit structure 210 in the substrate 2 . The bonding wires 220 electrically connect the external conductive bumps 31 with the circuit structure 210 , thereby realizing the system integration of the chip module composed of the first chip 101 and the second chip 20 and the circuit board 2 . The wire bonding process is the most commonly used circuit connection method in the integrated circuit packaging process. The method enables the thin metal wires or metal strips to be punched in sequence on the bonding points of the chip and the lead frame or the packaging substrate to form a circuit connection. The wire bonding process has high compatibility with the current packaging process, and has the advantages of simple process and low cost. Therefore, by using the wire bonding process, it is beneficial to reduce the packaging cost. In this embodiment, the bonding wire 220 is a metal wire, such as a gold wire or an aluminum wire. In this embodiment, the highest point of the bonding wire 220 is lower than the surface of the second chip 20 facing away from the first chip 101 . In the subsequent process, an encapsulation layer covering at least the chip module 100 and the bonding wire 220 will be formed. By making the highest part of the bonding wire 220 lower than the surface of the second chip 20 facing away from the first chip 101, the bonding wire 220 can be buried in the packaging layer. At the same time, it is easy to make the thickness of the package structure small. In other embodiments, the highest point of the bonding wire may also be flush with the surface of the second chip facing away from the chip.

Referring to FIG. 13 , in this embodiment, after the bonding wires 220 are formed, the packaging method further includes: forming a plastic sealing layer 240 , the plastic sealing layer 240 covers the upper surface of the circuit board 2 , and wraps the chip module 100 and the bonding wires 220 . The plastic sealing layer 240 fixes the chip module 100 formed by the first chip 101 and the second chip 20 on the circuit board 2 , so as to realize the package integration of the first chip 101 and the second chip 20 . Moreover, the plastic encapsulation layer 240 is used to achieve insulation, sealing and protection of the external conductive bumps 31 , the conductive bumps 30 and the bonding wires 220 . Therefore, the material of the plastic encapsulation layer 240 is an insulating material. In this embodiment, the material of the plastic encapsulation layer 240 includes one or both of a dielectric material and a plastic encapsulation material, and the dielectric material may be silicon oxide, silicon nitride or other dielectric materials. Specifically, the material of the plastic sealing layer 240 may be epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost, so it is widely used as packaging material for electronic devices and integrated circuits. As an example, the molding layer 240 may be formed by an injection molding process. In this embodiment, the plastic encapsulation layer 240 covers the chip module as a whole, so as to bury the second chip 20 , the first chip 101 , the external conductive bumps 31 and the bonding wires 220 , so as to improve the packaging reliability. In other embodiments, the top surface of the plastic sealing layer 240 may also be flush with the surface of the second chip 20 facing away from the first chip, or the plastic sealing layer 240 may cover part of the sidewall of the second chip 20 .

实施例Example 33

14 to 18 , in this embodiment, the first chip 101 has external electrodes 111 exposing the upper surface of the device wafer, and external conductive bumps 31 are formed on the external electrodes 111 by an electroplating process; the external conductive bumps 31 and The conductive bumps 30 are formed in the same electroplating process step; or the external conductive bumps 31 and the conductive bumps 30 are formed in different electroplating process steps. A plurality of interconnect chips 5 are provided, an interconnect structure is formed in the interconnect chip 5, and a part of the interconnect structure 51 is exposed on the lower surface of the interconnect chip 5; The interconnect structure 51 of the connecting chip 5 is electrically connected to the external conductive bump 31 .

The interconnection chip 5 is used to lead out the electrical properties of the external electrodes 111 . Therefore, at least one surface of the interconnection chip 5 exposes part of the interconnection structure 51 , so that the interconnection structure 51 can be electrically connected to the external electrodes 111 . By interconnecting the chips 5 , the lead terminal (eg, I/O terminal) of the chip module composed of the first chip 101 and the second chip 20 can be led to a terminal of the device wafer having the first bonding pad 110 and the external electrode 111 . Compared with the solution of leading the lead-out end to the side of the device wafer facing away from the first pad 110 and the external electrode 111, the device wafer can be processed without subsequent processing in this embodiment (for example, a backside thinning process is performed). or through-silicon via interconnection process), thereby reducing damage to the device wafer and improving packaging reliability, and making the packaging method suitable for system integration of various device wafers, thereby improving packaging compatibility accordingly.

In this embodiment, the semiconductor process is used to prepare the interconnect chip 5 to improve the process compatibility of the interconnect chip 5 preparation process, and to facilitate the formation of the interconnect chip 5 by a wafer-level preparation method, thereby improving the preparation efficiency. Specifically, a semiconductor substrate is provided; a plurality of interconnect structures 51 are formed in the semiconductor substrate; after the interconnect structures 51 are formed, the semiconductor substrate is cut to obtain a plurality of discrete interconnect chips 5 , wherein the semiconductor substrate Can be a silicon substrate.

As an example, the interconnection structure 51 penetrates through the interconnection chip 5, and both ends of the interconnection structure 51 are exposed, wherein one end is used for electrical connection with the external conductive bumps 31, and the other end is used for connection with other interconnection structures ( For example, terminals) to achieve electrical connection. Specifically, the interconnect chip 5 includes opposing first and second surfaces, and the interconnect structure 51 includes a plug 501 , an interconnect line (not shown) connected to the plug 501 , and a pad 502 , the pad 502 The exposed portion of the first surface of the interconnect chip 5 . That is, the interconnect structure 51 includes interconnect lines and pads 502 on the first surface, and plugs 501 embedded in the interconnect chip 5 from the second surface, the plugs 501 being connected to the interconnect lines. The first surface exposes part of the interconnection lines, and the part of the interconnection lines exposed by the first surface is used as the bonding pad 502 .

Interconnect lines can function as a redistribution layer (RDL). For example, when the first chip 101 has a plurality of external electrodes 111 , the plurality of external electrodes 111 can be connected by interconnecting wires, and the electrical properties of the plurality of external electrodes 111 can be drawn out through a plug 501 . The plug 501 is used to realize electrical connection with the lead terminal formed later. Moreover, the plug 501 has a certain height, which is beneficial to reduce the difficulty of forming the subsequent lead-out ends. In this embodiment, the material of the interconnection wire is aluminum. The aluminum process is relatively simple and the process cost is low. Therefore, by selecting the aluminum interconnect layer, it is beneficial to reduce the process difficulty and process cost of the packaging process. In other embodiments, the interconnect lines can also be other applicable conductive materials. In this embodiment, the material of the plug 501 is copper. The resistivity of copper is low, and by selecting copper material, it is beneficial to improve the electrical conductivity of the plug 501; moreover, the plug 501 is formed in the interconnection hole, and the filling of copper is good, thereby improving the plug 501 in the interconnection hole. quality of formation within. In other embodiments, the plug may also be of other applicable conductive materials. In other embodiments, the interconnect structure may also only include plugs extending through the interconnect chip, the plugs being correspondingly exposed portions of the first surface of the interconnect chip. In other embodiments, the interconnect structure includes interconnect lines and pads, which are exposed portions of the first surface of the interconnect chip.

In this embodiment, after the interconnection lines are formed, the plugs 501 are formed. Specifically, forming interconnect lines located on the first surface; using the surface of the interconnect lines facing the second surface as an etching stop position, etching the interconnect chip 5 from the second surface to form interconnect holes; filling the interconnect holes, Plugs 501 are formed. By forming the interconnection line first, it is easy to control the position where the etching stops during the formation of the interconnection hole. In other embodiments, the interconnect lines may also be formed after the plugs are formed.

In this embodiment, the thickness of the interconnect chip 5 is greater than or equal to the thickness of the second chip 20 . Subsequently, both the second chip 20 and the interconnect chip 5 are bonded to the first surface (upper surface) of the first chip 101 , and a package covering the second chip 20 and the interconnect chip 5 is also formed on the device wafer. The surface of the packaging layer facing away from the device wafer exposes the second surface of the interconnecting chip 5. Therefore, by making the thickness of the interconnecting chip 5 greater than or equal to the thickness of the second chip 20, it is convenient for the packaging layer to expose the second surface at the same time. , burying the second chip 20 therein. However, if the thickness difference between the interconnecting chip 5 and the second chip 20 is too large, the thickness of the subsequently formed package structure will be too large, which is not conducive to the development of device miniaturization. For this reason, in this embodiment, the thickness difference between the interconnecting chip 5 and the second chip 20 is 0 μm to 100 μm.

Referring to FIG. 16 , the second chip 20 and the interconnect chip 5 are bonded on the upper surface of the device wafer, and the first pad 21 is electrically connected to the conductive bump 30 , and the interconnect structure 51 of the interconnect chip 5 is connected to the external The conductive bumps 31 are electrically connected. In this embodiment, the steps of bonding the interconnect chip 5 on the device wafer/electrically connecting with the external conductive bumps 31 refer to Embodiment 1. Bonding the second chip 20 on the device wafer/with the conductive bumps 30 The steps of electrical connection are not repeated here. By bonding both the second chip 20 and the interconnecting chip 5 on the first chip 101 , the system integration of the second chip 20 and the interconnecting chip 5 and the device wafer is realized. In this embodiment, the area of the interconnect structure 51 exposed at the bottom of the interconnect chip 5 refers to the exposed area of the first pad; The area is greater than half of the cross-sectional area of the interconnect structure 51 . In an alternative solution, the external conductive bumps 31 and the interconnection structure 51 face each other, that is, in the direction perpendicular to the surface of the device wafer, they overlap each other to the greatest extent. In an optional solution, the cross-sectional area of the external conductive bump 31 is greater than 10 square micrometers to ensure structural strength.

Referring to FIG. 17 , in this embodiment, after bonding the second chip 20 and the interconnect chip 5 , the packaging method further includes: forming a plastic sealing layer 600 to cover the upper surface of the device wafer and wrap the second chip 20 and the interconnect chip 5 5. The top surface of the interconnect chip 5 and the interconnect structure 51 are exposed from the plastic encapsulation layer 600 ; a lead terminal electrically connected to the interconnect structure 51 is formed on the top surface of the plastic encapsulation layer 600 . For the material and formation method of the encapsulation layer 600, refer to the material and formation method of the encapsulation layer 50 in Embodiment 1. The encapsulation layer 600 covers the upper surface of the device wafer and wraps the second chip 20 and the interconnect chip 5 , that is, the encapsulation layer 600 fills the gap between the chips, and the plastic encapsulation layer realizes the protection of the second chip 20 and the interconnect chip 5 The sealing of the seal, so as to better isolate the air and moisture, thereby improving the encapsulation effect. In this embodiment, after the molding layer 600 is formed, the packaging layer 600 is planarized until the interconnect structure 51 on the top surface of the interconnect chip is exposed. The plastic encapsulation layer 600 is a flat surface, so as to facilitate the formation of the subsequent lead-out ends. In other embodiments, after the molding layer 600 is formed, the molding layer 600 above the interconnect chip 5 may be etched, thereby exposing the interconnect structure 51 of the interconnect chip 5 .

The second chip 20 and the corresponding first chip 101 constitute a chip module, the terminal is used as the input/output terminal of the chip module, and the chip module can be subsequently bonded to other substrates (eg circuit boards) through the terminal. In this embodiment, the process of forming the lead terminal includes a bump process. Compared with a wirebond process, this embodiment can implement wafer level packaging. Specifically, the lead terminal includes a redistribution layer 610 connected to the interconnect structure 51 and solder balls 62 located on the redistribution layer 610 . Specifically, the step of forming the lead terminal includes: forming a redistribution layer 610 on the top surface of the plastic sealing layer 600 connected to the top end of the interconnect structure 51 (ie, the end exposed by the second surface). The redistribution layer 610 is used to redistribute the top of the interconnect structure 51 . In this embodiment, the material of the redistribution layer 610 is aluminum. In other embodiments, the redistribution layer may also be other applicable conductive materials. As an example, the redistribution layer 610 may be formed by deposition and etching of corresponding materials. Wherein, the second chip 20 is covered by the plastic sealing layer 600, so as to realize the isolation of the redistribution layer 610 from the second chip 20. Correspondingly, the redistribution layer 610 may extend to the plastic sealing layer 600 above the second chip 20, so as to facilitate the The interconnect structure 51 is redistributed according to actual packaging requirements. An insulating layer 70 covering the redistribution layer 610 is formed, and an opening that exposes a portion of the redistribution layer 610 is formed in the insulating layer 70 . The openings are used to provide spatial locations for the formation of solder balls 62 . The insulating layer 70 is used to insulate between the redistribution layers 610, and is also used to provide a process platform for the formation of solder balls. In addition, the insulating layer 70 can also play the roles of waterproof, anti-oxidation, and anti-pollution. In this embodiment, the material of the insulating layer 70 is a photosensitive material. Correspondingly, the insulating layer 70 can be patterned by a photolithography process, which is beneficial to simplify the process steps and reduce the process cost. Specifically, the material of the insulating layer 70 may be photosensitive polyimide (PI), photosensitive benzocyclobutene (BCB) or photosensitive polybenzoxazole (PBO). In this embodiment, the insulating layer 70 covering the redistribution layer 610 is formed on the plastic sealing layer 600 by coating. Correspondingly, the insulating layer 70 is patterned by a photolithography process to expose part of the redistribution layer 610 . Solder balls 62 are formed in the openings, and the solder balls 62 and the redistribution layer 610 constitute terminals. In this embodiment, the solder balls 62 are formed by a bumping process. By selecting the bump process, it is beneficial to reduce the thickness of the conductive bumps 62, thereby reducing the thickness of the package structure. In this embodiment, the material of the solder balls 62 is copper. It should be noted that, in other embodiments, the lead-out terminal may also be formed by a ball-mounting process. It should also be noted that, in other embodiments, when the interconnect structure only includes interconnect lines and pads, after forming the plastic encapsulation layer and exposing the interconnect chips, and before forming the lead terminals, the wafer-level system packaging method further includes: : A plug embedded in the interconnect chip is formed from the upper surface of the interconnect chip, and the plug is connected to the interconnect line.

Referring to FIG. 18 , in one embodiment, after bonding the second die and the interconnect die on the device wafer (after FIG. 16 ), the method further includes: providing a capping substrate 80 that caps the first surface of the substrate 80 The accommodating cavity 81 is included, and the first surface of the capping substrate 80 and the device wafer are bonded together, and the accommodating cavity 81 covers at least a part of the second chip 20 . In an optional embodiment, after the cover substrate 80 is bonded on the device wafer, the formed cavity is a sealed cavity, which can prevent the contamination (moisture, dust, grease, etc.) of the device in the cavity from the external environment. In one embodiment, the upper surface of the interconnect chip exposes part of the interconnect structure, and the method further includes: forming an electrical lead-out structure 82 penetrating the capping substrate 80 , and one end of the electrical lead-out structure 82 is connected to the upper surface of the interconnect chip The other end of the exposed interconnect structure is located on the upper surface of the capping substrate 80 . In another embodiment, a side of the first chip opposite to the first bonding pad has a third bonding pad, a TSV structure is formed on the backside of the device wafer, and the TSV structure is connected to the third bonding pad.

实施例Example 44

19 to 21 , the difference between this embodiment and Embodiments 1-3 is that a cavity is required under the second chip 20 , and bonding the second chip on the device wafer includes: under the second chip 20 , a cavity is required. An adhesive layer is formed on the surface or the upper surface of the device wafer, and an opening 41 is formed in the adhesive layer; the second chip 20 is bonded on the device wafer through the adhesive layer, and the second chip 20 covers the opening 41 to form a cavity , the cavity is used as the working cavity of the second chip 20 . In this embodiment, the adhesive layer is a photolithographic bonding material 40 . The depth of the opening 41 is equal to or less than the thickness of the photolithographic bonding material 40 . The area where the opening 41 is formed corresponds to the working area of the second chip 20 . After the second chip is bonded in the later process, a cavity is formed, and the cavity is used as a working cavity of the second chip (eg, a thermal insulation cavity). When a cavity needs to be formed under the second chip 20, by forming an opening in the photolithographic bonding layer, process steps can be saved (otherwise the cavity would need to be formed when the second chip is fabricated). In this embodiment, the opening 41 is used for heat insulation, so the depth of the opening 41 is not limited, and the opening 41 may penetrate through the photolithographic bonding material 40 (the depth of the opening is the same as the thickness of the photolithographic bonding material 40 ) It is also possible to penetrate only a part of the thickness of the photolithographic bonding material 40 (the depth of the opening is smaller than the thickness of the photolithographic bonding material 40 ). In other embodiments, if the depth of the opening needs to be defined, a suitable thickness is formed when forming the photolithographic bonding material. For cavity-type bulk acoustic wave resonators (fbar) and surface acoustic wave resonators (SAW), a lower cavity is provided below the main resonance area, a cover is formed above, and an upper cavity is formed between the cover and the main resonance area. The cavity in the embodiment can be either an upper cavity or a lower cavity. For a solidly mounted bulk acoustic resonator (SMR), an upper cavity is formed above and between the covers, and the cavity in this embodiment can be used as the upper cavity. For the infrared thermopile sensor, a thermal insulation cavity for thermal insulation is provided below the functional area, and the cavity formed in this embodiment can be used as a thermal insulation cavity. For the ultrasonic sensor, the membrane-shaped vibrating part is suspended in the air, the upper surface is used to receive ultrasonic waves, and the lower surface covers the cavity. The cavity in this embodiment can be used as the lower cavity of the ultrasonic sensor.

实施例Example 55

This embodiment provides a wafer-level system packaging structure. Referring to FIG. 20 , the packaging structure includes: a device wafer, the upper surface of the device wafer has first pads 110 , and conductive bumps are electrically connected to the first pads 110 block 30, the conductive bump 30 is formed by electroplating process; the upper surface of the device wafer is provided with a photolithographic bonding material 40, and the photolithographic bonding material 40 has an opening 41; the second chip 20, the second chip 20 is bonded on the device wafer by a photolithographic bonding material 40 and covers the opening 41 to form a cavity, and the cavity is used as a working cavity of the second chip 20; the lower surface of the second chip 20 has a second pad 21, The second pads 21 are electrically connected to the conductive bumps 30 .

In this embodiment, the upper surface of the device wafer also has external electrodes 111, and the external conductive bumps 31 are electrically connected to the external electrodes 111, and the external conductive bumps 31 are formed by an electroplating process; the package structure includes an interconnect chip 5, which is interconnected An interconnection structure 51 is formed in the chip 5, and a part of the interconnection structure 51 is exposed on the lower surface of the interconnection chip 5; the interconnection chip 5 is bonded on the device wafer by a photolithographic bonding material 40; The external conductive bumps 31 are electrically connected.

It should be noted that each embodiment in this specification is described in a related manner, and the same and similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. .

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims

A wafer-level system packaging method, comprising: providing a device wafer, the device wafer including a plurality of first chips, the first chips having first chips exposing the upper surface of the device wafer bonding pads; forming conductive bumps on the first bonding pads through an electroplating process; after forming the conductive bumps, at least one second chip is provided, the lower surface of the second chip has a second bonding pad; The second chip is bonded on the device wafer, and the second pads of the second chip are electrically connected to the conductive bumps.
The wafer-level system packaging method according to claim 1, wherein the first chip further has an external electrode exposing the upper surface of the device wafer, and the method further comprises: performing an electroplating process on the device wafer. External conductive bumps are formed on the external electrodes; the external conductive bumps and the conductive bumps are formed in the same electroplating process step; or the external conductive bumps and the conductive bumps are formed in different electroplating process steps .
The wafer-level system packaging method according to claim 2, wherein the method further comprises: providing a plurality of interconnect chips, wherein an interconnect structure is formed in the interconnect chips, and a lower part of the interconnect chips is formed. Part of the interconnect structure is exposed on the surface; the interconnect chip is bonded on the upper surface of the device wafer, so that the interconnect structure of the interconnect chip is electrically connected to the external conductive bump.
The wafer-level system packaging method according to any one of claims 1-3, wherein the bonding the second chip on the device wafer comprises: under the second chip An adhesive layer is formed on the surface or the upper surface of the device wafer, and an opening is formed in the adhesive layer; the second chip is bonded on the device wafer through the adhesive layer, and the The second chip covers the opening to form a cavity, and the cavity serves as a working cavity of the second chip.
The method for manufacturing a wafer-level package structure according to claim 1, wherein bonding the second chip on the device wafer comprises: bonding the second chip with a photolithographic bonding material. The chip is bonded on the device wafer; the photolithographic bonding material includes: a film-like dry film or a liquid dry film.
The wafer-level packaging method according to claim 1, wherein the electroplating process comprises: electroless palladium immersion gold, wherein the time for chemical nickel is 30-50 minutes, and the time for chemical gold is 4-40 minutes, The time for chemical palladium is 7-32 minutes; or, the electroplating process includes chemical nickel-gold, wherein the time for chemical nickel is 30-50 minutes, and the time for chemical gold is 4-40 minutes.
The wafer level packaging method according to claim 1, wherein the area of the first bonding pad or the second bonding pad is 5-200 square micrometers; and/or, the transverse direction of the conductive bump is The cross-sectional area is greater than 10 square micrometers; and/or the height of the conductive bumps is 5-200 micrometers.
The wafer-level packaging method according to claim 1, wherein the material of the second pad and the conductive bump is metal, and the second pad and the conductive bump are bonded by a thermocompression bonding process The conductive bumps are electrically connected; each of the second bonding pads and each of the conductive bumps are thermocompressed one by one; or a plurality of the second bonding pads and a plurality of the conductive bumps are thermocompressed at the same time Bond.
The wafer level packaging method according to claim 1, wherein the material combination of the second pad and the conductive bump comprises gold-gold, copper-copper, copper-tin or gold-tin.
The wafer-level packaging method according to claim 1, wherein the projection of the first bonding pad and the second bonding pad in a direction perpendicular to the surface of the device wafer has an overlapping area, and the The area of the overlapping area is greater than half of the area of the first pad or the second pad.
The wafer-level packaging method according to claim 5, wherein the projection of the photolithographic bonding material on the surface of the device wafer is centered on the center of the second chip, and at least Covers 10% of the chip area.
The wafer level system packaging method according to claim 3, wherein after bonding the second chip and the interconnect chip on the device wafer, the method further comprises: providing a cover a substrate, the first surface of the capping substrate includes an accommodating cavity, the first surface of the capping substrate and the device wafer are bonded, and the accommodating cavity covers at least one of the second A part of the chip; the upper surface of the interconnect chip exposes a part of the interconnect structure to form an electrical lead-out structure penetrating the cover substrate, and one end of the electrical lead-out structure is connected to the top of the interconnect chip the interconnect structure whose surface is exposed, and the other end is located on the upper surface of the cover substrate; or, the first chip has a third pad on the side opposite to the first pad, and the device A through-silicon via structure is formed on the backside of the wafer, and the through-silicon via structure is connected to the third pad.
The wafer-level system packaging method according to claim 3, wherein after bonding the second chip and the interconnecting chip, the method further comprises: forming a plastic sealing layer to cover the upper surface of the device wafer, and wrapping the second chip and the interconnecting chip, the plastic sealing layer exposes the interconnecting structure on the upper surface of the interconnecting chip; and forming an electrical connection with the interconnecting structure on the top surface of the plastic sealing layer outgoing terminal.
The wafer level system packaging method according to claim 13, wherein forming the lead terminal comprises: forming a redistribution layer on the top surface of the plastic sealing layer, the redistribution layer electrically connecting the interconnect structure , forming an insulating layer on the redistribution layer and the plastic sealing layer, and electrically connecting the redistribution layer and the solder balls protruding from the surface of the insulating layer.
The wafer-level packaging method according to claim 1, wherein the surface of the second chip with the second pads is the front side, the side opposite to the front side is the back side, and the second chip is bonded to the Before placing the second chip on the device wafer, the second chip is temporarily bonded to the substrate through a bonding layer or electrostatic bonding; after the second chip is bonded to the substrate, the substrate is debonded.
The wafer-level system packaging method according to claim 5, wherein the method further comprises: patterning the photolithographic bonding material, and forming a surrounding wall structure around the area where the conductive bumps are pre-formed .
The wafer-level system packaging method according to claim 2, wherein after bonding the second chip, the method further comprises: cutting the device wafer to form a chip module, the chip module comprising bonding the second chip and the first chip together.
The wafer-level system packaging method according to claim 17, wherein after cutting the device wafer, the method further comprises: adhering the side of the chip module close to the first chip to a circuit board Above, the circuit board has a circuit structure; the bonding wire is formed by a wire bonding process, and the bonding wire electrically connects the external conductive bump and the circuit structure in the circuit board; the highest part of the bonding wire and all The upper surface of the second chip is flush, or the highest point of the bonding wire is lower than the upper surface of the second chip.
The wafer level system packaging method according to claim 3, wherein the interconnect structure comprises a plug, and the plug is an exposed part of the lower surface of the interconnect chip; or, the interconnect The structure includes a plug, an interconnection line connected to the plug, and a bonding pad, the bonding pad being an exposed part of the lower surface of the interconnection chip; or, the interconnection structure includes an interconnection line and a bonding pad and the bonding pad is the exposed part of the lower surface of the interconnect chip; after bonding the interconnect chip on the upper surface of the first chip, the method further includes: removing the interconnect chip from the interconnect chip An electrical lead-out structure is formed on the upper surface side of the lead-out structure, and the electrical lead-out structure is electrically connected with the interconnection structure.
A wafer-level system packaging structure, comprising: a device wafer, the upper surface of the device wafer has a first pad, the first pad is electrically connected with a conductive bump, the conductive bump The block is formed by an electroplating process; the upper surface of the device wafer is provided with a photolithographic bonding material, and the photolithographic bonding material has an opening; a second chip, the second chip passes through the The photolithographic bonding material is bonded on the device wafer and covers the opening to form a cavity, and the cavity is used as the working cavity of the second chip; the lower surface of the second chip has a second solder joint. pads, and the second pads are electrically connected to the conductive bumps.
The wafer-level system packaging structure according to claim 20, wherein the device wafer further has external electrodes on the upper surface, and external conductive bumps are electrically connected to the external electrodes, and the external conductive bumps are electrically connected to the external electrodes. It is formed by an electroplating process; the package structure includes an interconnection chip, an interconnection structure is formed in the interconnection chip, and a lower surface of the interconnection chip exposes a part of the interconnection structure; the interconnection chip passes through the interconnection chip. A photolithographic bonding material is adhered on the device wafer; the interconnection structure is electrically connected with the external conductive bumps.