CN117689732B - Image gray level rectangularity statistics and target searching method and system based on FPGA - Google Patents
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Abstract
The invention discloses an image gray level rectangularity statistics and target searching method and system based on an FPGA, and belongs to the technical field of image processing. The method comprises the following steps: s1: an image input caching stage; s2: a channel pixel distribution stage; s3: a window pixel distribution stage; s4: a straight square statistics stage; s5: and in the direct search stage, comparing the gray values of the pixel points in the first pixel point set to obtain the pixel point with the maximum gray value, and obtaining the pixel region with the maximum gray value according to the pixel coordinates of the pixel point with the maximum gray value. By means of a high-speed parallel signal processing architecture of the FPGA, all lines of a frame of image are distributed to a plurality of statistical units to perform ultra-high-speed parallel calculation, and a final total distribution result of all pixels is obtained. When all the statistics units are used for statistics, the maximum value of the gray value statistics is kept, namely, when final statistics is completed, the pixel region with the maximum gray value can be simultaneously given, and the coordinate position of the pixel region is given.
Description
Technical Field
The invention relates to the technical field of image processing, in particular to an image gray level rectangularity statistics and target searching method and system based on an FPGA.
Background
In image processing, it is generally necessary to perform gray value statistics on all pixel values of a frame of image to obtain a histogram of gray values of pixels, and search for which pixel matrix has the largest gray value in the image by taking a certain pixel matrix as a unit, so as to obtain the position of the target in the image. In general, such image processing is performed by a serial operation process by a CPU and a matrix operation is performed, and since the operation is performed by the CPU, a very high rate cannot be achieved.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides an image gray scale rectangularity statistics and target searching method and system based on an FPGA.
The aim of the invention is realized by the following technical scheme: the first aspect of the present invention provides: an image gray scale rectangularity statistics and target searching method based on FPGA comprises the following steps:
S1: the method comprises the steps that in an image input caching stage, a Field Programmable Gate Array (FPGA) distributes all data of an image to be processed to a plurality of BRAM units;
s2: in the channel pixel distribution stage, after all data of an image to be processed are cached to a plurality of BRAM units, an image caching module controls the plurality of BRAM units to output all data to a plurality of straight statistic channels;
s3: in the window pixel distribution stage, a plurality of straight side statistic channels distribute all line data to a plurality of pixel windows for gray level statistics, and pixel gray level values of all pixel points in all line data are obtained;
S4: in the straight side statistics stage, each pixel window is allocated with a block of RAM area for storing the distribution statistics value of pixel values, the address of the RAM stores the number of times of occurrence of the pixel points with the gray value the same as the address index, each pixel window corresponds to a straight side statistics module, each straight side statistics module completes straight side statistics operation and a real-time counter is used for recording the pixel point with the largest gray value counted by each straight side statistics module to obtain a first pixel point set;
S5: and in the direct search stage, comparing the gray values of the pixel points in the first pixel point set to obtain the pixel point with the maximum gray value, and obtaining the pixel region with the maximum gray value according to the pixel coordinates of the pixel point with the maximum gray value.
Preferably, said S1: the image input caching stage is used for counting the lines of the image to be processed to obtain line counts when the image to be processed is received; dividing the line count by the line number which can be accommodated by the BRAM unit to obtain a BRAM unit index; and taking the effective signal of the image line to be processed as a write enable signal of the BRAM unit.
Preferably, said S2: in the channel pixel distribution stage, the number of the straight statistic channels is one less than that of BRAM units; setting N BRAM units, wherein N-1 straight side statistic channels are provided, and the first straight side statistic channel receives row data transmitted by the first BRAM unit and the second BRAM unit; the second straight side statistical channel receives the line data transmitted by the second BRAM unit and the third BRAM unit; the N-1 th square statistical channel receives the N-1 th BRAM unit and row data transmitted by the N-1 th BRAM unit; the number of data output by each BRAM unit is the same; two adjacent BRAM units output data at intervals of one clock cycle.
Preferably, said S3: in the window pixel distribution stage, the address of the pixel point in the row data is subjected to modular operation on the row count to obtain the corresponding index of the pixel point in the row data, namely the column address of the pixel point; when distributing all the rows of data to the pixel windows, the column address is used to calculate which pixel window each pixel should be written to.
Preferably, said S4: in the direct square statistics stage, a RAM table is contained in the direct square statistics module, the gray value of a pixel is input to the address input end of the RAM table, the read-out interface of the RAM table is added with 1 to be connected with the write-in interface of the RAM table in a feedback manner, and when the effective signal of the pixel is high, the RAM table automatically completes the self-increment operation of the statistics result of the gray value of the corresponding pixel; and setting a maximum value variable and a column address variable in the square statistics module, wherein the initial values of the maximum value variable and the column address variable are 0, comparing the pixel point statistics value with the maximum value variable every time the square statistics module completes statistics of the gray value of a pixel point, if the maximum value variable is smaller than the pixel point statistics value, assigning the pixel point statistics value to the maximum value variable, writing the column address of the pixel point into the column address variable, and maintaining the maximum value.
Preferably, each of the straight statistical channels has a plurality of pixel windows and a real-time counter, and the number of the pixel windows of each of the straight statistical channels is the same.
A second aspect of the invention provides: an image gray scale rectangularity statistics and target searching system based on an FPGA, which is used for any one of the image gray scale rectangularity statistics and target searching methods based on the FPGA, comprises the following steps:
The image input buffer module distributes all data of an image to be processed to a plurality of BRAM units by utilizing a Field Programmable Gate Array (FPGA);
The channel pixel distribution module is used for controlling the plurality of BRAM units to output all the data into the plurality of straight statistic channels by utilizing the image caching module after all the data of the image to be processed are cached into the plurality of BRAM units;
the window pixel distribution module distributes all line data to a plurality of pixel windows by using a plurality of straight statistic channels to carry out gray statistics, so as to obtain pixel gray values of all pixel points in all line data;
The system comprises a direct statistics module, a first pixel point set, a second pixel point set, a third pixel point set, a fourth pixel point set, a fifth pixel point set, a sixth pixel point set, a third pixel point set, a fourth pixel point set, a fifth pixel point set, a sixth pixel point set, and a fourth pixel point set, wherein the third pixel point set is used for storing the first pixel point set;
The square search module is used for comparing the gray values of the pixel points in the first pixel point set to obtain the pixel point with the maximum gray value, and obtaining the pixel region with the maximum gray value according to the pixel coordinates of the pixel point with the maximum gray value.
The beneficial effects of the invention are as follows:
1) And distributing all lines of a frame of image to a plurality of statistical units by utilizing a high-speed parallel signal processing architecture of the FPGA, carrying out ultra-high-speed parallel calculation by the plurality of statistical units, and finally carrying out statistical operation on the statistical values of all the statistical units again to obtain a final total distribution result of all pixels.
2) When all the statistics units are used for statistics, the maximum value of the gray value statistics is kept, namely, when final statistics is completed, the pixel region with the maximum gray value can be simultaneously given, and the coordinate position of the pixel region is given.
Drawings
FIG. 1 is a schematic diagram of pixel areas of two adjacent pixel windows;
FIG. 2 is a schematic diagram of signal processing of a square statistics module;
FIG. 3 is a flowchart of the FPGA-based image gray scale rectangularity statistics and target search method of the present invention;
FIG. 4 is a flow chart of the image buffering to be processed;
Fig. 5 is a flowchart of a pixel point outputting a maximum gray value.
Detailed Description
The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by a person skilled in the art without any inventive effort, are intended to be within the scope of the present invention, based on the embodiments of the present invention.
The process of the present invention is described herein with respect to a gray scale of 128 x 128 frames. Here, the minimum pixel area for target search is set to 16×16 pixels, that is, a pixel gray distribution in a window is searched by using a 16×16 pixel array as the window. To improve the target search accuracy, there is an overlap of 8 pixels between all adjacent 16 x 16 pixel arrays. For example, the first pixel window has coordinates {1,1} to {16, 16}, and the second pixel window has coordinates {9,1} to {24, 16} ({ x, y } where x is the abscissa and y is the ordinate). As shown in FIG. 1 (window 1 on the left and window 2 on the right)
Referring to fig. 1-5, a first aspect of the present invention provides: an image gray scale rectangularity statistics and target searching method based on FPGA comprises the following steps:
S1: the method comprises the steps that in an image input caching stage, a Field Programmable Gate Array (FPGA) distributes all data of an image to be processed to a plurality of BRAM units;
s2: in the channel pixel distribution stage, after all data of an image to be processed are cached to a plurality of BRAM units, an image caching module controls the plurality of BRAM units to output all data to a plurality of straight statistic channels;
s3: in the window pixel distribution stage, a plurality of straight side statistic channels distribute all line data to a plurality of pixel windows for gray level statistics, and pixel gray level values of all pixel points in all line data are obtained;
S4: in the straight side statistics stage, each pixel window is allocated with a block of RAM area for storing the distribution statistics value of pixel values, the address of the RAM stores the number of times of occurrence of the pixel points with the gray value the same as the address index, each pixel window corresponds to a straight side statistics module, each straight side statistics module completes straight side statistics operation and a real-time counter is used for recording the pixel point with the largest gray value counted by each straight side statistics module to obtain a first pixel point set;
S5: and in the direct search stage, comparing the gray values of the pixel points in the first pixel point set to obtain the pixel point with the maximum gray value, and obtaining the pixel region with the maximum gray value according to the pixel coordinates of the pixel point with the maximum gray value. The whole flow of the image gray level rectangularity statistics and target searching method based on the FPGA is shown in figure 3. In order to increase the processing speed, the 128-line image is divided into 16 channels, 8 lines are each formed for each channel, and independent arithmetic processing is performed for each channel. Since the adjacent 16×16 pixel windows overlap by 8 pixels, there are 15 16×16 pixel windows per channel, and a total of 225 16×16 pixel windows per channel.
For each pixel window of 16×16, a RAM area is allocated to store the distribution statistics of the pixel values, the RAM depth is 256, the RAM address index represents the gray value, for example, address 0 stores the number of occurrences of the pixel with gray value 0, address 255 stores the number of occurrences of the pixel with gray value 255, and so on. The square statistical operation is completed by a square statistical module, each 16 x 16 pixel window corresponds to one square statistical module, and the inside of the square statistical module only comprises one RAM table. The input signal of the square module is provided with a clock, a pixel gray value and a pixel effective signal, the pixel gray value is directly connected to the address input end of the RAM table after being input, and the read output interface of the RAM is connected to the write input interface by adding 1 feedback, so that when the pixel effective signal is high, the RAM table automatically completes the statistics result self-increment operation of the corresponding gray value, and the single statistics operation is completed only by a single clock, thereby greatly improving the operation rate. After the direct statistics module completes single statistics, comparing the statistics result with the previous statistics result, keeping the maximum value, and recording the gray value corresponding to the maximum value and the coordinate corresponding to the gray value. The signal processing process of the square statistic module is shown in fig. 2.
The image is received by the FPGA and then is buffered in the DDR, then a frame of image is read from the DDR, the image is transferred into 16 RAMs, then the direct statistics is started, the 16 channels respectively read out image pixels from the 16 RAMs in sequence, and each image pixel point is distributed into 15 direct statistics modules of each channel according to the coordinates of the image for statistics. Since 8 pixels overlap in adjacent windows, all pixels except 8 pixels at the edge of the image are simultaneously sent to two adjacent square statistics modules for statistics. When all the row readings are completed for each of the 16 channels, the statistics of each pixel window are also completed. Finally, counting the counting result of the 225 pixel windows again to obtain the gray counting result of all pixels, and obtaining the coordinate position of the region with the maximum gray value.
Since the gray counting time of a single pixel point is only one clock period, and each channel is 8 rows of 1024 pixel points, each channel only needs 1024 clocks to complete operation, and each frame of image only needs 1024 clock periods to complete operation.
In some embodiments, the step S1: the image input caching stage is used for counting the lines of the image to be processed to obtain line counts when the image to be processed is received; dividing the line count by the line number which can be accommodated by the BRAM unit to obtain a BRAM unit index; and taking the effective signal of the image line to be processed as a write enable signal of the BRAM unit. The resolution of the image is 128×128, after the image is input, the image is respectively stored into 16 BRAM unit modules, and each BRAM unit can store 8 rows of images. When an image is received, counting the image rows, dividing the row count by 8 to obtain a corresponding BRAM unit index, wherein the value of the row count line_count is 0-127. The effective signal valid of the image line is used as a write enable signal of BRAM, the BRAM address addr= (line_index is 128) +pixel_count, wherein the value of the line_index is 0-7, the line count line_count carries out modular operation on 8 to obtain the pixel_count which is the count value of each line of pixels, the count is from 0-127, 0 represents the first pixel of each line, and 127 represents the last pixel of each line. The image caching flow is shown in fig. 4
In some embodiments, the step S2: in the channel pixel distribution stage, the number of the straight statistic channels is one less than that of BRAM units; setting N BRAM units, wherein N-1 straight side statistic channels are provided, and the first straight side statistic channel receives row data transmitted by the first BRAM unit and the second BRAM unit; the second straight side statistical channel receives the line data transmitted by the second BRAM unit and the third BRAM unit; the N-1 th square statistical channel receives the N-1 th BRAM unit and row data transmitted by the N-1 th BRAM unit; the number of data output by each BRAM unit is the same; two adjacent BRAM units output data at intervals of one clock cycle. After a frame of image is completely cached in 16 BRAM units, the image caching module controls the 16 BRAM units, reads the BRAM units in parallel at the same time, and sequentially outputs 8 lines of image data, namely, each BRAM unit continuously outputs 1024 pixel values. There are 15 squaring statistical channels in the squaring statistical module, where channel 1 receives data of BRAM units 1 and 2, channel 2 receives data of BRAM2 and BRAM3, channel 3 receives data of BRAM3 and BRAM4, and so on, channel 15 receives data of BRAM15 and BRAM16, i.e. each channel receives data of 16 lines with overlap of 8 lines of pixels. Since there is an overlap of 8 rows of pixels, two adjacent BRAMs are staggered by one clock cycle for data reading. For example, the channel 3 receives data of BRAM3 and BRAM4, the data output of BRAM3 and BRAM4 has two valid signals, and the write enable signal received by channel 3 has only one, when the data of BRAM3 and BRAM4 are output simultaneously, the two valid signals are valid simultaneously, and at this time, the write enable signal of channel 3 can only receive one of them, so that BRAM3 and BRAM4 need to be alternatively read by staggering one clock cycle, for example, BRAM3 is output when clock 0, and BRAM4 is output when clock 1. The flow of the pixel point with the maximum gray value is shown in fig. 5.
In some embodiments, the step S3: in the window pixel distribution stage, the address of the pixel point in the row data is subjected to modular operation on the row count to obtain the corresponding index of the pixel point in the row data, namely the column address of the pixel point; when distributing all the rows of data to the pixel windows, the column address is used to calculate which pixel window each pixel should be written to. Each of the 15 straight-sided statistical channels receives 16 rows of data input, 2048 pixels. These 2048 pixels are distributed in the channel to a 15 pixel window for gray scale statistics. When the BRAM outputs the pixel, the address where the pixel is located is also output, the range is 0-1023, and the index corresponding to the pixel in the row where the pixel is located, namely the column address of the pixel, can be obtained by performing modular operation on the value pair 127, and the range is 0-127. When distributing pixels to pixel windows, a column address is used to calculate which pixel window a pixel should be written into, and each pixel window has a BRAM with 256 depth for counting pixel values. There is also 8 pixel overlapping between the adjacent 15 pixel windows, for example, 8 pixel points with a column address of 8-15 are written into two windows of the pixel window 1 and the pixel window 2.
In some embodiments, the step S4: in the direct square statistics stage, a RAM table is contained in the direct square statistics module, the gray value of a pixel is input to the address input end of the RAM table, the read-out interface of the RAM table is added with 1 to be connected with the write-in interface of the RAM table in a feedback manner, and when the effective signal of the pixel is high, the RAM table automatically completes the self-increment operation of the statistics result of the gray value of the corresponding pixel; and setting a maximum value variable and a column address variable in the square statistics module, wherein the initial values of the maximum value variable and the column address variable are 0, comparing the pixel point statistics value with the maximum value variable every time the square statistics module completes statistics of the gray value of a pixel point, if the maximum value variable is smaller than the pixel point statistics value, assigning the pixel point statistics value to the maximum value variable, writing the column address of the pixel point into the column address variable, and maintaining the maximum value. Each pixel window of 16 x 16 is allocated with a RAM area to store the distribution statistic value of the pixel values, the RAM depth is 256, the RAM address index represents the gray value, for example, the address 0 stores the number of occurrences of the pixel point with the gray value of 0, the address 255 stores the number of occurrences of the pixel point with the gray value of 255, each pixel window corresponds to a straight side statistic module, and the inside of the straight side statistic module only comprises a RAM table. The input signal of the square module is provided with a clock, a pixel gray value and a pixel effective signal, the pixel gray value is directly connected to the address input end of the RAM table after being input, and the read output interface of the RAM is connected to the write input interface in a feedback way by adding 1, so that when the pixel effective signal is high, the RAM table automatically completes the statistics result self-increment operation of the corresponding gray value. Meanwhile, two variables histo _max and histo _col are maintained in the square statistics module, the initial value is 0, the statistics value of each pixel point is compared with histo _max when the module completes statistics of the pixel point, if histo _max is smaller than the statistics value, the statistics value is assigned to histo _max, and meanwhile, the column address is written into histo _col, namely, maximum value maintenance is carried out.
In some embodiments, there are multiple pixel windows and a real-time counter in each of the straight-side statistical channels, and the number of pixel windows in each of the straight-side statistical channels is the same. After all the BRAM pixels are written into 15 straight-side statistic channels, gray-scale straight-side statistic of the image is completed. Each straight channel has 15 pixel windows, and a real-time counter is arranged in the straight channel, and the counter returns to 0 after being filled with 15, and the counter is used for comparing the distribution maximum values of the 15 pixel windows in real time. After the statistics of the 15 straight statistic channels is completed, the distribution maximum value of 15 channels is obtained, and the maximum value of the gray distribution of all pixels is obtained by solving the maximum value of the 15 values, and the coordinates of the pixels corresponding to the corresponding distribution maximum value are obtained after the operation is completed because all the maximum values are associated with the coordinates.
A second aspect of the invention provides: an image gray scale rectangularity statistics and target searching system based on an FPGA, which is used for any one of the image gray scale rectangularity statistics and target searching methods based on the FPGA, comprises the following steps:
The image input buffer module distributes all data of an image to be processed to a plurality of BRAM units by utilizing a Field Programmable Gate Array (FPGA);
The channel pixel distribution module is used for controlling the plurality of BRAM units to output all the data into the plurality of straight statistic channels by utilizing the image caching module after all the data of the image to be processed are cached into the plurality of BRAM units;
the window pixel distribution module distributes all line data to a plurality of pixel windows by using a plurality of straight statistic channels to carry out gray statistics, so as to obtain pixel gray values of all pixel points in all line data;
The system comprises a direct statistics module, a first pixel point set, a second pixel point set, a third pixel point set, a fourth pixel point set, a fifth pixel point set, a sixth pixel point set, a third pixel point set, a fourth pixel point set, a fifth pixel point set, a sixth pixel point set, and a fourth pixel point set, wherein the third pixel point set is used for storing the first pixel point set;
The square search module is used for comparing the gray values of the pixel points in the first pixel point set to obtain the pixel point with the maximum gray value, and obtaining the pixel region with the maximum gray value according to the pixel coordinates of the pixel point with the maximum gray value.
The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.
Claims (7)
1. An image gray scale rectangularity statistics and target searching method based on FPGA is characterized in that: the method comprises the following steps:
S1: the method comprises the steps that in an image input caching stage, a Field Programmable Gate Array (FPGA) distributes all data of an image to be processed to a plurality of BRAM units;
s2: in the channel pixel distribution stage, after all data of an image to be processed are cached to a plurality of BRAM units, an image caching module controls the plurality of BRAM units to output all data to a plurality of straight statistic channels;
s3: in the window pixel distribution stage, a plurality of straight side statistic channels distribute all line data to a plurality of pixel windows for gray level statistics, and pixel gray level values of all pixel points in all line data are obtained;
S4: in the straight side statistics stage, each pixel window is allocated with a block of RAM area for storing the distribution statistics value of pixel values, the address of the RAM stores the number of times of occurrence of the pixel points with the gray value the same as the address index, each pixel window corresponds to a straight side statistics module, each straight side statistics module completes straight side statistics operation and a real-time counter is used for recording the pixel point with the largest gray value counted by each straight side statistics module to obtain a first pixel point set;
S5: and in the direct search stage, comparing the gray values of the pixel points in the first pixel point set to obtain the pixel point with the maximum gray value, and obtaining the pixel region with the maximum gray value according to the pixel coordinates of the pixel point with the maximum gray value.
2. The FPGA-based image gray scale rectangularity statistics and target searching method of claim 1, wherein: the S1: the image input caching stage is used for counting the lines of the image to be processed to obtain line counts when the image to be processed is received; dividing the line count by the line number which can be accommodated by the BRAM unit to obtain a BRAM unit index; and taking the effective signal of the image line to be processed as a write enable signal of the BRAM unit.
3. The FPGA-based image gray scale rectangularity statistics and target searching method of claim 1, wherein: s2: in the channel pixel distribution stage, the number of the straight statistic channels is one less than that of BRAM units; setting N BRAM units, wherein N-1 straight side statistic channels are provided, and the first straight side statistic channel receives row data transmitted by the first BRAM unit and the second BRAM unit; the second straight side statistical channel receives the line data transmitted by the second BRAM unit and the third BRAM unit; the N-1 th square statistical channel receives the N-1 th BRAM unit and row data transmitted by the N-1 th BRAM unit; the number of data output by each BRAM unit is the same; two adjacent BRAM units output data at intervals of one clock cycle.
4. The FPGA-based image gray scale rectangularity statistics and target searching method of claim 1, wherein: s3: in the window pixel distribution stage, the address of the pixel point in the row data is subjected to modular operation on the row count to obtain the corresponding index of the pixel point in the row data, namely the column address of the pixel point; when distributing all the rows of data to the pixel windows, the column address is used to calculate which pixel window each pixel should be written to.
5. The FPGA-based image gray scale rectangularity statistics and target searching method of claim 1, wherein: the S4: in the direct square statistics stage, a RAM table is contained in the direct square statistics module, the gray value of a pixel is input to the address input end of the RAM table, the read-out interface of the RAM table is added with 1 to be connected with the write-in interface of the RAM table in a feedback manner, and when the effective signal of the pixel is high, the RAM table automatically completes the self-increment operation of the statistics result of the gray value of the corresponding pixel; and setting a maximum value variable and a column address variable in the square statistics module, wherein the initial values of the maximum value variable and the column address variable are 0, comparing the pixel point statistics value with the maximum value variable every time the square statistics module completes statistics of the gray value of a pixel point, if the maximum value variable is smaller than the pixel point statistics value, assigning the pixel point statistics value to the maximum value variable, writing the column address of the pixel point into the column address variable, and maintaining the maximum value.
6. The FPGA-based image gray scale rectangularity statistics and target searching method of claim 1, wherein: each of the straight statistical channels has several pixel windows and one real-time counter, and the number of the pixel windows in each straight statistical channel is the same.
7. An image gray level rectangularity statistics and target search system based on FPGA is characterized in that: an FPGA-based image gray scale rectangularity statistics and target searching method for implementing any of claims 1-6, comprising:
The image input buffer module distributes all data of an image to be processed to a plurality of BRAM units by utilizing a Field Programmable Gate Array (FPGA);
The channel pixel distribution module is used for controlling the plurality of BRAM units to output all the data into the plurality of straight statistic channels by utilizing the image caching module after all the data of the image to be processed are cached into the plurality of BRAM units;
the window pixel distribution module distributes all line data to a plurality of pixel windows by using a plurality of straight statistic channels to carry out gray statistics, so as to obtain pixel gray values of all pixel points in all line data;
The system comprises a direct statistics module, a first pixel point set, a second pixel point set, a third pixel point set, a fourth pixel point set, a fifth pixel point set, a sixth pixel point set, a third pixel point set, a fourth pixel point set, a fifth pixel point set, a sixth pixel point set, and a fourth pixel point set, wherein the third pixel point set is used for storing the first pixel point set;
The square search module is used for comparing the gray values of the pixel points in the first pixel point set to obtain the pixel point with the maximum gray value, and obtaining the pixel region with the maximum gray value according to the pixel coordinates of the pixel point with the maximum gray value.
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