CN117687692A - NVME command processing device, method, equipment and medium - Google Patents
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Abstract
The application discloses NVME command processing device, method, equipment and medium, relates to the technical field of computers, and comprises the following steps: the NVME engine scheduling management module allocates tasks and cache resources for the NVME engine scheduling component; the first task module processes the task and sends the processing result to the submitting queue item processing module; the submitting queue entry processing module stores submitting queue entry information generated based on the processing result into a cache resource, sends a tail pointer of the current submitting queue entry to a disk, and sends finishing queue entry information to the finishing queue entry processing module; the completion queue entry processing module judges whether a first field of completion queue entry information is effective according to a first rule, judges whether the completion queue entry information is processed currently according to a second rule, and sends a head pointer of the current completion queue entry to a disk after the completion of the processing; and the second task module reports the completion state of the task. Therefore, the memory overhead of the CPU is reduced.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to an NVME command processing apparatus, method, device, and medium.
Background
SSD (Solid State Disk) realized based on PCIe (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard) interface is becoming more important because of its characteristics of high performance, low latency, etc. NVMe (Non-Volatile Memory Express, nonvolatile storage transport protocol) is a new generation of interface transport protocol, which specifies a communication protocol between a host and an NVM (Non-Volatile Memory) subsystem. Thereafter, nvme+pcie has evolved into a mainstream storage scheme.
The conventional IO (Input/Output) operation flow is: the first stage, the host sets PRP (Physical Region range, physical area page) in NVMe command; the host writes the command to the SQ queue (commit queue); the host informs the NVMe SSD controller of fetching an instruction through a doorbell register; in the second stage, after receiving the notification, the NVMe SSD controller fetches instructions from the SQ queue; the NVMe SSD controller executes corresponding data read-write carrying operation according to the instruction; after the NVMe SSD controller finishes executing, writing an instruction execution result into a CQ queue (completion queue); the NVMe SSD controller interrupts and notifies the host to execute feedback information in the CQ queue; and thirdly, after the host computer completes execution, notifying a doorbell register to reply to the NVMe SSD controller.
In the above operation flow, NVMe command processing, SQ queue management, CQ queue management, pointer update, and the like are realized by the CPU (Central Processing Unit ) of the host. Because the execution flow of one NVMe command is long, the time delay consumption is large, and more CPU resources are occupied, thereby affecting the performance of the whole system.
For this reason, the above-mentioned problems are to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention aims to provide an NVME command processing apparatus, method, device and medium, capable of reducing the memory overhead of a CPU, and the specific scheme is as follows:
in a first aspect, the present application discloses an NVME command processing apparatus, which interacts with a plurality of disks through a high-speed serial computer expansion bus standard controller, including: the NVME engine scheduling management module, a plurality of NVME engine scheduling components and a submission queue entry sharing cache, wherein the NVME engine scheduling components comprise a first task processing module, a submission queue entry processing module, a completion queue entry processing module and a second task processing module,
the NVME engine scheduling management module is used for distributing a target task and a first cache resource in the submission queue entry sharing cache for the NVME engine scheduling component;
The first task processing module is used for processing the target task distributed by the NVME engine scheduling management module and sending a processing result to the submitting queue entry processing module;
the commit queue entry processing module is used for storing commit queue entry information generated based on the processing result to the first cache resource, sending a tail pointer of a current commit queue entry to the disk so that the disk generates completion queue entry information according to the commit queue entry information, and then sending the completion queue entry information to the completion queue entry processing module;
the completion queue entry processing module is used for judging whether a first field of the completion queue entry information is effective according to a first rule, judging whether the completion queue entry information is currently processed according to a second rule if the first field of the completion queue entry information is effective, sending a head pointer of the current completion queue entry to the disk after the completion of the processing, and sending the processed completion queue entry information to the second task processing module;
and the second task processing module is used for determining the completion state of the target task according to the processed second field of the completion queue entry information and reporting the completion state.
Optionally, the commit queue entry processing module includes:
the commit queue entry processing unit is used for storing commit queue entry information generated based on the processing result to the first cache resource and sending the commit queue entry information in the first cache resource to a commit queue in the disk after receiving a target instruction;
and the submitting queue entry tail pointer management unit is used for sending the current submitting queue entry tail pointer to the disk so that the disk can determine the submitting queue entry information from the submitting queue according to the current submitting queue entry tail pointer, generate the finishing queue entry information according to the submitting queue entry information and then send the finishing queue entry information to the finishing queue entry processing module.
Optionally, the completion queue entry processing module includes:
the completion queue entry processing unit is used for judging whether the first field is effective according to the value relation between the first field and a first target register in the disk and according to the size relation between a completion queue entry head pointer and a completion queue entry tail pointer, and judging whether the completion queue entry information is currently processed according to whether the completion queue entry head pointer is equal to the completion queue entry tail pointer if the completion queue entry head pointer is effective;
And the completion queue entry head pointer management unit is used for updating the current completion queue entry head pointer after the completion queue entry information is processed by the completion queue entry processing unit, and sending the current completion queue entry head pointer to the disk.
Optionally, the completion queue entry processing unit is specifically configured to:
judging whether the value of the first field is the same as the value of the first target register;
if the value of the first field is the same as the value of the first target register, judging whether the tail pointer of the completion queue entry is not smaller than the head pointer of the completion queue entry;
if the tail pointer of the completion queue entry is not less than the head pointer of the completion queue entry, judging that the first field is valid;
if the tail pointer of the completion queue entry is smaller than the head pointer of the completion queue entry, judging that the first field is invalid;
if the value of the first field is opposite to the value of the first target register, judging whether the tail pointer of the completion queue entry is smaller than the head pointer of the completion queue entry;
if the tail pointer of the completion queue entry is smaller than the head pointer of the completion queue entry, judging that the first field is valid;
And if the tail pointer of the completion queue entry is not smaller than the head pointer of the completion queue entry, judging that the first field is invalid.
Optionally, the completion queue entry processing unit is specifically configured to:
if the first field is judged to be valid, judging whether the head pointer of the completion queue entry is equal to the tail pointer of the completion queue entry;
if the head pointer of the completion queue entry is equal to the tail pointer of the completion queue entry, processing the information of the completion queue entry;
if the head pointer of the completion queue entry is not equal to the tail pointer of the completion queue entry, saving the completion queue entry information to a second cache resource in the completion queue entry processing unit, and setting a bit position 1 of a second target register corresponding to the second cache resource.
Optionally, the completion queue entry processing unit is specifically configured to:
reading the values of the bits in the order of the bits in the second destination register;
and if the value of the bit is 1, acquiring and processing the completion queue entry information from the second cache resource corresponding to the bit, and setting the value of the bit to 0 after the processing is completed.
Optionally, the NVME command processing device interacts with a plurality of magnetic disks through a high-speed serial computer expansion bus standard controller and a high-speed serial computer expansion bus standard controller switching device.
In a second aspect, the present application discloses an NVME command processing method, applied to an NVME command processing device, where the NVME command processing device interacts with a plurality of disks through a high-speed serial computer expansion bus standard controller, and includes: the NVME engine scheduling management module, a plurality of NVME engine scheduling components and a submission queue entry sharing cache, wherein the NVME engine scheduling components comprise a first task processing module, a submission queue entry processing module, a completion queue entry processing module and a second task processing module, and the method comprises the following steps:
distributing a target task and a first cache resource in the submission queue entry sharing cache for the NVME engine scheduling component through the NVME engine scheduling management module;
processing the target task distributed by the NVME engine scheduling management module by using the first task processing module, and sending a processing result to the submitting queue entry processing module;
Storing commit queue entry information generated based on the processing result to the first cache resource by using the commit queue entry processing module, and sending a current commit queue entry tail pointer to the disk, so that the disk generates completion queue entry information according to the commit queue entry information, and then sending the completion queue entry information to the completion queue entry processing module;
judging whether a first field of the completion queue entry information is effective or not according to a first rule through the completion queue entry processing module, judging whether the completion queue entry information is processed currently or not according to a second rule if the first field of the completion queue entry information is effective, sending a head pointer of the current completion queue entry to the disk after the completion of the processing, and sending the processed completion queue entry information to the second task processing module;
and determining the completion state of the target task based on the second task processing module according to the processed second field of the completion queue entry information, and reporting the completion state.
In a third aspect, the present application discloses an electronic device comprising:
a memory for storing a computer program;
And a processor for executing the computer program to implement the NVME command processing method disclosed above.
In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program when executed by the processor implements the NVME command processing method disclosed above.
It can be seen that the present application proposes an NVME command processing apparatus, which interacts with a plurality of disks through a high-speed serial computer expansion bus standard controller, including: the system comprises an NVME engine scheduling management module, a plurality of NVME engine scheduling components and a commit queue entry sharing cache, wherein the NVME engine scheduling components comprise a first task processing module, a commit queue entry processing module, a completion queue entry processing module and a second task processing module, and the NVME engine scheduling management module is used for distributing a target task for the NVME engine scheduling components and a first cache resource in the commit queue entry sharing cache; the first task processing module is used for processing the target task distributed by the NVME engine scheduling management module and sending a processing result to the submitting queue entry processing module; the commit queue entry processing module is used for storing commit queue entry information generated based on the processing result to the first cache resource, sending a tail pointer of a current commit queue entry to the disk so that the disk generates completion queue entry information according to the commit queue entry information, and then sending the completion queue entry information to the completion queue entry processing module; the completion queue entry processing module is used for judging whether a first field of the completion queue entry information is effective according to a first rule, judging whether the completion queue entry information is currently processed according to a second rule if the first field of the completion queue entry information is effective, sending a head pointer of the current completion queue entry to the disk after the completion of the processing, and sending the processed completion queue entry information to the second task processing module; and the second task processing module is used for determining the completion state of the target task according to the processed second field of the completion queue entry information and reporting the completion state. In summary, for the target task issued by the host, the present application does not occupy too much CPU resources to perform subsequent processing on the target task, but implements task analysis, construction of entry information of the commit queue, management and update of the tail pointer of the commit queue entry, and management and update of the head pointer of the completion queue entry through the NVME command processing device. In this way, from the perspective of resource consumption, for the application scenario of the multi-NVME engine scheduling component, the method and the device allocate the combined unified scheduling of the target task and the cache resource through the NVME engine scheduling management module, effectively reduce the hardware area overhead and save the production cost. From the performance perspective analysis, the NVME command processing device greatly reduces the memory overhead of the CPU, and compared with software implementation, the NVME command processing device greatly reduces the time delay of software and the time delay of a system level, and for a large-scale system, the cost reduction and the time delay reduction of a part of the CPU bring greater performance benefits. In addition, the completion queue entry processing module judges whether the first field of the completion queue entry information is effective or not and judges whether the completion queue entry information is processed currently or not, so that the completion queue entry information is reordered, and the accuracy of management of the tail pointer of the submitted queue entry and the head pointer of the completion queue entry is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an NVME command processing apparatus disclosed in the present application;
FIG. 2 is a schematic diagram of a specific NVME command processing apparatus disclosed in the present application;
FIG. 3 is a flow chart of a first field validity determination of CQE information disclosed herein;
FIG. 4 is a schematic diagram illustrating a first field validity determination disclosed herein;
FIG. 5 is a schematic diagram illustrating another exemplary first field validity determination disclosed herein;
FIG. 6 is a schematic diagram of an NVME command processing device and disk connection disclosed in the present application;
FIG. 7 is a flow chart of an NVME command processing method disclosed in the present application;
fig. 8 is a block diagram of an electronic device disclosed in the present application.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the conventional operation flow, the CPU of the host implements NVMe command processing, SQ queue management, CQ queue management, pointer update, and the like. Because the execution flow of one NVMe command is long, the time delay consumption is large, and more CPU resources are occupied, thereby affecting the performance of the whole system.
Therefore, the embodiment of the application provides an NVME command processing scheme which can reduce the memory overhead of the CPU.
The embodiment of the application discloses an NVME command processing device, refer to fig. 1, and the NVME command processing device interacts with a plurality of magnetic discs 5 (for example, 5_1,5_m, etc.) through a high-speed serial computer expansion bus standard controller 4, and includes: the NVME engine scheduling management module 1, a plurality of NVME engine scheduling components 2 and a submission queue entry sharing cache 3, wherein the NVME engine scheduling components 2 comprise a first task processing module, a submission queue entry processing module, a completion queue entry processing module and a second task processing module.
The NVME engine scheduling management module 1 is configured to allocate a target task and the commit queue entry to the NVME engine scheduling component 2 to share a first cache resource in the cache 3.
In this embodiment, the NVME engine scheduling management module 1 is configured to dynamically allocate tasks and cache resources to different NVME engine scheduling components (for example, the NVME engine scheduling component 2_1, the NVME engine scheduling component 2_m, etc.) according to a user's requirement, where the cache resources share the cache resources in the cache 3 for a commit queue entry, in the commit queue entry sharing cache 3, the different NVME engine scheduling components correspond to cache resources with different sizes, and the multiple NVME engine scheduling components share the cache resources through time division multiplexing, so as to adapt to different application scenarios. For example, the present embodiment allocates a first cache resource in the commit queue entry shared cache 3 for the NVME engine scheduling component 2.
The first task processing module is configured to process the target task allocated by the NVME engine scheduling management module 1, and send a processing result to the commit queue entry processing module.
In this embodiment, the first task processing module is configured to receive and verify accuracy of a task, report a task that does not meet requirements, execute a task flow for a task that meets requirements, and complete a corresponding PRP information conversion and PRP information moving flow.
The commit queue entry processing module is used for storing commit queue entry information generated based on the processing result to the first cache resource, sending a tail pointer of a current commit queue entry to the disk so that the disk generates completion queue entry information according to the commit queue entry information, and then sending the completion queue entry information to the completion queue entry processing module.
Referring to fig. 2, the commit queue entry processing module specifically includes: the commit queue entry processing unit is used for storing commit queue entry information generated based on an NVMe protocol and the processing result to the first cache resource, and sending the commit queue entry information in the first cache resource to a commit queue in the disk after receiving a target instruction; and the commit queue entry tail pointer management unit is used for sending the current commit queue entry tail pointer (namely the updated commit queue entry tail pointer) to the disk so that the disk can determine the commit queue entry information from the commit queue according to the current commit queue entry tail pointer, generate the completion queue entry information according to the commit queue entry information and then send the completion queue entry information to the completion queue entry processing module.
It should be noted that the target instruction is an instruction for characterizing that a commit queue inside the disk has free space. It is further noted that the commit queue entry tail pointer management unit sends updated commit queue entry tail pointers to the disk when a first aggregation condition is met, wherein the first aggregation condition is that the number of updated commit queue entry tail pointers meets a preset number.
The completion queue entry processing module is used for judging whether a first field of the completion queue entry information is effective according to a first rule, judging whether the completion queue entry information is processed currently according to a second rule if the first field of the completion queue entry information is effective, sending a head pointer of the current completion queue entry to the disk after the completion of the processing, and sending the processed completion queue entry information to the second task processing module.
It should be noted that, since the NVME command processing apparatus interacts with several disks through the high-speed serial computer expansion bus standard controller, and the high-speed serial computer expansion bus standard controller includes a related data transfer manner, the data transfer manner can improve the data transmission efficiency, but the transferred data is not required to strictly adhere to the coming and going data, so that in order to be compatible with PCIe devices of different manufacturers and the potential development direction of future NVME devices, it is necessary to implement the reordering of the data at the completion queue entry processing module.
In this embodiment, the completion queue entry processing module specifically includes: the completion queue entry processing unit is used for judging whether the first field is effective according to the value relation between the first field and a first target register in the disk and according to the size relation between a completion queue entry head pointer and a completion queue entry tail pointer, and judging whether the completion queue entry information is currently processed according to whether the completion queue entry head pointer is equal to the completion queue entry tail pointer if the completion queue entry head pointer is effective; and the completion queue entry head pointer management unit is used for updating the current completion queue entry head pointer after the completion queue entry information is processed by the completion queue entry processing unit, and sending the updated completion queue entry head pointer to the disk when a second aggregation condition is met, wherein the second aggregation condition is that the number of updated completion queue entry tail pointers meets the preset number.
In a first specific embodiment, if the value of the first field is the same as the value of the first target register, determining whether the tail pointer of the completion queue entry is not smaller than the head pointer of the completion queue entry, if the tail pointer of the completion queue entry is not smaller than the head pointer of the completion queue entry, determining that the first field is valid, and if the tail pointer of the completion queue entry is smaller than the head pointer of the completion queue entry, determining that the first field is invalid.
In a second specific embodiment, if the value of the first field is opposite to the value of the first target register, determining whether the tail pointer of the completion queue entry is smaller than the head pointer of the completion queue entry, if the tail pointer of the completion queue entry is smaller than the head pointer of the completion queue entry, determining that the first field is valid, and if the tail pointer of the completion queue entry is not smaller than the head pointer of the completion queue entry, determining that the first field is invalid.
In one aspect, if the first field is determined to be valid, determining whether the head pointer of the completion queue entry is equal to the tail pointer of the completion queue entry, and if the head pointer of the completion queue entry is equal to the tail pointer of the completion queue entry, processing the completion queue entry information.
On the other hand, if the head pointer of the completion queue entry is not equal to the tail pointer of the completion queue entry, the completion queue entry information is saved to a second cache resource in the completion queue entry processing unit, and the bit position 1 of a second target register corresponding to the second cache resource is saved. Further, the value of the bit is read according to the order of the bits in the second target register, when the value of the bit is read, if the value of the bit is 1, the completion queue entry information is obtained and processed from the second cache resource corresponding to the bit, and after the processing is completed, the value of the bit is set to 0.
The above process is described by way of a specific example, see fig. 3:
the completion queue entry processing unit maintains a first target register (i.e. cur_p) inside, and in this embodiment, according to the relationship between the first field (i.e. phase tag) of the CQE information (completion queue entry) and cur_p and the size relationship between the CQT (completion queue tail, completion queue entry tail pointer) and the CQH (completion queue head, completion queue entry head pointer), it is noted that the initial value of cur_p is identical to the initial value of phase tag, and when the CQH register wraps around at the bottom, the cur_p register is inverted. Referring to fig. 4 and 5, if the phase tag is the same as cur_p and CQT is equal to or greater than CQH, it is determined that the phase tag of the CQE information is valid, and if the phase tag is equal to or greater than CQH ～ cur_p is the same, and CQT is smaller than CQH, then the phase tag of the CQE information is determined to be valid, and the rest determines that the phase tag of the CQE information is invalid.
Further, regarding the CQE information valid for the phase tag, whether to process the CQE information currently is determined according to whether the CQT and the CQH are equal, if so, the CQE information is processed, if not, the CQE information is cached in the second cache resource, and the corresponding register cqe_ Vld is set to 1, then the CQE information in the second cache resource is processed sequentially, after the processing is completed, the corresponding register is set to 0, and regarding the invalid CQE information, the CQE information is written in the second cache resource, but the corresponding register cqe_ Vld is not updated, and is reported in error.
In summary, the method ensures that SQH (submission queue head, submitted queue entry head pointer) information fed back by a disk is not misplaced back and forth based on a mode of sequentially processing CQE information, and further, SQH information in the CQE information is sent to a corresponding SQ pointer management unit for pointer management of an SQ queue, so that errors in SQ pointer management are avoided.
In addition, the completion queue entry processing unit is further used for performing CQE completion status processing and detection, and specifically comprises the steps of checking the read CQE information, judging the reasonability of each field and analyzing the status of disk feedback.
And the second task processing module is used for determining the completion state of the target task according to the processed second field of the completion queue entry information and reporting the completion state.
In this embodiment, the second task processing module is configured to determine a completion status of the target task according to the second field of the processed completion queue entry information, and report the completion status.
It should be pointed out that the application is suitable for the working scene of single disk, multiple disk, direct connection disk, switching equipment lower hanging disk. In a direct-connection disk scene, the high-speed serial computer expansion bus standard controller directly hangs an NVMe disk; under the non-direct connection disk scene, the high-speed serial computer expansion bus standard controller is hung under the high-speed serial computer expansion bus standard controller switching equipment, and the NVMe disk is hung under the high-speed serial computer expansion bus standard controller switching equipment. Referring to fig. 6, the NVME engine scheduling management module in the NVME command processing apparatus interacts with a plurality of disks through the high-speed serial computer expansion bus standard controller and the high-speed serial computer expansion bus standard controller switching device, so that the high-speed serial computer expansion bus standard controller can be connected with more NVME disks through the high-speed serial computer expansion bus standard controller switching device.
Further, the CQE information is sequentially read out for processing, but in some situations, in order to improve the processing capability of the disk, it may be necessary to send out the CQE information out of order to improve the processing efficiency of the system, and for such situations that the CQE information may exist out of order, the present application can also implement reordering of the CQE information by using the queue entry processing module, so as to improve the expansibility of the system.
In summary, on one hand, the application provides an NVME command processing device, which can dynamically configure the number of scheduling components of an NVME engine, dynamically configure SQE buffers (submission queue entry, submit queue entries), process NVME task commands, and realize management of SQT pointer CQH pointers, so as to adapt to different NVME application scenarios. And aiming at the scene of CQE information sequence or disorder, the reordering of the CQE information can be realized, and the compatibility and the robustness of the system are obviously improved. In the second aspect, the application is easy to carry out adaptive modification when the NVMe protocol is updated or expanded, does not need to redesign a hardware circuit of the NVMe engine, is convenient and easy to use, and has strong adaptability.
It can be seen that the present application proposes an NVME command processing apparatus, which interacts with a plurality of disks through a high-speed serial computer expansion bus standard controller, including: the system comprises an NVME engine scheduling management module, a plurality of NVME engine scheduling components and a commit queue entry sharing cache, wherein the NVME engine scheduling components comprise a first task processing module, a commit queue entry processing module, a completion queue entry processing module and a second task processing module, and the NVME engine scheduling management module is used for distributing a target task for the NVME engine scheduling components and a first cache resource in the commit queue entry sharing cache; the first task processing module is used for processing the target task distributed by the NVME engine scheduling management module and sending a processing result to the submitting queue entry processing module; the commit queue entry processing module is used for storing commit queue entry information generated based on the processing result to the first cache resource, sending a tail pointer of a current commit queue entry to the disk so that the disk generates completion queue entry information according to the commit queue entry information, and then sending the completion queue entry information to the completion queue entry processing module; the completion queue entry processing module is used for judging whether a first field of the completion queue entry information is effective according to a first rule, judging whether the completion queue entry information is currently processed according to a second rule if the first field of the completion queue entry information is effective, sending a head pointer of the current completion queue entry to the disk after the completion of the processing, and sending the processed completion queue entry information to the second task processing module; and the second task processing module is used for determining the completion state of the target task according to the processed second field of the completion queue entry information and reporting the completion state. In summary, for the target task issued by the host, the present application does not occupy too much CPU resources to perform subsequent processing on the target task, but implements task analysis, construction of entry information of the commit queue, management and update of the tail pointer of the commit queue entry, and management and update of the head pointer of the completion queue entry through the NVME command processing device. In this way, from the perspective of resource consumption, for the application scenario of the multi-NVME engine scheduling component, the method and the device allocate the combined unified scheduling of the target task and the cache resource through the NVME engine scheduling management module, effectively reduce the hardware area overhead and save the production cost. From the performance perspective analysis, the NVME command processing device greatly reduces the memory overhead of the CPU, and compared with software implementation, the NVME command processing device greatly reduces the time delay of software and the time delay of a system level, and for a large-scale system, the cost reduction and the time delay reduction of a part of the CPU bring greater performance benefits. In addition, the completion queue entry processing module judges whether the first field of the completion queue entry information is effective or not and judges whether the completion queue entry information is processed currently or not, so that the completion queue entry information is reordered, and the accuracy of management of the tail pointer of the submitted queue entry and the head pointer of the completion queue entry is ensured.
Correspondingly, the embodiment of the application also discloses an NVME command processing method which is applied to the NVME command processing device, wherein the NVME command processing device interacts with a plurality of disks through a high-speed serial computer expansion bus standard controller, and the method comprises the following steps: the method comprises the following steps of (1) an NVME engine scheduling management module, a plurality of NVME engine scheduling components and a submission queue entry sharing cache, wherein the NVME engine scheduling components comprise a first task processing module, a submission queue entry processing module, a completion queue entry processing module and a second task processing module, and the method comprises the following steps of:
step S11: and distributing a target task and the first cache resource in the shared cache of the submitted queue entry to the NVME engine scheduling component through the NVME engine scheduling management module.
Step S12: and processing the target task distributed by the NVME engine scheduling management module by using the first task processing module, and sending a processing result to the submission queue entry processing module.
Step S13: and saving the commit queue entry information generated based on the processing result to the first cache resource by using the commit queue entry processing module, and sending a tail pointer of the current commit queue entry to the disk so that the disk generates completion queue entry information according to the commit queue entry information, and then sending the completion queue entry information to the completion queue entry processing module.
Step S14: judging whether a first field of the completion queue entry information is effective or not according to a first rule through the completion queue entry processing module, judging whether the completion queue entry information is processed currently or not according to a second rule if the first field of the completion queue entry information is effective, sending a head pointer of the current completion queue entry to the disk after the completion of the processing, and sending the processed completion queue entry information to the second task processing module.
Step S15: and determining the completion state of the target task based on the second task processing module according to the processed second field of the completion queue entry information, and reporting the completion state.
Therefore, the present application proposes an NVME command processing method, where the NVME command processing device interacts with a plurality of disks through a high-speed serial computer expansion bus standard controller, including: the NVME engine scheduling management module, a plurality of NVME engine scheduling components and a submission queue entry sharing cache, wherein the NVME engine scheduling components comprise a first task processing module, a submission queue entry processing module, a completion queue entry processing module and a second task processing module, and the method comprises the following steps: distributing a target task and a first cache resource in the submission queue entry sharing cache for the NVME engine scheduling component through the NVME engine scheduling management module; processing the target task distributed by the NVME engine scheduling management module by using the first task processing module, and sending a processing result to the submitting queue entry processing module; storing commit queue entry information generated based on the processing result to the first cache resource by using the commit queue entry processing module, and sending a current commit queue entry tail pointer to the disk, so that the disk generates completion queue entry information according to the commit queue entry information, and then sending the completion queue entry information to the completion queue entry processing module; judging whether a first field of the completion queue entry information is effective or not according to a first rule through the completion queue entry processing module, judging whether the completion queue entry information is processed currently or not according to a second rule if the first field of the completion queue entry information is effective, sending a head pointer of the current completion queue entry to the disk after the completion of the processing, and sending the processed completion queue entry information to the second task processing module; and determining the completion state of the target task based on the second task processing module according to the processed second field of the completion queue entry information, and reporting the completion state. In summary, for the target task issued by the host, the present application does not occupy too much CPU resources to perform subsequent processing on the target task, but implements task analysis, construction of entry information of the commit queue, management and update of the tail pointer of the commit queue entry, and management and update of the head pointer of the completion queue entry through the NVME command processing device. In this way, from the perspective of resource consumption, for the application scenario of the multi-NVME engine scheduling component, the method and the device allocate the combined unified scheduling of the target task and the cache resource through the NVME engine scheduling management module, effectively reduce the hardware area overhead and save the production cost. From the performance perspective analysis, the NVME command processing device greatly reduces the memory overhead of the CPU, and compared with software implementation, the NVME command processing device greatly reduces the time delay of software and the time delay of a system level, and for a large-scale system, the cost reduction and the time delay reduction of a part of the CPU bring greater performance benefits. In addition, the completion queue entry processing module judges whether the first field of the completion queue entry information is effective or not and judges whether the completion queue entry information is processed currently or not, so that the completion queue entry information is reordered, and the accuracy of management of the tail pointer of the submitted queue entry and the head pointer of the completion queue entry is ensured.
Further, the embodiment of the application also provides electronic equipment. Fig. 8 is a block diagram of an electronic device 20, according to an exemplary embodiment, and the contents of the diagram should not be construed as limiting the scope of use of the present application in any way.
Fig. 8 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a display screen 23, an input output interface 24, a communication interface 25, a power supply 26, and a communication bus 27. The memory 22 is used for storing a computer program, and the computer program is loaded and executed by the processor 21 to implement relevant steps in the NVME command processing method disclosed in any one of the foregoing embodiments. In addition, the electronic device 20 in the present embodiment may be specifically an electronic computer.
In this embodiment, the power supply 26 is used to provide an operating voltage for each hardware device on the electronic device 20; the communication interface 25 can create a data transmission channel between the electronic device 20 and an external device, and the communication protocol to be followed is any communication protocol applicable to the technical solution of the present application, which is not specifically limited herein; the input/output interface 24 is used for obtaining external input data or outputting external output data, and the specific interface type thereof may be selected according to the specific application needs, which is not limited herein.
The memory 22 may be a read-only memory, a random access memory, a magnetic disk, an optical disk, or the like, and the resources stored thereon may include the computer program 221, which may be stored in a temporary or permanent manner. Among them, the computer program 221 may further include a computer program that can be used to perform other specific works, in addition to the computer program that can be used to perform the NVME command processing method performed by the electronic device 20 disclosed in any of the foregoing embodiments.
Further, the embodiment of the application also discloses a computer readable storage medium for storing a computer program; wherein the computer program when executed by the processor implements the NVME command processing method disclosed above.
For specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.
In this application, each embodiment is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between the embodiments refer to the devices disclosed in the embodiments, so that the description is relatively simple because it corresponds to the method disclosed in the embodiments, and the relevant parts refer to the description of the method section.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above describes in detail a method, apparatus, device and storage medium for processing NVME commands provided in the present application, and specific examples are applied to illustrate principles and implementations of the present application, where the above description of the examples is only used to help understand the method and core idea of the present application; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. An NVME command processing apparatus, the NVME command processing apparatus interacting with a plurality of disks through a high-speed serial computer expansion bus standard controller, comprising: the NVME engine scheduling management module, a plurality of NVME engine scheduling components and a submission queue entry sharing cache, wherein the NVME engine scheduling components comprise a first task processing module, a submission queue entry processing module, a completion queue entry processing module and a second task processing module,
the NVME engine scheduling management module is used for distributing a target task and a first cache resource in the submission queue entry sharing cache for the NVME engine scheduling component;
The first task processing module is used for processing the target task distributed by the NVME engine scheduling management module and sending a processing result to the submitting queue entry processing module;
the commit queue entry processing module is used for storing commit queue entry information generated based on the processing result to the first cache resource, sending a tail pointer of a current commit queue entry to the disk so that the disk generates completion queue entry information according to the commit queue entry information, and then sending the completion queue entry information to the completion queue entry processing module;
the completion queue entry processing module is used for judging whether a first field of the completion queue entry information is effective according to a first rule, judging whether the completion queue entry information is currently processed according to a second rule if the first field of the completion queue entry information is effective, sending a head pointer of the current completion queue entry to the disk after the completion of the processing, and sending the processed completion queue entry information to the second task processing module;
and the second task processing module is used for determining the completion state of the target task according to the processed second field of the completion queue entry information and reporting the completion state.
2. The NVME command processing apparatus of claim 1, wherein the commit queue entry processing module comprises:
the commit queue entry processing unit is used for storing commit queue entry information generated based on the processing result to the first cache resource and sending the commit queue entry information in the first cache resource to a commit queue in the disk after receiving a target instruction;
and the submitting queue entry tail pointer management unit is used for sending the current submitting queue entry tail pointer to the disk so that the disk can determine the submitting queue entry information from the submitting queue according to the current submitting queue entry tail pointer, generate the finishing queue entry information according to the submitting queue entry information and then send the finishing queue entry information to the finishing queue entry processing module.
3. The NVME command processing apparatus of claim 1, wherein the completion queue entry processing module comprises:
the completion queue entry processing unit is used for judging whether the first field is effective according to the value relation between the first field and a first target register in the disk and according to the size relation between a completion queue entry head pointer and a completion queue entry tail pointer, and judging whether the completion queue entry information is currently processed according to whether the completion queue entry head pointer is equal to the completion queue entry tail pointer if the completion queue entry head pointer is effective;
And the completion queue entry head pointer management unit is used for updating the current completion queue entry head pointer after the completion queue entry information is processed by the completion queue entry processing unit, and sending the current completion queue entry head pointer to the disk.
4. The NVME command processing apparatus of claim 3, wherein the completion queue entry processing unit is specifically configured to:
judging whether the value of the first field is the same as the value of the first target register;
if the value of the first field is the same as the value of the first target register, judging whether the tail pointer of the completion queue entry is not smaller than the head pointer of the completion queue entry;
if the tail pointer of the completion queue entry is not less than the head pointer of the completion queue entry, judging that the first field is valid;
if the tail pointer of the completion queue entry is smaller than the head pointer of the completion queue entry, judging that the first field is invalid;
if the value of the first field is opposite to the value of the first target register, judging whether the tail pointer of the completion queue entry is smaller than the head pointer of the completion queue entry;
If the tail pointer of the completion queue entry is smaller than the head pointer of the completion queue entry, judging that the first field is valid;
and if the tail pointer of the completion queue entry is not smaller than the head pointer of the completion queue entry, judging that the first field is invalid.
5. The NVME command processing apparatus of claim 4, wherein the completion queue entry processing unit is specifically configured to:
if the first field is judged to be valid, judging whether the head pointer of the completion queue entry is equal to the tail pointer of the completion queue entry;
if the head pointer of the completion queue entry is equal to the tail pointer of the completion queue entry, processing the information of the completion queue entry;
if the head pointer of the completion queue entry is not equal to the tail pointer of the completion queue entry, saving the completion queue entry information to a second cache resource in the completion queue entry processing unit, and setting a bit position 1 of a second target register corresponding to the second cache resource.
6. The NVME command processing apparatus of claim 5, wherein the completion queue entry processing unit is specifically configured to:
Reading the values of the bits in the order of the bits in the second destination register;
and if the value of the bit is 1, acquiring and processing the completion queue entry information from the second cache resource corresponding to the bit, and setting the value of the bit to 0 after the processing is completed.
7. The NVME command processing apparatus of any one of claims 1 to 6, wherein the NVME command processing apparatus interacts with a number of disks through a high speed serial computer expansion bus standard controller and a high speed serial computer expansion bus standard controller switching device.
8. The NVME command processing method is characterized by being applied to an NVME command processing device, wherein the NVME command processing device interacts with a plurality of magnetic disks through a high-speed serial computer expansion bus standard controller, and comprises the following steps of: the NVME engine scheduling management module, a plurality of NVME engine scheduling components and a submission queue entry sharing cache, wherein the NVME engine scheduling components comprise a first task processing module, a submission queue entry processing module, a completion queue entry processing module and a second task processing module, and the method comprises the following steps:
Distributing a target task and a first cache resource in the submission queue entry sharing cache for the NVME engine scheduling component through the NVME engine scheduling management module;
processing the target task distributed by the NVME engine scheduling management module by using the first task processing module, and sending a processing result to the submitting queue entry processing module;
storing commit queue entry information generated based on the processing result to the first cache resource by using the commit queue entry processing module, and sending a current commit queue entry tail pointer to the disk, so that the disk generates completion queue entry information according to the commit queue entry information, and then sending the completion queue entry information to the completion queue entry processing module;
judging whether a first field of the completion queue entry information is effective or not according to a first rule through the completion queue entry processing module, judging whether the completion queue entry information is processed currently or not according to a second rule if the first field of the completion queue entry information is effective, sending a head pointer of the current completion queue entry to the disk after the completion of the processing, and sending the processed completion queue entry information to the second task processing module;
And determining the completion state of the target task based on the second task processing module according to the processed second field of the completion queue entry information, and reporting the completion state.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the NVME command processing method of claim 8.
10. A computer-readable storage medium for storing a computer program; wherein the computer program when executed by a processor implements the NVME command processing method of claim 8.
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