CN117673148A - Power semiconductor - Google Patents
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- CN117673148A CN117673148A CN202211072013.0A CN202211072013A CN117673148A CN 117673148 A CN117673148 A CN 117673148A CN 202211072013 A CN202211072013 A CN 202211072013A CN 117673148 A CN117673148 A CN 117673148A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 239000000872 buffer Substances 0.000 claims abstract description 87
- 239000002184 metal Substances 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 abstract description 11
- 230000003071 parasitic effect Effects 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 8
- 230000005669 field effect Effects 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- 230000004888 barrier function Effects 0.000 description 12
- 238000002513 implantation Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Abstract
The power semiconductor includes a base layer, an epitaxial layer, a source electrode, and a first metal layer. The substrate layer includes an active region, a buffer region and a termination region. The buffer region surrounds the active region, and the termination region surrounds the active region. The epitaxial layer is on the base layer. The epitaxial layer is located in the active region, the buffer region and the termination region. The epitaxial layer has a first conductivity type. The source electrode is located in the active region. The first metal layer is located in the buffer. The first metal layer is connected with the source electrode, so that the diode in the buffer area is used as a diode connected with the metal oxide semiconductor field effect transistor in the active area in parallel, the area of the parasitic diode can be enlarged, and the current of the parasitic diode can be improved. The active region, the buffer region and the termination region are formed in the same package. The first metal layer and the source electrode are integrally formed. The process of the buffer region can be combined with the process of the active region, so that the power semiconductor has the technical effects of protecting a circuit, improving efficiency, reducing cost and reducing volume under the condition of reducing one package.
Description
Technical Field
The present disclosure relates to a power semiconductor.
Background
Additional diodes and field effect transistors are required in the power module in parallel to protect the overall circuit and to improve overall performance. However, the field effect transistor and the diode in the power semiconductor element are two packages separated, and the process is complex and the cost is high. In addition, although the field effect transistor itself has a parasitic diode, the area is smaller, the current which can be carried is lower, and the product requirement cannot be met.
In view of this, how to provide a power semiconductor that can overcome the above problems is still one of the targets of the current efforts in the industry.
Disclosure of Invention
One aspect of the present disclosure is a power semiconductor.
In one embodiment of the present disclosure, a power semiconductor includes a base layer, an epitaxial layer, a source electrode, and a first metal layer. The substrate layer includes an active region, a buffer region and a termination region. The buffer region surrounds the active region, and the termination region surrounds the active region. The epitaxial layer is on the base layer. The epitaxial layer is located in the active region, the buffer region and the terminal region, and has a first conductivity type. The source electrode is located in the active region. The first metal layer is located in the buffer. The first metal layer is connected with the source electrode.
In one embodiment of the present disclosure, the power semiconductor further comprises a gate electrode and a first oxide layer. The gate electrode is located in the active region. The first oxide layer is in the active region, wherein the first oxide layer surrounds the gate electrode, and the first metal layer surrounds the gate electrode and the first oxide layer.
In one embodiment of the present disclosure, the power semiconductor further comprises a second oxide layer located in the termination region.
The second oxide layer is connected to the first oxide layer.
In one embodiment of the present disclosure, the termination region is located between the active region and the buffer region, and the buffer region surrounds the termination region.
In one embodiment of the present disclosure, the power semiconductor further comprises a second oxide layer located in the termination region.
The second oxide layer surrounds the first metal layer.
In one embodiment of the present disclosure, the buffer region is located between the active region and the termination region, and the termination region surrounds the buffer region.
In one embodiment of the present disclosure, the epitaxial layer further comprises a doped region. The doped region is located in the buffer region. The doped region is located on one side of the epitaxial layer facing the first metal layer, and the doped region has a second conductivity type.
In an embodiment of the disclosure, the epitaxial layer further includes a plurality of doped regions. The doped region is located in the buffer region. The doped region is located on one side of the epitaxial layer facing the first metal layer, and the doped region has a second conductivity type.
In one embodiment of the present disclosure, the epitaxial layer includes a plurality of trenches. The trench is located in the buffer. The first metal layer extends into the trench of the epitaxial layer, and the trench is located above the doped region.
In one embodiment of the present disclosure, the epitaxial layer includes a plurality of trenches. The trench is located in the buffer. The first metal layer extends into the trench of the epitaxial layer, and the doped region surrounds the trench.
In the above embodiment, the first metal layer of the power semiconductor is connected to the source electrode, so that the diode in the buffer region is used as a diode connected in parallel with the mosfet in the active region. Thus, the parasitic diode area can be enlarged and the current of the parasitic diode can be increased. The active region, the buffer region and the termination region of the present disclosure are formed in the same package. The first metal layer and the source electrode are integrally formed. In other words, the buffer process can be combined with the active region process, so that the power semiconductor has the technical effects of protecting the circuit and improving the performance under the condition of reducing one package. Therefore, the power semiconductor disclosed by the invention can also have the effects of reducing the cost and the volume.
Drawings
Fig. 1 is a top view of a power semiconductor according to an embodiment of the present disclosure.
Fig. 2 is a cross-sectional view taken along line 2-2 of fig. 1.
Fig. 3 is a top view of a power semiconductor according to another embodiment of the present disclosure.
Fig. 4 is a cross-sectional view taken along line 4-4 of fig. 3.
Fig. 5 is a cross-sectional view of a buffer according to another embodiment of the present disclosure.
Fig. 6 is a cross-sectional view of a buffer according to yet another embodiment of the present disclosure.
Fig. 7 is a cross-sectional view of a buffer according to yet another embodiment of the present disclosure.
Detailed Description
Various embodiments of the invention are disclosed in the accompanying drawings, and for purposes of explanation, numerous practical details are set forth in the following description. However, it should be understood that these practical details are not to be taken as limiting the invention. That is, in some embodiments of the invention, these practical details are unnecessary. Furthermore, for the sake of simplicity of the drawing, some of the well-known structures and elements are shown in the accompanying drawings in a simplified schematic manner. And the thickness of layers and regions in the drawings may be exaggerated for clarity and like reference numerals refer to like elements throughout the description of the drawings.
Fig. 1 is a top view of a power semiconductor 100 according to an embodiment of the present disclosure. Fig. 2 is a cross-sectional view taken along line 2-2 of fig. 1. Referring to fig. 2, the power semiconductor 100 includes a base layer 110 and an epitaxial layer 120. Referring to fig. 1 and 2, the base layer 110 includes an active region 112, a buffer region 114, and a termination region 116. In the view of fig. 1, both the buffer 114 and termination 116 regions are annular. The buffer region 114 and the termination region 116 surround the active region 112.
In the present embodiment, the buffer region 114 is located between the active region 112 and the terminal region 116, and the terminal region 116 surrounds the buffer region 114, but the disclosure is not limited thereto. The epitaxial layer 120 is located on the base layer 110. Epitaxial layer 120 is located in active region 112, buffer region 114 and termination region 116. In other words, the epitaxial layer 120 extends from the active region 112 to the buffer region 114 and the termination region 116.
The power semiconductor 100 in this embodiment is an N-type (first conductivity type) element. The epitaxial layer 120 and the base layer 110 have a first conductivity type (N-type). The base layer 110 is an N-type heavily doped substrate (n+). The epitaxial layer 120 has a lower doping concentration (N-) than the substrate layer 110. The epitaxial layer 120 is a semiconductor epitaxial layer and provides a drift region between the source S and the drain D.
As shown in fig. 2, the power semiconductor 100 further includes a source electrode 130 and a first metal layer 140. The source electrode 130 is located in the active region 112. The first metal layer 140 is located in the buffer 114. The first metal layer 140 is connected to the source electrode 130. The power semiconductor 100 further includes a drain electrode 150 and a second metal layer 160. The drain electrode 150 is located in the active region 112. The second metal layer 160 is located in the buffer 114. The second metal layer 160 is connected to the drain electrode 150. The source electrode 130 and the first metal layer 140 are located above the epitaxial layer 120. The drain electrode 150 and the second metal layer 160 are located under the base layer 110. The base layer 110 and the epitaxial layer 120 are located between the source electrode 130 and the drain electrode 150, and also between the first metal layer 140 and the second metal layer 160.
As shown in fig. 2, the power semiconductor 100 further includes a gate electrode 170 and a first oxide layer 180. The gate electrode 170 and the first oxide layer 180 are located in the active region 112. The gate electrode 170 and the first oxide layer 180 are located between the source electrode 130 and the epitaxial layer 120. The gate electrode 170 is a polysilicon gate and the first oxide layer 180 is silicon oxide. The first oxide layer 180 surrounds the gate electrode 170 and separates the gate electrode 170 from the epitaxial layer 120. In this embodiment, the first metal layer 140 in the buffer region 114 surrounds the gate electrode 170 and the first oxide layer 180 in the active region 112.
The power semiconductor 100 further includes a doped well region 122, a source region 132, and a heavily doped region 124 in the active region 112. The doped well region 122 is a P-type doped region (second conductivity type), and the source region 132 is an N-type doped region. The source region 132 and the heavily doped region 124 are located in the doped well region 122. The source electrode 130 is electrically connected to the source region 132. Heavily doped region 124 is a P-type heavily doped region (p+). The channel region CH is formed between the P-type doped well region 122 and the N-type source region 132.
The power semiconductor 100 further includes a second oxide layer 190 located in the termination region 116 and the first doped region 126. The first doped region 126 is located on a side of the epitaxial layer 120 facing the second oxide layer 190. The second oxide layer 190 covers the first doped region 126 and the epitaxial layer 120. The second oxide layer 190 located in the termination region 116 surrounds the first metal layer 140 located in the buffer region 114. In the present embodiment, the power semiconductor 100 includes a plurality of first doped regions 126 separated from each other, but the disclosure is not limited thereto. The first doped region 126 is a P-type doped region, i.e., the first doped region 126 and the heavily doped region 124 have the same conductivity type. The first doped region 126 serves as a field ring structure for reducing the phenomenon of electric field concentration. The specific structure of the termination region 116 in the present embodiment is merely an example, and is not intended to limit the disclosure.
The active region 112 is a vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) having a source S, a drain D and a gate G. Generally, the heavily doped P-type region 124 and the epitaxial N-type layer 120 in the active region 112 form a parasitic diode of the mosfet. However, the parasitic diode in the active region 112 has a small area and can carry a low current. The first metal layer 140 in the buffer region 114 and the epitaxial layer 120 are combined to form a Schottky barrier diode (Schottky Barrier Diode, SBD). Since the first metal layer 140 is connected to the source electrode 130, the Schottky Barrier Diode (SBD) in the buffer region 114 acts as a diode in parallel with the mosfet in the active region 112. Thus, the parasitic diode area can be enlarged and the current of the parasitic diode can be increased. In other embodiments, the buffer 114 may have other types of diodes therein, as will be described in more detail in subsequent paragraphs.
The active region 112, buffer region 114, and termination region 116 of the present disclosure are formed within the same package. Specifically, the first metal layer 140 and the source electrode 130 are integrally formed, and the first doped region 126 and the heavily doped region 124 may be formed in the same implantation step. In other words, the process of the buffer region 114 can be combined with the process of the active region 112, so that the power semiconductor 100 has the technical effects of protecting the circuit and improving the performance while reducing one package. Therefore, the power semiconductor 100 of the present disclosure may also have the effects of reducing the cost and the volume.
Fig. 3 is a top view of a power semiconductor 100a according to another embodiment of the present disclosure. Fig. 4 is a cross-sectional view taken along line 4-4 of fig. 3. The power semiconductor 100a includes a base layer 110a and an epitaxial layer 120. The base layer 110a includes an active region 112a, a buffer region 114a, and a termination region 116a. In the perspective of fig. 3, both the buffer 114a and termination 116a regions are annular. The buffer region 114a and the termination region 116a surround the active region 112a.
In the present embodiment, the terminal region 116a is located between the active region 112a and the buffer region 114a, and the buffer region 114a surrounds the terminal region 116a. The epitaxial layer 120 is located on the base layer 110 a. Epitaxial layer 120 extends from active region 112a to buffer region 114a and termination region 116a. In this embodiment, the second oxide layer 190 located in the termination region 116a is connected to the first oxide layer 180 located in the active region 112a.
The conductivity type and doping concentration of the base layer 110a, epitaxial layer 120, doped well region 122, source region 132, and heavily doped region 124 of the power semiconductor 100a are substantially the same as those of the power semiconductor 100 shown in fig. 2. In this embodiment, the source electrode 130a of the power semiconductor 100a also extends to the buffer region 114a and is connected to the first metal layer 140 in the termination region 116a. In other words, the second oxide layer 190 is located between the source electrode 130a and the epitaxial layer 120. The first metal layer 140 surrounds the first oxide layer 180 and the second oxide layer 190.
In this embodiment, the power semiconductor 100a further includes a second doped region 128 located in the buffer region 114 a. The second doped region 128 is a P-type heavily doped region (p+), i.e., the second doped region 128, the first doped region 126 and the heavily doped region 124 have the same conductivity type (second conductivity type). The second doped region 128 is located on a side of the epitaxial layer 120 facing the first metal layer 140. The second doped region 128 of the P-type in the buffer region 114a and the epitaxial layer 120 of the N-type constitute a PN diode. In other embodiments, the power semiconductor 100a may not have the second doped region 128, i.e., the Schottky Barrier Diode (SBD) of the power semiconductor 100 shown in fig. 2 may be applied in the buffer region 114a of the power semiconductor 100 a. Likewise, in other embodiments, the buffer 114 of the power semiconductor 100 may also have a PN diode in the buffer 114a of the power semiconductor 100 a.
The active region 112a, the buffer region 114a, and the termination region 116a of the present disclosure are formed in the same package. Specifically, the first metal layer 140 and the source electrode 130a are integrally formed, and the second doped region 128, the first doped region 126 and the heavily doped region 124 may be formed in the same implantation step. In other words, the process of the buffer region 114a may be combined with the process of the active region 112a. Therefore, the power semiconductor 100b has the same technical effects as the power semiconductor 100, and will not be described herein.
Fig. 5 is a cross-sectional view of a buffer 114b according to yet another embodiment of the present disclosure. The buffer region 114b is substantially the same as the buffer region 114a of the power semiconductor 100a shown in fig. 4, except that the buffer region 114a in this embodiment is a junction barrier schottky diode (Junction Barrier Schottky diode, JBS).
In this embodiment, a plurality of second doped regions 128a are located in the epitaxial layer 120. The second doped region 128a is located on a side of the epitaxial layer 120 facing the first metal layer 140. Junction barrier schottky diodes (JBS) in the buffer region 114b may also be used in the power semiconductor 100 shown in fig. 2 as well as in the power semiconductor 100a shown in fig. 4.
Fig. 6 is a cross-sectional view of a buffer 114c according to yet another embodiment of the present disclosure. The buffer 114c is substantially the same as the buffer 114b shown in fig. 5, except that the buffer 114c is a trench junction barrier schottky Diode (Trench Junction Barrier Schottky Diode, TJBS Diode).
In this embodiment, the epitaxial layer 120 includes a plurality of trenches 120T located in the buffer region 114 c. The first metal layer 140a extends into the trench 120T of the epitaxial layer 120, and the trench 120T is located above the second doped region 128 b. The trench junction barrier schottky Diode (TJBS Diode) in the buffer region 114c may be applied to the power semiconductor 100 shown in fig. 2 and the power semiconductor 100a shown in fig. 4.
Fig. 7 is a cross-sectional view of a buffer 114d according to yet another embodiment of the present disclosure. The buffer 114d is substantially the same as the buffer 114c shown in FIG. 6, and the buffer 114d is another type of trench junction barrier Diode (TJBS Diode). In this embodiment, the second doped region 128c surrounds the trench 120T. The trench junction barrier schottky Diode (TJBS Diode) in the buffer 114d may be applied to the power semiconductor 100 shown in fig. 2 and the power semiconductor 100a shown in fig. 4.
In summary, the first metal layer of the power semiconductor of the present disclosure is connected to the source electrode, so that the diode in the buffer region is used as a diode connected in parallel with the mosfet in the active region. Thus, the parasitic diode area can be enlarged and the current of the parasitic diode can be increased. The active region, the buffer region and the termination region of the present disclosure are formed in the same package. The first metal layer and the source electrode are integrally formed. In other words, the buffer process can be combined with the active region process, so that the power semiconductor has the technical effects of protecting the circuit and improving the performance under the condition of reducing one package. Therefore, the power semiconductor disclosed by the invention can also have the effects of reducing the cost and the volume.
While the present invention has been described with reference to the above embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention, and it is intended that the scope of the invention be limited only by the appended claims.
[ symbolic description ]
100,100a,100b power semiconductor
110 substrate layer
112,112a active region
114,114a,114b,114c,114d: buffers
116,116a termination area
120 epitaxial layer
120T groove
122 doped well region
124 heavily doped region
126 first doped region
128,128a,128b,128c: a second doped region
130,130a source electrode
132 source region
140,140a first metal layer
150 drain electrode
160 second metal layer
170 gate electrode
180 first oxide layer
190 second oxide layer
CH channel region
S: source electrode
D drain electrode
G: grid electrode
2-2,4-4 line segments.
Claims (10)
1. A power semiconductor, comprising:
a base layer comprising an active region, a buffer region, and a termination region, wherein the buffer region surrounds the active region and the termination region surrounds the active region;
an epitaxial layer on the base layer, wherein the epitaxial layer is in the active region, the buffer region, and the termination region, and the epitaxial layer has a first conductivity type;
a source electrode in the active region; and
and the first metal layer is positioned in the buffer area, and the first metal layer is connected with the source electrode.
2. The power semiconductor of claim 1, further comprising:
a gate electrode in the active region; and
a first oxide layer is in the active region, wherein the first oxide layer surrounds the gate electrode and the first metal layer surrounds the gate electrode and the first oxide layer.
3. The power semiconductor of claim 2, further comprising:
and a second oxide layer in the termination region, wherein the second oxide layer is connected to the first oxide layer.
4. A power semiconductor according to any one of claims 1, 2, 3, wherein the termination region is located between the active region and the buffer region, and the buffer region surrounds the termination region.
5. The power semiconductor of claim 1, further comprising:
a second oxide layer in the termination region, wherein the second oxide layer surrounds the first metal layer.
6. The power semiconductor of any one of claims 1, 2, 5, wherein the buffer region is located between the active region and the termination region, and the termination region surrounds the buffer region.
7. The power semiconductor of any one of claims 1, 2, 3, 5, wherein the epitaxial layer further comprises a doped region, the doped region being located in the buffer region, the doped region being located on a side of the epitaxial layer facing the first metal layer, and the doped region being of a second conductivity type.
8. The power semiconductor of claim 1, wherein the epitaxial layer further comprises a plurality of doped regions in the buffer region, the plurality of doped regions being on a side of the epitaxial layer facing the first metal layer, and the plurality of doped regions being of a second conductivity type.
9. The power semiconductor of claim 8, wherein the epitaxial layer comprises a plurality of trenches in the buffer, the first metal layer extends into the plurality of trenches of the epitaxial layer, and the plurality of trenches are located above the plurality of doped regions.
10. The power semiconductor of claim 8, wherein the epitaxial layer comprises a plurality of trenches in the buffer, the first metal layer extends into the plurality of trenches of the epitaxial layer, and the plurality of doped regions surrounds the plurality of trenches.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211072013.0A CN117673148A (en) | 2022-09-01 | 2022-09-01 | Power semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211072013.0A CN117673148A (en) | 2022-09-01 | 2022-09-01 | Power semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117673148A true CN117673148A (en) | 2024-03-08 |
Family
ID=90066940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211072013.0A Pending CN117673148A (en) | 2022-09-01 | 2022-09-01 | Power semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117673148A (en) |
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2022
- 2022-09-01 CN CN202211072013.0A patent/CN117673148A/en active Pending
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