CN117672814A - Passivation layer growth method and insulated gate bipolar transistor wafer - Google Patents
Passivation layer growth method and insulated gate bipolar transistor wafer Download PDFInfo
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Abstract
The embodiment of the invention provides a passivation layer growth method and an insulated gate bipolar transistor wafer. Projecting ultraviolet rays on the surface of the wafer provided with the front metal layer based on the passivation layer design; printing photosensitive polyimide to the position on the surface of the wafer, where ultraviolet rays are projected; the photosensitive polyimide is solidified and molded under the projection of ultraviolet rays, so that a passivation layer meeting the design of the passivation layer is formed. The passivation layer can be accurately configured at the required position on the surface of the wafer according to the chip design requirement, and the thickness is controllable, so that the prepared passivation layer has high uniformity, and the etching process can be omitted, thereby avoiding the possible adverse effect of the etching process on the surface of the wafer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a passivation layer growth method and an insulated gate bipolar transistor wafer.
Background
In the prior art, in the preparation of insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) wafers, it is involved to grow a passivation layer on the wafer surface. Generally, a passivation layer is usually formed by spin coating a thermosetting polyimide on a wafer surface, and then etching. However, the passivation layer processed in this way is thin in the center and thick in the edge, and it is difficult to obtain a passivation layer with high uniformity, which affects the performance of the insulated gate bipolar transistor wafer.
Disclosure of Invention
The embodiment of the invention provides a method for growing a passivation layer and an insulated gate bipolar transistor wafer, which are used for solving the problem of uneven passivation layer of the insulated gate bipolar transistor wafer.
The embodiment of the invention discloses a method for growing a passivation layer, which comprises the following steps:
projecting ultraviolet rays on the surface of the wafer provided with the front metal layer based on the passivation layer design;
printing photosensitive polyimide to the position on the surface of the wafer, where ultraviolet rays are projected;
the photosensitive polyimide is solidified and molded under the projection of ultraviolet rays, so that a passivation layer meeting the design of the passivation layer is formed.
Optionally, the step of projecting ultraviolet light on the surface of the wafer provided with the front metal layer based on the passivation layer design includes:
projecting ultraviolet rays layer by layer and/or point by point on the surface of the wafer provided with the front metal layer based on the passivation layer design;
the photosensitive polyimide is solidified and molded under the projection of ultraviolet rays, and a passivation layer meeting the design of the passivation layer is formed, and the method comprises the following steps:
the photosensitive polyimide is cured and formed layer by layer and/or point by point under ultraviolet projection to form a passivation layer meeting the design of the passivation layer.
Optionally, the photosensitive polyimide is cured layer by layer and/or point by point under ultraviolet projection to form a passivation layer meeting the design of the passivation layer, which comprises the following steps:
determining a target forming mode corresponding to the photosensitive polyimide curing forming as layer-by-layer and/or point-by-point curing forming based on the area of the wafer;
and controlling the photosensitive polyimide to be cured and molded under the projection of ultraviolet rays by adopting the target molding mode to form passivation meeting the design of a passivation layer.
Optionally, the photosensitive polyimide is prepared by the following steps:
synthesizing polyamide acid by using dianhydride and diamine to obtain polyamide acid solution;
performing thermal imidization on the polyamic acid solution in air to obtain a thermosetting polyimide solution;
adding resin with photosensitive functional groups into the thermosetting polyimide solution to obtain a polyimide resin solution with photocuring performance;
and removing the solvent in the polyimide resin solution with the photo-curing performance to obtain photosensitive polyimide powder.
Alternatively, the resin having photosensitive functional groups includes an epoxy acrylate having an unsaturated double bond or an epoxy functional group.
Optionally, the wafer provided with the front metal layer is prepared by the following method:
forming a first groove surface on the surface of a first wafer by depositing metal tungsten and etching;
and forming a wafer provided with a front metal layer on the first groove surface by depositing aluminum.
Optionally, the first wafer is prepared by the following method:
forming a hard mask on the front surface of the second wafer;
etching to form a groove and carrying out gate oxidation treatment;
depositing polysilicon on the surface of the groove to form a groove gate;
injecting first ions to form a P well, and injecting second ions to form an N+ region;
depositing undoped silicon glass and boron phosphorus silicon glass to form a dielectric layer;
opening holes among the grooves to obtain a third wafer;
and depositing a Ti/TiN layer on the front surface of the third wafer to obtain a first wafer.
Optionally, the second wafer is prepared by the following method:
oxidizing a preset N-type substrate to form a silicon oxide layer;
etching the surface of the silicon oxide layer, and injecting boron ions into the etching area to form a p+ area;
and etching to form an active region and a field oxide region to obtain a second wafer.
Optionally, the method further comprises:
thinning the thickness of the wafer through a grinding process on the back of the wafer provided with the front metal layer;
injecting third ions into the back of the wafer provided with the front metal layer to form a P+ region, and carrying out laser annealing treatment;
and depositing a back metal layer on the back of the wafer provided with the front metal layer.
The embodiment of the invention also provides an insulated gate bipolar transistor wafer, and the passivation layer of the insulated gate bipolar transistor wafer is prepared by adopting the method disclosed by the embodiment of the invention.
The embodiment of the invention has the following advantages:
through adopting the projection ultraviolet ray, print photosensitive polyimide to the wafer surface projects there is ultraviolet ray department, photosensitive polyimide solidifies the shaping under the ultraviolet ray projection, forms the passivation layer that satisfies the passivation layer design, can be according to the required position of chip design requirement ground on wafer surface and dispose the passivation layer accurately, and thickness is controllable for the passivation layer degree of consistency of preparation is high, and can save the etching procedure, avoids the possible harmful effects that brings of etching procedure to wafer surface.
Drawings
FIG. 1 is a flow chart of steps of a method for growing a passivation layer according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an igbt wafer process according to an embodiment of the invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 1, a step flow chart of a passivation layer growth method provided in an embodiment of the present invention is shown, which may specifically include the following steps:
step 101, projecting ultraviolet rays on the surface of the wafer provided with the front metal layer based on the passivation layer design;
specifically, in the wafer preparation process, the wafer can be subjected to graphical design according to the chip requirement, and the arrangement of functions in the finally produced wafer meets the chip design requirement through a series of processes such as etching, deposition and the like. Therefore, the embodiment of the invention can design the pattern of the passivation layer, and correspondingly projects ultraviolet rays at the position where the passivation layer needs to be grown on the surface of the wafer provided with the front metal layer based on the design requirement of the passivation layer, so that the passivation layer is arranged at the corresponding position based on the ultraviolet rays.
Generally, the passivation layer may be disposed on the surface of the wafer where the front side metal layer is uncovered, so that the surface of the wafer is flat and the front side metal layer is protected. Thus, the passivation layer may be generally designed to cover the uneven areas of the front surface of the wafer and around the front metal layer.
In a specific implementation, in order to further protect the front surface of the wafer, a layer of SiN may be deposited on the front surface of the wafer by using a sputtering process before the passivation layer is deployed, so as to further strengthen the passivation layer of the wafer and play a role in buffering protection.
102, printing photosensitive polyimide to a position on the surface of the wafer, where ultraviolet rays are projected;
in the embodiment of the invention, the photosensitive polyimide can be printed to the position on the surface of the wafer, on which ultraviolet rays are projected, so that the photosensitive polyimide is deployed to the position on the surface of the wafer, on which the passivation layer needs to be grown.
And step 103, curing and forming the photosensitive polyimide under ultraviolet projection to form a passivation layer meeting the design of the passivation layer.
In embodiments of the present invention, the photosensitive polyimide may be sensitive to ultraviolet light. The photosensitive polyimide can be cured and molded under the projection of ultraviolet rays. The irradiation position of ultraviolet rays can be changed step by step according to actual needs, and photosensitive polyimide is deployed at the corresponding position, so that the corresponding passivation layer is formed according to the design of the passivation layer. In this way, the growth position and thickness of the passivation layer are highly controllable, and the formed passivation layer can have better flatness. Meanwhile, the etching process is not needed, so that adverse effects on the surface of the wafer can be properly reduced.
Optionally, the step of projecting ultraviolet light on the surface of the wafer provided with the front metal layer based on the passivation layer design includes:
s11, designing layer by layer and/or projecting ultraviolet rays point by point on the surface of the wafer provided with the front metal layer based on the passivation layer;
in the embodiment of the invention, the passivation layer can be regarded as a three-dimensional structure, and in order to improve the growth precision of the passivation layer, the passivation layer can be divided into multiple layers or multiple points based on the design of the passivation layer, and ultraviolet rays are projected layer by layer and/or point by point on the surface of the wafer provided with the front metal layer, so that the passivation layer can be formed layer by layer and/or point by point, and the precision of the passivation layer can be greatly improved.
The photosensitive polyimide is solidified and molded under the projection of ultraviolet rays, and a passivation layer meeting the design of the passivation layer is formed, and the method comprises the following steps:
s21, curing and forming the photosensitive polyimide layer by layer and/or point by point under ultraviolet projection to form a passivation layer meeting the design of the passivation layer.
Specifically, under the condition of ultraviolet ray layer-by-layer and/or point-by-point projection, a proper amount of photosensitive polyimide can be applied at an ultraviolet ray projection position, and the photosensitive polyimide is cured and formed under the irradiation of ultraviolet rays, so that a passivation layer at the current layer surface and/or the current point position can be formed, and as the ultraviolet ray projection position changes, the photosensitive polyimide is continuously applied at the corresponding position, so that the photosensitive polyimide is cured and formed layer by layer and/or point by point under the ultraviolet ray projection, and the passivation layer can be formed with high precision.
Optionally, the photosensitive polyimide is cured layer by layer and/or point by point under ultraviolet projection to form a passivation layer meeting the design of the passivation layer, which comprises the following steps:
s31, determining that a target molding mode corresponding to the photosensitive polyimide curing molding is layer-by-layer and/or point-by-point curing molding based on the area of the wafer;
in one embodiment of the invention, layer-by-layer and/or point-by-point curing is employed, which may be determined based on the area of the wafer. Under the condition that the area of the wafer is relatively large, the progress required by growing the passivation layer can be relatively low, then the passivation layer can be cured and formed in a layer-by-layer mode, the photosensitive polyimide is arranged layer by layer, the efficiency can be higher than that of the photosensitive polyimide arranged point by point, and the precision can be kept better.
Under the condition that the area of the wafer is smaller, the passivation layer needs to be grown in a high-precision mode at the moment, the passivation layer is prevented from generating adverse effects on other front faces such as a front metal layer, the passivation layer can be deployed in a point-by-point mode at the moment, and the deployment of the passivation layer is completed in a high-precision mode.
The passivation layer can be deployed by adopting the mode of layer-by-layer curing and forming and the mode of point-by-point curing and forming according to actual needs. For example, each layer of ultraviolet projection can be further divided into a plurality of areas, when passivation layers are required to be deployed in all of a certain area, the whole area can be quickly paved by adopting a layer-by-layer curing molding mode aiming at the area, and when areas needing to be avoided such as a front metal layer exist in the certain area, the passivation layers are required to be deployed at a higher progress at the moment, and then the passivation layers can be accurately deployed to positions meeting the design requirements of the passivation layers by adopting a point-by-point curing molding mode.
Therefore, a proper molding mode can be selected based on the area of the wafer, and the molding mode can be used as a target molding mode corresponding to the curing molding of the photosensitive polyimide, so that the passivation layer generation speed is properly improved, and the good progress is kept.
S32, controlling the photosensitive polyimide to be cured and molded under the projection of ultraviolet rays by adopting the target molding mode, and forming a passivation layer meeting the design of the passivation layer.
After the target forming mode is determined, ultraviolet rays can be controlled to be projected onto the surface of the wafer in a corresponding mode, photosensitive polyimide is controlled to be deployed at the ultraviolet ray projection position, and the photosensitive polyimide is cured and formed to form the passivation layer meeting the design of the passivation layer.
In one embodiment of the present invention, the photosensitive polyimide is prepared by:
s41, synthesizing polyamic acid by using dianhydride and diamine to obtain polyamic acid solution;
in specific implementation, polyimide is mainly synthesized from diamine and dianhydride, and compared with a plurality of other heterocyclic polymers, such as monomers of polybenzimidazole, polybenzoxazole, polybenzothiazole, polyquinoxaline, polyquinoline and the like, the polyimide has wide raw material sources and is easy to synthesize. Polyimide can be prepared by low-temperature polycondensation of dianhydride and diamine in a polar solvent such as DMF (dimethylformamide), DMAc (dimethylacetamide), NMP (N-methyl-2-pyrrolidone) or THF (tetrahydrofuran)/methanol to obtain soluble polyamic acid.
S42, performing thermal imidization on the polyamic acid solution in air to obtain a thermosetting polyimide solution;
in specific implementation, the polyamic acid solution is heated to about 300 ℃ for dehydration after film formation or spinning, and is converted into polyimide through thermal imidization into a ring, so as to obtain a thermosetting polyimide solution.
Alternatively, acetic anhydride and a tertiary amine catalyst may be added to the polyamic acid to perform chemical dehydration cyclization, thereby obtaining a polyimide solution or powder. The dianhydride and diamine may also be polycondensed by heating in a high boiling point solvent, such as a phenolic solvent, to give a polyimide in one step. In addition, polyimide can be obtained by reacting dibasic ester of tetrabasic acid with diamine; alternatively, the polyamic acid may be converted to the polyisoimide first and then converted to the polyimide by reheating.
S43, adding resin with photosensitive functional groups into the thermosetting polyimide solution to obtain polyimide resin solution with photo-curing performance.
Thereafter, a resin having a photosensitive functional group may be added to the thermosetting polyimide solution, and the thermosetting polyimide may undergo a crosslinking reaction with the resin having a photosensitive functional group, thereby forming a photo-curable polyimide resin solution.
And S44, removing the solvent in the polyimide resin solution with the photo-curing performance to obtain photosensitive polyimide powder.
Thereafter, the solvent in the polyimide resin solution with photo-curing property can be removed by evaporating the solvent, adding an anti-solvent, etc., to obtain a polyimide resin with photo-curing property in the polyimide resin solution with photo-curing property, and dispersing the polyimide resin with photo-curing property, thereby obtaining the photosensitive polyimide powder.
Alternatively, the resin with photosensitive functional groups comprises epoxy acrylate with unsaturated double bond or epoxy functional groups, and the functional groups can have sensitivity and response capability to light, so that polyimide crosslinked with the unsaturated double bond or epoxy functional groups of the epoxy acrylate can generate photosensitivity, and the polyimide can be applied to the generation of passivation layers.
In one embodiment of the present invention, the wafer provided with the front metal layer is prepared by the following method:
s51, forming a first groove surface on the surface of the first wafer by etching deposited metal tungsten;
in particular, tungsten has a high melting point, high density and good electromigration properties, and is therefore commonly used in microelectronic devices to fabricate electrodes, wires and contact materials. By depositing metal tungsten on the wafer surface, a metal layer with good conductivity can be formed, and the shape and size of the groove face can be precisely controlled. Meanwhile, the interface layer can be formed, so that the adhesiveness and compatibility between the wafer and other materials are improved. Meanwhile, the substrate can be protected to a certain extent in the etching process, and the substrate is prevented from being further damaged. Therefore, the first groove surface can be formed on the surface of the first wafer through depositing metal tungsten for etching, so that the front metal layer can be further deployed later, and the firmness is improved.
And S52, forming a wafer provided with a front metal layer on the first groove surface by depositing aluminum.
Specifically, aluminum can be deposited on the surface on which the metal tungsten has been deposited, and the aluminum can be used as a wire on the surface of the wafer, and can be more firmly arranged on the surface of the wafer through the metal tungsten, so that a front metal layer is formed, and the wafer provided with the front metal layer is obtained.
Optionally, the first wafer is prepared by the following method:
s53, forming a hard mask on the front surface of the second wafer;
in particular implementations, a hard mask may be first formed on the front surface of the second wafer before etching the wafer surface to protect other functional layers previously formed on the wafer surface. The hard mask may be silicon nitride, silicon oxide, etc., as the present invention is not limited in this regard.
S54, etching to form a groove and performing gate oxidation treatment;
in the embodiment of the invention, in order to keep the concentration of carriers uniformly distributed, the on-state loss is reduced without influencing the tail current and the turn-off loss, and the trench gate structure can be arranged in the wafer. The main difference from the normal planar gate structure is that when the IGBT is on, the inversion channel of the P-type emitter is vertical rather than lateral, which means that there is no JFET (Junction Field Effect Transistor ) effect. The conductivity modulation efficiency near the emitter region is high due to the injection of a large number of electrons.
Thus, the front surface of the second wafer may be first etched to form a trench, and thereafter gate oxidation may be performed to form an insulating layer, isolating the gate line and the substrate.
S55, depositing polysilicon on the surface of the groove to form a groove gate;
thereafter, after the gate oxidation process is completed, a trench gate may be formed by depositing polysilicon on the trench surface. Polysilicon has good conductivity and can be used as electrodes, wires, interconnection structures and the like. By depositing polysilicon on the trench surface, a layer of material with good conductivity properties can be formed for connection and signal transmission of electronic devices.
S56, injecting first ions to form a P well, and injecting second ions to form an N+ region;
specifically, the first ions can be implanted at corresponding positions to form P-wells according to chip design requirements. By forming a P-well. The first ion may be a P-type dopant such as boron.
Specifically, a P-type region can be formed on an N-type substrate by forming a P-well to achieve electrical isolation between N-type and P-type transistors. And simultaneously, the electric field distribution of the transistor can be adjusted, so that the performance and the reliability of the transistor are improved. The PN junction capacitor can reduce the capacitance effect of the PN junction and improve the switching speed and noise resistance of the transistor.
Thereafter, a second ion may be further implanted over the P-well to form an n+ region. The second ion may be an N-type dopant such as phosphorus or the like. The n+ region is typically used to form source, drain, and contact electrode regions to provide a low resistance current path.
S57, depositing undoped silicon glass and borophosphosilicate glass to form a dielectric layer;
thereafter, undoped silicate glass and borophosphosilicate glass may be further deposited to form a dielectric layer. The main function of the dielectric layer is to isolate the charge between the gate and the main pole, preventing current from flowing directly. By providing electrical isolation, the control of the IGBT is realized by ensuring that the gate signal does not directly affect the main pole. In the embodiment of the invention, undoped silicate glass (NSG) and borophosphosilicate glass (BPSG) can be adopted as the dielectric layer, and in particular, the deposition of the undoped silicate glass and the borophosphosilicate glass can be realized by Chemical Vapor Deposition (CVD) or physical vapor deposition (PECVD) and other technologies.
S58, opening holes among the grooves to obtain a third wafer;
in the embodiment of the invention, in order to enhance the electric field control and reduce the charge accumulation effect, holes can be formed between the grooves to provide more channels, so that the charges can flow more easily and the charge accumulation is reduced. Wherein, at least one hole penetrating undoped silicon glass and borophosphosilicate glass can be opened when the hole is opened, and the third wafer is obtained.
And S59, depositing a Ti/TiN layer on the front surface of the third wafer to obtain the first wafer.
In a specific implementation, a Ti/TiN layer may be further deposited on the front surface of the third wafer, so as to further improve the hardness of the wafer surface, and obtain the first wafer.
In one embodiment of the present invention, the second wafer is prepared by the following method:
s61, oxidizing a preset N-type substrate to form a silicon oxide layer;
first, a preset N-type substrate may be oxidized to form a silicon oxide layer. The silicon oxide layer may provide electrical isolation, isolating the N-type substrate from other electrodes or layers, preventing unintended flow of current.
S62, etching the surface of the silicon oxide layer, and injecting boron ions into the etching area to form a p+ area;
thereafter, etching may be performed on the surface of the silicon oxide layer, and boron ions may be implanted into the etched region to form a p+ region, so as to form an electrical conduction channel.
And S63, etching to form an active region and a field oxide region, thereby obtaining a second wafer.
Thereafter, an etching process may be further performed to form an active region and a field oxide region. The active region is an active region in the transistor for controlling the flow of current. By forming the active region by etching, the channel length and width of the transistor can be defined, thereby controlling the flow characteristics of the current. The field oxide region is an insulating layer in the transistor that serves to isolate the gate from the active region. It can prevent current leakage between the gate and the active region and provide electric field control.
Optionally, the method further comprises:
s71, thinning the thickness of the wafer through a grinding process on the back of the wafer provided with the front metal layer;
firstly, the thickness of the wafer can be thinned through a grinding process according to the thickness requirement of the wafer to be actually formed, so that the wafer can subsequently meet the process requirement.
S72, third ions are injected into the back surface of the wafer provided with the front metal layer to form a P+ region, and laser annealing treatment is carried out;
thereafter, a third ion, which may be a P-type dopant such as boron, may be implanted into the back side of the wafer provided with the front side metal layer to form a p+ region. And then, rapidly repairing damage to the wafer caused by the implanted ions through laser annealing treatment.
And S73, depositing a back metal layer on the back of the wafer provided with the front metal layer.
Thereafter, a backside metal layer may be deposited on the backside of the wafer provided with the front side metal layer to form a backside electrode.
The embodiment of the invention also provides an insulated gate bipolar transistor wafer, and the passivation layer of the insulated gate bipolar transistor wafer is prepared by adopting the method disclosed by the embodiment of the invention, and is not described herein again.
Through adopting the projection ultraviolet ray, print photosensitive polyimide to the wafer surface projects there is ultraviolet ray department, photosensitive polyimide solidifies the shaping under the ultraviolet ray projection, forms the passivation layer that satisfies the passivation layer design, can be according to the required position of chip design requirement ground on wafer surface and dispose the passivation layer accurately, and thickness is controllable for the passivation layer degree of consistency of preparation is high, and can save the etching procedure, avoids the possible harmful effects that brings of etching procedure to wafer surface.
Referring to fig. 2, a process for fabricating an insulated gate bipolar transistor wafer according to an embodiment of the invention is shown, and the process specifically includes the following steps:
the first step: substrate oxidation (INT Oxide) on N-type silicon substrate surface by high temperature thermal diffusion process
The preset N-type substrate may be oxidized to form a silicon oxide layer. The silicon oxide layer may provide electrical isolation, isolating the N-type substrate from other electrodes or layers, preventing unintended flow of current.
And a second step of: and (3) coating Photoresist (PR) on the surface of the oxidized substrate, performing exposure, development and etching through an annular mask, and injecting high-dose boron into the etched area of the oxide layer to form a P+ area so as to form an electrified channel.
And a third step of: etching to form field oxide and Active region (Active Area)
An etching process may be further performed to form the active region and the field oxide region. The active region is an active region in the transistor for controlling the flow of current. By forming the active region by etching, the channel length and width of the transistor can be defined, thereby controlling the flow characteristics of the current. The field oxide region is an insulating layer in the transistor that serves to isolate the gate from the active region. It can prevent current leakage between the gate and the active region and provide electric field control.
Fourth step: hard mask (Hardmask) deposition
Before etching the wafer surface, a hard mask may be first formed on the front surface of the second wafer in order to protect other functional layers previously formed on the wafer surface. The hard mask may be silicon nitride, silicon oxide, etc., as the present invention is not limited in this regard.
Fourth step: trench silicon etch and Gate oxide
In order to maintain a uniform carrier concentration distribution, the on-state loss is reduced without affecting the tail current and the off-loss, a trench gate structure may be deployed in the wafer. The main difference from the normal planar gate structure is that when the IGBT is on, the inversion channel of the P-type emitter is vertical rather than lateral, which means that there is no JFET effect. The conductivity modulation efficiency near the emitter region is high due to the injection of a large number of electrons. Thus, the front surface of the second wafer may be first etched to form a trench, and thereafter gate oxidation may be performed to form an insulating layer, isolating the gate line and the substrate.
Fifth step: polysilicon (poly) deposition to form trench gates (gate poly) and etching
After the gate oxidation process is completed, the trench gate may be formed by depositing polysilicon on the trench surface. Polysilicon has good conductivity and can be used as electrodes, wires, interconnection structures and the like. By depositing polysilicon on the trench surface, a layer of material with good conductivity properties can be formed for connection and signal transmission of electronic devices.
Sixth step: p-well (P-well) implant and N+ implant
And injecting first ions at corresponding positions according to the chip design requirement to form a P well. By forming a P-well. The first ion may be a P-type dopant such as boron. By forming the P-well, a P-type region can be formed on the N-type substrate to achieve electrical isolation between the N-type and P-type transistors. Thereafter, a second ion may be further implanted over the P-well to form an n+ region. The second ion may be an N-type dopant such as phosphorus or the like. The n+ region is typically used to form source, drain, and contact electrode regions to provide a low resistance current path.
Seventh step: undoped silicate glass (NSG) and borophosphosilicate glass (BPSG) are deposited to form a dielectric layer (ILD)
Undoped silicate glass and borophosphosilicate glass are further deposited to form a dielectric layer. The main function of the dielectric layer is to isolate the charge between the gate and the main pole, preventing current from flowing directly. By providing electrical isolation, the control of the IGBT is realized by ensuring that the gate signal does not directly affect the main pole. In the embodiment of the invention, undoped silicon glass (NSG) and borophosphosilicate glass (BPSG) can be used as the dielectric layer.
Eighth step: hole (Contact) etching to open a hole through undoped silicate glass (NSG) and borophosphosilicate glass (BPSG) between two trenches
To enhance electric field control and reduce charge accumulation effects, openings may be provided between trenches to provide more channels for easier charge flow and reduced charge accumulation. Wherein, at least one hole penetrating undoped silicon glass and borophosphosilicate glass can be opened when the hole is opened, and the third wafer is obtained.
Ninth step: ti/TiN layer deposition and rapid annealing
A Ti/TiN layer may be further deposited on the front surface of the third wafer to further increase the hardness of the wafer surface.
Tenth step: metal deposition, first metal tungsten W deposition etching, then front metal AL deposition
And forming a first groove surface on the surface of the first wafer by depositing metal tungsten for etching so as to further deploy a front metal layer and improve the firmness. Thereafter, aluminum may be deposited on the surface on which the metal tungsten has been deposited, and the aluminum may be used as a wire on the wafer surface, which may be more firmly disposed on the wafer surface by the metal tungsten, thereby forming a front metal layer, resulting in a wafer provided with the front metal layer.
Eleventh step: and growing a passivation layer, firstly depositing a layer of SiN on the surface of the metal aluminum layer by adopting a sputtering process, then controlling ultraviolet light controlled by a computer through software to form projection or movable laser points, carrying out point-by-point or layer-by-layer curing and forming on photosensitive polyimide according to the chip design requirement, and finally forming the passivation layer with the required thickness.
Twelfth step: thinning the back surface, turning the wafer after the front surface process is normally finished, and thinning the thickness of the wafer through a grinding process
The thickness of the wafer can be thinned through a grinding process according to the thickness requirement of the wafer to be actually formed, so that the wafer can subsequently meet the process requirement.
Thirteenth step: backside p+ implant and laser annealing
A third ion, which may be a P-type dopant such as boron, may be implanted into the back side of the wafer provided with the front side metal layer to form a p+ region. And then, rapidly repairing damage to the wafer caused by the implanted ions through laser annealing treatment.
Fourteenth step: backside metal deposition
A backside metal layer may be deposited on the backside of the wafer provided with the front side metal layer to form a backside electrode.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims (10)
1. A method of growing a passivation layer, the method comprising:
projecting ultraviolet rays on the surface of the wafer provided with the front metal layer based on the passivation layer design;
printing photosensitive polyimide to the position on the surface of the wafer, where ultraviolet rays are projected;
the photosensitive polyimide is solidified and molded under the projection of ultraviolet rays, so that a passivation layer meeting the design of the passivation layer is formed.
2. The method of claim 1, wherein the step of projecting ultraviolet light on the surface of the wafer provided with the front side metal layer based on the passivation layer design comprises:
projecting ultraviolet rays layer by layer and/or point by point on the surface of the wafer provided with the front metal layer based on the passivation layer design;
the photosensitive polyimide is solidified and molded under the projection of ultraviolet rays, and a passivation layer meeting the design of the passivation layer is formed, and the method comprises the following steps:
the photosensitive polyimide is cured and formed layer by layer and/or point by point under ultraviolet projection to form a passivation layer meeting the design of the passivation layer.
3. The method of claim 2, wherein the photosensitive polyimide is cured layer by layer and/or point by point under uv projection to form a passivation layer that meets the passivation layer design, comprising:
determining a target forming mode corresponding to the photosensitive polyimide curing forming as layer-by-layer and/or point-by-point curing forming based on the area of the wafer;
and controlling the photosensitive polyimide to be cured and molded under the projection of ultraviolet rays by adopting the target molding mode to form passivation meeting the design of a passivation layer.
4. The method of claim 1, wherein the photosensitive polyimide is prepared by:
synthesizing polyamide acid by using dianhydride and diamine to obtain polyamide acid solution;
performing thermal imidization on the polyamic acid solution in air to obtain a thermosetting polyimide solution;
adding resin with photosensitive functional groups into the thermosetting polyimide solution to obtain a polyimide resin solution with photocuring performance;
and removing the solvent in the polyimide resin solution with the photo-curing performance to obtain photosensitive polyimide powder.
5. A method according to claim 3, wherein the resin having photosensitive functional groups comprises an epoxy acrylate having unsaturated double bonds or epoxy functional groups.
6. The method of claim 1, wherein the wafer provided with the front side metal layer is prepared by:
forming a first groove surface on the surface of a first wafer by depositing metal tungsten and etching;
and forming a wafer provided with a front metal layer on the first groove surface by depositing aluminum.
7. The method of claim 6, wherein the first wafer is prepared by:
forming a hard mask on the front surface of the second wafer;
etching to form a groove and carrying out gate oxidation treatment;
depositing polysilicon on the surface of the groove to form a groove gate;
injecting first ions to form a P well, and injecting second ions to form an N+ region;
depositing undoped silicon glass and boron phosphorus silicon glass to form a dielectric layer;
opening holes among the grooves to obtain a third wafer;
and depositing a Ti/TiN layer on the front surface of the third wafer to obtain a first wafer.
8. The method of claim 1, wherein the second wafer is prepared by:
oxidizing a preset N-type substrate to form a silicon oxide layer;
etching the surface of the silicon oxide layer, and injecting boron ions into the etching area to form a p+ area;
and etching to form an active region and a field oxide region to obtain a second wafer.
9. The method according to claim 1, wherein the method further comprises:
thinning the thickness of the wafer through a grinding process on the back of the wafer provided with the front metal layer;
injecting third ions into the back of the wafer provided with the front metal layer to form a P+ region, and carrying out laser annealing treatment;
and depositing a back metal layer on the back of the wafer provided with the front metal layer.
10. An insulated gate bipolar transistor wafer, wherein a passivation layer of the insulated gate bipolar transistor wafer is prepared by the method of any one of claims 1-9.
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