CN117668319B

CN117668319B - Data query method, electronic device and storage medium

Info

Publication number: CN117668319B
Application number: CN202410142128.5A
Authority: CN
Inventors: 张强
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2024-02-01
Filing date: 2024-02-01
Publication date: 2024-06-18
Anticipated expiration: 2044-02-01
Also published as: CN117668319A

Abstract

The application provides a data query method, electronic equipment and a storage medium, and relates to the technical field of terminals, wherein when the electronic equipment executes a first task, if the electronic equipment does not query first data required by the first task from a first memory, the electronic equipment queries whether the first memory is cached with L2P table information from a logical address to a physical address of the first data; if the electronic equipment inquires the L2P table information of the first data from the first memory, the electronic equipment acquires the first data from the second memory based on the L2P table information of the first data; the first memory comprises a first memory area and a second memory area, wherein the first memory area is used for storing L2P table information of preset high-frequency data, and the second memory area is used for storing L2P table information of data required by executing tasks with different priorities. The L2P table information of different data is stored in the partition, so that the cache hit rate of the first memory can be improved, and the data query speed can be improved.

Description

Data query method, electronic device and storage medium

Technical Field

The present application relates to the field of terminal technologies, and in particular, to a data query method, an electronic device, and a storage medium.

Background

With the development of electronic devices, functions supported by the electronic devices are becoming more and more abundant. In the process of using the electronic device by the user, the electronic device may simultaneously run a plurality of applications, including a foreground application and a background application. When an electronic device executes a task or process of a foreground application or a background application, data needs to be acquired from a storage device, and if the data is not acquired timely, the data may be perceived by a user, so that the experience of the user using the electronic device is affected.

Therefore, how to increase the data query speed of the electronic device is a problem to be solved.

Disclosure of Invention

The embodiment of the application provides a data query method, electronic equipment and a storage medium, which can improve the data query speed of the electronic equipment.

In a first aspect, an embodiment of the present application provides a data query method, applied to an electronic device, where the electronic device includes a first memory and a second memory, the first memory is an internal memory of the electronic device, and the second memory is an external memory of the electronic device, and the method includes: when the electronic equipment executes the first task, if the electronic equipment does not inquire the first data from the first memory, the electronic equipment inquires whether the first memory caches the L2P table information from the logical address to the physical address of the first data, wherein the L2P table information of the first data is used for indicating the physical address of the first data in the second memory; if the electronic equipment inquires the L2P table information of the first data from the first memory, the electronic equipment acquires the first data from the second memory based on the L2P table information of the first data; the first memory comprises a first memory area and a second memory area, wherein the first memory area is used for storing L2P table information of preset high-frequency data, the second memory area is used for storing L2P table information of data required by executing tasks with different priorities, and the first data are data required by executing the first task.

The first memory may be a host memory shown in fig. 5, the second memory may be a universal flash UFS storage device shown in fig. 5, the first task may be a task a shown in fig. 9, the first task may be a VIP task (important task) or a non-VIP task (non-important task), and the L2P table information of the first data includes a mapping table from a logical address to a physical address of the first data. The first storage area may be a static area of the HPB memory shown in fig. 5, and the second storage area may be a dynamic area of the HPB memory shown in fig. 5, and illustratively, the second storage area stores L2P table information of data required for VIP tasks and L2P table information of data required for non-VIP tasks.

In the method, the first storage area and the second storage area are divided in the first memory of the electronic device, different areas are used for storing L2P table information of different data, the first storage area stores L2P table information of some high-frequency data, the second storage area stores L2P table information of data required by tasks with different priorities, partition management is carried out on the L2P table information of different data in a partition storage mode, fairness of resource partition is guaranteed, and cache hit rate of the first memory can be improved to a certain extent. Therefore, when the electronic device executes the first task, the L2P table information of the first data of the first task can be acquired from the first memory with high probability, the first data can be acquired from the second memory based on the L2P table information of the first data, the data query speed can be improved, and the io performance of the device can be improved.

In an alternative embodiment of the first aspect, the electronic device includes a first processing module and a second processing module, the first processing module being responsible for managing and controlling the first memory, the second processing module being responsible for managing and controlling the second memory; the electronic device querying whether the first memory caches the L2P table information of the first data, including: the first processing module inquires whether the first memory caches L2P table information of the first data; if the electronic device queries the L2P table information of the first data from the first memory, the electronic device obtains the first data from the second memory based on the L2P table information of the first data, including: if the first processing module inquires L2P table information of the first data from the first memory; the first processing module sends a first query request to the second processing module, wherein the first query request comprises L2P table information of first data; the second processing module obtains the first data from the first storage space of the second memory based on the L2P table information of the first data, and sends a first query response to the first processing module, the first query response including the first data.

The first processing module may be the CPU1 shown in fig. 5, the second processing module may be the CPU2 shown in fig. 5, the first query request may be the io request 1 shown in fig. 9, and the first query response may be the io response 1 shown in fig. 9. The first storage space of the second memory may be a storage space of the NAND flash memory shown in fig. 5.

The method shows an interaction flow of an internal module when the electronic device queries the first data, after the first processing module obtains the L2P table information of the first data from the first memory, the first processing module needs to issue a query request to the second processing module of the second memory, the second processing module obtains the first data from the first storage space of the second memory based on the L2P table information, and returns the first data to the first processing module so that the first processing module executes the first task. The L2P table information of the first data is not required to be queried by the second processing module in the process, so that the data query time is shortened, and the data query speed is improved.

In an optional embodiment of the first aspect, the first processing module queries the first memory for L2P table information of the first data, including: the first processing module queries L2P table information of the first data from a first storage area of the first memory or queries L2P table information of the first data from a second storage area of the first memory.

For example, if the first data is high frequency data, the L2P table information of the first data is stored in the first storage area of the first memory. If the first data is frequently accessed VIP task or non-VIP task data (data other than high frequency data), the L2P table information of the first data is stored in the second storage area of the first memory.

In the method, if the first data is high-frequency data or frequently accessed data of the VIP task or the non-VIP task, the electronic equipment can directly hit the L2P table information of the first data in the first memory, further can acquire the physical address of the first data in the second memory according to the L2P table information of the first data, and can quickly acquire the first data according to the physical address, so that the data query speed is improved.

In an optional embodiment of the first aspect, if the first processing module does not query the L2P table information of the first data from the first memory, the first processing module sends a second query request to the second processing module, where the second query request includes an identifier of the first data; the second processing module obtains L2P table information of the first data from a first storage space of the second memory based on the identification of the first data; the second processing module acquires the first data from the first storage space based on the L2P table information of the first data; the second processing module sends a second query response to the first processing module, the second query response including the first data and the L2P table information for the first data.

The second query request may be the io request 2 shown in fig. 9, the identification of the first data may be an inode of the first data, and the second query response may be the io response 2 shown in fig. 9.

In the above method, if the first data is not high-frequency data or frequently accessed VIP task or non-VIP task data, the electronic device cannot acquire the L2P table information of the first data from the first memory, the electronic device needs to acquire the L2P table information of the first data from the first memory space of the second memory first, and then acquire the first data from the first memory space of the second memory based on the L2P table information of the first data, that is, the electronic device needs to access the first memory space twice to acquire the first data and the L2P table information of the first data.

In an alternative embodiment of the first aspect, the first processing module stores the L2P table information of the first data to the second storage area of the first memory in response to receiving the second query response.

In the above method, after the first processing module of the electronic device obtains the first data and the L2P table information of the first data, the L2P table information of the first data may be stored in the second storage area of the first memory, so as to be used in a subsequent query.

In an optional embodiment of the first aspect, the second storage area of the first memory includes an L2P linked list of first priority tasks and an L2P linked list of second priority tasks, the first priority being higher than the second priority; the first processing module stores L2P table information of the first data to a second storage area of the first memory, including: if the first task is a first priority task, the first processing module adds the L2P table information of the first data to an L2P linked list of the first priority task; or if the first task is a second priority task, the first processing module adds the L2P table information of the first data to an L2P linked list of the second priority task.

In an alternative embodiment, a first processing module of the electronic device obtains a task tag of a first task, and determines whether the first task is a VIP task or a non-VIP task.

The L2P linked list of the first priority task includes L2P table information of data required by the first priority task, for example, the L2P linked list of the first priority task is the L2P linked list of the VIP task shown in fig. 7. The L2P linked list of second priority tasks includes L2P table information for the tasks required for the second priority, e.g., the L2P linked list of second priority tasks may be an L2P linked list of non-VIP tasks.

According to the method, the electronic device can add the L2P table information of the first data required by executing the first task to the L2P linked list of the corresponding task priority according to the priority of the first task, so that partition management of the L2P table information of different data is realized, fairness of resource partition is guaranteed, and the cache hit rate of the first memory can be improved to a certain extent.

In an optional embodiment of the first aspect, if the first task is a first priority task, the first processing module adds L2P table information of the first data to an L2P linked list of the first priority task, including: if the number of the L2P tables of the L2P linked list of the first priority task reaches the preset number, the first processing module eliminates at least one L2P table in the L2P linked list of the first priority task based on the least recently used LRU strategy, and then adds the L2P table information of the first data to the L2P linked list of the first priority task. Or alternatively

If the first task is a second priority task, the first processing module adds the L2P table information of the first data to an L2P linked list of the second priority task, including: if the number of the L2P tables of the L2P linked list of the second priority task reaches the preset number, the first processing module eliminates at least one L2P table in the L2P linked list of the second priority task based on the least recently used LRU strategy, and then adds the L2P table information of the first data to the L2P linked list of the second priority task.

The eliminated L2P table may be an L2P table with expires variables of 0 in the L2P linked list, or an L2P table with the last N expires variables after the expires variables in the L2P linked list are ordered from big to small, for example, N is 1 or 2.

In the above method, when determining that the L2P table information of the first data is added to the L2P linked list of the task with a certain priority, if the number of L2P tables of the L2P linked list has reached a preset number, the electronic device needs to eliminate at least one L2P table that is least recently used from the L2P linked list, thereby releasing a storage space to add the L2P table of the first data that is currently used. The L2P linked list in the first storage area of the first memory is dynamically updated, so that the first memory has higher cache hit rate.

In an alternative embodiment of the first aspect, the method further comprises: after the electronic equipment is started or restarted, the electronic equipment acquires configuration information, wherein the configuration information comprises a file name and an identifier of preset high-frequency data; the electronic equipment acquires L2P table information of the high frequency data from the second memory; the electronic device stores the L2P table information of the high frequency data to a first storage area of the first memory.

According to the method, the electronic equipment acquires the L2P table information of the high-frequency data from the second memory in advance based on the configuration information, and writes the L2P table information of the high-frequency data into the first storage area of the first memory, so that when the task related to the high-frequency data is executed, the electronic equipment can acquire the L2P table information of the high-frequency data from the first memory, and the high-frequency data query speed is improved.

In an optional embodiment of the first aspect, the electronic device further includes a configuration module, and the electronic device obtains configuration information, including: the configuration module acquires a configuration file from an external memory, and acquires configuration information by analyzing the configuration file; the configuration module sends configuration information to a first processing module of the electronic equipment; the electronic device obtains the L2P table information of the high frequency data from the second memory, and the L2P table information comprises: the first processing module sends a third query request to the second processing module of the electronic device, wherein the third query request comprises the identification of the high-frequency data; the second processing module acquires L2P table information of the high frequency data from the first storage space or the second storage space of the second memory based on the identification of the high frequency data; the second processing module sends a third query response to the first processing module, wherein the third query response comprises L2P table information of the high-frequency data; the electronic device stores the L2P table information of the high frequency data to a first storage area of a first memory, including: the first processing module stores the L2P table information of the high frequency data to a first storage area of the first memory.

The method shows the interaction flow of the internal module when the electronic equipment initializes the first storage area of the first memory, and the L2P table information of the high-frequency data is written into the first storage area of the first memory through the information interaction of the first processing module and the second processing module.

In an alternative embodiment of the first aspect, the method further comprises: the electronic equipment acquires update configuration information, wherein the update configuration information comprises a file name and an identifier of newly added high-frequency data; the electronic equipment acquires the newly added L2P table information of the high frequency data from the second memory; the electronic device stores the L2P table information of the newly added high frequency data to the first storage area of the first memory.

In the above method, considering the expansion of the performance of the electronic device, the data of the task related to the expansion function may be high frequency data, and then the L2P table information of the high frequency data needs to be updated to the first storage space of the first memory, so as to optimize the L2P table information of the first storage space of the first memory of the electronic device, so that when the task related to the high frequency data is executed, the electronic device can obtain the L2P table information of the high frequency data from the first memory, thereby improving the query speed of the high frequency data.

In a second aspect, an embodiment of the present application provides an electronic device, including: one or more processors and memory; the memory is coupled to one or more processors, the memory for storing computer program code, the computer program code comprising computer instructions, the one or more processors invoking the computer instructions to cause the electronic device to perform the method as in any of the first aspects.

In a third aspect, an embodiment of the present application provides a chip system, where the chip system is applied to an electronic device, and the chip system includes one or more processors, where the one or more processors are configured to invoke computer instructions to cause the electronic device to perform the method according to any of the first aspects.

In a fourth aspect, embodiments of the present application provide a computer-readable storage medium comprising computer instructions that, when run on an electronic device, cause the electronic device to perform the method of any one of the first aspects.

In a fifth aspect, embodiments of the present application provide a computer program product comprising computer program code which, when run on an electronic device, causes the electronic device to perform the method according to any of the first aspects.

It should be understood that the second to fifth aspects of the present application correspond to the technical solutions of the first aspect of the present application, and the advantages obtained by each aspect and the corresponding optional embodiments are similar, and are not repeated.

Drawings

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

FIG. 2 is a flowchart illustrating a data query method according to an embodiment of the present application;

FIG. 3 is a second flowchart of a data query method according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an LRU algorithm according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of an electronic device according to a second embodiment of the present application;

FIG. 6 is a schematic diagram illustrating an initialization process of a static region in HPB memory according to an embodiment of the application;

FIG. 7 is a schematic diagram of an L2P linked list of a dynamic region of an HPB memory according to an embodiment of the application;

FIG. 8 is a schematic diagram illustrating a process flow of an HPB L2P management module in a host system according to an embodiment of the application;

FIG. 9 is a third flowchart of a data query method according to an embodiment of the present application;

FIG. 10 is a flowchart of a data query method according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The io (input/output) performance of an electronic device refers to the performance of the electronic device in terms of reading and writing, transmitting, and executing programs. Improving the io performance of the electronic equipment has important significance in the aspects of improving user experience, enhancing multi-task processing capacity, improving system performance, prolonging the service life of the electronic equipment and the like.

The technical scheme provided by the embodiment of the application is mainly used for improving the io performance of the electronic equipment.

In order to facilitate understanding of the solution, the structure of the electronic device according to the embodiment of the present application will be first described below.

The software system of the electronic device may employ a layered architecture, an event driven architecture, a microkernel architecture, a microservice architecture, or a cloud architecture. In the embodiment of the application, a software system with a layered architecture is taken as an android system as an example, and the structure of the electronic equipment is illustrated by an example.

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application. The layered architecture divides the software system of the electronic device into several layers, each of which has a distinct role and division of labor. The layers communicate with each other through a software interface. As shown in fig. 1, the electronic device includes an application layer, an application framework layer, a kernel layer, and a hardware layer.

The application layer may include applications such as cameras, calendars, conversations, maps, navigation, bluetooth, music, and the like.

The application framework layer may provide an application programming interface (application programming interface, API) and programming framework for application programs of the application layer.

The kernel layer is a layer between hardware and software, and in the embodiment of the present application, the kernel layer includes a host system including a central processing unit (Central Processing Unit, CPU) (such as CPU1 in fig. 1), a host memory (host memory), and a host control interface (host controller interface). The CPU1 can access the USF storage device of the hardware layer through the host control interface. The host memory may cache portions of data, which may also be referred to as host memory or main memory.

When the electronic device executes a certain process or a certain task in the process, a host system of the electronic device has a requirement for reading data, and if the host system does not acquire the data from the host memory, the host system needs to send an io request to the USF storage device to trigger the USF storage device to acquire the data. The above procedure can be regarded as an io operation performed by the electronic device, which is generally referred to as an operation inside the electronic device, not a user-triggered operation.

For example, when the electronic device executes the process of starting the application a, the process includes obtaining the starting animation data of the application a, and if the starting animation data of the application a is not cached in the host memory of the host system, the host system sends an io request to the USF storage device to trigger the USF storage device to obtain the starting animation data of the application a.

In an embodiment of the application, the hardware layer comprises a universal flash (Universal Flash Storage, USF) storage device, which comprises a storage device controller (storage device controller) and NAND flash. The memory device controller includes a CPU (such as CPU2 in fig. 1), a static random access memory (Static Random Access Memory, SRAM), and a NAND controller. NAND flash memory is a type of nonvolatile memory.

The CPU2 may be regarded as a main processor in the USF storage device and is mainly responsible for processing io requests sent by an upper layer of the electronic device (e.g. an application layer, an application framework layer or a kernel layer), and resolving logical addresses of data in the io requests.

The SRAM in the storage device controller can be considered as the memory of the USF storage device, where the L2P (Logical to Physical) table of data is stored. The L2P table is a mapping table with a logical address as an index and a physical address as a content, and is used for mapping from the logical address to the physical address, i.e. converting the logical address into the physical address. Logical addresses refer to virtual addresses generated by an operating system or application program for accessing data in a memory or storage device. The physical address refers to a physical location where data is actually stored.

After resolving the logical address of the data in the io request, the CPU2 may obtain the physical address of the data in the storage medium NAND by querying the L2P table corresponding to the data in the SRAM.

Due to cost limitation, the SRAM in the UFS storage device usually has only a few megabits, and cannot store the address mapping table of the entire NAND, that is, the L2P table stored in the SRAM is not complete, so that a situation that the L2P table cannot hit may occur. At this time, the UFS storage device needs to make an additional query to the NAND to obtain the L2P table corresponding to the data. See fig. 2 for a specific process.

Fig. 2 is a flowchart illustrating a data query method according to an embodiment of the present application. As shown in fig. 2, when the host system of the electronic device performs a certain process or a certain task in the process, the process of acquiring data may include:

S0, the CPU1 of the host system accesses the host memory.

If the host memory does not query the data, the method can be performed:

S1. CPU1 sends an io request to CPU2 of the USF storage device. Illustratively, CPU1 sends an io request to CPU2 via the host control interface.

S2, in response to receiving the io request, the CPU2 accesses the SRAM and queries an L2P table corresponding to the data.

If the CPU2 does not query the L2P table corresponding to the data in the SRAM, it may execute:

s3, the CPU2 accesses NAND through the NAND controller and inquires an L2P table corresponding to the data.

S4, after the CPU2 inquires the L2P table corresponding to the data, the L2P table corresponding to the data is stored in the SRAM.

S5, the CPU2 accesses NAND through the NAND controller to acquire data.

Based on the L2P table corresponding to the data in the SRAM, the CPU2 acquires the physical address of the data in the NAND, accesses the NAND through the NAND controller, and acquires the data from the physical address.

S6, the CPU2 sends an io response to the CPU1, wherein the io response can comprise data and an L2P table corresponding to the data.

After the CPU1 receives the L2P table corresponding to the data, the L2P table corresponding to the data may be stored in the host memory.

In this embodiment, both the host memory of the host system and the SRAM of the USF miss the L2P table, requiring the CPU2 of the USF to make an additional query to the NAND to obtain the L2P table. After the L2P table is obtained, the obtained L2P table can be respectively stored into a host memory of a host system and an SRAM of a USF, so that a basis is provided for subsequent inquiry.

In some embodiments, if the CPU2 queries the SRAM for the L2P table corresponding to the data, S5 and S6 are performed.

In this embodiment, the host memory of the host system misses the L2P table, but the USF memory hits the L2P table, the CPU2 of the USF retrieves data from the NAND via the NAND controller based on the L2P table, and returns the data to the host system.

Based on the above embodiment, in the process of querying a process or task data, the following delays mainly relate to:

(1) The host memory of the host system experiences a page fault (page fault) to the time delay of generating the io request.

This delay is the delay of S0. Page faults refer to events that occur when a host system fails to query the host memory for desired data or a file page corresponding to the data, also referred to as page fault events.

(2) And the host system sends the delay of the io request to the USF storage device. The time delay is S1

(3) The USF memory device incorporates a delay in the access of the CPU2 to the SRAM. The time delay is S2

(4) When the built-in CPU2 of the USF storage device does not query the L2P table (i.e., the L2P cache miss of the UFS storage device) through the SRAM, the NAND-generated latency is accessed. This delay is the delay of S3.

(5) And a delay in which the USF storage device built-in CPU2 accesses the data stored in the NAND and returns the data to the host system. This delay is the delay of S5 and S6.

Of the above delays, (4) and (5) take the longest time, i.e., the maximum delay is mainly the delay of accessing the NAND, including the delay of accessing the NAND to query the corresponding L2P table of data, and the delay of accessing the NAND to acquire data.

The HPB (Host Performance Booster) scheme is a scheme for optimizing the io performance of the electronic device, and the main idea is to divide a part of memory in a host memory of a host system (for example, the size of the host memory of a mobile phone is usually several GB to several tens GB), usually several tens to several tens megabytes, for example, divide 64M memory for an HPB scheme, and store part of L2P table information in a USF storage device, which is equivalent to increasing the SRAM storage space of the USF. Thus, when the host memory does not store data, the CPU1 may preferentially query the L2P table information corresponding to the data from the host memory to acquire the physical address of the data. Typically, the size of the L2P table information corresponding to data (also referred to as a file) is about 1/1000 of the size of the data itself.

In one example, if the L2P table corresponding to the data is hit in main memory, a significant portion of the latency, such as the latency of accessing NAND to query the L2P table corresponding to the data, can be saved, thereby improving the io performance of the device. In another example, if the L2P table corresponding to the data is not hit in the host memory, CPU1 sends an io request to the USF storage device.

Fig. 3 is a flowchart of a data query method according to an embodiment of the present application. Based on the embodiment of fig. 2, as shown in fig. 3, before executing S1, the method further includes:

S7, the CPU1 of the host system accesses the host memory and inquires the L2P table corresponding to the data.

When the CPU1 of the host system does not query the host memory for data, the CPU1 further queries the host memory for an L2P table corresponding to the data.

In some embodiments, if the CPU1 queries the L2P table corresponding to the data in the host memory, it may execute:

s8. The CPU1 accesses the NAND through the CPU2 and the NAND controller to acquire data.

CPU1 sends a query request 1 to CPU2, wherein the query request 1 comprises an L2P table corresponding to data. After receiving the inquiry request, the CPU2 does not need to inquire the SRAM, and obtains the physical address of the data in the NAND from the L2P table corresponding to the data. The CPU2 issues a query request 2 to the NAND controller, the query request 2 including a physical address of the data in the NAND, and the NAND controller acquires the data based on the physical address. The NAND controller returns the queried data to the CPU1 through the CPU 2.

In the embodiment, the HPB scheme is adopted, the host memory directly hits the L2P table, and the host system acquires data from the NAND based on the L2P table, so that the response speed of the electronic equipment is improved.

In some embodiments, if the CPU1 does not query the L2P table corresponding to the data in the host memory, S1 to S6 may be executed.

In this embodiment, the host memory does not hit the L2P table, and the host system initiates an io request to the USF storage device to obtain the data and the L2P table corresponding to the data.

Typically, the NAND storage medium is divided into different regions (regions), each region corresponding to a L2P table. For example, the NAND storage medium includes an area 1 and an area 2, the L2P table corresponding to the area 1 is used for storing the mapping relationship between the logical address and the physical address of the data in the area 1, and the L2P table corresponding to the area 2 is used for storing the mapping relationship between the logical address and the physical address of the data in the area 2.

The HPB scheme described above, the host memory employs a least recently Used (LEAST RECENTLY LRU) policy to cache L2P table information. Exemplary, FIG. 4 is a schematic diagram of an LRU algorithm according to an embodiment of the present application. As shown in fig. 4, at a certain moment, the L2P table information cached in the host memory may be regarded as an L2P linked list, where the L2P linked list includes L2P tables of a plurality of regions, and each L2P table of a region is configured with a read_timeout_ expires variable (hereinafter referred to as expires variable) for recording the number of times the region has been accessed recently.

In one example, when a new region is accessed, the L2P table corresponding to the region is linked to the L2P linked list, and the expires variable of the L2P table corresponding to the region is initialized to 100, such as L2P table_1 in fig. 4.

In one example, if an area is not accessed every 1s, the expires variable of the L2P table corresponding to the area is reduced by 1, and when the expires variable is reduced to 0, the L2P table corresponding to the area is eliminated from the L2P linked list, such as the L2P table_n in fig. 4.

In one example, if the expires variable of the L2P table corresponding to a region is reduced to 40, and the region is accessed again, the expires variable of the L2P table corresponding to the region is reset to 100, as in fig. 4, the expires variable of the L2P table_n-1 is greater than the expires variable of the L2P table_n-2.

Based on the above examples, the L2P linked list is not a first-in-first-out linked list, and one or more L2P tables are eliminated based on expires variable sizes of the respective L2P tables in the L2P linked list. For example, at a certain moment, if there is an L2P linked list with expires variable being 0 in the linked list, the L2P table (possibly one or more) with expires variable being 0 is eliminated, if there is no L2P linked list with expires variable being 0 in the linked list, expires variables of all L2P tables in the linked list are ordered from big to small, the L2P table corresponding to the last N expires variables is eliminated, N is a positive integer, for example, N is 1 or 2.

Ideally, by adopting the HPB scheme, the host system queries the host memory, and if the L2P table corresponding to the data is hit, the response speed of the query data can be improved. However, it is found through practical tests that the actual hit rate of the HPB scheme L2P table in the host memory is only about ten percent, and the main reason is that the LRU algorithm used by the HPB scheme has the following problems:

firstly, in the using process of the electronic device, the io amount (the number of times of io requests) is usually large, different data or files may be continuously accessed in a short time, and the elimination rate of the L2P table in the L2P linked list is obviously insufficient.

Secondly, for the android system, if there are a large number of background applications io in some scenes, most of the L2P tables stored in the L2P linked list are L2P tables related to the background applications io, and the L2P tables related to the foreground applications io are cached less, which affects the io response speed for the foreground applications. The background application io refers to the related io of the background application, and the background application refers to an application program in background running. The foreground application io refers to an io related to a foreground application, which refers to an application being opened, operated, or currently being displayed by a user.

In view of the above problems, an embodiment of the present application provides an electronic device, which performs region division on a storage region of a host memory of a host system of the electronic device, so that different storage regions store different L2P table information, and optimizes a storage mechanism of an L2P table in the host memory. Furthermore, the HPB L2P management module in the host system of the electronic equipment controls the storage and elimination of the L2P table in the host memory, and the cache hit rate of the host memory is improved, so that the io performance of the electronic equipment is improved.

The improvement of the host system of the electronic device is explained in detail below with reference to fig. 5.

Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application. On the basis of the electronic device shown in fig. 1, as shown in fig. 5, a host system of the electronic device includes an HPB L2P management module and an HPB memory in addition to a CPU1, a host memory and a host control interface.

The HPB L2P management module is responsible for managing L2P table information in HPB memory and controlling the execution of the improved HPB scheme, see below for details. The host memory may cache, in addition to part of the data, L2P table information of a part of the data, where the L2P table information is stored in the HPB memory, i.e., the HPB memory is a medium storing the L2P table.

In some embodiments, the HPB memory may also be referred to as HPB memory, which is part of the host memory described above. Specifically, the HPB memory is divided into two regions, a static region (pinned region) and a dynamic region (dynamic region), respectively.

The static area is used to store L2P table information for high frequency data, and the L2P table of the static area is typically fixed. Illustratively, the static area in fig. 5 stores an L2P table of high frequency data 1 to high frequency data n. Thus, when the host system needs to acquire high-frequency data, the L2P table corresponding to the high-frequency data can be acquired from the static area of the HPB memory so as to acquire the physical address of the high-frequency data in the NAND, and the data query speed can be improved.

The dynamic region is used to store a dynamic L2P linked list, and L2P tables in the L2P linked list may be eliminated, and the L2P linked list of the dynamic region includes two types of L2P linked lists. Exemplary, as shown in fig. 5, the dynamic region includes a first L2P linked list and a second L2P linked list, where the L2P tables in the first L2P linked list are all L2P tables of VIP tasks, and the L2P tables in the second L2P linked list are all L2P tables of non-VIP tasks. The VIP tasks have a higher priority than the non-VIP tasks. The HPB L2P management module is responsible for managing the first L2P linked list and the second L2P linked list so as to improve the hit rate of the L2P table in the HPB memory.

It should be noted that a process of an application may include multiple tasks, task a being one of the multiple tasks. At time t, task a is a VIP task, and at time t+n, task a may be a non-VIP task, i.e., the same task may be marked as different types of tasks at different times. Accordingly, the L2P table corresponding to the task a may be added to the first L2P linked list or the second L2P linked list, but the L2P table corresponding to the task can only be added to one of the two linked lists at the same time. Furthermore, the same task may correspond to different applications, e.g. a certain process of application a comprises task a, and a certain process of application B also comprises task a.

It should be noted that VIP tasks are typically foreground tasks, e.g., tasks that are interacting with a user. VIP tasks may also be some of the more important background tasks, such as tasks responsible for application keep-alive, tasks responsible for network connectivity and data processing, and so forth. The non-VIP task is typically a background task, e.g., an update task of an application running in the background, etc.

Based on the foregoing embodiments, the static area of the HPB memory stores L2P table information of high frequency data. The electronic device can adopt a dynamic model and a sliding model to execute a large number of test cases so as to determine the file name, inode and other information of the high-frequency data. The dynamic model can be used for executing different test cases of different application programs to detect io performance of the electronic device, such as executing the test case of playing video in video application, or executing the test case of logging in or logging out of video application, and the like. The sliding model may be used to execute sliding operation related use cases on user interfaces of different applications to detect io performance of the electronic device. The tester writes the file name and inode of the high frequency data into an xml configuration file, which may be stored in an external memory of the electronic device (e.g., UFS storage device). After the electronic device is started or restarted, the electronic device may read the xml configuration file from the external memory to initialize the static region in the HPB memory.

The inode of the high-frequency data refers to an identifier of the high-frequency data in a kernel layer, and the kernel layer can uniquely determine the high-frequency data based on the identifier. The electronic device may generate a logical address of the high frequency data based on the inode of the high frequency data so that L2P table information of the high frequency data may be acquired from the NAND or SRAM.

The details of the static area of HPB memory are described below in conjunction with FIG. 6.

Fig. 6 is a schematic diagram illustrating an initialization process of a static area in an HPB memory according to an embodiment of the present application. Taking an android system as an example, as shown in fig. 6, after the electronic device is started or restarted, the electronic device executes a system initialization process, and during system initialization, a configuration module (a parser module in fig. 6) in an application program framework layer of the electronic device obtains an xml configuration file from an external memory, and analyzes the xml configuration file to obtain configuration information such as a file name and inode of high-frequency data. The configuration module issues configuration information to iaware modules of the application framework layer. After receiving the configuration information, the iaware module may send the configuration information to the HPB L2P management module of the kernel layer of the electronic device through the proc file system. After receiving the configuration information, the HPB L2P management module sends an L2P request to the USF storage device by utilizing a communication protocol of an HPB native, wherein the L2P request comprises an inode of high-frequency data, and the L2P request is used for requesting to acquire L2P table information corresponding to the high-frequency data. After receiving the L2P request, the USF storage device acquires L2P table information corresponding to the high frequency data, and sends an L2P response to the HPB L2P management module, wherein the L2P response comprises the L2P table information corresponding to the high frequency data. After receiving the L2P response, the HPB L2P management module stores L2P table information corresponding to the high frequency data in a static area of the HPB memory, for example, in fig. 5, the L2P table information corresponding to the high frequency data includes L2P tables of the high frequency data 1 to the high frequency data n.

It should be noted that the iaware module shown in fig. 6 may be regarded as an interface module for the application framework layer to send data to the kernel layer, and the proc file system may be regarded as an interface module for the kernel layer.

In the running process of an electronic device, a plurality of tasks are usually executed simultaneously, and the tasks comprise a foreground task and a background task, wherein the foreground task usually involves user interaction, and the priority of the foreground task is higher than that of the background task. However, some foreground tasks have a dependency on background tasks, and therefore not all background tasks are unimportant. In view of this, the electronic device may dynamically tag each task based on the current task running situation, where the tag may be classified into a VIP tag or a non-VIP tag, so as to tag the importance degree of the task, and maintain, in the HPB memory, L2P table information corresponding to relevant data of the VIP task and L2P table information corresponding to relevant data of the non-VIP task, respectively, so as to improve the cache hit rate of the host memory.

The relevant contents of the dynamic region of the HPB memory are described in detail below in conjunction with FIG. 7.

Exemplary, FIG. 7 is a schematic diagram of an L2P linked list of a dynamic region of HPB memory provided by an embodiment of the application. As shown in fig. 7, the dynamic storage of the dynamic region of the HPB memory is two types of L2P linked lists, i.e., an L2P linked list of VIP tasks and an L2P linked list of non-VIP tasks, respectively. The L2P linked list of the VIP task comprises a mapping table of logical addresses and physical addresses of relevant data of the VIP task, namely an L2P table corresponding to the relevant data of the VIP task, and the L2P linked list of the non-VIP task comprises a mapping table of logical addresses and physical addresses of relevant data of the non-VIP task, namely an L2P table corresponding to the relevant data of the non-VIP task.

Both L2P linked lists adopt the LRU policy, that is, a counting method is used, each L2P table in the L2P linked list introduces a variable expires, if the L2P table is not referenced every more than one second, expires is decremented, a new L2P table is added to the L2P linked list, and the L2P linked list space is full, so that the L2P table with the minimum expires is preferentially eliminated.

When the host system of the electronic device executes a certain task, the HPB L2P management module shown in fig. 7 is responsible for monitoring a page fault event of the host memory, and when the page fault event occurs, that is, when the host system does not acquire related data of the task from the host memory, the HPB L2P management module queries whether the HPB memory has an L2P table corresponding to the related data of the task, if not, the HPB L2P management module sends an io request to the USF storage device to acquire the data of the page fault and the L2P table corresponding to the data. When the L2P table corresponding to the data is obtained, the HPB L2P management module may add the L2P table corresponding to the data to the corresponding L2P linked list based on the tag (VIP tag or non-VIP tag) of the task. The above process is described in detail below in connection with a few specific examples.

In an example, when the electronic device performs a task with a VIP tag, the electronic device needs to access relevant data of the VIP task stored in the NAND, if a host system of the electronic device does not acquire relevant data of the VIP task from a host memory, that is, a page fault occurs, an HPB L2P management module of the host system sends an io request to a USF storage device, the USF storage device responds to the io request and sends an io response to the HPB L2P management module, where the io response includes the relevant data of the VIP task and an L2P table corresponding to the relevant data of the VIP task. And the HPB L2P management module adds an L2P table corresponding to the relevant data of the VIP task into an L2P linked list of the VIP task in the dynamic area. Illustratively, in FIG. 7, the HPB L2P management module adds the L2P table_1 to an L2P linked list of VIP tasks.

In one example, if the number of L2P tables in the L2P linked list of the VIP task has reached a maximum value, the least recently used LRU policy may be used to eliminate at least one L2P table in the L2P linked list of the current VIP task before adding the L2P table corresponding to the relevant data of the new VIP task. Illustratively, in fig. 7, if the expires variable of the L2P table_3 in the L2P linked list of the VIP task is 0 or is the minimum value of the expires variable of the L2P table in the L2P linked list of the current VIP task, the L2P table_3 is eliminated.

In an example, when the electronic device performs a task of a non-VIP tag, the electronic device needs to access relevant data of the non-VIP task stored in the NAND, if a host system of the electronic device does not acquire relevant data of the non-VIP task from a host memory, that is, a page fault occurs, an HPB L2P management module of the host system sends an io request to a USF storage device, the USF storage device responds to the io request and sends an io response to the HPB L2P management module, and the io response includes the relevant data of the non-VIP task and an L2P table corresponding to the relevant data of the non-VIP task. And the HPB L2P management module adds an L2P table corresponding to the relevant data of the non-VIP task into an L2P linked list of the non-VIP task in the dynamic area. Illustratively, in FIG. 7, the HPB L2P management module adds the L2P table_1' to an L2P linked list of non-VIP tasks.

In one example, if the number of L2P tables in the L2P linked list of the non-VIP task has reached a maximum value, the least recently used LRU policy may be used to eliminate at least one L2P table in the L2P linked list of the current non-VIP task before adding the L2P table corresponding to the relevant data of the new non-VIP task. Illustratively, in fig. 7, if the expires variable of the L2P table_2 'in the L2P linked list of the non-VIP task is 0 or is the minimum value of the expires variable of the L2P table in the L2P linked list of the current non-VIP task, the L2P table_2' is eliminated.

Based on the foregoing embodiments, the process flow of the HPB L2P management module in the host system is generally described below in conjunction with fig. 8.

Fig. 8 is a schematic process flow diagram of an HPB L2P management module in a host system according to an embodiment of the present application. As shown in fig. 8, after the electronic device is turned on or restarted, the HPB L2P management module receives the indication information of system initialization from the configuration module of the application framework layer to perform the system initialization process, and specifically, see S901 to S906 of the embodiment of fig. 9.

After the static region of the HPB memory is initialized, the HPB L2P management module can respectively traverse two L2P linked lists of the dynamic region, wherein the traversing aims to eliminate the L2P tables meeting the conditions so as to release the memory space of the dynamic region. The L2P table satisfying the condition may be, for example, an L2P table with expires variable being 0, or an L2P table corresponding to the last N expires variables after sorting from large to small according to expires variable.

In fig. 8, the HPB L2P management module first traverses the L2P linked list of the VIP task to obtain expires variables of each L2P table in the L2P linked list of the VIP task, and eliminates the L2P table satisfying the above condition from the L2P linked list of the VIP task. After the traversal of the L2P linked list of the VIP task is completed, expires variables of each L2P table in the L2P linked list of the non-VIP task are obtained in the same mode, and the L2P table meeting the conditions is eliminated from the L2P linked list of the non-VIP task. After the traversal of the L2P linked list of the VIP task and the non-VIP task is completed, the HPB L2P management module performs a monitoring mode.

In some embodiments, the traversing of the L2P linked list of non-VIP tasks may also be performed first, followed by the traversing of the L2P linked list of VIP tasks. Or simultaneously performing a traversal of the L2P linked list of VIP tasks and non-VIP tasks.

The HPB L2P management module monitors whether page faults occur or not in a monitoring mode, and if the host system executes a certain task and does not acquire relevant data of the task from the host memory, the HPB L2P management module considers that the page faults occur. When the HPB L2P management module determines that the page fault occurs, it is first determined whether the task in which the page fault occurs is a VIP task, and the HPB L2P management module may determine whether the task is a VIP task or a non-VIP task by acquiring a task tag.

In an example, the HPB L2P management module determines that the current task is a VIP task, the HPB L2P management module determines whether the number of L2P tables in the L2P linked list of the VIP task reaches a preset number, if the number does not reach the preset number, the HPB L2P management module may directly add the L2P table corresponding to the relevant data of the current task (i.e., the new L2P table) to the L2P linked list of the VIP task, and if the number reaches the preset number, the HPB L2P management module performs traversal of the L2P linked list of the VIP task to eliminate at least one L2P table from the L2P linked list of the VIP task. In some embodiments, after performing the traversal of the L2P linked list of VIP tasks, the HPB L2P management module may also perform the traversal of the L2P linked list of non-VIP tasks.

In another example, the HPB L2P management module determines that the current task is a non-VIP task, the HPB L2P management module determines whether the number of L2P tables in the L2P linked list of the non-VIP task reaches a preset number, if the number does not reach the preset number, the HPB L2P management module may directly add the L2P table (i.e., the new L2P table) corresponding to the relevant data of the current task to the L2P linked list of the non-VIP task, and if the number reaches the preset number, the HPB L2P management module performs traversal of the L2P linked list of the non-VIP task to eliminate at least one L2P table from the L2P linked list of the non-VIP task. In some embodiments, after performing the traversal of the L2P linked list of the non-VIP task, the HPB L2P management module may also perform the traversal of the L2P linked list of the VIP task.

The above embodiment shows a process flow of the HPB L2P management module, where the HPB L2P management module is not only responsible for initializing L2P table information in a static area of the HPB memory, but also for maintaining two dynamically changing L2P linked lists in a dynamic area of the HPB memory, so as to improve a hit rate of L2P table information cached by the HPB memory, thereby improving io performance of the electronic device.

Based on the foregoing embodiments, when the electronic device executes a foreground task or a background task, data related to the task may be obtained from the host memory or the UFS storage device based on the data query method provided in the embodiments of the present application. Through the storage optimization of the HPB memory in the host system and the performance optimization of the HPB L2P management module, the speed of acquiring the physical address of the data can be improved, so that the response speed of inquiring or writing the data is improved, and the optimization of the performance of the electronic equipment io is realized.

The following describes in detail the data query method provided in the embodiment of the present application with reference to fig. 9 and fig. 10.

Fig. 9 is a flowchart of a data query method according to an embodiment of the present application. As shown in fig. 9, the data query method includes a process of initializing a static area of the HPB memory and a data query process, which are respectively described below.

In FIG. 9, the process of initializing a static region of HPB memory includes:

s901, after the electronic equipment is started or restarted, a configuration module of an application program framework layer sends indication information of system initialization to a CPU1 of a host system of a kernel layer.

The instruction information is used to instruct the CPU1 to perform initialization of the static area of the HPB memory.

S902. The CPU1 sends a configuration request to the configuration module, the configuration request requesting to obtain configuration information of the static area of the HPB memory of the host system.

S903. the configuration module sends a configuration response to the CPU 1.

In an example, the HPB L2P management module of the CPU1 sends a configuration request to the configuration module, and after receiving the configuration request, the configuration module obtains an xml configuration file, and parses the xml configuration file to obtain configuration information of a static area of the HPB memory of the host system, where the configuration information includes a file name and inode of high frequency data, and so on. The configuration module sends a configuration response to the HPB L2P management module of the CPU1, the configuration response including the configuration information.

S904a. the CPU1 sends an L2P request 1 to the CPU2 of the UFS storage device, the L2P request 1 including an inode of high frequency data.

In one example, the HPB L2P management module of the CPU1 sends an L2P request 1 to the CPU2, and after the CPU2 receives the L2P request 1, it queries whether the SRAM of the UFS storage device has an L2P table corresponding to the high frequency data.

In some embodiments, if the CPU2 queries the L2P table corresponding to the high frequency data from the SRAM of the UFS storage device, the processing is performed: s905a. CPU2 sends an L2P response 1 to CPU1, where L2P response 1 includes an L2P table corresponding to the high frequency data.

In this embodiment, the CPU2 directly acquires the L2P table corresponding to the high frequency data from the SRAM.

In some embodiments, if the CPU2 does not query the L2P table corresponding to the high frequency data from the SRAM of the UFS storage device, the method is performed: s904b, CPU2 sends an L2P request 1 to the NAND controller of the UFS storage device. After receiving the L2P request 1, the NAND controller obtains an L2P table corresponding to the high frequency data from the NAND based on the inode of the high frequency data in the L2P request 1.

After S904b, execution: s905b. the NAND controller sends an L2P response 1 to the CPU2, where the L2P response 1 includes an L2P table corresponding to the high frequency data.

After S905b, S905a is performed.

In this embodiment, the CPU2 accesses NAND through the NAND controller to acquire an L2P table corresponding to high frequency data.

After S905a, execution:

S906, the CPU1 stores an L2P table corresponding to the high frequency data into a static area of the HPB memory.

In one example, the HPB L2P management module of CPU1 stores the L2P table corresponding to the high frequency data into a static region of HPB memory.

S901 to S906 illustrate a process of initializing a static area of the HPB memory after the electronic device is started or restarted, so as to provide data support for a subsequent data query procedure.

In fig. 9, the data query flow includes:

S907. When the CPU1 of the host system executes task a, it is queried whether the host memory stores data of task a.

In this embodiment, the task a may be a foreground task or a background task of an application program. Illustratively, task A is a task that obtains boot animation data for an application.

In some embodiments, if the CPU1 does not query the host memory for task a data, a page fault event is generated. After the CPU1 monitors the page fault event through the HPB L2P management module, it may execute:

S908, the CPU1 of the host system inquires whether the HPB memory has an L2P table corresponding to the data of the task A.

The CPU1 queries whether the HPB memory has an L2P table corresponding to the data of the task A through the HPB L2P management module.

In some embodiments, if the HPB L2P management module queries the HPB memory for the L2P table corresponding to the data of task a, the method further comprises:

S909. The CPU1 of the host system transmits an io request 1 to the CPU2 of the UFS storage device, the io request 1 including the L2P table corresponding to the data of the task a.

S910. the CPU2 sends a query request 1 to the NAND controller, the query request 1 being for requesting acquisition of data of task a.

Query request 1 includes the physical address of task a's data in NAND. After the NAND controller receives the query request 1, the data of task A is acquired from the NAND based on the physical address of the data of task A in the NAND.

S911. The NAND controller transmits a query response 1 to the CPU2, the query response 1 including the data of task a.

S912. the CPU2 transmits an io response 1 to the CPU1, the io response i including the data of the task a.

After the CPU1 receives the io response 1, it executes the task a based on the data of the task a in the io response 1. For example, the data of the task a is the startup animation data of a certain application program, and after the CPU1 receives the data of the task a, the data is transmitted to an upper layer to display the startup animation data.

In this embodiment, when the host system does not cache the task a, but caches the L2P table corresponding to the task a data, the host system may send the L2P table to the UFS storage device, so that the CPU2 of the UFS storage device may obtain the task a data from the NAND through the NAND controller based on the L2P table, which may improve the data query speed.

In some embodiments, if the HPB L2P management module does not query the HPB memory for the L2P table corresponding to the data of task a, the method further comprises:

s913. The CPU1 of the host system transmits an io request 2 to the CPU2 of the UFS storage device, the io request 2 including inode of the data of the task a.

S914. CPU2 sends L2P request 2 to the NAND controller, L2P request 2 including inode of task a' S data.

After receiving the L2P request 2, the NAND controller acquires the L2P table corresponding to the data of task a from the NAND based on the inode of the data of task a.

S915, the NAND controller sends an L2P response 2 to the CPU2, wherein the L2P response 2 comprises an L2P table corresponding to the data of the task A.

S916. CPU2 sends query request 2 to the NAND controller, query request 2 including the physical address of task a.

After the NAND controller receives the query request 2, task A data is obtained from the NAND based on the physical address of task A.

S917. The NAND controller transmits a query response 2 to the CPU2, the query response 2 including the data of task a.

S918. The CPU2 transmits an io response 2 to the CPU1 of the host system, the io response 2 including the data of the task a and the L2P table corresponding to the data of the task a.

After the CPU1 receives the io response 2, the CPU1 executes the task 2 based on the data of the task a in the io response 2. The CPU1 stores the L2P table corresponding to the data of the task A into the HPB memory, and can be used for subsequent data query.

In this embodiment, in the case that the host system does not cache the task a and does not cache the L2P table corresponding to the data of the task a, the host system sends an io request to the UFS storage device to request the data of the task a and the L2P table corresponding to the data. The CPU2 of the UFS storage device needs to acquire the L2P table corresponding to the data of the task a from the NAND first, then acquire the data of the task a from the NAND based on the L2P table, and after accessing the NAND for two rounds, the UFS storage device returns an io response to the host system, where the io response includes the data of the task a and the L2P table corresponding to the data. The data query speed is slower than in the previous embodiment.

In some embodiments, after S912 or S918, performing:

S919. CPU1 of the host system updates the L2P linked list of the dynamic region of HPB memory.

The CPU1 updates the L2P linked list of the dynamic region of HPB memory through the HPB L2P management module. The L2P linked list of the dynamic region of the HPB memory includes an L2P linked list of VIP tasks and an L2P linked list of non-VIP tasks. The CPU1 controls the updating of the L2P linked list of the VIP task and the L2P linked list of the non-VIP task through the HPB L2P management module.

The HPB L2P management module acquires the label of the task A to determine whether the task A is a VIP task or a non-VIP task.

In an example, the tag of the task a is a VIP tag, the task a is a VIP task, and after the HPB L2P management module obtains an L2P table corresponding to the data of the task a, the L2P linked list of the VIP task is controlled to be updated.

Updating the L2P linked list of VIP tasks includes: adding an L2P table corresponding to the data of the task A to an L2P linked list of the VIP task, and initializing expires variables (such as setting to 100) of the L2P table corresponding to the data of the task A; and updating expires variables of the remaining L2P tables in the L2P linked list of the VIP task, wherein the updating strategy is not expanded again by taking the LRU strategy into consideration.

In an example, if the number of L2P tables in the L2P linked list of the VIP task reaches the preset number, before adding the L2P table corresponding to the data of the task a to the L2P linked list of the VIP task, the method further includes: at least one L2P table is eliminated from the L2P linked list of VIP tasks. The elimination policy refers to the LRU policy previously described and is not expanded here.

In an example, the label of the task a is a non-VIP label, the task a is a non-VIP task, and after the HPB L2P management module obtains an L2P table corresponding to the data of the task a, the HPB L2P management module controls to update an L2P linked list of the non-VIP task.

Updating the L2P linked list of non-VIP tasks includes: adding an L2P table corresponding to the data of the task A to an L2P linked list of the non-VIP task, and initializing expires variables (such as setting to 100) of the L2P table corresponding to the data of the task A; and updating expires variables of the remaining L2P tables in the L2P linked list of the non-VIP task, wherein the updating strategy is referred to the LRU strategy and is not expanded.

In an example, if the number of L2P tables in the L2P linked list of the non-VIP task reaches the preset number, before adding the L2P table corresponding to the data of the task a to the L2P linked list of the non-VIP task, the method further includes: at least one L2P table is eliminated from the L2P linked list of non-VIP tasks. The elimination policy refers to the LRU policy previously described and is not expanded here.

With the expansion of the functions of the electronic device, the data in the processes or tasks related to the expansion functions may be high frequency data, and then the L2P tables corresponding to the high frequency data need to be written into the static area of the HPB memory to optimize the io request of the electronic device. In view of the limitation of the static area storage space, the L2P table information in the static area of the HPB memory may be periodically updated, for example, a part of the L2P table corresponding to the high frequency data is added, and a part of the L2P table corresponding to the high frequency data is deleted. The flow of updating the static area of the HPB memory will be described below by taking an L2P table corresponding to newly added high frequency data as an example.

Fig. 10 is a flowchart of a data query method according to an embodiment of the present application. As shown in fig. 10, the data query method includes:

S1001. The configuration module of the application framework layer transmits update configuration information to the CPU1 of the host system of the kernel layer.

The configuration module, upon receiving the update configuration information, transmits the update configuration information to the CPU1 of the host system. The update configuration information includes a file name, inode, and the like of the newly added high-frequency data.

S1002a. the CPU1 of the host system transmits an L2P request 3 to the CPU2 of the UFS storage device, the L2P request 3 including an inode of newly added high frequency data.

In some embodiments, if the CPU2 queries the L2P table corresponding to the newly added high frequency data from the SRAM of the UFS storage device, the processing is performed: s1003a. the CPU2 sends an L2P response 3 to the CPU1 of the host system, where the L2P response 3 includes an L2P table corresponding to the newly added high frequency data.

In some embodiments, if the CPU2 does not query the L2P table corresponding to the newly added high frequency data from the SRAM of the UFS storage device, the method is performed: s1002b. CPU2 sends an L2P request 3 to the NAND controller of the UFS storage device. After receiving the L2P request 3, the NAND controller obtains an L2P table corresponding to the new high-frequency data from the NAND based on the inode of the new high-frequency data in the L2P request 3.

After S1002b, execution: s1003b. the NAND controller sends an L2P response 3 to the CPU2, where the L2P response 3 includes an L2P table corresponding to the newly added high frequency data.

After S1003b, S1003a is performed.

After S1003a, execution:

S1004, the CPU1 of the host system stores the L2P table corresponding to the newly added high frequency data into the static area of the HPB memory.

In one example, the HPB L2P management module of CPU1 stores the L2P table corresponding to the newly added high frequency data to a static region of HPB memory.

S1001 to S1004 illustrate a process of updating the static area of the HPB memory, which is used to write the L2P table corresponding to the new high frequency data into the static area of the HPB memory, so as to provide data support for the subsequent data query flow.

Based on the foregoing embodiments, the embodiments of the present application provide a data query method, which is applied to an electronic device, where the electronic device includes a first memory and a second memory, the first memory is an internal memory of the electronic device, and the second memory is an external memory of the electronic device, and the method includes:

When the electronic equipment executes the first task, if the electronic equipment does not inquire the first data from the first memory, the electronic equipment inquires whether the first memory caches the L2P table information from the logical address to the physical address of the first data, wherein the L2P table information of the first data is used for indicating the physical address of the first data in the second memory;

If the electronic equipment inquires the L2P table information of the first data from the first memory, the electronic equipment acquires the first data from the second memory based on the L2P table information of the first data.

The first memory comprises a first memory area and a second memory area, the first memory area is used for storing L2P table information of preset high-frequency data, the second memory area is used for storing L2P table information of data required by executing tasks with different priorities, and the first data are data required by executing the first task.

In an alternative embodiment, the electronic device includes a first processing module and a second processing module, the first processing module being responsible for managing and controlling the first memory, the second processing module being responsible for managing and controlling the second memory; the electronic device querying whether the first memory caches the L2P table information of the first data, including: the first processing module inquires whether the first memory caches L2P table information of the first data; if the electronic device queries the L2P table information of the first data from the first memory, the electronic device obtains the first data from the second memory based on the L2P table information of the first data, including: if the first processing module inquires L2P table information of the first data from the first memory; the first processing module sends a first query request to the second processing module, wherein the first query request comprises L2P table information of first data; the second processing module obtains the first data from the first storage space of the second memory based on the L2P table information of the first data, and sends a first query response to the first processing module, the first query response including the first data.

In an alternative embodiment, the first processing module queries the first memory for L2P table information of the first data, including: the first processing module queries L2P table information of the first data from a first storage area of the first memory or queries L2P table information of the first data from a second storage area of the first memory.

In an alternative embodiment, if the first processing module does not query the L2P table information of the first data from the first memory, the first processing module sends a second query request to the second processing module, where the second query request includes an identifier of the first data; the second processing module obtains L2P table information of the first data from a first storage space of the second memory based on the identification of the first data; the second processing module acquires the first data from the first storage space based on the L2P table information of the first data; the second processing module sends a second query response to the first processing module, the second query response including the first data and the L2P table information for the first data.

In an alternative embodiment, the first processing module stores the L2P table information of the first data to the second storage area of the first memory in response to receiving the second query response.

In an alternative embodiment, the second storage area of the first memory includes an L2P linked list of the first priority task and an L2P linked list of the second priority task, the first priority being higher than the second priority; the first processing module stores L2P table information of the first data to a second storage area of the first memory, including: if the first task is a first priority task, the first processing module adds the L2P table information of the first data to an L2P linked list of the first priority task; or if the first task is a second priority task, the first processing module adds the L2P table information of the first data to an L2P linked list of the second priority task.

In an alternative embodiment, if the first task is a first priority task, the first processing module adds the L2P table information of the first data to an L2P linked list of the first priority task, including: if the number of the L2P tables of the L2P linked list of the first priority task reaches the preset number, the first processing module eliminates at least one L2P table in the L2P linked list of the first priority task based on the least recently used LRU strategy, and then adds the L2P table information of the first data to the L2P linked list of the first priority task. Or alternatively

In an alternative embodiment, the method further comprises: after the electronic equipment is started or restarted, the electronic equipment acquires configuration information, wherein the configuration information comprises a file name and an identifier of preset high-frequency data; the electronic equipment acquires L2P table information of the high frequency data from the second memory; the electronic device stores the L2P table information of the high frequency data to a first storage area of the first memory.

In an alternative embodiment, the electronic device further includes a configuration module, and the electronic device obtains configuration information, including: the configuration module acquires a configuration file from an external memory, and acquires configuration information by analyzing the configuration file; the configuration module sends configuration information to a first processing module of the electronic equipment; the electronic device obtains the L2P table information of the high frequency data from the second memory, and the L2P table information comprises: the first processing module sends a third query request to the second processing module of the electronic device, wherein the third query request comprises the identification of the high-frequency data; the second processing module acquires L2P table information of the high frequency data from the first storage space or the second storage space of the second memory based on the identification of the high frequency data; the second processing module sends a third query response to the first processing module, wherein the third query response comprises L2P table information of the high-frequency data; the electronic device stores the L2P table information of the high frequency data to a first storage area of a first memory, including: the first processing module stores the L2P table information of the high frequency data to a first storage area of the first memory.

In an alternative embodiment, the method further comprises: the electronic equipment acquires update configuration information, wherein the update configuration information comprises a file name and an identifier of newly added high-frequency data; the electronic equipment acquires the newly added L2P table information of the high frequency data from the second memory; the electronic device stores the L2P table information of the newly added high frequency data to the first storage area of the first memory.

The data query method provided by the embodiment of the application can be applied to any electronic device, and the electronic device can also be called a terminal (terminal), a User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT) and the like. The electronic device may be a mobile phone with a touch screen, a smart television, a wearable device, a tablet (Pad), a computer with wireless transceiving functionality, a Virtual Reality (VR) electronic device, an augmented reality (augmented reality, AR) electronic device, a wireless terminal in industrial control (industrial control), a wireless terminal in unmanned (self-driving), a wireless terminal in teleoperation (remote medical surgery), a wireless terminal in smart grid (SMART GRID), a wireless terminal in transportation security (transportation safety), a wireless terminal in smart city (SMART CITY), a wireless terminal in smart home (smart home), etc. The embodiment of the application does not limit the specific technology and the specific equipment form adopted by the electronic equipment.

Fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in fig. 11, the electronic device 100 includes: processor 110, external memory interface 120, internal memory 121, universal serial bus (universal serial bus, USB) interface 130, charge management module 140, power management module 141, battery 142, antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, sensor 180, keys 190, camera 193, display 194.

It is to be understood that the structure illustrated in the present embodiment does not constitute a specific limitation on the electronic apparatus 100. In some embodiments, electronic device 100 may include more or fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

It should be understood that the interfacing relationship between the modules illustrated in the embodiments is only illustrative and not limiting on the structure of the electronic device 100. In some embodiments, the electronic device 100 may also employ different interfaces in the above embodiments, or a combination of interfaces.

Processor 110 may include one or more processing units. Wherein the different processing units may be separate devices or may be integrated in one or more processors. A memory may also be provided in the processor 110 for storing instructions and data.

In the embodiment of the present application, the processor 110 may be configured to invoke the computer program in the memory, so that the electronic device executes the data query scheme provided in the embodiment of the present application, so as to improve the io performance of the electronic device.

The USB interface 130 is an interface conforming to the USB standard specification, and may be used to connect a charger to charge an electronic device, or may be used to transmit data between the electronic device and a peripheral device, or may be used to connect an earphone, and play audio through the earphone.

The charge management module 140 is configured to receive a charge input from a charger. The power management module 141 is used for connecting the battery 142, and the charge management module 140 and the processor 110.

The wireless communication function of the electronic device 100 may be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, a modem processor, a baseband processor, and the like. The mobile communication module 150 may provide a solution for wireless communication including 2G/3G/4G/5G, etc., applied to the electronic device 100. The wireless communication module 160 may provide solutions for wireless communication including wireless local area network (wireless local area networks, WLAN), bluetooth, global navigation satellite system (global navigation SATELLITE SYSTEM, GNSS), frequency modulation (frequency modulation, FM), NFC, infrared (IR), etc. applied to the electronic device 100.

The electronic device 100 may implement display functions through a GPU, a display screen 194, an application processor, and the like. The GPU is a microprocessor for image processing, and is connected to the display 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute instructions to generate or change display information.

The electronic device 100 may include 1 or more display screens 194, the display screens 194 for displaying images, videos, and the like. The electronic device 100 may implement photographing functions through an Image Signal Processing (ISP) module, one or more cameras 193, video codecs, a GPU, one or more display screens 194, an application processor, and the like. The camera 193 is used to capture still images or video. In some embodiments, electronic device 100 may include one or more cameras 193.

The external memory interface 120 may be used to connect an external memory card, such as a Micro SD card, to enable expansion of the memory capabilities of the electronic device 100. The external memory card communicates with the processor 110 through an external memory interface 120 to implement data storage functions.

The internal memory 121 may be used to store one or more computer programs, including instructions. The processor 110 may cause the electronic device 100 to execute various functional applications, data processing, and the like by executing the above-described instructions stored in the internal memory 121. In an embodiment of the present application, the internal memory may correspond to the host memory of the foregoing embodiment.

The sensor 180 may include one or more of the following, for example: pressure sensors, gyroscopic sensors, barometric pressure sensors, magnetic sensors, acceleration sensors, distance sensors, proximity sensors, fingerprint sensors, temperature sensors, touch sensors, ambient light sensors, or bone conduction sensors, among others.

The embodiment of the application also provides electronic equipment, which comprises: one or more processors and a memory coupled with the one or more processors, the memory for storing computer program code, the computer program code comprising computer instructions, the one or more processors invoking the computer instructions to cause the electronic device to perform steps as in the foregoing method embodiments, the implementation principle and technical effects of which are similar to those of the foregoing related embodiments, and will not be repeated here.

The embodiment of the application also provides a chip system, which is applied to electronic equipment, the chip system comprises one or more processors, the one or more processors are used for calling computer instructions to enable the electronic equipment to execute the steps in the embodiment of the method, and the implementation principle and technical effects are similar to those of the related embodiment, and are not repeated here.

Embodiments of the present application further provide a computer readable storage medium, where the computer readable storage medium includes computer instructions, when the computer instructions are executed on an electronic device, cause the electronic device to perform steps in the foregoing method embodiments, and the implementation principle and technical effects are similar to those of the foregoing related embodiments, which are not repeated herein.

Embodiments of the present application also provide a computer program product, where the computer program product includes computer program code, when the computer program code runs on an electronic device, causes the electronic device to perform the steps in the foregoing method embodiments, and the implementation principle and technical effects are similar to those of the foregoing related embodiments, which are not repeated herein.

The methods described in the above embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer readable media can include computer storage media and communication media and can include any medium that can transfer a computer program from one place to another. The storage media may be any target media that is accessible by a computer.

In some embodiments, the computer readable medium may include RAM, ROM, a compact disk-read only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium targeted for carrying or storing the desired program code in the form of instructions or data structures and accessible by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (Digital Subscriber Line, DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes optical disc, laser disc, optical disc, digital versatile disc (DIGITAL VERSATILE DISC, DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should be noted that, the user information (including but not limited to user equipment information, user personal information, etc.) and the data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present application are information and data authorized by the user or fully authorized by each party, and the collection, use and processing of the related data need to comply with related laws and regulations and standards, and provide corresponding operation entries for the user to select authorization or rejection.

The foregoing detailed description of the invention has been presented for purposes of illustration and description, and it should be understood that the foregoing is by way of illustration and description only, and is not intended to limit the scope of the invention.

Claims

1. The data query method is characterized by being applied to electronic equipment, wherein the electronic equipment comprises a first memory and a second memory, the first memory is an internal memory of the electronic equipment, and the second memory is an external memory of the electronic equipment, and the method comprises the following steps:

When the electronic device executes a first task, if the electronic device does not query first data from the first memory, the electronic device queries whether the first memory caches logical address to physical address L2P table information of the first data, wherein the L2P table information of the first data is used for indicating the physical address of the first data in the second memory;

If the electronic equipment inquires the L2P table information of the first data from the first memory, the electronic equipment acquires the first data from the second memory based on the L2P table information of the first data;

The first memory comprises a first memory area and a second memory area, wherein the first memory area is used for storing L2P table information of preset high-frequency data, the high-frequency data are data in processes or tasks related to an extended function, the second memory area is used for storing L2P table information of data required for executing tasks with different priorities, and the first data are data required for executing the first task.

2. The method of claim 1, wherein the electronic device comprises a first processing module and a second processing module, the first processing module being responsible for managing and controlling the first memory and the second processing module being responsible for managing and controlling the second memory;

The electronic device querying whether the first memory caches the L2P table information of the first data includes:

The first processing module inquires whether the first memory caches L2P table information of the first data;

If the electronic device queries the L2P table information of the first data from the first memory, the electronic device obtains the first data from the second memory based on the L2P table information of the first data, including:

if the first processing module inquires L2P table information of the first data from the first memory;

The first processing module sends a first query request to the second processing module, wherein the first query request comprises L2P table information of the first data;

The second processing module obtains the first data from the first storage space of the second memory based on the L2P table information of the first data, and sends a first query response to the first processing module, wherein the first query response comprises the first data.

3. The method of claim 2, wherein the first processing module querying the L2P table information for the first data from the first memory comprises:

the first processing module queries L2P table information of the first data from a first storage area of the first memory or queries L2P table information of the first data from a second storage area of the first memory.

4. The method according to claim 2, wherein the method further comprises:

If the first processing module does not query the L2P table information of the first data from the first memory, the first processing module sends a second query request to the second processing module, wherein the second query request comprises the identification of the first data;

the second processing module obtains L2P table information of the first data from a first storage space of the second memory based on the identification of the first data;

the second processing module obtains the first data from the first storage space based on the L2P table information of the first data;

the second processing module sends a second query response to the first processing module, the second query response including the first data and L2P table information for the first data.

5. The method according to claim 4, wherein the method further comprises:

in response to receiving the second query response, the first processing module stores L2P table information for the first data to the second storage region of the first memory.

6. The method of claim 5, wherein the second storage area of the first memory comprises an L2P linked list of first priority tasks and an L2P linked list of second priority tasks, the first priority being higher than the second priority; the first processing module storing L2P table information of the first data to the second storage area of the first memory, comprising:

If the first task is the first priority task, the first processing module adds the L2P table information of the first data to an L2P linked list of the first priority task; or alternatively

And if the first task is the second priority task, the first processing module adds the L2P table information of the first data to an L2P linked list of the second priority task.

7. The method of claim 6, wherein the step of providing the first layer comprises,

If the first task is the first priority task, the first processing module adds the L2P table information of the first data to an L2P linked list of the first priority task, including:

If the number of the L2P tables of the L2P linked list of the first priority task reaches a preset number, the first processing module eliminates at least one L2P table in the L2P linked list of the first priority task based on the least recently used LRU strategy, and then adds the L2P table information of the first data into the L2P linked list of the first priority task;

If the first task is the second priority task, the first processing module adds the L2P table information of the first data to an L2P linked list of the second priority task, including:

And if the number of the L2P tables of the L2P linked list of the second priority task reaches the preset number, the first processing module eliminates at least one L2P table in the L2P linked list of the second priority task based on the least recently used LRU strategy, and then adds the L2P table information of the first data into the L2P linked list of the second priority task.

8. The method according to any one of claims 1 to 7, further comprising:

after the electronic equipment is started or restarted, the electronic equipment acquires configuration information, wherein the configuration information comprises a file name and an identifier of preset high-frequency data;

the electronic equipment acquires the L2P table information of the high frequency data from the second memory;

the electronic device stores the L2P table information of the high-frequency data to the first storage area of the first memory.

9. The method of claim 8, wherein the step of determining the position of the first electrode is performed,

The electronic device further includes a configuration module, and the electronic device obtains configuration information, including: the configuration module acquires a configuration file from an external memory, and acquires the configuration information by analyzing the configuration file;

The configuration module sends the configuration information to a first processing module of the electronic equipment; the electronic device obtains the L2P table information of the high frequency data from the second memory, including: the first processing module sends a third query request to a second processing module of the electronic device, wherein the third query request comprises the identification of the high-frequency data; the second processing module obtains the L2P table information of the high frequency data from the first storage space or the second storage space of the second memory based on the identification of the high frequency data; the second processing module sends a third query response to the first processing module, wherein the third query response comprises L2P table information of the high-frequency data;

The electronic device storing L2P table information of the high frequency data to the first storage area of the first memory, including: the first processing module stores the L2P table information of the high frequency data to the first storage area of the first memory.

10. The method according to any one of claims 1 to 7, further comprising:

the electronic equipment acquires update configuration information, wherein the update configuration information comprises a file name and an identifier of newly added high-frequency data;

The electronic equipment acquires the L2P table information of the newly-added high-frequency data from the second memory;

the electronic device stores the L2P table information of the newly added high-frequency data into the first storage area of the first memory.

11. An electronic device, the electronic device comprising: one or more processors and memory;

The memory is coupled with the one or more processors, the memory for storing computer program code comprising computer instructions that the one or more processors invoke to cause the electronic device to perform the method of any of claims 1-10.

12. A chip system for application to an electronic device, the chip system comprising one or more processors to invoke computer instructions to cause the electronic device to perform the method of any of claims 1 to 10.

13. A computer readable storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform the method of any one of claims 1 to 10.

14. A computer program product, characterized in that the computer program product comprises computer program code which, when run on an electronic device, causes the electronic device to perform the method of any one of claims 1 to 10.