CN114880251B

CN114880251B - Memory cell access method, memory cell access device and terminal equipment

Info

Publication number: CN114880251B
Application number: CN202210812129.7A
Authority: CN
Inventors: 李婧
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2022-07-12
Filing date: 2022-07-12
Publication date: 2023-08-29
Anticipated expiration: 2042-07-12
Also published as: CN114880251A

Abstract

The application provides a storage unit access method, an access device and a terminal device, which are beneficial to shortening the time of the terminal device responding to an operation instruction and improving the user experience. The method comprises the following steps: receiving a first operation instruction input by a user; determining a first logical address corresponding to the first operation instruction; acquiring a first physical address corresponding to a first logical address based on a first L2P address mapping table, wherein the first L2P address mapping table is stored in a processor, and the first L2P address mapping table comprises a mapping relation between the physical address and the logical address of a first storage space in a memory; and accessing the storage space indicated by the first physical address.

Description

Memory cell access method, memory cell access device and terminal equipment

Technical Field

The present application relates to the field of terminal technologies, and in particular, to a method, an apparatus, and a terminal device for accessing a storage unit.

Background

When a user operates the terminal device, the processor converts each operation instruction of the user into a command for addressing data in the memory by using a logical address, then the processor sends the logical address to the memory, and correspondingly, after the memory receives the logical address, the processor converts the logical address into a target physical address based on a logical-to-address mapping table (also referred to as an L2P address mapping table or an L2P mapping table), and operates a storage unit indicated by the target physical address.

Wherein an L2P address mapping table is used for logical address to physical address translation and typically the L2P mapping table is located in a static random access memory (static random access memory, SRAM) in memory.

However, because the capacity of the SRAM is limited, the L2P mapping table in the current SRAM can only store the mapping relationship between the logical address and the physical address of a part of the storage units, so that the access of the terminal device to the storage units depends on the implementation of the internal algorithm of the memory, thereby causing the long time of the terminal device responding to the operation instruction and poor user experience.

Disclosure of Invention

The application provides a storage unit access method, an access device and a terminal device, which are beneficial to shortening the time of the terminal device responding to an operation instruction and improving the user experience.

In a first aspect, a method for accessing a storage unit is provided, applied to a terminal device, where the terminal device includes a processor and a memory, a first logical-to-physical L2P address mapping table is stored in the processor, and the first L2P address mapping table includes a mapping relationship between a physical address and a logical address of a first storage space in the memory, and the method includes: receiving a first operation instruction input by a user; determining a first logical address corresponding to the first operation instruction; acquiring a first physical address corresponding to a first logical address based on a first L2P address mapping table; and accessing the storage space indicated by the first physical address.

In this embodiment, after the terminal device receives the first operation instruction and determines the first logical address corresponding to the first operation instruction based on the processor in the terminal device, the processor in the terminal device may directly obtain the first physical address corresponding to the first logical address based on the first L2P address mapping table, and then tell the first physical address to the memory, instead of telling the first logical address to the memory, so that the memory accesses the storage space indicated by the first physical address. It can be appreciated that in this implementation, since the processing rate of the processor is generally greater than that of the memory, it is helpful to shorten the time for the terminal device to respond to the operation instruction, and improve the user experience.

Furthermore, it can be further understood that, in the prior art, if there is no first physical address corresponding to the first logical address in the L2P address mapping table in the memory, the terminal device obtains the mapping relationship between the first logical address and the first physical address based on a series of algorithms, which results in a relatively long time. In the technical scheme, if the mapping relation between the first logical address and the first physical address which are not stored in the memory is stored in the processor, a series of algorithms are not needed to obtain the mapping relation between the first logical address and the first physical address, so that the time of the terminal equipment responding to the operation instruction is shortened, and the user experience is improved.

And in another aspect, under the condition that the storage space in the memory is insufficient to store the corresponding relation between the logical address and the physical address, the method is simple in implementation mode and can reduce improvement difficulty and further reduce improvement cost by storing the corresponding relation into the processor and searching the physical address from the processor based on the corresponding relation.

With reference to the first aspect, in one possible implementation manner, the first storage space includes all storage spaces in the memory.

It can be understood that in this implementation manner, by storing the mapping relationship between the logical addresses and the physical addresses in all the storage spaces in the memory in the processor, when the terminal device receives any one of the operation instructions input by the user, the processor in the terminal device can quickly find the logical address and the physical address corresponding to the operation instruction input by the user. Therefore, the process of sending the logical address to the memory and finding the physical address based on the logical address is not required to be executed, so that the time of the terminal equipment responding to the operation instruction can be improved, and the user experience is improved.

With reference to the first aspect, in one possible implementation manner, the first storage space includes a portion of storage space in the memory, a second L2P address mapping table is stored in the memory, the second L2P address mapping table includes a mapping relationship between a physical address and a logical address of the second storage space in the memory, and the second storage space is a storage space except the first storage space in all storage spaces in the memory.

In the present application, the first L2P address mapping table is also referred to as a first L2P mapping table, and the second L2P address mapping table is referred to as a second L2P mapping table.

In the implementation manner, the mapping relation between the physical address and the logical address of one part of the storage space is stored in the processor, and the mapping relation between the physical address and the logical address of the other part of the storage space is stored in the memory, so that when the mapping relation between the logical address and the physical address is not stored in the memory of a certain storage space, the mapping relation between the logical address and the physical address of the storage space is obtained without the memory based on an internal algorithm, and therefore, the time of the terminal equipment responding to the operation instruction can be improved, and the user experience is improved.

With reference to the first aspect, in one possible implementation manner, a second operation instruction input by a user is received; determining a second logical address corresponding to the second operation instruction; determining whether a second physical address corresponding to the second logical address is included in the first L2P address mapping table; if the first L2P address mapping table does not have the second physical address corresponding to the second logical address, acquiring the second physical address corresponding to the second logical address based on the second L2P address mapping table; and accessing the storage space indicated by the second physical address.

In this implementation manner, after the terminal device receives the second operation instruction and determines the second logical address corresponding to the second operation instruction, if the second physical address corresponding to the second logical address is not found based on the first L2P address mapping table in the processor, the terminal device searches from the second L2P address mapping table in the memory, so as to access the storage unit indicated by the second physical address.

With reference to the first aspect, in one possible implementation manner, the method for accessing a storage unit provided by the present application further includes: determining whether a first physical address corresponding to the first logical address is included in the second L2P address mapping table; the method for acquiring the first physical address corresponding to the first logical address based on the first L2P address mapping table comprises the following steps: if the second L2P address mapping table does not have the first physical address corresponding to the first logical address, the first physical address corresponding to the first logical address is acquired based on the first L2P address mapping table.

It should be understood that in the prior art, if there is no first logical address in the L2P mapping table (i.e., the second L2P mapping table) in the memory, the terminal device may obtain the mapping relationship between the first logical address and the first physical address based on a series of algorithms, resulting in a relatively long time. However, in this implementation, when the first physical address corresponding to the first logical address is not found in the memory, the first physical address is found in the L2P mapping table in the processor, so that no additional algorithm is required to be performed, and in general, the mapping relationship between the first logical address and the first physical address obtained based on a series of algorithms may be longer than the duration of the first physical address found in the processor when the terminal device cannot find the first physical address in the memory, so that the duration of accessing the storage space indicated by the first physical address is facilitated to be shortened, thereby facilitating the improvement of the user experience.

With reference to the first aspect, in one possible implementation manner, the method includes receiving a first operation instruction input by a user, determining a first logical address corresponding to the first operation instruction, and acquiring a first physical address corresponding to the first logical address based on a first L2P address mapping table; accessing the memory space indicated by the first physical address, including: the processor sends a first physical address to the memory; and after the memory receives the first physical address, accessing the memory space indicated by the first physical address.

In the implementation manner, the terminal equipment realizes that the memory accesses the storage space indicated by the first physical address by sending the first physical address to the memory through the processor.

In a second aspect, the present application provides an access device for a storage unit, applied to a terminal device, where the terminal device includes a processor and a memory, a first logical-to-physical L2P address mapping table is stored in the processor, and the first L2P address mapping table includes a mapping relationship between a physical address and a logical address of a first storage space in the memory, and the device includes: the receiving and transmitting module is used for receiving a first operation instruction input by a user; the first processing module is used for determining a first logic address corresponding to the first operation instruction; the first processing module is further used for acquiring a first physical address corresponding to the first logical address based on the first L2P address mapping table; the first processing module is further configured to access the storage space indicated by the first physical address.

With reference to the second aspect, in one possible implementation manner, the first storage space includes all storage spaces in the memory.

With reference to the second aspect, in one possible implementation manner, the first storage space includes a part of storage space in the memory, the memory stores a second L2P address mapping table, the second L2P address mapping table includes a mapping relationship between a physical address and a logical address of the second storage space in the memory, and the second storage space is a storage space except the first storage space in all storage spaces in the memory.

With reference to the second aspect, in one possible implementation manner, the transceiver module is further configured to: receiving a second operation instruction input by a user; the first processing module is further configured to: determining a second logical address corresponding to the second operation instruction; determining whether a second physical address corresponding to the second logical address is included in the first L2P address mapping table; if the first L2P address mapping table does not have the second physical address corresponding to the second logical address, acquiring the second physical address corresponding to the second logical address based on the second L2P address mapping table; and accessing the storage space indicated by the second physical address.

With reference to the second aspect, in one possible implementation manner, the first processing module is further configured to: determining whether a first physical address corresponding to the first logical address is included in the second L2P address mapping table; if the second L2P address mapping table does not have the first physical address corresponding to the first logical address, the first physical address corresponding to the first logical address is acquired based on the first L2P address mapping table.

With reference to the second aspect, in one possible implementation manner, the method includes receiving a first operation instruction input by a user, determining a first logical address corresponding to the first operation instruction, and acquiring a first physical address corresponding to the first logical address based on a first L2P address mapping table; the first processing module is further configured to: controlling the transceiver module to send a first physical address to the memory; and the second processing module is used for accessing the storage space indicated by the first physical address after the memory receives the first physical address.

In a third aspect, the present application provides a terminal device comprising a processor coupled to a memory, operable to execute instructions in the memory to implement a method according to any one of the possible implementations of the first aspect.

Optionally, the terminal device further comprises a memory.

Optionally, the terminal device further comprises a transceiver, and the processor is coupled to the transceiver.

In a fourth aspect, the present application provides a processing apparatus comprising a processor and a memory. The processor is configured to read instructions stored in the memory and to receive signals via the receiver and to transmit signals via the transmitter to perform the method of any one of the possible implementations of the first aspect.

Optionally, the processor is one or more and the memory is one or more.

Alternatively, the memory may be integrated with the processor or the memory may be separate from the processor.

In a specific implementation process, the memory may be a non-transient (non-transitory) memory, for example, a Read Only Memory (ROM), which may be integrated on the same chip as the processor, or may be separately disposed on different chips.

It should be appreciated that the related data interaction process, for example, transmitting the indication information, may be a process of outputting the indication information from the processor, and the receiving the capability information may be a process of receiving the input capability information by the processor. Specifically, the data output by the processing may be output to the transmitter, and the input data received by the processor may be from the receiver. Wherein the transmitter and receiver may be collectively referred to as a transceiver.

The processing means in the fourth aspect may be a chip, and the processor may be implemented by hardware or software, and when implemented by hardware, the processor may be a logic circuit, an integrated circuit, or the like; when implemented in software, the processor may be a general-purpose processor, implemented by reading software code stored in a memory, which may be integrated in the processor, or may reside outside the processor, and exist separately.

In a fifth aspect, the present application provides a computer readable storage medium storing a computer program (which may also be referred to as code, or instructions) which, when run on a computer, causes the computer to perform the method of any one of the possible implementations of the first aspect.

In a sixth aspect, the present application provides a computer program product comprising: a computer program (which may also be referred to as code, or instructions) which, when executed, causes a computer to perform the method of any one of the possible implementations of the first aspect.

Drawings

Fig. 1 is a schematic structural diagram of a terminal device according to an embodiment of the present application;

Fig. 2 is a schematic structural diagram of a terminal device according to an embodiment of the present application in response to a user operation;

fig. 3 is a schematic diagram of a specific process of an operation of a terminal device according to an embodiment of the present application in response to a user input;

FIG. 4 is a schematic diagram of a memory structure of a memory according to an embodiment of the present application;

FIG. 5 is a flowchart illustrating a method for accessing a memory cell according to an embodiment of the present application;

FIG. 6 is a schematic diagram of an interface for inputting a first operation command according to an embodiment of the present application;

FIG. 7 is a schematic diagram of an architecture between a processor and a memory according to an embodiment of the present application;

FIG. 8 is a schematic diagram illustrating an internal implementation of a method for accessing a memory cell according to an embodiment of the present application;

FIG. 9 is a schematic structural diagram of an access device according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a terminal device according to another embodiment of the present application.

Detailed Description

The technical scheme of the application will be described below with reference to the accompanying drawings.

In order to clearly describe the technical solution of the embodiments of the present application, in the embodiments of the present application, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. For example, the first chip and the second chip are merely for distinguishing different chips, and the order of the different chips is not limited. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.

It should be noted that, in the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.

The access method of the storage unit provided by the embodiment of the application can be applied to the terminal equipment with the display function. The terminal device may also be referred to as a terminal (terminal), a User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT), etc. The terminal device may be a mobile phone, a smart television, a wearable device, a tablet (Pad), a computer with wireless transceiving function, a Virtual Reality (VR) terminal device, an augmented reality (augmented reality, AR) terminal device, a wireless terminal in industrial control (industrial control), a wireless terminal in unmanned driving (self-driving), a wireless terminal in teleoperation (remote medical surgery), a wireless terminal in smart grid (smart grid), a wireless terminal in transportation safety (transportation safety), a wireless terminal in smart city (smart city), a wireless terminal in smart home (smart home), or the like. The embodiment of the application does not limit the specific technology and the specific equipment form adopted by the terminal equipment.

In order to better understand the embodiments of the present application, the following describes a hardware structure of the terminal device according to the embodiments of the present application. Fig. 1 is a schematic structural diagram of a terminal device according to an embodiment of the present application:

Fig. 1 shows a schematic structural diagram of a terminal device. The terminal device may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charge management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, keys 190, a motor 191, an indicator 192, a camera 193, a display 194, and a subscriber identity module (subscriber identification module, SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyro sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, and the like.

It will be appreciated that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the terminal device. In other embodiments of the application, the terminal device may include more or less components than illustrated, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The processor 110 may include one or more processing units, such as: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and/or a neural network processor (neural-network processing unit, NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors.

The controller can generate operation control signals according to the instruction operation codes and the time sequence signals to finish the control of instruction fetching and instruction execution.

A memory may also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may hold instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to reuse the instruction or data, it may be called from memory. Repeated accesses are avoided and the latency of the processor 110 is reduced, thereby improving the efficiency of the system.

In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose input/output (GPIO) interface, a subscriber identity module (subscriber identity module, SIM) interface, and/or a universal serial bus (universal serial bus, USB) interface, among others.

The I2C interface is a bi-directional synchronous serial bus comprising a serial data line (SDA) and a serial clock line (derail clock line, SCL). In some embodiments, the processor 110 may contain multiple sets of I2C buses. The processor 110 may be coupled to the touch sensor 180K, charger, flash, camera 193, etc., respectively, through different I2C bus interfaces. For example: the processor 110 may be coupled to the touch sensor 180K through an I2C interface, so that the processor 110 and the touch sensor 180K communicate through an I2C bus interface to implement a touch function of the terminal device.

The I2S interface may be used for audio communication. In some embodiments, the processor 110 may contain multiple sets of I2S buses. The processor 110 may be coupled to the audio module 170 via an I2S bus to enable communication between the processor 110 and the audio module 170. In some embodiments, the audio module 170 may transmit an audio signal to the wireless communication module 160 through the I2S interface, to implement a function of answering a call through the bluetooth headset.

PCM interfaces may also be used for audio communication to sample, quantize and encode analog signals. In some embodiments, the audio module 170 and the wireless communication module 160 may be coupled through a PCM bus interface. In some embodiments, the audio module 170 may also transmit audio signals to the wireless communication module 160 through the PCM interface to implement a function of answering a call through the bluetooth headset. Both the I2S interface and the PCM interface may be used for audio communication.

The UART interface is a universal serial data bus for asynchronous communications. The bus may be a bi-directional communication bus. It converts the data to be transmitted between serial communication and parallel communication. In some embodiments, a UART interface is typically used to connect the processor 110 with the wireless communication module 160. For example: the processor 110 communicates with a bluetooth module in the wireless communication module 160 through a UART interface to implement a bluetooth function. In some embodiments, the audio module 170 may transmit an audio signal to the wireless communication module 160 through a UART interface, to implement a function of playing music through a bluetooth headset.

The MIPI interface may be used to connect the processor 110 to peripheral devices such as a display 194, a camera 193, and the like. The MIPI interfaces include camera serial interfaces (camera serial interface, CSI), display serial interfaces (display serial interface, DSI), and the like. In some embodiments, processor 110 and camera 193 communicate through a CSI interface to implement a photographing function of the terminal device. The processor 110 and the display 194 communicate via a DSI interface to implement the display function of the terminal device.

The GPIO interface may be configured by software. The GPIO interface may be configured as a control signal or as a data signal. In some embodiments, a GPIO interface may be used to connect the processor 110 with the camera 193, the display 194, the wireless communication module 160, the audio module 170, the sensor module 180, and the like. The GPIO interface may also be configured as an I2C interface, an I2S interface, a UART interface, an MIPI interface, etc.

The USB interface 130 is an interface conforming to the USB standard specification, and may specifically be a Mini USB interface, a Micro USB interface, a USB Type C interface, or the like. The USB interface 130 may be used to connect a charger to charge a terminal device, or may be used to transfer data between the terminal device and a peripheral device. And can also be used for connecting with a headset, and playing audio through the headset. The interface may also be used to connect other electronic devices, such as AR devices, etc.

It will be understood that the interface connection relationship between the modules illustrated in the embodiment of the present application is illustrated schematically, and does not constitute a structural limitation of the terminal device. In other embodiments of the present application, the terminal device may also use different interfacing manners in the foregoing embodiments, or a combination of multiple interfacing manners.

The charge management module 140 is configured to receive a charge input from a charger. The charger can be a wireless charger or a wired charger. In some wired charging embodiments, the charge management module 140 may receive a charging input of a wired charger through the USB interface 130. In some wireless charging embodiments, the charge management module 140 may receive wireless charging input through a wireless charging coil of the terminal device. The charging management module 140 may also supply power to the terminal device through the power management module 141 while charging the battery 142.

The power management module 141 is used for connecting the battery 142, and the charge management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and/or the charge management module 140 to power the processor 110, the internal memory 121, the display 194, the camera 193, the wireless communication module 160, and the like. The power management module 141 may also be configured to monitor battery capacity, battery cycle number, battery health (leakage, impedance) and other parameters. In other embodiments, the power management module 141 may also be provided in the processor 110. In other embodiments, the power management module 141 and the charge management module 140 may be disposed in the same device.

The wireless communication function of the terminal device may be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, a modem processor, a baseband processor, and the like.

The antennas 1 and 2 are used for transmitting and receiving electromagnetic wave signals. Antennas in the terminal device may be used to cover single or multiple communication bands. Different antennas may also be multiplexed to improve the utilization of the antennas. For example: the antenna 1 may be multiplexed into a diversity antenna of a wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.

The mobile communication module 150 may provide a solution for wireless communication including 2G/3G/4G/5G or the like applied on a terminal device. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (low noise amplifier, LNA), etc. The mobile communication module 150 may receive electromagnetic waves from the antenna 1, perform processes such as filtering, amplifying, and the like on the received electromagnetic waves, and transmit the processed electromagnetic waves to the modem processor for demodulation. The mobile communication module 150 can amplify the signal modulated by the modem processor, and convert the signal into electromagnetic waves through the antenna 1 to radiate. In some embodiments, at least some of the functional modules of the mobile communication module 150 may be disposed in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 may be provided in the same device as at least some of the modules of the processor 110.

The modem processor may include a modulator and a demodulator. The modulator is used for modulating the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used for demodulating the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low frequency baseband signal to the baseband processor for processing. The low frequency baseband signal is processed by the baseband processor and then transferred to the application processor. The application processor outputs sound signals through an audio device (not limited to the speaker 170A, the receiver 170B, etc.), or displays images or video through the display screen 194. In some embodiments, the modem processor may be a stand-alone device. In other embodiments, the modem processor may be provided in the same device as the mobile communication module 150 or other functional module, independent of the processor 110.

The wireless communication module 160 may provide solutions for wireless communication including wireless local area network (wireless local area networks, WLAN) (e.g., wireless fidelity (wireless fidelity, wi-Fi) network), bluetooth (BT), global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field wireless communication technology (near field communication, NFC), infrared technology (IR), etc. applied on the terminal device. The wireless communication module 160 may be one or more devices that integrate at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, modulates the electromagnetic wave signals, filters the electromagnetic wave signals, and transmits the processed signals to the processor 110. The wireless communication module 160 may also receive a signal to be transmitted from the processor 110, frequency modulate it, amplify it, and convert it to electromagnetic waves for radiation via the antenna 2.

In some embodiments, the antenna 1 of the terminal device is coupled to the mobile communication module 150 and the antenna 2 is coupled to the wireless communication module 160 so that the terminal device can communicate with the network and other devices through wireless communication technology. Wireless communication techniques may include global system for mobile communications (global system for mobile communications, GSM), general packet radio service (general packet radio service, GPRS), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (wideband code division multiple access, WCDMA), time division code division multiple access (time-division code division multiple access, TD-SCDMA), long term evolution (long term evolution, LTE), BT, GNSS, WLAN, NFC, FM, and/or IR techniques, among others. The GNSS may include a global satellite positioning system (global positioning system, GPS), a global navigation satellite system (global navigation satellite system, GLONASS), a beidou satellite navigation system (beidou navigation satellite system, BDS), a quasi zenith satellite system (quasi-zenith satellite system, QZSS) and/or a satellite based augmentation system (satellite based augmentation systems, SBAS).

The terminal device implements display functions through a GPU, a display screen 194, an application processor, and the like. The GPU is a microprocessor for image processing, and is connected to the display 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

The display screen 194 is used for displaying images, displaying videos, receiving sliding operations, and the like. The display 194 includes a display panel. The display panel may employ a liquid crystal display (liquid crystal display, LCD), an organic light-emitting diode (OLED), an active-matrix organic light emitting diod (AMOLED), a flexible light-emitting diode (flex), a mini, a Micro-OLED, a quantum dot light-emitting diode (quantum dot light emitting diodes, QLED), or the like. In some embodiments, the terminal device may include 1 or N display screens 194, N being a positive integer greater than 1.

The terminal device may implement photographing functions through an ISP, a camera 193, a video codec, a GPU, a display screen 194, an application processor, and the like.

The ISP is used to process data fed back by the camera 193. For example, when photographing, the shutter is opened, light is transmitted to the camera photosensitive element through the lens, the optical signal is converted into an electrical signal, and the camera photosensitive element transmits the electrical signal to the ISP for processing, so that the electrical signal is converted into an image visible to naked eyes. ISP can also optimize the noise, brightness and skin color of the image. The ISP can also optimize parameters such as exposure, color temperature and the like of a shooting scene. In some embodiments, the ISP may be provided in the camera 193.

The camera 193 is used to capture still images or video. The object generates an optical image through the lens and projects the optical image onto the photosensitive element. The photosensitive element may be a charge coupled device (charge coupled device, CCD) or a Complementary Metal Oxide Semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, which is then transferred to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV, or the like format. In some embodiments, the terminal device may include 1 or N cameras 193, N being a positive integer greater than 1.

The digital signal processor is used for processing digital signals, and can process other digital signals besides digital image signals. For example, when the terminal device selects a frequency bin, the digital signal processor is used to fourier transform the frequency bin energy, etc.

Video codecs are used to compress or decompress digital video. The terminal device may support one or more video codecs. In this way, the terminal device may play or record video in multiple encoding formats, for example: dynamic picture experts group (moving picture experts group, MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

The NPU is a neural-network (NN) computing processor, and can rapidly process input information by referencing a biological neural network structure, for example, referencing a transmission mode between human brain neurons, and can also continuously perform self-learning. Applications such as intelligent cognition of terminal equipment can be realized through NPU, for example: image recognition, face recognition, speech recognition, text understanding, etc.

The external memory interface 120 may be used to connect an external memory card, such as a Micro SD card, to realize expansion of the memory capability of the terminal device. The external memory card communicates with the processor 110 through an external memory interface 120 to implement data storage functions. For example, files such as music, video, etc. are stored in an external memory card.

The internal memory 121 may be used to store computer-executable program code that includes instructions. The internal memory 121 may include a storage program area and a storage data area. The storage program area may store an application program (such as a sound playing function, an image playing function, etc.) required for at least one function of the operating system, etc. The storage data area may store data created during use of the terminal device (such as audio data, phonebook, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory, and may further include a nonvolatile memory such as at least one magnetic disk storage device, a flash memory device, a universal flash memory (universal flash storage, UFS), and the like. The processor 110 performs various functional applications of the terminal device and data processing by executing instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor.

The terminal device may implement audio functions through an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, an application processor, and the like. Such as music playing, recording, etc.

The audio module 170 is used to convert digital audio information into an analog audio signal output and also to convert an analog audio input into a digital audio signal. The audio module 170 may also be used to encode and decode audio signals. In some embodiments, the audio module 170 may be disposed in the processor 110, or a portion of the functional modules of the audio module 170 may be disposed in the processor 110.

The speaker 170A, also referred to as a "horn," is used to convert audio electrical signals into sound signals. The terminal device can listen to music through the speaker 170A or listen to hands-free calls.

A receiver 170B, also referred to as a "earpiece", is used to convert the audio electrical signal into a sound signal. When the terminal device picks up a call or voice message, the voice can be picked up by placing the receiver 170B close to the human ear.

Microphone 170C, also referred to as a "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a call or transmitting voice information, the user can sound near the microphone 170C through the mouth, inputting a sound signal to the microphone 170C. The terminal device may be provided with at least one microphone 170C. In other embodiments, the terminal device may be provided with two microphones 170C, and may implement a noise reduction function in addition to collecting sound signals. In other embodiments, the terminal device may be further provided with three, four or more microphones 170C to collect sound signals, reduce noise, identify the source of sound, implement directional recording functions, etc.

The earphone interface 170D is used to connect a wired earphone. The headset interface 170D may be a USB interface 130 or a 3.5mm open mobile electronic device platform (open mobile terminal platform, OMTP) standard interface, a american cellular telecommunications industry association (cellular telecommunications industry association of the USA, CTIA) standard interface.

The pressure sensor 180A is used to sense a pressure signal, and may convert the pressure signal into an electrical signal. In some embodiments, the pressure sensor 180A may be disposed on the display screen 194. The pressure sensor 180A is of various types, such as a resistive pressure sensor, an inductive pressure sensor, a capacitive pressure sensor, and the like. The capacitive pressure sensor may be a capacitive pressure sensor comprising at least two parallel plates with conductive material. The capacitance between the electrodes changes when a force is applied to the pressure sensor 180A. The terminal device determines the strength of the pressure from the change in capacitance. When a touch operation is applied to the display 194, the terminal device detects the intensity of the touch operation based on the pressure sensor 180A. The terminal device may also calculate the position of the touch based on the detection signal of the pressure sensor 180A. In some embodiments, touch operations that act on the same touch location, but at different touch operation strengths, may correspond to different operation instructions.

The gyro sensor 180B may be used to determine a motion gesture of the terminal device. In some embodiments, the angular velocity of the terminal device about three axes (i.e., x, y, and z axes) may be determined by the gyro sensor 180B. The gyro sensor 180B may be used for photographing anti-shake. Illustratively, when the shutter is pressed, the gyro sensor 180B detects the shake angle of the terminal device, calculates the distance to be compensated by the lens module according to the angle, and makes the lens counteract the shake of the terminal device through the reverse motion, thereby realizing anti-shake. The gyro sensor 180B may also be used for navigating, somatosensory game scenes.

The air pressure sensor 180C is used to measure air pressure. In some embodiments, the terminal device calculates altitude from barometric pressure values measured by barometric pressure sensor 180C, aiding in positioning and navigation.

The magnetic sensor 180D includes a hall sensor. The terminal device may detect the opening and closing of the flip cover using the magnetic sensor 180D. In some embodiments, when the terminal device is a flip machine, the terminal device may detect the opening and closing of the flip according to the magnetic sensor 180D. And then according to the detected opening and closing state of the leather sheath or the opening and closing state of the flip, the characteristics of automatic unlocking of the flip and the like are set.

The acceleration sensor 180E may detect the magnitude of acceleration of the terminal device in various directions (typically three axes). The magnitude and direction of gravity can be detected when the terminal device is stationary. The method can also be used for identifying the gesture of the terminal equipment, and is applied to application programs such as horizontal and vertical screen switching, pedometers and the like.

A distance sensor 180F for measuring a distance. The terminal device may measure the distance by infrared or laser. In some embodiments, the terminal device may range using the distance sensor 180F to achieve fast focusing.

The proximity light sensor 180G may include, for example, a Light Emitting Diode (LED) and a light detector, such as a photodiode. The light emitting diode may be an infrared light emitting diode. The terminal device emits infrared light outwards through the light emitting diode. The terminal device detects infrared reflected light from nearby objects using a photodiode. When sufficient reflected light is detected, it can be determined that there is an object in the vicinity of the terminal device 100. When insufficient reflected light is detected, the terminal device may determine that there is no object in the vicinity of the terminal device. The terminal device can use the proximity light sensor 180G to detect that the user holds the terminal device close to the ear for communication, so as to automatically extinguish the screen to achieve the purpose of saving electricity. The proximity light sensor 180G may also be used in holster mode, pocket mode to automatically unlock and lock the screen.

The ambient light sensor 180L is used to sense ambient light level. The terminal device may adaptively adjust the brightness of the display 194 based on the perceived ambient light level. The ambient light sensor 180L may also be used to automatically adjust white balance when taking a photograph. The ambient light sensor 180L may also cooperate with the proximity light sensor 180G to detect if the terminal device is in a pocket to prevent false touches.

The fingerprint sensor 180H is used to collect a fingerprint. The terminal equipment can utilize the collected fingerprint characteristics to realize fingerprint unlocking, access the application lock, fingerprint photographing, fingerprint incoming call answering and the like.

The temperature sensor 180J is for detecting temperature. In some embodiments, the terminal device performs a temperature processing strategy using the temperature detected by temperature sensor 180J. For example, when the temperature reported by the temperature sensor 180J exceeds a threshold, the terminal device performs a reduction in performance of a processor located near the temperature sensor 180J in order to reduce power consumption for implementing thermal protection. In other embodiments, the terminal device heats the battery 142 when the temperature is below another threshold to avoid the terminal device from being abnormally shut down due to low temperatures. In other embodiments, when the temperature is below a further threshold, the terminal device performs boosting of the output voltage of the battery 142 to avoid abnormal shutdown caused by low temperatures.

The touch sensor 180K, also referred to as a "touch device". The touch sensor 180K may be disposed on the display screen 194, and the touch sensor 180K and the display screen 194 form a touch screen, which is also called a "touch screen". The touch sensor 180K is for detecting a touch operation acting thereon or thereabout. The touch sensor may communicate the detected touch operation to the application processor to determine the touch event type. Visual output related to touch operations may be provided through the display 194. In other embodiments, the touch sensor 180K may also be disposed on the surface of the terminal device at a different location than the display 194.

The bone conduction sensor 180M may acquire a vibration signal. In some embodiments, bone conduction sensor 180M may acquire a vibration signal of a human vocal tract vibrating bone pieces. The bone conduction sensor 180M may also contact the pulse of the human body to receive the blood pressure pulsation signal. In some embodiments, bone conduction sensor 180M may also be provided in a headset, in combination with an osteoinductive headset. The audio module 170 may parse out a voice signal based on the vibration signal of the vocal part vibration bone piece obtained by the bone conduction sensor 180M, and implement a voice function. The application processor can analyze heart rate information based on the blood pressure beat signals acquired by the bone conduction sensor 180M, so that a heart rate detection function is realized.

The keys 190 include a power-on key, a volume key, etc. The keys 190 may be mechanical keys. Or may be a touch key. The terminal device may receive key inputs, generating key signal inputs related to user settings of the terminal device and function control.

The motor 191 may generate a vibration cue. The motor 191 may be used for incoming call vibration alerting as well as for touch vibration feedback. For example, touch operations acting on different applications (e.g., photographing, audio playing, etc.) may correspond to different vibration feedback effects. The motor 191 may also correspond to different vibration feedback effects by touching different areas of the display screen 194. Different application scenarios (such as time reminding, receiving information, alarm clock, game, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect may also support customization.

The indicator 192 may be an indicator light, may be used to indicate a state of charge, a change in charge, a message indicating a missed call, a notification, etc.

The SIM card interface 195 is used to connect a SIM card. The SIM card may be contacted and separated from the terminal device by inserting the SIM card interface 195 or extracting it from the SIM card interface 195. The terminal device may support 1 or N SIM card interfaces, N being a positive integer greater than 1. The SIM card interface 195 may support Nano SIM cards, micro SIM cards, and the like. The same SIM card interface 195 may be used to insert multiple cards simultaneously. The types of the plurality of cards may be the same or different. The SIM card interface 195 may also be compatible with different types of SIM cards. The SIM card interface 195 may also be compatible with external memory cards. The terminal equipment interacts with the network through the SIM card to realize the functions of communication, data communication and the like. In some embodiments, the terminal device employs esims, namely: an embedded SIM card. The eSIM card can be embedded in the terminal device and cannot be separated from the terminal device.

For the terminal device described in fig. 1, when the user operates the terminal device pair, the terminal device may respond to the user's operation. For example, fig. 2 is a schematic structural diagram of a terminal device according to an embodiment of the present application in response to a user operation. The terminal device may be a mobile phone, as shown in an interface a in fig. 2, after the user clicks the micro-letter application icon in the interface a, the mobile phone responds to the operation of clicking the micro-letter application icon by the user, displays an interface b in fig. 2, and then the user can obtain the desired information from the interface b.

It should be understood that the user's operation may be considered to be sending an operation instruction to the terminal device, which is also referred to as a first operation instruction in the present application. It is described herein that the embodiment of the present application does not limit the specific type of operation of the user. For example, the operation may be a click operation or a biometric operation.

Next, a specific procedure of the terminal device in response to the operation of the user will be described with reference to fig. 3. As shown in fig. 3: after the user inputs the first operation instruction, as shown in fig. 3, the processor 301 in the terminal device converts the first operation instruction of the user into a command for addressing the data in the memory 302 using the first logical address, and then the processor 301 sends the first logical address to the memory 302, where the memory 302 includes a micro processing unit 3021, a static random access memory (static random access memory, SRAM) 3022 and a plurality of storage units 3023, and the SRAM includes a logical-to-physical address mapping table (also referred to as an L2P address mapping table or an L2P mapping table), and the L2P mapping table is used for converting the logical address into the physical address. Accordingly, after the memory 302 receives the first logical address, the micro-processing unit 3021 converts the first logical address into a first physical address based on the L2P mapping table in the SRAM 3022, and then accesses the storage unit indicated by the first physical address.

It is to be noted that the specific structure in the memory 302 is not limited in this embodiment. For example, a memory cell controller may also be included.

Optionally, if the first operation instruction indicates an operation that wants to read data, the operating based on the storage unit indicated by the first physical address may include: after the micro processing unit 3021 in the memory 302 obtains the first data from the first physical address, the first data is sent to the processor 301, and then the processor 301 may output and display the first data.

However, due to the limited capacity of SRAM, the L2P mapping table in current SRAM can only store the mapping relationship between logical addresses and physical addresses of a part of memory cells. In this case, when the processor 301 sends the first logical address to the memory 302, if there is no first physical address corresponding to the first logical address in the L2P table, the memory 302 needs to determine the first physical address corresponding to the first logical address based on some internal algorithm so that the storage unit indicated by the first physical address can be accessed.

Fig. 4 is a schematic diagram illustrating a memory structure of a memory according to an embodiment of the present application. As shown in fig. 4, the memory includes a memory cell 1, a memory cell 2, a memory cell 3, a memory cell 4, and a memory cell 5, until the memory cells 32768, that is, there are 32768 memory cells in total, and one memory cell can store one byte. It will be appreciated that for each of the 32768 memory cells, there is a corresponding physical address and logical address, and therefore, the L2P mapping table in SRAM should include a mapping relationship between the physical address and logical address corresponding to each of the 32768 memory cells. However, since the SRAM is a cache memory interposed between the microprocessor unit and the plurality of memory units, the read/write speed is high but the price is high, and thus the capacity of the SRAM of the memory is limited due to the limitation of hardware resources and costs, so that the L2P mapping table included in the current SRAM can only store the mapping relationship of the logical address and the physical address of a part of the memory units. For example, the mapping relationship between the physical addresses and the physical addresses corresponding to the storage units 1 to 15000 is stored, so, if the processor converts a certain operation instruction of the user into a command for addressing the data in the memory chip by using the logical address, if the logical address corresponding to the operation instruction is the logical address corresponding to the storage unit 20000, but the mapping relationship between the logical address and the physical address of the storage unit 20000 is not included in the L2P mapping table, in this case, the memory needs to determine the first physical address corresponding to the first logical address based on some internal algorithm, and operate the storage unit indicated by the first target physical address.

Therefore, in the method, the access of the terminal equipment to the storage unit depends on the internal algorithm implementation of the memory, so that the time for the terminal equipment to respond to the operation instruction is longer, and the user experience is poor.

In view of this, an embodiment of the present application provides a method for accessing a memory cell. The method may be performed by a terminal device, which may be a mobile phone, for example.

As shown in fig. 5, the method 500 may include the steps of:

s501, receiving a first operation instruction input by a user.

It should be understood that the user's operation may be considered as sending an operation instruction, also referred to as a first operation instruction in the present application, to the terminal device, and accordingly, the terminal device receives the first operation instruction and operates in response to the first operation instruction.

The user may send the first operation instruction to the terminal device by clicking the application program, for example. As shown in fig. 2, after the user clicks the micro-letter application icon in the interface a, the mobile phone responds to the operation of clicking the micro-letter application icon by the user to display the interface b in fig. 2, and then the user can obtain corresponding information from the interface b.

The user may send the first operation instruction to the terminal device by clicking an icon in the interface after entering the application program, for example. For example, as shown in fig. 6, the user may click my in the c interface, the mobile phone displays the d interface in fig. 6 in response to the user clicking my icon, and the user may obtain corresponding information from the d interface.

In this embodiment, the first operation instruction received from the user specifically refers to that the processor in the terminal device receives the first operation instruction.

S502, determining a first logical address corresponding to the first operation instruction.

The terminal device includes a processor and a memory.

In this embodiment, a first logical-to-physical L2P address mapping table is stored in the processor. The first L2P address mapping table includes a mapping relationship between a physical address and a logical address of a first storage space in the memory.

In one implementation, the first memory space in this example includes all of the memory space in the memory. In other words, in this embodiment, the first L2P address mapping table includes a mapping relationship between a physical address and a logical address of each storage unit in the memory. For example, assuming that the memory includes 32768 memory cells, the first L2P address mapping table includes a mapping relationship between a physical address and a logical address of each of the 32768 memory cells.

In another embodiment, the first memory space comprises a portion of memory space in the memory. In this case, a second L2P address mapping table may also be stored in the memory, where the second L2P address mapping table includes a mapping relationship between a physical address and a logical address of a second storage space in the memory, where the second storage space is a storage space other than the first storage space in all storage spaces of the memory. That is, in this embodiment, an L2P address mapping table (i.e., a first L2P address mapping table) is included in the processor, an L2P address mapping table (i.e., a second L2P address mapping table) is included in the memory, the first L2P address mapping table includes a mapping relationship between a physical address and a logical address of each storage unit in a portion of the storage space in the memory, and the second L2P address mapping table includes a mapping relationship between a physical address and a logical address of each storage unit in another portion of the storage space in the memory. For example, taking the above memory including 32768 memory cells as an example, in this embodiment, the mapping relationship between the physical address and the logical address of one portion of the memory cells may be put into the memory, and the mapping relationship between the physical address and the logical address of another portion of the memory cells may be put into the processor.

In the present application, the terminal device receiving the first operation instruction specifically means that a processor in the terminal device receives the first operation instruction. In this embodiment, after the processor receives the first operation instruction, the processor may determine a logical address corresponding to the first operation instruction, which is also referred to as a first logical address. The detailed implementation process of how the processor determines the logical address based on the operation instruction input by the user may refer to the description in the related art, and will not be described herein.

S503, acquiring a first physical address corresponding to the first logical address based on the first L2P address mapping table.

In this embodiment, after the processor in the terminal device determines the first logical address based on the first operation instruction, the physical address corresponding to the first logical address may be obtained based on the first L2P address mapping table in the processor, which is also referred to as the first physical address. It may also be said that, after the processor determines the first logical address based on the first operation instruction, a physical address having a mapping relationship with the first logical address, that is, the first physical address, may be obtained from the first L2P address mapping table in the processor.

S504, accessing the storage space indicated by the first physical address.

Specifically, when the processor obtains the first physical address corresponding to the first logical address based on the first L2P address mapping table, the first physical address is sent to the memory, and then the memory finds a memory space indicated by the first physical address from all the memory spaces, and accesses the memory space, for example, performs a read operation or a write operation on the memory space.

In this embodiment, after the terminal device receives the first operation instruction and determines the first logical address corresponding to the first operation instruction, the first physical address corresponding to the first logical address may be obtained directly based on the first L2P address mapping table in the processor. It can be appreciated that in this implementation, since the processing rate of the processor is generally greater than the storage rate in the memory, the duration of accessing the storage space indicated by the first physical address is advantageously shortened, thereby facilitating improvement of user experience.

Furthermore, it can be further understood that, in the prior art, if there is no first physical address corresponding to the first logical address in the L2P mapping table in the memory, the terminal device obtains the mapping relationship between the first logical address and the first physical address based on a series of algorithms, which results in a relatively long time. In the technical scheme, the mapping relation between the first logical address and the first physical address which are not stored in the memory is stored in the processor, so that the mapping relation between the first logical address and the first physical address is not required to be obtained based on a series of algorithms, and the method is beneficial to shortening the time length when the memory space indicated by the first physical address is accessed, and is beneficial to improving the user experience.

In the present application, the first L2P address mapping table is also referred to as a first L2P mapping table, and the second L2P address mapping table is also referred to as a second L2P mapping table.

Optionally, in the present application, when the processor includes a mapping relationship between a physical address and a logical address of a part of a storage space in the memory (i.e., the processor includes a first L2P mapping table), and the processor includes a mapping relationship between a physical address and a logical address of another part of a storage space in the memory (i.e., the memory includes a second L2P mapping table), after receiving the first operation instruction and determining the first logical address, the processor in the terminal device in this embodiment may first determine whether the second L2P mapping table includes a first physical address corresponding to the first logical address, and then, after determining that the second L2P mapping table does not include the first physical address corresponding to the first logical address, acquire the first physical address corresponding to the first logical address based on the first L2P mapping table.

It should be understood that in the prior art, if there is no first logical address in the L2P mapping table (i.e., the second L2P mapping table) in the memory, the terminal device may obtain the mapping relationship between the first logical address and the first physical address based on a series of algorithms, resulting in a relatively long time. However, in this implementation, when the first physical address corresponding to the first logical address is not found in the memory, the first physical address is found in the first L2P mapping table in the processor, so that no additional algorithm is required to be performed, and in general, the mapping relationship between the first logical address and the first physical address obtained based on a series of algorithms may be longer than the duration of the first physical address found in the processor when the terminal device cannot find the first physical address in the memory, which is helpful for shortening the duration of accessing the storage space indicated by the first physical address, thereby helping to improve the user experience.

Optionally, in the present application, when the processor includes a mapping relationship between a physical address and a logical address of a part of a storage space in the memory (i.e., the processor includes a first L2P mapping table), and when the processor includes a mapping relationship between a physical address and a logical address of another part of a storage space in the memory (i.e., the memory includes a second L2P mapping table), after receiving an operation instruction input by a user, the processor in the terminal device is also referred to as a second operation instruction in the present application, if the processor in the terminal device determines that the processor in the terminal device has no second physical address corresponding to the second logical address after determining the second logical address corresponding to the second operation instruction, then the terminal device obtains the second physical address corresponding to the second logical address from the second L2P mapping table in the memory, and then accesses the storage space indicated by the second physical address.

In this implementation manner, after the terminal device receives the second operation instruction and determines the second logical address corresponding to the second operation instruction, if the second physical address corresponding to the second logical address is not found based on the first L2P mapping table in the processor, the terminal device will search from the second L2P mapping table in the memory, so as to achieve access to the storage unit indicated by the second physical address.

For ease of understanding, taking the example that the first storage space includes all storage spaces in the memory, that is, taking the example that the processor includes a first L2P mapping table, where the first L2P mapping table includes a mapping relationship between a physical address and a logical address of each storage unit in the memory, an architecture diagram of accessing the memory and an internal implementation method of the terminal device in the embodiment of the present application are described. In this embodiment, the first L2P mapping table is also referred to as a full L2P mapping table.

As shown in fig. 7, in this embodiment, the full L2P mapping table stored in the processor includes the mapping relationship between the logical addresses and the physical addresses of the whole storage space of the memory.

Specifically, as shown in fig. 8, the internal implementation process includes:

s801, the processor receives a first operation instruction input by a user.

For example, the processor 701 in fig. 7 receives a first operation instruction input by a user.

S802, the processor determines a first logical address corresponding to the first operation instruction.

For example, the processor 701 in fig. 7 determines a first logical address corresponding to the first operation instruction.

S803, the processor obtains a first physical address corresponding to a first logical address based on a first L2P address mapping table, wherein the first L2P address mapping table comprises mapping relations between physical addresses and logical addresses of each storage space in the memory.

For example, the processor 701 in fig. 7 obtains a first physical address corresponding to a first logical address based on a first L2P address mapping table.

S804, the processor sends the first physical address to the memory.

For example, the processor 701 in fig. 7 sends a first physical address to the memory 702.

S805, the memory accesses the storage space indicated by the first physical address.

Specifically, the microprocessor unit 7021 in the memory 702 receives the first physical address and accesses the storage space (the storage unit 7023 in fig. 7).

In this embodiment, the memory cell may further include more structures, for example, the SRAM 7022 or the memory cell controller shown in fig. 7 is also included.

The method provided by the embodiment of the present application is described in detail above with reference to fig. 1 to 8, and the terminal device provided by the embodiment of the present application will be described in detail below with reference to fig. 9 and 10.

Fig. 9 shows an access device provided by an embodiment of the present application, where the access device is applied to a terminal device, and the terminal device includes a processor and a memory, where a first logical-to-physical L2P address mapping table is stored in the processor, and the first L2P address mapping table includes a mapping relationship between a physical address and a logical address of a first storage space in the memory, and the access device includes: the transceiver module 901 is configured to receive a first operation instruction input by a user; a first processing module 902, configured to determine a first logical address corresponding to the first operation instruction; the first processing module 902 is further configured to obtain a first physical address corresponding to the first logical address based on the first L2P address mapping table; the first processing module 902 is further configured to access the storage space indicated by the first physical address.

Optionally, the first storage space includes all storage spaces in the memory.

Optionally, the first storage space includes a part of storage space in the memory, the memory stores a second L2P address mapping table, the second L2P address mapping table includes a mapping relationship between a physical address and a logical address of the second storage space in the memory, and the second storage space is a storage space except the first storage space in all storage spaces in the memory.

Optionally, the transceiver module 901 is further configured to: receiving a second operation instruction input by a user; the first processing module 902 is further configured to: determining a second logical address corresponding to the second operation instruction; determining whether a second physical address corresponding to the second logical address is included in the first L2P address mapping table; if the first L2P address mapping table does not have the second physical address corresponding to the second logical address, acquiring the second physical address corresponding to the second logical address based on the second L2P address mapping table; and accessing the storage space indicated by the second physical address.

Optionally, the first processing module 902 is further configured to: determining whether a first physical address corresponding to the first logical address is included in the second L2P address mapping table; if the second L2P address mapping table does not have the first physical address corresponding to the first logical address, the first physical address corresponding to the first logical address is acquired based on the first L2P address mapping table.

Optionally, the first processing module 902 is further configured to: the control transceiver module 901 sends a first physical address to the memory; the apparatus further includes a second processing module 903, where the second processing module 903 is configured to access the storage space indicated by the first physical address after the memory receives the first physical address.

It should be understood that the access means shown in fig. 9 are embodied in the form of functional modules. The term module herein may refer to an application specific integrated circuit (application specific integrated circuit, ASIC), an electronic circuit, a processor (e.g., a shared, dedicated, or group processor, etc.) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that support the described functionality. In an alternative example, it will be understood by those skilled in the art that the access device shown in fig. 9 may be specifically a terminal device in the foregoing method embodiment, or the access device shown in fig. 9 may be used to execute each flow and/or step corresponding to the terminal device in the foregoing method embodiment, which is not repeated herein.

The access device shown in fig. 9 has a function of implementing the corresponding steps executed by the terminal device in the method embodiment; the above functions may be implemented by hardware, or may be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the functions described above.

In an embodiment of the present application, the access device shown in fig. 9 may also be a chip or a chip system, for example: system on chip (SoC).

Fig. 10 is a schematic block diagram of a terminal device 1000 according to an embodiment of the present application. The terminal device 1000 includes a processor 1010, a communication interface 1020 and a memory 1030. Wherein the processor 1010, the communication interface 1020 and the memory 1030 are in communication with each other via an internal connection path, the memory 1030 is configured to store instructions, and the processor 1010 is configured to execute the instructions stored in the memory 1030 to control the communication interface 1020 to transmit signals and/or receive signals.

It should be understood that terminal device 1000 may be specifically a terminal device in the above-described method embodiment, or the functions of the terminal device in the above-described method embodiment may be integrated in terminal device 1000, and terminal device 1000 may be configured to perform each step and/or flow corresponding to the terminal device in the above-described method embodiment. The memory 1030 may optionally include read-only memory and random access memory, and provide instructions and data to the processor. A portion of the memory may also include non-volatile random access memory. For example, the memory may also store information of the device type. The processor 1010 may be configured to execute instructions stored in the memory, and when the processor executes the instructions, the processor may perform steps and/or flows corresponding to the terminal device in the above-described method embodiments.

It is to be appreciated that in embodiments of the application, the processor 1010 may be a central processing unit (central processing unit, CPU), which may also be other general purpose processors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in the processor for execution. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor executes instructions in the memory to perform the steps of the method described above in conjunction with its hardware. To avoid repetition, a detailed description is not provided herein.

The application also provides a computer readable storage medium for storing a computer program for implementing the method corresponding to the terminal device in the method embodiment.

The application also provides a chip system which is used for supporting the terminal equipment to realize the functions shown in the embodiment of the application in the embodiment of the method.

The present application also provides a computer program product comprising a computer program (which may also be referred to as code, or instructions) which, when run on a computer, is adapted to perform the method corresponding to the terminal device shown in the above-mentioned method embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system, apparatus and module may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.

The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely a specific implementation of the present application, but the scope of the embodiments of the present application is not limited thereto, and any person skilled in the art may easily think about changes or substitutions within the technical scope of the embodiments of the present application, and all changes and substitutions are included in the scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.

Claims

1. The access method of the storage unit is characterized by being applied to terminal equipment, wherein the terminal equipment comprises a processor and a memory, a first logic-to-physical L2P address mapping table is stored in the processor, the first logic-to-physical L2P address mapping table comprises a mapping relation between a physical address and a logical address of a first storage space in the memory, and the method comprises the following steps:

wherein the first storage space comprises a part of storage space in the memory; the memory stores a second logical-to-physical L2P address mapping table, wherein the second logical-to-physical L2P address mapping table comprises a mapping relation between a physical address and a logical address of a second storage space in the memory, and the second storage space is a storage space except the first storage space in all storage spaces in the memory;

receiving a second operation instruction input by a user;

determining a second logical address corresponding to the second operation instruction;

determining whether a second physical address corresponding to the second logical address is included in the first logical-to-physical L2P address mapping table;

if the first logical-to-physical L2P address mapping table does not have the second physical address corresponding to the second logical address, acquiring the second physical address corresponding to the second logical address based on the second logical-to-physical L2P address mapping table;

And accessing the storage space indicated by the second physical address.

2. The method according to claim 1, wherein the method further comprises:

receiving a first operation instruction input by a user;

determining a first logic address corresponding to the first operation instruction;

determining whether a first physical address corresponding to the first logical address is included in the second logical-to-physical (L2P) address mapping table;

acquiring a first physical address corresponding to the first logical address based on the first logical-to-physical (L2P) address mapping table;

accessing a storage space indicated by the first physical address;

the obtaining, based on the first logical-to-physical L2P address mapping table, a first physical address corresponding to the first logical address includes:

and if the first physical address corresponding to the first logical address does not exist in the second logical-to-physical (L2P) address mapping table, acquiring the first physical address corresponding to the first logical address based on the first logical-to-physical (L2P) address mapping table.

3. The method of claim 2, wherein the receiving a first operation instruction input by a user, the determining a first logical address corresponding to the first operation instruction, and the obtaining, based on the first logical-to-physical L2P address mapping table, a first physical address corresponding to the first logical address are performed by the processor;

The accessing the storage space indicated by the first physical address includes:

the processor sending the first physical address to the memory;

and after the memory receives the first physical address, accessing a memory space indicated by the first physical address.

4. A device for accessing a memory unit, characterized in that the device comprises means for performing the method according to any of claims 1 to 3.

5. A terminal device, comprising: a processor coupled to a memory for storing a computer program which, when invoked by the processor, causes the terminal device to perform the method of any one of claims 1 to 3.

6. A computer readable storage medium storing a computer program comprising instructions for implementing the method of any one of claims 1 to 3.