CN117667814A

CN117667814A - I2C data reading and writing method, device, equipment and computer readable medium

Info

Publication number: CN117667814A
Application number: CN202311464259.7A
Authority: CN
Inventors: 王明亮
Original assignee: Zhejiang Cambridge Communication Equipment Co ltd; CIG Shanghai Co Ltd
Current assignee: Zhejiang Cambridge Communication Equipment Co ltd; CIG Shanghai Co Ltd
Priority date: 2023-11-06
Filing date: 2023-11-06
Publication date: 2024-03-08

Abstract

The application provides a method, a device, equipment and a computer readable medium for reading and writing I2C data. The method can be at least used for solving the technical problem that the waveform discrimination efficiency of a plurality of slaves is low in the existing I2C circuit; sequentially associating a master computer with a plurality of slave computers along the wire path; based on a host computer and a plurality of slaves adjacent to the host computer, constructing a corresponding read-write area; the host outputs a low-level signal of the TEST N, and determines that a time period of the low-level signal of the TEST N is a time period of a read-write area of an Mth slave adjacent to the host; according to the time period of the low level signal of the TEST N, data reading and writing are carried out on the reading and writing area of the M-th slave machine; the N and the M are integers which are larger than or equal to 1, the N and the M are equal, the I2C data can be tested later, and the read-write area of the Mth slave machine can be quickly found according to a low-level signal of the TEST N, so that the testing efficiency of the I2C waveform is improved.

Description

I2C data reading and writing method, device, equipment and computer readable medium

Technical Field

The present disclosure relates to the field of I2C data technologies, and in particular, to a method, an apparatus, a device, and a computer readable medium for reading and writing I2C data.

Background

With the development of technology, the I2C circuit is widely used in various industries of life. In the related art, a plurality of slaves are often hung on a bus of an I2C circuit, when testing the I2C bus waveform, a relevant worker often does not know which slave corresponds to the measured waveform, so that the worker needs to manually read data of each byte of the waveform, then find the waveform of the slave address through a manual comparison mode, and further judge which slave corresponds to the measured waveform, however, in the related art, the process of judging which slave corresponds to the measured waveform through the manual comparison mode is time-consuming and labor-consuming, and the judging efficiency of the waveforms of the plurality of slaves is low.

Disclosure of Invention

An object of the present application is to provide a method, an apparatus, a device, and a computer readable medium for reading and writing I2C data, which are at least used for solving a technical problem that waveform discrimination efficiency of a plurality of slaves is low in an existing I2C circuit.

To achieve the above object, some embodiments of the present application provide a method for reading and writing I2C data, which is applied to an I2C circuit, where the method for reading and writing I2C data includes: sequentially associating a master computer with a plurality of slave computers along the wire path; based on a host computer and a plurality of slaves adjacent to the host computer, constructing a corresponding read-write area; the host outputs a low-level signal of the TEST N, and determines that a time period of the low-level signal of the TEST N is a time period of a read-write area of an Mth slave adjacent to the host; according to the time period of the low level signal of the TEST N, data reading and writing are carried out on the reading and writing area of the M-th slave machine; wherein, N and M are integers greater than or equal to 1, and N and M are equal.

Some embodiments of the present application further provide an I2C data read-write device, including: the association module is used for sequentially associating one host machine with a plurality of slave machines along the wire path; the area module is used for constructing a corresponding read-write area based on a host computer and a plurality of slaves adjacent to the host computer; the acquisition module is used for outputting a low-level signal of the TEST N by the host and determining that the time period of the low-level signal of the TEST N is the time period of the read-write area of the Mth slave adjacent to the host; the reading module is used for reading and writing data in the reading and writing area of the M-th slave machine according to the time period when the low-level signal of the TEST N appears; wherein, N and M are integers greater than or equal to 1, and N and M are equal.

Some embodiments of the present application further provide an I2C data reading and writing device, including: one or more processors; the I2C data circuit comprises a host computer and a plurality of slaves; sequentially associating a master computer with a plurality of slave computers along the wire path; and a memory storing computer program instructions that, when executed, cause the processor to perform the method of reading and writing I2C data described above.

Some embodiments of the present application also provide a computer readable medium having stored thereon computer program instructions executable by a processor to implement the above-described I2C data read-write method.

Compared with the prior art, in the scheme provided by the embodiment of the application, one host machine and a plurality of slave machines are sequentially associated along the wire path; based on a host computer and a plurality of slaves adjacent to the host computer, constructing a corresponding read-write area; the host outputs a low-level signal of the TEST N, and determines that a time period of the low-level signal of the TEST N is a time period of a read-write area of an Mth slave adjacent to the host; according to the time period of the low level signal of the TEST N, data reading and writing are carried out on the reading and writing area of the M-th slave machine; the N and the M are integers which are larger than or equal to 1, the N and the M are equal, the I2C data can be tested later, and the read-write area of the Mth slave machine can be quickly found according to a low-level signal of the TEST N, so that the testing efficiency of the I2C waveform is improved.

Drawings

Fig. 1 is a schematic flow chart of a method for reading and writing I2C data according to an embodiment of the present application;

FIG. 2 shows a flow chart of S110 in FIG. 1;

FIG. 3 shows a flowchart of S120 in FIG. 1;

FIG. 4 shows a flowchart of S130 in FIG. 1;

fig. 5 shows a flowchart of S140 in fig. 1;

fig. 6 is an actual circuit diagram of a method for reading and writing I2C data according to an embodiment of the present application;

FIG. 7 is a schematic diagram corresponding to FIG. 6;

FIG. 8 illustrates a block diagram of an I2C data read-write device according to one embodiment of the present application;

fig. 9 is a schematic structural diagram of an I2C data read-write device according to an embodiment of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

Referring to fig. 1 to 7, the embodiment of the present application further provides a method for reading and writing I2C data, which is applied to an I2C circuit, where the method for reading and writing I2C data includes:

step S110, sequentially associating a master computer with a plurality of slave computers along the wire path;

step S120, based on a host computer and a plurality of slaves adjacent to the host computer, constructing a corresponding read-write area;

step S130, the host outputs a low level signal of the TEST N, and determines that a time period of the low level signal of the TEST N is a time period of a read-write area of an Mth slave adjacent to the host;

step S140, performing data reading and writing on the reading and writing area of the mth slave according to the period of time when the low level signal of the TEST N appears; wherein, N and M are integers greater than or equal to 1, and N and M are equal.

In the scheme provided by the embodiment of the application, a host machine and a plurality of slave machines are sequentially associated along an electric wire path; based on a host computer and a plurality of slaves adjacent to the host computer, constructing a corresponding read-write area; the host outputs a low-level signal of the TEST N, and determines that a time period of the low-level signal of the TEST N is a time period of a read-write area of an Mth slave adjacent to the host; according to the time period of the low level signal of the TEST N, data reading and writing are carried out on the reading and writing area of the M-th slave machine; the N and the M are integers which are larger than or equal to 1, the N and the M are equal, the I2C data can be tested later, and the read-write area of the Mth slave machine can be rapidly found according to a low-level signal of the TEST N, so that the testing efficiency of the I2C waveform is improved.

In step S110, one master and a plurality of slaves are sequentially associated along the wire path.

In the embodiment of the application, one host computer and a plurality of slaves are ordered based on the wire path, and the slaves are ordered from the one host computer, and the slaves can be respectively provided with corresponding numbers so as to sequentially associate the one host computer and the slaves adjacent to the host computer along the wire path, thereby realizing association between the one host computer and the slaves so as to further control a read-write area formed between the one host computer and the slaves. It is understood that the plurality of slaves is at least two slaves.

Specifically, in some embodiments of the present application, the step S110 may specifically include the following steps:

step S111, obtaining an electric wire path;

in the embodiment of the application, the electric wires in the I2C-based circuit are acquired, and the electric wires are traversed in sequence according to the electric wires so as to determine the electric wire paths, so that the acquisition of the electric wire paths is realized. In this process, one master and a plurality of slaves may be sequentially ordered according to the wire path.

Step S112, setting a master computer point and a plurality of slave computer points for the wire path;

step S113, configuring a host according to a host point, and configuring corresponding slaves by a plurality of slave points;

in the embodiment of the application, a mark can be performed in the wire path, and one master point and a plurality of slave points are arranged in the wire path, so that the master point corresponds to the master, the plurality of slave points correspond to the plurality of slaves, and the master and the plurality of slaves are sequentially associated in the wire, so that the position relationship between the master and the plurality of slaves is determined.

In some embodiments of the present application, the configuring a master according to a master point, and configuring corresponding slaves by a plurality of slave points may include: acquiring a host point; configuring a host based on a host point, and associating two wires with the host; setting a plurality of slave points based on two wires; and configuring corresponding slaves at a plurality of slave points, wherein one slave is electrically connected with two wires at the same time, so that the master is sequentially associated with the slaves according to the two wires.

Step S114, sequentially associating a master machine with a plurality of slave machines based on the wire path.

In the embodiment of the application, one host computer and a plurality of slave computers are sequentially associated based on the wire path, and the host computer and the slave computers are sequentially connected through wires, so that a read-write area between the host computer and the slave computers is determined, and subsequent read-write operation on the read-write area is facilitated.

In step S120, a corresponding read/write area is constructed based on the master and a plurality of slaves adjacent to the master.

In the embodiment of the present application, after the position of the host and the position of one slave adjacent to the host are acquired, the position of the host is taken as a starting point, and a plurality of slaves are marked along the wire path, and then an initial area is built based on the position of the host and the position of the target slave adjacent to the host, and further a read-write area corresponding to the plurality of slaves is built in sequence according to the initial area and the mark, so that the response to the read-write area where the low level is located is facilitated.

Specifically, in some embodiments of the present application, the step S120 may specifically include the following steps

Step S121, acquiring the position of a host computer and the position of a slave computer adjacent to the host computer;

step S122, marking a plurality of slaves along the wire path by taking the position of the master as a starting point;

in the embodiment of the application, the position of the host and the position of one slave adjacent to the host are obtained, and the position of the host and the position of one slave adjacent to the host are marked so as to take the position of the host as a starting point and mark a plurality of slaves along the wire path, thereby realizing the marks of a plurality of slaves and further realizing the marks of a plurality of read-write areas. Wherein in some examples, assuming that the plurality of slaves includes 6 slaves, respectively, the 6 slaves may be marked as slave 1, slave 2, slave 3, slave 4, slave 5, slave 6 in that order. In some other examples, the steps of labeling the slaves are not limited to using numerical labels, such as, for example, letters, combinations of numbers and letters, etc., and the embodiments are not specifically limited in this regard.

Step S123, constructing a starting area based on the position of the host and the position of the target slave adjacent to the host;

step S124, sequentially constructing a plurality of read-write areas corresponding to the slaves according to the initial area and the labels.

In an embodiment of the present application, a starting area is constructed based on a location of a master and a location of a target slave adjacent to the master, wherein the target slave is any one of a plurality of slaves and may be numbered according to a wire path. Specifically, a plurality of read-write areas corresponding to the slaves can be sequentially constructed according to the starting area and the labels. It should be noted that the number of the start areas is 1, and the start areas are read-write areas corresponding to the first low-level signal.

In step S130, the master outputs a low level signal of TEST N, and determines a period of time in which the low level signal of TEST N exists as a period of time in a read/write area of an mth slave adjacent to the master.

Specifically, in some embodiments of the present application, the step S130 may specifically include the following steps:

step S131, obtaining a low-level signal of a host output TEST N and a time period in which the low-level signal of the TEST N is located;

step S132, the time period of the low level signal of the output TEST N of the host computer is matched with the time period of the read-write area of the M-th slave computer;

in the embodiment of the application, the low level signal of the host output TEST N and the time period of the low level signal of the TEST N are acquired so as to match the time period of the read-write area of the mth slave based on the time period of the low level signal of the host output TEST N. As shown in fig. 6 and 7, when TEST1 is set low, the slave 1 performs reading or writing; when TEST2 is set low, the slave 2 reads or writes; and so on, when TEST N is set low, slave M reads or writes. Therefore, when testing the I2C waveform, the slave only needs to TEST according to the low level signal of the corresponding TEST N, and at the moment, the rising edge or the falling edge of the TEST N signal can be triggered once, so that the I2C waveform of the corresponding slave can be grabbed.

In step S140, data is read from and written to the read/write area of the mth slave according to the period of time when the low level signal of the TEST N appears.

Specifically, in some embodiments of the present application, the step S140 may specifically include the following steps:

step S141, determining the sequence of the read-write areas of a plurality of slaves according to the time sequence of the low level signals of the initial area and the TEST N;

step S142, according to the sequence of the read-write areas of the plurality of slaves, performing data read-write on the read-write areas of the plurality of slaves, wherein a starting area is used as a data read-write starting point;

after the data read/write is performed on the read/write area of the mth slave machine according to the period of time when the low level signal of the TEST N appears, the method may further include: testing the I2C data; the method for performing the test comprises the following steps: a rising edge or a falling edge of the one-shot TEST N signal; determining a low level signal of the TEST N signal based on a rising edge or a falling edge of the TEST N signal; the time period of the low level signal of the TEST N signal is the time period of the I2C data read/write area of the mth slave. In some examples, an oscilloscope may be used to trigger a rising or falling edge of the TEST N signal once. However, in some other examples, other relevant devices that can trigger the rising edge or the falling edge of the TEST N signal may be used, which is not specifically limited in the embodiments of the present application.

Referring to fig. 8, some embodiments of the present application further provide an I2C data read-write apparatus 200, where the apparatus 200 may include:

an association module 210, configured to sequentially associate one master machine with a plurality of slave machines along the wire path;

the area module 220 is configured to construct a corresponding read-write area based on a host and a plurality of slaves adjacent to the host;

an acquisition module 230, configured to output a low level signal of TEST N by a host, and determine a period of time when the low level signal of TEST N exists as a period of time of a read-write area of an mth slave adjacent to the host;

a read-write module 240, configured to read and write data in a read-write area of the mth slave according to a period of time when the low level signal of the TEST N appears; wherein, N and M are integers greater than or equal to 1, and N and M are equal.

In addition, the embodiment of the application further provides an I2C data reading and writing device, and the structure of the device may be as shown in fig. 9, where the device includes a memory 31 for storing computer readable instructions and a processor 32 for executing the computer readable instructions, where the computer readable instructions when executed by the processor trigger the processor to execute the I2C data reading and writing method. The I2C data reading and writing equipment further comprises an I2C data circuit, wherein the I2C data circuit comprises a host computer and a plurality of slaves; one master is associated with a plurality of slaves in sequence along the wire path.

The methods and/or embodiments of the present application may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts. The above-described functions defined in the method of the present application are performed when the computer program is executed by a processing unit.

It should be noted that, the computer readable medium described in the present application may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

In the present application, however, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations of the present application may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

The flowchart or block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of devices, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

As another aspect, the present application also provides a computer-readable medium, which may be contained in the apparatus described in the above embodiments; or may be present alone without being fitted into the device. The computer readable medium carries one or more computer readable instructions executable by a processor to implement the steps of the methods and/or techniques of the various embodiments of the present application described above.

In a typical configuration of the present application, the terminals, the devices of the services network each include one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.

Computer-readable media include both permanent and non-permanent, removable and non-removable media, and information storage may be implemented by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape storage or other magnetic storage devices, or any other non-transmission medium which can be used to store information that can be accessed by a computing device.

In addition, the embodiment of the application also provides a computer program which is stored in the computer equipment, so that the computer equipment executes the method for executing the control code.

It should be noted that the present application may be implemented in software and/or a combination of software and hardware, for example, using Application Specific Integrated Circuits (ASIC), a general purpose computer or any other similar hardware device. In some embodiments, the software programs of the present application may be executed by a processor to implement the above steps or functions. Likewise, the software programs of the present application (including associated data structures) may be stored on a computer readable recording medium, such as RAM memory, magnetic or optical drive or diskette and the like. In addition, some steps or functions of the present application may be implemented in hardware, for example, as circuitry that cooperates with the processor to perform various steps or functions.

It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is evident that the word "comprising" does not exclude other elements or steps, and that the singular does not exclude a plurality. A plurality of units or means recited in the apparatus claims can also be implemented by means of one unit or means in software or hardware. The terms first, second, etc. are used to denote a name, but not any particular order.

Claims

1. The I2C data reading and writing method is characterized by being applied to an I2C circuit, and the I2C data reading and writing method comprises the following steps:

sequentially associating a master computer with a plurality of slave computers along the wire path;

based on a host computer and a plurality of slaves adjacent to the host computer, constructing a corresponding read-write area;

the host outputs a low-level signal of the TEST N, and determines that a time period of the low-level signal of the TEST N is a time period of a read-write area of an Mth slave adjacent to the host;

according to the time period of the low level signal of the TEST N, data reading and writing are carried out on the reading and writing area of the M-th slave machine; wherein, N and M are integers greater than or equal to 1, and N and M are equal.

2. The method for reading and writing I2C data according to claim 1, wherein the sequentially associating a master computer with a plurality of slave computers along the wire path includes:

acquiring a wire path;

setting a wire path to a master computer point and a plurality of slave computer points;

configuring a host according to a host point, and configuring corresponding slaves by a plurality of slave points;

one master is sequentially associated with a plurality of slaves based on the wire path.

3. The method for reading and writing I2C data according to claim 2, wherein said configuring a host according to a host point and configuring corresponding slaves by a plurality of slave points includes:

acquiring a host point;

configuring a host based on a host point, and associating two wires with the host;

setting a plurality of slave points based on two wires;

and configuring corresponding slaves at a plurality of slave points, wherein one slave is electrically connected with two wires at the same time, so that the master is sequentially associated with the slaves according to the two wires.

4. The method for reading and writing I2C data according to claim 1, wherein the constructing a corresponding read-write area based on a master and a plurality of slaves adjacent to the master includes:

acquiring the position of a host and the position of a slave adjacent to the host;

marking a plurality of slaves along the wire path with the position of the master as a starting point;

constructing a starting area based on the position of the host and the position of a target slave adjacent to the host;

and sequentially constructing a plurality of read-write areas corresponding to the slaves according to the starting area and the labels.

5. The method according to claim 1, wherein the host outputs a low level signal of TEST N and determines a period of time in which the low level signal of TEST N exists as a period of time in a read/write area of an mth slave adjacent to the host, comprising:

acquiring a low-level signal of a host output TEST N and a time period in which the low-level signal of the TEST N is positioned;

the period of time in which the low level signal of TEST N is output based on the master matches the period of time of the read-write area of the mth slave.

6. The method for reading and writing I2C data according to claim 4, wherein the step of reading and writing data from and to the read and write area of the mth slave according to a period of time when the low level signal of the TEST N occurs includes:

determining the sequence of the read-write areas of a plurality of slaves according to the time sequence of the occurrence of the low-level signals of the initial area and the TEST N;

and according to the sequence of the read-write areas of the plurality of slaves, performing data read-write on the read-write areas of the plurality of slaves, wherein the starting area is used as a data read-write starting point.

7. The I2C data reading and writing method according to any one of claims 1 to 6, wherein after the data reading and writing is performed on the reading and writing area of the mth slave machine according to a period in which the low level signal of the TEST N appears, the method further comprises: testing the I2C data; the method for performing the test comprises the following steps:

a rising edge or a falling edge of the one-shot TEST N signal;

determining a low level signal of the TEST N signal based on a rising edge or a falling edge of the TEST N signal;

the time period of the low level signal of the TEST N signal is the time period of the I2C data read/write area of the mth slave.

8. An I2C data reading and writing apparatus, comprising:

the association module is used for sequentially associating one host machine with a plurality of slave machines along the wire path;

the area module is used for constructing a corresponding read-write area based on a host computer and a plurality of slaves adjacent to the host computer;

the acquisition module is used for outputting a low-level signal of the TEST N by the host and determining that the time period of the low-level signal of the TEST N is the time period of the read-write area of the Mth slave adjacent to the host;

the read-write module is used for reading and writing data in the read-write area of the M-th slave machine according to the time period of occurrence of the low-level signal of the TEST N; wherein, N and M are integers greater than or equal to 1, and N and M are equal.

9. An I2C data reading and writing device, the device comprising:

one or more processors;

the I2C data circuit comprises a host computer and a plurality of slaves; sequentially associating a master computer with a plurality of slave computers along the wire path; and

a memory storing computer program instructions that, when executed, cause the processor to perform the method of reading and writing I2C data according to any one of claims 1 to 7.

10. A computer readable medium having stored thereon computer program instructions executable by a processor to implement the method of reading and writing I2C data according to any of claims 1 to 7.