CN117667786A

CN117667786A - Data transmission method of electronic equipment and electronic equipment

Info

Publication number: CN117667786A
Application number: CN202311865407.6A
Authority: CN
Inventors: 朱正义; 李辉
Original assignee: Lenovo Beijing Ltd
Current assignee: Lenovo Beijing Ltd
Priority date: 2023-12-29
Filing date: 2023-12-29
Publication date: 2024-03-08

Abstract

The application discloses a data transmission method of electronic equipment and the electronic equipment, wherein the electronic equipment comprises a control module, an input/output bus and at least one storage module; each storage module is connected with the control module through a group of input/output buses; the data transmission method of the electronic equipment comprises the following steps: the control module transmits clock signals and data signals to the storage module through the input/output bus; the memory module responds to the clock signal and performs data transmission more than twice in one clock period according to the data signal.

Description

Data transmission method of electronic equipment and electronic equipment

Technical Field

The present disclosure relates to the field of data transmission technologies, and in particular, to a data transmission method of an electronic device and an electronic device.

Background

Due to the rapid development of artificial intelligence AI, the data demand is greatly improved, but the access speed of the memory is limited by the existing access devices, interfaces and the like, and the access speed of the memory is gradually unable to meet the higher and higher data demand. Therefore, there is a need to solve the problem of insufficient data demand caused by low data transmission rate in the prior art.

Disclosure of Invention

An embodiment of the application aims to provide a data transmission method of electronic equipment and the electronic equipment.

In a first aspect, an embodiment of the present application provides a data transmission method of an electronic device, where the electronic device includes a control module, an input/output bus, and at least one storage module; each storage module is connected with the control module through a group of input/output buses;

the control module transmits clock signals and data signals to the memory module through the input/output bus;

the memory module responds to the same clock signal and performs data transmission for more than two times in one clock period according to the data signal.

In one possible implementation manner, the memory module includes at least two memories, a target memory corresponding to each phase is determined according to a plurality of phases in one clock cycle, and data transmission is performed from the target memory according to a data signal, so that the memory module achieves data transmission more than two times in one clock cycle.

In one possible embodiment, the memory module comprises at least two memories;

determining a target memory corresponding to each phase according to a plurality of phases in one clock cycle, and performing data transmission from the target memory according to a data signal, wherein the method comprises the following steps:

and determining at least two target memories corresponding to each phase according to a plurality of phases in one clock cycle, and carrying out data transmission from the target memories according to the data signals corresponding to each target memory, wherein each memory is provided with corresponding data signals.

In one possible embodiment, the clock cycle has a plurality of phases, and the phase difference between any two adjacent phases is the same.

In one possible embodiment, each memory is respectively subjected to at least two data transfers within a clock cycle.

In one possible implementation, when the memory module includes two memories, four phases are set for one clock cycle, and the four phases are 0 degrees, 90 degrees, 180 degrees, and 270 degrees in order; two memories transmit data according to four phases according to the data signal

In one possible implementation manner, the data transmission method further includes:

the memories for data transmission at 0 degrees and 180 degrees are the same, and the memories for data transmission at 90 degrees and 270 degrees are the same; or (b)

The memories for data transmission at 0 degrees and 90 degrees are the same, and the memories for data transmission at 180 degrees and 270 degrees are the same.

In one possible implementation, when the memory module comprises two of the memories,

the two memories are arranged on two sides of the printed circuit board and share one group of pins of the printed circuit board; or (b)

The two memories are arranged on one side of the printed circuit board, the two memories are connected through the connecting plate, the two memories are packaged into a packaged chip, and the packaged chip is connected with pins of the printed circuit board.

In a second aspect, an embodiment of the present application further provides an electronic device, where the electronic device includes a control module, an input/output bus, and at least one storage module; each storage module is connected with the control module through a group of input/output buses;

In a third aspect, an embodiment of the present application further provides an electronic device, including: a processor and a memory storing machine-readable instructions executable by the processor, the processor and the memory in communication via a bus when the electronic device is operating, the machine-readable instructions when executed by the processor performing the steps of the data transmission method of the electronic device of any one of the above.

According to the embodiment of the application, the control module is connected with at least one storage module, and when data transmission is carried out, the storage module can respond to the same clock signal, so that data transmission is carried out for more than two times according to the data signal in one clock period, and the data transmission rate is effectively improved.

Drawings

In order to more clearly illustrate the technical solutions of the present application or the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 shows a flowchart of a data transmission method of an electronic device provided in the present application;

FIG. 2 shows a schematic structural diagram of an electronic device provided by the present application;

FIG. 3 shows a circuit diagram of an electronic device provided by the present application;

FIG. 4 is a graph showing the correspondence between each phase and two memories in one clock cycle provided by the present application;

FIG. 5 is a schematic diagram of a memory module according to the present application;

FIG. 6 is a schematic diagram of another memory module according to the present application;

FIG. 7 shows a schematic structural diagram of another electronic device provided herein;

fig. 8 shows a schematic structural diagram of another electronic device provided in the present application.

Detailed Description

Various aspects and features of the present application are described herein with reference to the accompanying drawings.

It should be understood that various modifications may be made to the embodiments of the application herein. Therefore, the above description should not be taken as limiting, but merely as exemplification of the embodiments. Other modifications within the scope and spirit of this application will occur to those skilled in the art.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the application and, together with a general description of the application given above and the detailed description of the embodiments given below, serve to explain the principles of the application.

These and other characteristics of the present application will become apparent from the following description of a preferred form of embodiment, given as a non-limiting example, with reference to the accompanying drawings.

It is also to be understood that, although the present application has been described with reference to some specific examples, a person skilled in the art will certainly be able to achieve many other equivalent forms of the present application, having the characteristics as set forth in the claims and hence all coming within the field of protection defined thereby.

The foregoing and other aspects, features, and advantages of the present application will become more apparent in light of the following detailed description when taken in conjunction with the accompanying drawings.

Specific embodiments of the present application will be described hereinafter with reference to the accompanying drawings; however, it is to be understood that the disclosed embodiments are merely exemplary of the application, which can be embodied in various forms. Well-known and/or repeated functions and constructions are not described in detail to avoid obscuring the application with unnecessary or excessive detail. Therefore, specific structural and functional details disclosed herein are not intended to be limiting, but merely serve as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present application in virtually any appropriately detailed structure.

The specification may use the word "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," which may each refer to one or more of the same or different embodiments as per the application.

For the convenience of understanding the present application, a detailed description will be first provided of a data transmission method of an electronic device.

Fig. 1 shows a flowchart of a data transmission method of an electronic device provided in an embodiment of the present application, where specific steps include S101 and S102.

S101, the control module transmits clock signals and data signals to the storage module through the input/output bus.

S102, the storage module responds to the same clock signal, and data transmission is carried out for more than two times in one clock period according to the data signal.

In a specific implementation, an electronic device of an embodiment of the present application includes a control module, an input-output bus, and at least one memory module. Referring to the schematic structural diagram of the electronic device shown in fig. 2, each memory module in the embodiment of the present application is connected to the control module through a set of input/output buses. The control module comprises a memory controller, and further comprises a port physical interface (Port Physical Layer, PHY) chip, wherein the memory controller can realize data transmission with the outside through the PHY chip.

Further, data transmission is performed between the control module and the storage module, so that data of the storage module is read or written into the storage module. Optionally, when data is transmitted between the control module and the storage module, the control module transmits the clock signal and the data signal to the storage module through the input/output bus.

The data transmission method of the embodiment of the application can enable the memory module to perform data transmission for more than two times according to the data signal in one clock period, and effectively improve the data transmission rate compared with the existing memory which performs data transmission for one time or two times in one clock period.

Further, the memory module comprises at least two memories, and the at least two memories are controlled to transmit data based on one clock period corresponding to the clock signal, wherein the memories can be dynamic random access memories (Dynamic Random Access Memory, DRAM). Alternatively, there may be a plurality of phases corresponding to one clock cycle, that is, each phase corresponds to one data transmission, based on which, according to the plurality of phases in one clock cycle, a target memory corresponding to each phase is determined, and data transmission is performed from the target memory according to the data signal, so that the memory module achieves data transmission more than twice in one clock cycle. The target memory corresponding to each phase is a memory for transmitting data at the phase time.

Optionally, a target memory corresponding to each phase is preset for each phase, and a corresponding relation between each phase and the corresponding memory is stored in a relation table of the storage module. When determining the target memory corresponding to each phase, the target memory can be determined based on a preset relation table.

For example, four phases corresponding to 0 degree, 90 degrees, 180 degrees and 270 degrees are included in one clock period, after a clock signal and a data signal are received, a target memory corresponding to each of the four phases is searched from a relation table, and then the target memory corresponding to each phase is subjected to data transmission according to the data signal according to the phase sequence. In this embodiment, each phase may be set to correspond to one target memory, or two phases may be set to correspond to one target memory, and when two phases correspond to one target memory, 0 degrees and 90 degrees may be set to correspond to the same target memory, and 180 degrees and 270 degrees may correspond to the same target memory; it is also possible to set 0 degrees and 180 degrees to correspond to the same target memory, and 90 degrees and 270 degrees to correspond to the same target memory. At this time, four data transmission can be performed within one clock period, so that the data transmission efficiency is greatly improved.

Still another example may further include eight phases corresponding to 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees in one clock cycle, after receiving the clock signal and the data signal, searching the target memory corresponding to each of the eight phases from the relational table, and then, according to the above phase sequence, making the target memory corresponding to each phase perform data transmission according to the data signal. Similarly, in this embodiment, each phase may be set to correspond to one target memory, or two phases may be set to correspond to one target memory, and in this embodiment, eight data transmissions can be performed within one clock period, which has higher data transmission efficiency.

In the above example, each phase corresponds to one target memory, respectively, i.e., data transfer is performed by only one memory at each phase. In a specific implementation, it is also possible to provide that one phase corresponds to at least two memories, i.e. that data transfer takes place from at least two memories at one phase.

If at least two memories corresponding to one phase are provided, that is, the number of target memories corresponding to one phase is at least two. On the basis, the target memory corresponding to each phase is determined according to a plurality of phases in one clock cycle, at least two target memories corresponding to each phase are determined according to a plurality of phases in one clock cycle when data transmission is carried out from the target memories according to data signals, and data transmission is carried out from the target memories according to the data signals corresponding to each target memory.

In a specific implementation, in a scenario where one phase corresponds to at least two memories, each memory has a corresponding data signal, that is, at the same phase, different memories transmit different data signals through different data signal lines.

For example, two phases corresponding to 0 degrees and 180 degrees in one clock cycle correspond, and after receiving a clock signal and a data signal, the target memory corresponding to each of the two phases, specifically, two target memories corresponding to the target memory a and the target memory B, are searched from the relation table. Therefore, after the clock signal and the data signal are received, the memory divides the data signal according to the phase to obtain a first sub-data signal when the phase is 0 degrees and a second sub-data signal when the phase is 180 degrees, then at the 0-degree phase point, the first sub-data signal is simultaneously transmitted through the data signal line corresponding to the target memory a and the data signal line corresponding to the target memory B, and at the 180-degree phase point, the second sub-data signal is simultaneously transmitted through the data signal line corresponding to the target memory a and the data signal line corresponding to the target memory B. It can be seen that the object of improving the data transmission efficiency can be achieved in this example as well.

It should be noted that, when the number of target memories corresponding to one phase is at least two, data transmission may also be performed based on the state of each target memory. For example, when determining that the phase corresponds to three target memories of the target memory a, the target memory B, and the target memory C, the states of the target memory a, the target memory B, and the target memory C, such as the data available space, the response speed, and the like, are further queried, and then the data transmission is completed through the target memories in which both the data available space and the response speed reach the transmission conditions. The transmission condition includes that the available space of the data is larger than the preset space and the response speed is larger than the preset speed.

As can be seen from the above examples, in the embodiments of the present application, if there are multiple phases in one clock cycle, the phase difference between any two adjacent phases is the same. And each memory performs data transmission at least twice in a clock period, so that data transmission more than twice in one clock period can be realized, and the data transmission efficiency is improved.

As one example, fig. 3 shows a circuit diagram of an electronic device, which is only one example, but it should be understood in the art that the technical scope of the present application is not limited thereto.

Referring to the electronic device shown in fig. 3, the control module thereof includes a memory controller (Memoey controller) and a PHY chip, an input-output bus sets a Double Data Rate (DDR) bus, the memory module includes two memories DRAM a and DRAM B, and accordingly, four phases are set in order of 0 degrees, 90 degrees, 180 degrees, and 270 degrees in one clock cycle. After the memory controller transmits the clock signal and the data signal to the memory module through the DDR bus, the two memories perform data transmission according to the data signal in four phases, that is, the DRAM A and the DRAM B perform data transmission according to 0 degree, 90 degrees, 180 degrees and 270 degrees.

In practical application, the memories for data transmission at 0 degrees and 180 degrees can be set to be the same, and the memories for data transmission at 90 degrees and 270 degrees can be set to be the same; it is also possible to set the memory for data transmission at 0 degrees and 90 degrees to be the same, and the memory for data transmission at 180 degrees and 270 degrees to be the same. As long as it is possible to perform data transmission more than twice in one clock cycle.

As one example, fig. 4 shows a correspondence map between each phase and two memories DRAM a and DRAM B in one clock cycle. In connection with fig. 3 and 4,Memoey controller, a Write Clock (WCK) and a Data (Data Quad, DQ) are transmitted to the memory module through the DDR BUS, and the memory responds to the WCK according to the correspondence between the phase and the memory shown in fig. 4, so as to perform Data transmission according to DQ. Specifically, when the phase point of the write clock cycle corresponding to WCK is 0 degrees and 180 degrees, data transmission is performed by DRAM a, and when the phase point of the write clock cycle corresponding to WCK is 90 degrees and 270 degrees, data transmission is performed by DRAM B. As can be seen from fig. 4, both the DRAM a and the DRAM B correspond to the rising edge of the clock cycle when data is transferred.

In connection with the examples shown in fig. 3 and 4, embodiments of the present application effectively enable data transmission from a data signal more than twice in one clock cycle. Accordingly, the response manner of the read clock signal is the same as the response manner of the write clock signal, and the embodiments of the present application will not be repeated.

When the memory module includes two memories, the embodiments of the present application illustrate two ways of memory connection. Referring to the schematic structure of a memory module shown in fig. 5, the memory module includes two memories, i.e., DRAM a and DRAM B, mounted on both sides of a printed circuit board (Printed Circuit Board, PCB), the two memories sharing a set of pins of the printed circuit board. Referring to the schematic structure of another memory module shown in fig. 6, the memory module includes two memories, i.e., DRAM a and DRAM B, mounted on one side of a printed circuit board, specifically, the two memories are connected through a connection board, the two memories are packaged as a packaged chip, and the packaged chip is connected to pins of the printed circuit board.

Based on the same inventive concept, the embodiment of the present application provides an electronic device, and since the principle of solving the problem of the electronic device in the present application is similar to that of the data transmission method described in the present application, the implementation of the electronic device may refer to the implementation of the method, and the repetition is omitted.

Fig. 7 shows a schematic diagram of an electronic device according to an embodiment of the present application, where the electronic device includes a control module 701, an input-output bus, and at least one memory module 702; each memory module 702 is connected to the control module 701 through a set of input/output buses;

the control module 701 transmits a clock signal and a data signal to the memory module through the input/output bus;

the memory module 702 is responsive to the same clock signal for more than two data transfers based on the data signal in one clock cycle.

In yet another example, the memory module 702 includes at least two memories, and a target memory corresponding to each phase is determined according to a plurality of phases in one clock cycle, and data is transferred from the target memory according to a data signal, so that the memory module achieves data transfer more than two times in one clock cycle.

In yet another example, the storage module 702 includes at least two memories;

the memory module 702 determines a target memory corresponding to each phase according to a plurality of phases in one clock cycle, and when performing data transmission from the target memory according to a data signal, the memory module includes:

In yet another example, the one clock cycle has a plurality of phases, and the phase difference between any adjacent two phases is the same.

In yet another example, each of the memories performs data transfer at least twice in a clock cycle, respectively.

In yet another example, when the memory module includes two memories, four phases are set for one clock cycle, the four phases being 0 degrees, 90 degrees, 180 degrees, and 270 degrees in order; and the two memories are used for carrying out data transmission according to the data signals and the four phases.

In yet another example of the present invention,

In yet another example, where the memory module includes two of the memories,

The embodiment of the present application provides an electronic device, where a schematic structural diagram of the electronic device may be shown in fig. 8, and the electronic device at least includes a memory 801 and a processor 802, where the memory 801 stores a computer program, and the processor 802 implements a method provided by any embodiment of the present application when executing the computer program on the memory 801. Exemplary, electronic device computer program steps are as follows S11 and S12:

s11, the control module transmits clock signals and data signals to the storage module through the input/output bus;

and S12, the control storage module responds to the same clock signal, and data transmission is carried out for more than two times in one clock period according to the data signal.

The embodiment of the application provides a storage medium, which is a computer readable medium and stores a computer program, and when the computer program is executed by a processor, the method provided by any embodiment of the application is implemented, including the following steps S21 and S22:

s21, the control module transmits clock signals and data signals to the storage module through the input/output bus;

s22, the storage module is controlled to respond to the same clock signal, and data transmission is carried out for more than two times in one clock period according to the data signal.

Alternatively, in the present embodiment, the storage medium may include, but is not limited to: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes. Optionally, in this embodiment, the processor performs the method steps described in the above embodiment according to the program code stored in the storage medium. Alternatively, specific examples in this embodiment may refer to examples described in the foregoing embodiments and optional implementations, and this embodiment is not described herein. It will be appreciated by those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be centralized on a single computing device, or distributed across a network of computing devices, or they may alternatively be implemented in program code executable by computing devices, such that they may be stored in a memory device for execution by the computing devices and, in some cases, the steps shown or described may be performed in a different order than what is shown or described, or they may be implemented as individual integrated circuit modules, or as individual integrated circuit modules. Thus, the present application is not limited to any specific combination of hardware and software.

Furthermore, although exemplary embodiments have been described herein, the scope thereof includes any and all embodiments having equivalent elements, modifications, omissions, combinations (e.g., of the various embodiments across), adaptations or alterations as pertains to the present application. Elements in the claims are to be construed broadly based on the language employed in the claims and are not limited to examples described in the present specification or during the practice of the present application, which examples are to be construed as non-exclusive. It is intended, therefore, that the specification and examples be considered as exemplary only, with a true scope and spirit being indicated by the following claims and their full scope of equivalents.

The above description is intended to be illustrative and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. For example, other embodiments may be used by those of ordinary skill in the art upon reading the above description. In addition, in the above detailed description, various features may be grouped together to streamline the application. This is not to be interpreted as an intention that the disclosed features not being claimed are essential to any claim. Rather, the subject matter of the present application is capable of less than all of the features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that these embodiments may be combined with one another in various combinations or permutations. The scope of the application should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

While various embodiments of the present application have been described in detail, the present application is not limited to these specific embodiments, and various modifications and embodiments can be made by those skilled in the art based on the conception of the present application, which modifications and modifications are within the scope of the present application as defined in the appended claims.

Claims

1. The data transmission method of the electronic equipment comprises a control module, an input/output bus and at least one storage module; each storage module is connected with the control module through a group of input/output buses;

2. The data transmission method according to claim 1, wherein the memory module includes at least two memories, a target memory corresponding to each phase is determined according to a plurality of phases in one clock cycle, and data transmission is performed from the target memory according to the data signal, so that the memory module achieves data transmission more than twice in one clock cycle.

3. The data transmission method according to claim 2, wherein the memory module includes at least two memories;

4. The data transmission method according to claim 2, wherein if there are a plurality of phases in one clock cycle, the phase difference between any adjacent two phases is the same.

5. The data transmission method according to claim 2, wherein each of the memories performs data transmission at least twice in a clock cycle.

6. The data transmission method according to claim 1, wherein when the memory module includes two memories, four phases are set for one clock cycle, the four phases being 0 degrees, 90 degrees, 180 degrees, and 270 degrees in this order; and the two memories are used for carrying out data transmission according to the data signals and the four phases.

7. The data transmission method of claim 6, further comprising:

8. A data transmission method according to any one of claims 1 to 7, wherein, when said memory module comprises two of said memories,

9. An electronic device comprising a control module, an input-output bus, and at least one memory module; each storage module is connected with the control module through a group of input/output buses;

10. An electronic device, comprising: a processor and a memory storing machine readable instructions executable by the processor, the processor and the memory communicating over a bus when the electronic device is running, the machine readable instructions when executed by the processor performing the steps of the data transmission method of an electronic device as claimed in any one of claims 1 to 8.