CN117667553A - System, method, medium and equipment for testing SLT (serial port communication) of computing chip based on serial port communication tool - Google Patents

Abstract

The application provides a serial port communication tool-based computing chip SLT test system, a serial port communication tool-based computing chip SLT test method, a serial port communication tool-based computing chip SLT test medium and serial port communication tool-based computing chip SLT test equipment, wherein the serial port communication tool-based computing chip SLT test system comprises: the first development board is provided with a main control chip and a serial port interface; the second development board is electrically connected with the first development board; the second development board is provided with a to-be-detected computing chip; a computer device provided with a serial communication means; the serial port communication tool is electrically connected with a serial port interface on the first development board to establish serial port communication; the computer equipment responds to the user operation to generate a corresponding chip test instruction, and transmits the chip test instruction to a main control chip on the first development board through the serial communication tool; the operating system of the first development board is loaded with SLT test software corresponding to the current to-be-tested computing chip, and after receiving a chip test instruction, the operating system of the first development board carries out chip test on the to-be-tested computing chip on the second development board. The method and the device solve the technical problems of insufficient flexibility, long test time and high time cost in the prior SLT test of the computing chip.

Description

System, method, medium and equipment for testing SLT (serial port communication) of computing chip based on serial port communication tool

Technical Field

The present disclosure relates to the field of chip testing technologies, and in particular, to a computing chip SLT testing system, method, medium, and apparatus based on a serial port communication tool.

Background

The chip SLT (System-level Test) Test is a process of testing a chip at the whole System level, and aims to verify the function, performance and reliability of the chip in an actual application scene and ensure the normal operation of the chip. In general, the operation process of the chip SLT test is to place the packaged chip on a test board, and record the test result by using matched SLT test software or conventional system software.

For computing chips, SLT testing is a system-level test software specifically designed for high-performance computing chips for yield screening of the computing chips. However, the existing SLT test performed on the computing chip still has the technical problems of insufficient flexibility, long test time and high time cost.

Disclosure of Invention

In view of the above drawbacks of the prior art, an object of the present application is to provide a computing chip SLT test system, method, medium and device based on a serial port communication tool, which are used for solving the technical problems of insufficient flexibility, long test time and high time cost of the current SLT test on the computing chip.

To achieve the above and other related objects, a first aspect of the present application provides a serial port communication tool-based computing chip SLT test system, including: the first development board is provided with a main control chip and a serial port interface; the second development board is electrically connected with the first development board; the second development board is provided with a to-be-detected computing chip; a computer device provided with a serial communication means; the serial port communication tool is electrically connected with a serial port interface on the first development board to establish serial port communication; the computer equipment responds to user operation to generate a corresponding chip test instruction, and transmits the chip test instruction to a main control chip on the first development board through the serial port communication tool; and the operating system of the first development board where the main control chip is located is loaded with SLT test software corresponding to the current to-be-tested computing chip, and after receiving the chip test instruction, the to-be-tested computing chip on the second development board is subjected to chip test.

In some embodiments of the first aspect of the present application, the main control chip classifies the to-be-tested computing chip into a plurality of classes according to different chip performances, and stores a chip test result of the to-be-tested computing chip on a file system of an operating system of the first development board for export to matched test management software for analyzing the chip test result.

In some embodiments of the first aspect of the present application, the main control chip classifies the computing chip to be tested into a plurality of grades according to different chip performances, and the grading manner includes the following steps: the master control chip obtains the accuracy and working current of each computing chip to be tested; judging whether the working current obtained by the test meets the standard or not, and grading each computing chip to be tested according to the accuracy.

In some embodiments of the first aspect of the present application, the computer device uses a serial port communication tool to test the to-be-tested computing chip by using an instruction line manner, and changes the corresponding test instruction according to different requirements.

In some embodiments of the first aspect of the present application, the Linux system of the computer device generates corresponding SLT test software according to the current computing chip to be tested, and remotely transmits the generated SLT test software to an operating system on a development board where the main control chip is located based on the scp remote transmission instruction.

In some embodiments of the first aspect of the present application, the computer device changes the frequency points that the computing chip can run and the voltage range corresponding to the frequency points by sending an instruction line to the main control chip according to the performance of the computing chip to be tested currently.

In some embodiments of the first aspect of the present application, the computer device sets a plurality of sets of frequency points and voltage data for the same computing chip to be tested, where each set of frequency points and voltage data includes data of a corresponding frequency point and a plurality of different voltage points corresponding to the frequency point; and repeatedly testing the to-be-tested computing chip by using the multiple groups of frequency points and voltage data to form a matrix test point of frequency and voltage.

In some embodiments of the first aspect of the present application, after the current computing chip to be tested completes the chip test, the SLT test software running on the operating system of the first development board where the main control chip is located is switched from the test state to the waiting state; and after the current computing chip to be tested is taken out and replaced by the next computing chip to be tested, the SLT test software is switched from the waiting state to the test state.

In some embodiments of the first aspect of the present application, the serial port communication tool includes any one of the following: mini tool, puTTY tool, kermit tool, picocom tool, and cutcom tool.

To achieve the above and other related objects, a second aspect of the present application provides a serial communication tool-based computing chip SLT test method, which is applied to a computer device in the computing chip SLT test system; the method comprises the following steps: generating corresponding chip test instructions in response to user operations; and transmitting the chip test instruction to a main control chip on a first development board through a serial port communication tool arranged on the computer equipment so as to test the current to-be-tested computing chip on a second development board by an operating system of the first development board loaded with SLT test software corresponding to the current to-be-tested computing chip.

To achieve the above and other related objects, a third aspect of the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the serial port communication tool-based computing chip SLT testing method.

To achieve the above and other related objects, a fourth aspect of the present application provides a computer apparatus, comprising: a processor and a memory; the memory is used for storing a computer program, and the processor is used for executing the computer program stored in the memory, so that the terminal executes the serial communication tool-based computing chip SLT test method.

As described above, the computing chip SLT test system, method, medium and device based on serial port communication tool of the present application has the following beneficial effects: according to the method, the serial port communication tool is used, the SLT software test is carried out on the computing chip in a mode of using the instruction line, the test instruction can be changed rapidly, intuitively and conveniently according to different requirements, the comprehensive screening is carried out according to the chip functions, the yield problem of a large number of chips is analyzed, the types are classified according to the performance differences of the chips, and the chips are used later. Therefore, the method and the device effectively solve the technical problems of insufficient flexibility, long test time and high time cost of the existing SLT test on the computing chip.

Drawings

Fig. 1 is a schematic structural diagram of a serial communication tool-based computing chip SLT test system according to an embodiment of the present application.

Fig. 2 is a flow chart of a method for testing a computing chip SLT based on a serial port communication tool according to an embodiment of the present application.

Fig. 3 is a schematic structural diagram of a computer device according to an embodiment of the present application.

Detailed Description

Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.

It is noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present application. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "upper," and the like, may be used herein to facilitate a description of one element or feature as illustrated in the figures as being related to another element or feature.

In this application, unless specifically stated and limited otherwise, the terms "mounted," "connected," "secured," "held," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.

Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, operations, elements, components, items, categories, and/or groups. The terms "or" and/or "as used herein are to be construed as inclusive, or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; A. b and C). An exception to this definition will occur only when a combination of elements, functions or operations are in some way inherently mutually exclusive.

In order to solve the problems in the background art, the invention provides a serial communication tool-based computing chip SLT test system, a serial communication tool-based computing chip SLT test method, a serial communication tool-based computing chip SLT test medium and serial communication equipment, and aims to perform SLT software test on the computing chip in a command line mode, so that test commands can be quickly, intuitively and conveniently changed according to different requirements, and the computing chip SLT test medium can be comprehensively screened according to chip functions, analyze yield problems of a large number of chips, classify the chips according to performance differences of the chips and wait for subsequent use. Therefore, the method and the device effectively solve the technical problems of insufficient flexibility, long test time and high time cost of the existing SLT test on the computing chip.

In order to make the objects, technical solutions and advantages of the present invention more apparent, further detailed description of the technical solutions in the embodiments of the present invention will be given by the following examples with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Before explaining the present invention in further detail, terms and terminology involved in the embodiments of the present invention will be explained, and the terms and terminology involved in the embodiments of the present invention are applicable to the following explanation:

<1> slt (System-level Test) Test: the chip test is performed at the whole system level, and aims to verify the functions, performances and reliability of the chip in the actual application scene and ensure the normal operation of the chip.

<2> minicom: a serial port communication tool is a Linux terminal tool used for communicating with serial port equipment (such as a debugging switch, a Modem and the like), and a product logs in a system with root authority.

<3> development plate: a circuit board for embedded system development comprises a series of hardware components including a central processing unit, a memory, an input device, an output device, a data path/bus, and an external resource interface.

<4> instruction line: one way to interact with a computer system by typing instructions and parameters is a text interface, also known as an instruction line interface. Generally, in the instruction line, a user inputs an instruction and a parameter through a keyboard, and performs a corresponding operation after pressing an enter key. The instruction line interface provides a straightforward and flexible way to control and manage the computer system, performing various tasks and operations.

<5> calculation chip: an integrated circuit chip for performing computation and data processing. The computing chip is an integrated circuit composed of a large number of transistors, and can amplify and switch electric signals, and complex logic operation and numerical computation are realized by utilizing the switching characteristics and the current control capability of the transistors.

<6> master control chip: the device is a core component of a main board or a hard disk, is a bridge for connecting all devices, and is also a brain for controlling the operation of the devices.

<7> test management software: the system is a tool for managing test requirements, plans, use cases and implementation processes and tracking software defects in the software development process. By using test management software, testers or developers can more conveniently record and monitor the results of each test activity and stage, find out defects and errors of the software, and record defects and improvement suggestions found in the test activity. By using test management software, test cases can be multiplexed by multiple test activities or phases, and test analysis reports and statistics can be output.

The embodiment of the invention provides a serial communication tool-based computing chip SLT test method, a serial communication tool-based computing chip SLT test method system and a storage medium for storing an executable program for realizing the serial communication tool-based computing chip SLT test method. With respect to implementation of the serial communication tool-based computing chip SLT test method, an exemplary implementation scenario of the serial communication tool-based computing chip SLT test will be described.

Fig. 1 shows a schematic structural diagram of a computing chip SLT test system based on a serial port communication tool in an embodiment of the present invention. The computing chip SLT test system based on the serial port communication tool in this embodiment mainly includes the following:

the first development board 11 is provided with a main control chip 13 and a serial port interface (not shown).

A second development board 12 electrically connected to the first development board 11; the second development board 12 is provided with a computing chip 14 to be tested.

A computer device 15 provided with serial communication means 16; the serial communication tool 16 is electrically connected to the serial interface on the first development board 11 to establish serial communication.

The computer device 15 generates a corresponding chip test instruction in response to a user operation, and transmits the chip test instruction to the main control chip 13 on the first development board 11 through the serial port communication tool 16; the operating system of the main control chip 13 is loaded with SLT test software corresponding to the current to-be-tested computing chip 14, and performs chip test on the to-be-tested computing chip 14 on the second development board 12 after receiving the chip test instruction.

It should be understood that a computing chip is an integrated circuit chip for performing computation and data processing. The computing chip is an integrated circuit composed of a large number of transistors, and can amplify and switch electric signals, and complex logic operation and numerical computation are realized by utilizing the switching characteristics and the current control capability of the transistors. The core components of the computing chip include a central processing unit (Central Processing Unit, CPU). The central processing unit (Central Processing Unit, CPU) includes: an arithmetic logic unit (Arithmetic and logic unit, ALU), registers, and control units, among others. An arithmetic logic unit (Arithmetic and logic unit, ALU) is responsible for arithmetic and logical operations, registers for storing data and instructions, and control units for controlling and coordinating the operation of the various components. The main control chip is a core component of a main board or a hard disk, is a bridge for connecting all devices, and is also a brain for controlling the operation of the devices. The main board control chip is a south-pointing north-pointing bridge chip, and the south-pointing bridge chip is responsible for communication among I/O buses, such as PCI buses, USB buses, LAN buses, ATA buses, SATA buses, audio controllers, keyboard controllers, real-time clock controllers, advanced power management and the like; the north bridge chip is responsible for interfacing with the central processing unit (Central Processing Unit, CPU) and controlling memory.

It should be noted that, in the embodiment of the present invention, the serial port communication tool includes, but is not limited to, the following: mini tools, puTTY tools, kermit tools, picocom tools, cutcom tools, etc. Specifically, the mini tool is a Linux serial communication tool, and can be used for communicating with serial devices (such as a debug switch, a Modem and the like). The puTTY tool is a serial interface connection software, which is commonly used for remote login control functions. The Kermit tool is a serial communication software with two forms of instruction and non-instruction: various Kermint instructions running on the host can be input in the instruction form; the non-instruction form is a terminal of the target machine, the screen of the terminal is used for prompting the operation information of the target board, and the keyboard is used for typing the input of the target board. The picocom tool is a serial port debugging tool, and can be used for communicating with serial port equipment and sending a request or an instruction to the equipment. The Cutecom tool is a graphical serial port terminal, can send information to an interface and read the information, and has the characteristics of simplicity in operation and easiness in application.

Illustratively, consider the minicom tool as an example to explain how testing of a computing chip is accomplished: when the chip test is performed, the current to-be-tested computing chip 14 is placed on the second development board 12 and is electrically connected with the first development board 11 where the main control chip 13 is located. The first development board 11 establishes serial communication connection with the mini tool through the serial interface. After the connection is successful, the computer device 15 may send an instruction to the first development board 11 through the mini tool, or may receive test result data from the first development board 11, so as to perform serial port debugging and interactive operation. The SLT test software runs on the operating system of the main control chip 13, the operating system of the main control chip 13 is usually a Linux operating system, a test instruction is sent in a mini tool in a mode of an instruction line, and the main control chip 13 communicates with the to-be-tested computing chip 14 to complete a series of test tasks.

In some examples, the main control chip 13 classifies the to-be-tested computing chip 14 into a plurality of grades according to different chip performances, and stores the chip test result of the to-be-tested computing chip 14 on a file system of an operating system of the first development board 11 for export to matched test management software to analyze the chip test result.

Further, the main control chip 13 classifies the to-be-measured computing chip 14 into a plurality of grades according to different chip performances, and the grading manner comprises the following steps: the master control chip 13 obtains the accuracy and working current of each calculation chip 14 to be measured; judging whether the working current obtained by the test meets the standard or not and grading each computing chip 14 to be tested according to the accuracy.

The first development board 11 is configured as a Linux operating system, and the chip test results of the computing chip to be tested 14 are stored on a Linux file system. It should be appreciated that in Linux systems common files and directory files are stored on disks or tapes called block physical devices. A set of Linux systems supports several physical disks, each of which may define one or more file systems. Each file system consists of a sequence of logical blocks, one logical disk space is typically divided into several sections of different usage, namely boot blocks, superblocks, inode areas, and data areas, etc.

Optionally, the test management software may be any one of the following test case management software: testCenter test management software, testManager test management software, AQDirector test management software, testLink test management software, QATraq test management software, oKit test management software, and the like.

In the embodiment of the present invention, the computer device 15 uses the serial communication tool 16 to test the to-be-tested computing chip 14 by using an instruction line manner, and changes the corresponding test instruction according to different requirements.

By using a minicom tool, the chip is tested in a mode of using an instruction line, so that test instructions can be correspondingly changed according to different requirements, the best test effect is achieved, and because the interaction mode of a development board where the main control chip is originally located is not friendly, after the minicom tool is used, a user can realize chip testing by inputting the instruction line in a mode of interaction based on a graphical interface, and user experience is greatly improved. Taking the test of selecting voltage and frequency points as an example: the initial voltage is 400mV, the initial frequency is 500mHz, the end voltage is 400mV, the end frequency is 600mHz, and the growth frequency is increased by 25mHz each time (the growth frequency of other values can be set). Under other requirements, the initial voltage, the initial frequency, the end voltage and the end frequency can be set in advance, and the direct test is performed.

In the embodiment of the invention, the Linux system of the computer equipment generates corresponding SLT test software according to the current computing chip to be tested, and remotely transmits the generated SLT test software to the operating system on the development board where the main control chip is located based on the scp remote transmission instruction. It should be understood that the different computing chips are different, so that the required SLT test software is also different, and after the computing chip to be tested is replaced, the SLT test software running on the main control chip should be correspondingly changed.

It should be noted that, the scp instruction of the Linux system is mainly used for file transmission between the local host and the remote host. Illustratively, the usual usage of scp instructions is as follows: 1) Transmitting a file from a local host to a remote host: transmitting the file on the local host to a designated target path of the remote host; 2) Transmitting a file from a remote host to a local host: transmitting the file on the remote host to a designated target path of the local host; 3) Transmitting the whole catalogue: the entire directory and its contents can be recursively transferred using the "-r" option; 4) Designating a port number: if the SSH server port of the remote host is not the default 22 port, the port number may be specified using the "-P" option. It should be noted that the above examples are for illustration only and are not intended to be limiting.

In the embodiment of the invention, the computer equipment changes the frequency points which can run by the computing chip and the voltage range corresponding to the frequency points in a mode of sending the instruction line to the main control chip according to the performance of the computing chip to be tested currently, so that the flexibility is high. It is worth to say that, just by means of the serial port communication tool, the user can input the instruction line on the computer equipment based on the mode of graphical interface interaction, thereby change frequency point and voltage range, the flexibility is high.

Further, the computer equipment sets a plurality of groups of frequency points and voltage data for the same computing chip to be tested, wherein each group of frequency points and voltage data comprises corresponding frequency points and data of a plurality of different voltage points corresponding to the frequency points; and repeatedly testing the to-be-tested computing chip by using the multiple groups of frequency points and voltage data to form matrix test points of frequency and voltage, wherein the data are comprehensive and have high coverage rate.

In the embodiment of the invention, after the chip test of the current computing chip to be tested is finished, SLT test software running on an operating system of a first development board where a main control chip is located is switched from a test state to a waiting state; and after the current computing chip to be tested is taken out and replaced by the next computing chip to be tested, the SLT test software is switched from the waiting state to the test state. It is worth to say that in the whole test process, the SLT test software is not stopped, and only state switching exists, so that the chip test time is low in cost and high in test efficiency.

In the embodiment of the invention, the computer equipment uses the test software to actually measure the actual computing power of the computing chip according to the theoretical computing power of the computing chip, and comprehensively analyzes other important factors such as temperature and the like in the testing process of the computing chip, and tests the performance grade of the computing chip after the testing is finished, so that the screening is strict.

For the convenience of understanding by those skilled in the art, the following SLT test software use cases for the computing chips are further described, and the specific implementation process is as follows:

and placing one computing chip into a development board, and connecting the development board with the development board of the main control chip. The development board where the main control chip is located is connected to the mini serial communication tool through a serial interface. And establishing communication connection with the serial device by using a mini serial communication tool. And sending a command to serial port equipment in the mini serial port communication tool, and communicating with the computing chip by the main control chip.

And (3) firstly performing power-on operation, addressing the computing chip, and then testing the test point after the addressing is passed. After the test is finished, the chips are classified according to the failure level according to the test result, the test software is in a waiting state at the moment, the next computing chip to be tested is replaced, then the test software is started again, the test is repeated in a circulating way, and the test is finished and the power-off operation is carried out after all the computing chips are finished. The test results are saved in a file system of the development board operating system. And after the test result is exported, carrying out batch analysis of the computing chips. After the analysis is completed, the SLT test on the computing chip is completed.

In the above, the embodiment of the invention provides a serial communication tool-based computing chip SLT test system. Hereinafter, the method, terminal and medium for testing the computing chip SLT based on the serial port communication tool provided by the present invention will be further described with reference to other embodiments.

Fig. 2 is a schematic flow chart of a method for testing SLT of a computing chip based on a serial port communication tool in an embodiment of the invention. It should be understood that the method for testing the SLT of the computing chip based on the serial port communication tool is applied to the computer device in the system for testing the SLT of the computing chip based on the serial port communication tool in the above embodiment. The method for testing the SLT of the computing chip comprises the following steps:

step S21: corresponding chip test instructions are generated in response to user operations.

In an embodiment of the present invention, the generating, in response to a user operation, a corresponding chip test instruction includes: the computer equipment tests the chip to be tested by using a serial port communication tool and an instruction line mode, and changes corresponding test instructions according to different requirements.

Step S22: and transmitting the chip test instruction to a main control chip on a first development board through a serial port communication tool arranged on the computer equipment so as to test the current to-be-tested computing chip on a second development board by an operating system of the first development board loaded with SLT test software corresponding to the current to-be-tested computing chip.

In the embodiment of the invention, the Linux system of the computer equipment generates corresponding SLT test software according to the current computing chip to be tested, and remotely transmits the generated SLT test software to the operating system on the development board where the main control chip is located based on the scp remote transmission instruction.

In the embodiment of the invention, the computer equipment changes the frequency points which can run by the computing chip and the voltage range corresponding to the frequency points in a mode of sending an instruction line to the main control chip according to the performance of the computing chip to be tested currently.

Further, the computer equipment sets a plurality of groups of frequency points and voltage data for the same computing chip to be tested, wherein each group of frequency points and voltage data comprises corresponding frequency points and data of a plurality of different voltage points corresponding to the frequency points; and repeatedly testing the to-be-tested computing chip by using the multiple groups of frequency points and voltage data to form a matrix test point of frequency and voltage.

Further, after the chip test of the current to-be-tested computing chip is finished, SLT test software running on an operating system of a first development board where the main control chip is located is switched from a test state to a waiting state; and after the current computing chip to be tested is taken out and replaced by the next computing chip to be tested, the SLT test software is switched from the waiting state to the test state.

It should be appreciated that the serial communication tool includes any of the following: mini tool, puTTY tool, kermit tool, picocom tool, and cutcom tool.

It should be noted that, the implementation manner of the computing chip SLT testing method based on the serial port communication tool provided in the embodiment of the present invention is similar to the above computing chip SLT testing system based on the serial port communication tool, so that the description thereof is omitted.

Referring to fig. 3, an optional hardware structure diagram of a computer device 300 according to an embodiment of the present invention is shown, where the computer device 300 may be a mobile phone, a tablet device, a personal digital processing device, a factory background processing device, etc. The computer device 300 includes: at least one processor 301, a memory 302, at least one network interface 304, and a user interface 306. The various components in the device are coupled together by a bus system 305. It is understood that the bus system 305 is used to enable connected communications between these components. The bus system 305 includes a power bus, a control bus, and a status signal bus in addition to the data bus. But for clarity of illustration the various buses are labeled as bus systems in fig. 3.

The user interface 306 may include, among other things, a display, keyboard, mouse, trackball, click gun, keys, buttons, touch pad, or touch screen, etc.

It is to be appreciated that memory 302 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read Only Memory (ROM), a programmable Read Only Memory (PROM, programmable Read-Only Memory), which serves as an external cache, among others. By way of example, and not limitation, many forms of RAM are available, such as static random Access Memory (SRAM, staticRandom Access Memory), synchronous static random Access Memory (SSRAM, synchronous Static RandomAccess Memory). The memory described by embodiments of the present invention is intended to comprise, without being limited to, these and any other suitable types of memory.

The memory 302 in embodiments of the present invention is used to store various categories of data to support the operation of the computer device 300. Examples of such data include: any executable programs for operating on computer device 300, such as operating system 3021 and application programs 3022; the operating system 3021 contains various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application 3022 may include various applications such as a Media Player (Media Player), a Browser (Browser), etc. for implementing various application services. The method for testing the computing chip SLT based on the serial port communication tool provided by the embodiment of the invention can be contained in the application 3022.

The method disclosed in the above embodiment of the present invention may be applied to the processor 301 or implemented by the processor 301. The processor 301 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuitry of hardware in the processor 301 or instructions in the form of software. The processor 301 may be a general purpose processor, a digital signal processor (DSP, digital Signal Processor), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. Processor 301 may implement or perform the methods, steps and logic blocks disclosed in embodiments of the present invention. The general purpose processor 301 may be a microprocessor or any conventional processor or the like. The steps of the accessory optimization method provided by the embodiment of the invention can be directly embodied as the execution completion of the hardware decoding processor or the execution completion of the hardware and software module combination execution in the decoding processor. The software modules may be located in a storage medium having memory and a processor reading information from the memory and performing the steps of the method in combination with hardware.

In an exemplary embodiment, the computer device 300 may be implemented by one or more application specific integrated circuits (ASIC, application Specific Integrated Circuit), DSPs, programmable logic devices (PLDs, programmable Logic Device), complex programmable logic devices (CPLDs, complex Programmable Logic Device) for performing the aforementioned methods.

Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by computer program related hardware. The aforementioned computer program may be stored in a computer readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.

In the embodiments provided herein, the computer-readable storage medium may include read-only memory, random-access memory, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, U-disk, removable hard disk, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. In addition, any connection is properly termed a computer-readable medium. For example, if the instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable and data storage media do not include connections, carrier waves, signals, or other transitory media, but are intended to be directed to non-transitory, tangible storage media. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

In summary, the application provides a serial communication tool-based computing chip SLT test system, a serial communication tool-based computing chip SLT test method, a serial communication tool-based computing chip SLT software test medium and a serial communication tool-based computing chip SLT software test device, so that test instructions can be quickly, intuitively and conveniently changed according to different requirements, and the test instructions can be comprehensively screened according to chip functions, so that yield problems of a large number of chips are analyzed, and the chips are classified according to performance differences of the chips and are used later. Therefore, the method and the device effectively solve the technical problems of insufficient flexibility, long test time and high time cost of the existing SLT test on the computing chip. Therefore, the method effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles of the present application and their effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications and variations which may be accomplished by persons skilled in the art without departing from the spirit and technical spirit of the disclosure be covered by the claims of this application.

Claims (12)

1. A serial port communication tool-based computing chip SLT test system, comprising:

the first development board is provided with a main control chip and a serial port interface;

the second development board is electrically connected with the first development board; the second development board is provided with a to-be-detected computing chip;

a computer device provided with a serial communication means; the serial port communication tool is electrically connected with a serial port interface on the first development board to establish serial port communication;

the computer equipment responds to user operation to generate a corresponding chip test instruction, and transmits the chip test instruction to a main control chip on the first development board through the serial port communication tool; and the operating system of the first development board where the main control chip is located is loaded with SLT test software corresponding to the current to-be-tested computing chip, and after receiving the chip test instruction, the to-be-tested computing chip on the second development board is subjected to chip test.

2. The system according to claim 1, wherein the master control chip classifies the computing chips to be tested into a plurality of classes according to different chip performances, and stores the chip test results of the computing chips to be tested on a file system of an operating system of the first development board for export to matched test management software for analysis of the chip test results.

3. The serial port communication tool-based computing chip SLT test system according to claim 2, wherein the master control chip classifies the computing chips to be tested into a plurality of classes according to different chip performances, and the class classification method includes the following steps: the master control chip obtains the accuracy and working current of each computing chip to be tested; judging whether the working current obtained by the test meets the standard or not, and grading each computing chip to be tested according to the accuracy.

4. The serial port communication tool-based computing chip SLT testing system according to claim 1, wherein the computer device tests the computing chip to be tested by using the serial port communication tool and using an instruction line mode, and changes the corresponding test instruction according to different requirements.

5. The system for testing the SLT of the computing chip based on the serial port communication tool according to claim 1, wherein the Linux system of the computer equipment generates corresponding SLT test software according to the current computing chip to be tested, and remotely transmits the generated SLT test software to the operating system on the development board where the main control chip is located based on the scp remote transmission instruction.

6. The system according to claim 1, wherein the computer device changes the frequency points that the computing chip can run and the voltage range corresponding to the frequency points by sending instruction lines to the main control chip according to the performance of the computing chip to be tested.

7. The serial port communication tool-based computing chip SLT test system according to claim 6, wherein the computer device sets a plurality of sets of frequency points and voltage data for the same computing chip to be tested, each set of frequency points and voltage data comprising data of a corresponding frequency point and a plurality of different voltage points corresponding to the frequency point; and repeatedly testing the to-be-tested computing chip by using the multiple groups of frequency points and voltage data to form a matrix test point of frequency and voltage.

8. The system for testing the SLT of the computing chip based on the serial port communication tool as set forth in claim 7, wherein after the current computing chip to be tested completes the chip test, the SLT test software running on the operating system of the first development board where the main control chip is located is switched from the test state to the waiting state; and after the current computing chip to be tested is taken out and replaced by the next computing chip to be tested, the SLT test software is switched from the waiting state to the test state.

9. The serial communication tool based computing chip SLT test system of claim 1, wherein the serial communication tool includes any one of: mini tool, puTTY tool, kermit tool, picocom tool, and cutcom tool.

10. A serial communication tool-based computing chip SLT test method, characterized by being applied to the computer device in the computing chip SLT test system according to any one of claims 1 to 9; the method comprises the following steps:

generating corresponding chip test instructions in response to user operations;

and transmitting the chip test instruction to a main control chip on a first development board through a serial port communication tool arranged on the computer equipment so as to test the current to-be-tested computing chip on a second development board by an operating system of the first development board loaded with SLT test software corresponding to the current to-be-tested computing chip.

11. A computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the serial communications tool based computing chip SLT testing method of claim 10.

12. A computer device, comprising: a processor and a memory;

the memory is used for storing a computer program;

the processor is configured to execute the computer program stored in the memory, so that the terminal performs the serial port communication tool-based computing chip SLT testing method according to claim 10.