CN117651030A

CN117651030A - Multi-queue data processing method and device based on FPGA network card

Info

Publication number: CN117651030A
Application number: CN202311606770.6A
Authority: CN
Inventors: 王晋军; 蒋超
Original assignee: Lenovo Beijing Ltd
Current assignee: Lenovo Beijing Ltd
Priority date: 2023-11-28
Filing date: 2023-11-28
Publication date: 2024-03-05

Abstract

The application discloses a multi-queue data processing method and device based on an FPGA network card, wherein the multi-queue data processing method comprises the following steps: analyzing the received data packet to obtain the multi-element group information of the data packet; determining a first queue sequence number of a queue to which the data packet belongs according to the multi-element group information of the data packet; determining a shared storage area to which the queue belongs according to the first queue sequence number and the preset number; the shared memory area is a RAM memory area which is used by a preset number of queues together in a time division multiplexing mode; and writing the data packet into a queue of the first queue serial number in the shared storage area.

Description

Multi-queue data processing method and device based on FPGA network card

Technical Field

The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for processing multi-queue data based on an FPGA network card _。

Background

In the existing multi-queue processing of the FPGA network card, RAM resources in the FPGA chip are utilized according to blocks, namely each queue occupies one or more RAM resources, and a group of read-write interfaces of each queue are independent from each other.

The exclusive RAM has simple queue mode, does not need to consider the problem of read-write access conflict, but needs a large amount of RAM resources, so that the number of the supportable queues is small, and the waste of partial RAM resources is caused.

Disclosure of Invention

In view of this, the present application provides a method and an apparatus for processing multi-queue data based on an FPGA network card, so as to solve the technical problem of resource waste existing in the current queue mode of the exclusive RAM of the FPGA network card.

In a first aspect, an embodiment of the present application provides a method for processing multi-queue data based on an FPGA network card, including:

analyzing the received data packet to obtain the multi-element group information of the data packet;

determining a first queue sequence number of a queue to which the data packet belongs according to the multi-element group information of the data packet;

determining a shared storage area to which the queue belongs according to the first queue sequence number and the preset number;

the shared memory area is a RAM memory area which is used by a preset number of queues together in a time division multiplexing mode;

and writing the data packet into a queue of the first queue serial number in the shared storage area.

In one possible implementation manner, before the parsing the received data packet to obtain the multi-group information of the data packet, the method further includes:

dividing the shared memory area and distributing the shared memory area to a preset number of queues;

and setting a first queue sequence number of the queue.

In one possible implementation, after writing the data packet to the queue of the first queue sequence number in the shared memory region, the method further includes:

and reading the data packet from the queue of the first queue serial number.

In one possible implementation, the FPGA network card includes a plurality of links; before the received data packet is parsed to obtain the multi-group information of the data packet, the method further comprises:

determining the number of idle queues of each link according to the number of queues of each link and the preset number;

and distributing a shared memory area for the link according to the number of the queues of the link and the number of the idle queues.

In one possible implementation, the FPGA network card includes a plurality of links; determining, according to the first queue sequence number and the preset number, a shared memory area to which the queue belongs, including:

determining a queue sequence number offset value of the link according to the idle queue quantity of all links before the link to which the data packet belongs;

determining a second queue sequence number of the queue based on a sum of the first queue sequence number and the queue sequence number offset value;

and determining a shared storage area to which the queue belongs according to the second queue sequence number and the preset number.

reading the data packet from the queue of the second queue serial number;

and determining the first queue sequence number of the queue according to the second queue sequence number of the queue and the link to which the data packet belongs.

In one possible implementation manner, determining the first queue sequence number of the queue according to the second queue sequence number of the queue and the link to which the data packet belongs includes:

and determining the first queue sequence number of the queue based on the difference between the second queue sequence number of the queue and the queue sequence number offset value of the link.

In one possible implementation manner, the determining, according to the multi-element group information of the data packet, the first queue serial number of the queue to which the data packet belongs includes:

and processing the multi-group information of the data packet by utilizing a symmetrical hash algorithm, and determining a first queue sequence number of a queue to which the data packet belongs.

In a second aspect, an embodiment of the present application provides a multi-queue data processing device based on an FPGA network card, including:

the analysis unit is used for analyzing the received data packet to obtain the multi-element group information of the data packet;

a first determining unit, configured to determine, according to the multi-element group information of the data packet, a first queue sequence number of a queue to which the data packet belongs;

a second determining unit, configured to determine, according to the first queue sequence number and a preset number, a shared storage area to which the queue belongs;

and the processing unit is used for writing the data packet into a queue of the first queue serial number in the shared storage area.

In a third aspect, an embodiment of the present application provides an FPGA network card, including: a memory and a processor, the memory for storing an executable program; the processor executes the executable program to implement the steps of the methods of embodiments of the present application.

In the embodiment of the application, a group of RAM resources are virtualized into a plurality of copies, a plurality of interfaces are provided, and a time division multiplexing mode is adopted for a plurality of queues to use; the depth of the RAM queue can be adjusted according to the fine granularity of requirements, the maximum number of queues which can be provided in the design of the FPGA network card is effectively increased, the technical problem that a large amount of storage resources are consumed by an exclusive RAM scheme, so that the resource waste is caused is solved, and the full utilization of the RAM resources is realized.

Drawings

In order to more clearly illustrate the technical solutions of the present application or the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a diagram of an FPGA-based intelligent network card architecture;

FIG. 2 is a schematic diagram of a conventional FPGA network card with multiple queues in the RAM;

FIG. 3 is a flowchart of a method for processing multi-queue data based on an FPGA network card according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a shared memory area according to an embodiment of the present application;

FIG. 5 is a flowchart illustrating steps for allocating shared memory to queues of each link according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a shared memory area of two links according to an embodiment of the present application;

FIG. 7 is a flowchart of a method for processing multi-queue data of a multi-link FPGA network card according to an embodiment of the present application;

fig. 8 is a functional block diagram of a multi-queue data processing device based on an FPGA network card according to an embodiment of the present application.

Detailed Description

Various aspects and features of the present application are described herein with reference to the accompanying drawings.

It should be understood that various modifications may be made to the embodiments of the application herein. Therefore, the above description should not be taken as limiting, but merely as exemplification of the embodiments. Other modifications within the scope and spirit of this application will occur to those skilled in the art.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the application and, together with a general description of the application given above and the detailed description of the embodiments given below, serve to explain the principles of the application.

These and other characteristics of the present application will become apparent from the following description of a preferred form of embodiment, given as a non-limiting example, with reference to the accompanying drawings.

It is also to be understood that, although the present application has been described with reference to some specific examples, those skilled in the art can certainly realize many other equivalent forms of the present application.

The foregoing and other aspects, features, and advantages of the present application will become more apparent in light of the following detailed description when taken in conjunction with the accompanying drawings.

Specific embodiments of the present application will be described hereinafter with reference to the accompanying drawings; however, it is to be understood that the disclosed embodiments are merely exemplary of the application, which can be embodied in various forms. Well-known and/or repeated functions and constructions are not described in detail to avoid obscuring the application with unnecessary or excessive detail. Therefore, specific structural and functional details disclosed herein are not intended to be limiting, but merely serve as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present application in virtually any appropriately detailed structure.

The specification may use the word "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," which may each refer to one or more of the same or different embodiments as per the application.

First, the design concept of the embodiment of the present application will be briefly described.

At present, the intelligent network card based on the FPGA chip design has more and more requirements, compared with the common standard network card, the FPGA can customize and unload some processing tasks on the original CPU according to the requirement due to the programmable characteristic, so that the intelligent network card based on the FPGA has more and more wide application, and the general architecture design of the intelligent network card based on the FPGA is shown in the following figure 1.

The FPGA is used as a resource-oriented chip, the supported functions and offloading tasks are strictly limited by available on-chip resources, particularly RAM storage resources in the chip are more intense, and in a millions of FPGA chips, at most, thousands of RAM resources are available. In a general intelligent network card architecture, multi-queue processing is an important functional module, which is designed based on RAM resources in an FPGA chip, and directly determines the communication efficiency of DPDK driving on an FPGA and a multi-core CPU. Along with the improvement of the capability of the multi-core CPU at present, the number of queues required to be provided by the network card side is higher and higher, the demand pressure on RAM resources on the FPGA is also higher and higher, and how to increase the number of queues processed by the multi-queues within the available resource range becomes an important technical index of the FPGA network card.

At present, RAM resources in the FPGA chip are utilized in blocks, i.e. each queue occupies one or more RAM resources, and each queue has a set of read-write interfaces, which are independent from each other, as shown in fig. 2. The exclusive RAM has a simple queue mode, and does not need to consider the problem of read-write access conflict, but a large amount of RAM resources are needed, so that the number of supportable queues is limited. Taking xcvu3pFPGA of Xilinx as an example, when implementing multiple queues in an exclusive RAM mode, deducting service logic overhead, the rest RAM resources can support 8 queue demands at most, so that the demands of multi-core CPU and DPDK on the number of multiple queues can not be met, and when the RAM is exclusive, a large-capacity RAM resource, such as a special 288Kb UltraRAM resource, can only be allocated to one queue, and fine granularity adjustment can not be performed on the RAM resource according to the depth of the queue, so that part RAM resource waste is caused.

In order to solve the technical problems, the application provides a new queue design scheme of a shared RAM, a group of RAM resources are virtualized into a plurality of parts, a plurality of interfaces are provided, and a time division multiplexing mode is adopted for a plurality of queues to use; the depth of the RAM queue can be adjusted according to the fine granularity of requirements, and the maximum number of queues which can be provided in the design of the FPGA network card is effectively increased, so that the RAM resource is fully utilized, and the technical problem that the exclusive RAM scheme consumes a large amount of storage resources and causes resource waste is solved.

In addition, for the problem of read-write conflict of accessing a certain group of RAM simultaneously when a queue design scheme of the shared RAM is used for a plurality of links, the application provides isolation measures of the links so as to avoid the occurrence of conflict.

After the application scenario and the design idea of the embodiment of the present application are introduced, the technical solution provided by the embodiment of the present application is described below.

For the convenience of understanding the application, the multi-queue data processing method based on the FPGA network card provided by the application is described in detail first, where the multi-queue data processing method based on the FPGA network card in the embodiment of the application is applied to the FPGA network card, and further the execution body in the embodiment of the application is the FPGA network card.

As shown in fig. 3, an embodiment of the present application provides a multi-queue data processing method based on an FPGA network card, including the following steps:

step 101: analyzing the received data packet to obtain the multi-element group information of the data packet;

illustratively, the data packets are from traffic data received through an ethernet port of the FPGA network card; the multi-tuple information of the data packet is quintuple information, wherein the quintuple information comprises: source IP address, source port, destination IP address, destination port and transport layer protocol.

Step 102: determining a first queue sequence number of a queue to which the data packet belongs according to the multi-element group information of the data packet;

illustratively, the multi-element group information of the data packet is processed by using a symmetrical hash algorithm, and a first queue sequence number of a queue to which the data packet belongs is determined. Wherein one queue is used to store data packets having the same tuple information.

Step 103: determining a shared storage area to which the queue belongs according to the first queue sequence number and the preset number; the shared memory area is a RAM memory area which is used by a preset number of queues together in a time division multiplexing mode;

in order to improve the utilization rate of the RAM storage area and enable the RAM to store more queues, in this embodiment of the present application, one RAM storage area may be used by K (preset number) queues together, that is, K queues share one RAM storage area, where K may be adjusted in fine granularity according to the depth requirement of the queues, and preferably, K is 2, 4 or 8.

Because each shared memory area is used by K queues together, a write arbitration module and a read arbitration module are designed for each shared memory area, wherein the write arbitration module is used for realizing the arbitration processing from the write interfaces of the K queues to 1 write interface of the RAM memory area, and the read arbitration module is used for realizing the arbitration processing from the read interfaces of the K queues to 1 read interface of the RAM memory area; the arbitration adopts a time division multiplexing mode to write the data of a plurality of queues into a RAM storage area.

The write arbitration module of the shared memory area maintains a head pointer, a tail pointer and a write pointer of each queue to which the write arbitration module belongs; the read arbitration module monitors the status of each queue and maintains a read pointer for the queue.

Specifically, the sequence number of the shared memory area to which the queue belongs can be determined by calculating an integer quotient of the sequence number of the first queue to a preset number.

Step 104: and writing the data packet into a queue of the first queue serial number in the shared storage area.

According to the embodiment of the application, the data packets of the queues are written into the RAM storage area, compared with the existing technical scheme that one RAM storage area is used for one queue, the RAM in the FPGA chip can support more queues, the number of queues processed by the multiple queues is increased in the available resource range, and therefore the utilization rate of RAM resources is increased.

Further, before implementing step 101, a storage area needs to be allocated to each queue, which specifically includes:

dividing the shared memory area and distributing the shared memory area to a preset number of queues; and setting a first queue sequence number of the queue.

Illustratively, as shown in FIG. 4, the total number of queues is N, the number of queues ranges from 0 to N-1, and each shared memory area is divided into 8 parts; the first shared memory area is allocated to the queues 0-7, the first shared memory area is allocated to the queues 8-15, and so on, the last shared memory area is allocated to i x 8-N-1, wherein i is the number of shared memory areas minus 1.

By allocating one RAM storage area to K queues for common use, the number of queues supported by the FPGA network card is increased by K times, and large-block RAM resources such as UltraRAM can be fully utilized, so that resource waste is avoided.

Further, after implementing step 104, the data packets in the queue need to be read out and forwarded, which specifically includes: and reading the data packet from the queue of the first queue serial number.

Alternatively, the data packet may be read from the queue of the first queue sequence number, in the following two determination manners.

First determination method

And polling the queue according to the first queue sequence number, and reading a data packet from the non-empty queue.

Second determination mode

And when the queue with the monitoring sequence number of the first queue has data packet writing, reading the data packet from the queue.

According to the embodiment of the application, the independent reading process is adopted to read the data packet from the queue and transmit the data packet, so that the backlog of the data packet can be effectively reduced, and the situation that the new data packet cannot be written due to the fact that the queue is full is prevented.

The application scene of the technical scheme is that the FPGA network card has only one link, and the problem of read-write conflict does not exist in one link. For a plurality of link application scenes of the FPGA network card for providing a plurality of PCIe interfaces; since the shared memory area is allocated with the total number of queues and the shared queue value K, it may result in queues of two adjacent links being allocated to the same shared memory area, which may cause a problem that two data packets from two links simultaneously require access to one shared memory area at the same time. For example, there are two PCIe interfaces each configured with 12 queues, the shared memory area for 8 queues; when the first PCIe interface requires the read queue 10 and the second PCIe interface requires the read queue 1, accesses of the two PCIe interfaces fall in a shared storage area at the same time, so that time division multiplexing cannot process the accesses, and read-write conflicts are caused.

In view of the above technical problems, the present application proposes a solution, as shown in fig. 4, to physically isolate the shared memory areas of two links. When the network card is initialized, the number of queues of each link is obtained, then the number of queues of each link and the shared queue value K are subjected to residual operation to obtain the number of queues (recorded as slide_Qian) which need to be adjusted for each link, then all the queue numbers of the second link are upwards adjusted by slide_qid0 values, all the queue numbers of the third link are upwards adjusted by slide_qid0+slide_qid1 values, and so on, so that all the links are physically started from a new RAM storage area, and write arbitration is carried out according to the adjusted queue numbers. During read arbitration, the queue number obtained on the second link is adjusted downward by the value slide_qid0, the queue number obtained on the third link is adjusted downward by the value slide_qid0+slide_qid1, and so on, the original queue number information is restored.

The following describes in detail a multi-queue data processing method of an FPGA network card comprising a plurality of links.

When the FPGA network card includes a plurality of links, before step 101, the method further includes:

When the FPGA network card includes multiple links, it may happen that queues of the two links use a RAM storage area together, so as to generate a read-write collision problem; by executing the steps, the situation that one RAM storage area is used for the queues of two links together is avoided, and therefore physical isolation of the two links is achieved. The specific implementation process is as shown in fig. 5:

step A1: acquiring the number of queues of each link;

step A2: performing remainder operation on the preset number of the queues of each link to obtain the number of idle queues of each link;

step A3: calculating the sum of the number of queues and the number of idle queues of each link to be used as the number of virtual queues of each link;

step A4: allocating independent link storage areas for each link according to the total number of queues; the total number of queues is the sum of the virtual number of queues of all links;

step A5: calculating the number of virtual queues of each link and an integer quotient S of a preset number, and distributing S shared memory areas for the corresponding links;

step A6: dividing each shared memory area and distributing the shared memory areas to K queues; the first queue sequence number of each queue is set.

Illustratively, as shown in fig. 6, the number of queues of the first link is N, and the number of queues of the second link is M; performing redundancy operation on the N and the set shared queue value K to obtain the idle queue quantity slide_qid0 of the first link; performing redundancy operation on M and the shared queue value K to obtain the idle queue quantity slide_qid1 of the second link; the sum of N, slide _qid0, M and slide_qid1 is taken as the total number of queues; distributing a shared memory area for each link according to the total number of queues so as to realize physical isolation; the first link uses the number of the links plus slide_qid0 to allocate the shared memory area, and the second link uses the number of the queues plus slide_qid1 to allocate the shared memory area.

As shown in fig. 7, after the allocation of the shared memory area of each link is completed, when the FPGA network card receives a data packet, the following processing steps are performed:

step B1: analyzing the received data packet to obtain the multi-element group information of the data packet;

step B2: determining a first queue sequence number of a queue to which the data packet belongs according to the multi-element group information of the data packet;

step B3: determining a queue sequence number offset value of the link according to the idle queue quantity of all links before the link to which the data packet belongs;

step B4: determining a second queue sequence number of the queue based on a sum of the first queue sequence number and the queue sequence number offset value;

step B5: determining a shared storage area to which the queue belongs according to the second queue sequence number and the preset number;

step B6: and writing the data packet into a queue of the first queue serial number in the shared storage area.

Specifically, for the queue of the first link, the sequence number of the first queue is the same as the sequence number of the second queue; for the queue of the second link, the second queue sequence number is equal to the sum of the first queue sequence number and slide_qid0; for the third link's queue, the second queue sequence number is equal to the sum of the first queue sequence number and slide_qid0+slide_qid1, and so on.

By setting the second queue sequence number of the queue, when the data packets are written into the queue, the data packets of the two links can be prevented from being written into the same RAM storage area, so that the writing conflict is effectively avoided.

reading the data packet from the queue of the second queue serial number;

Optionally, reading the data packet from the queue of the second queue sequence number; reference may be made to the following two determination modes.

First determination method

And polling the queue according to the sequence number of the second queue, and reading a data packet from the non-empty queue.

Second determination mode

And when the queue with the monitored sequence number of the second queue has data packet writing, reading the data packet from the queue.

In the multilink scene, the embodiment of the application writes the data packet according to the second queue sequence number of the queue, and correspondingly reads the data packet according to the second queue sequence number of the queue, so that the data packet can be prevented from being read and accessed to the same RAM storage area at the same time, and the read conflict is effectively avoided. Further, determining the first queue sequence number of the queue according to the second queue sequence number of the queue and the link to which the data packet belongs, includes:

Illustratively, the second queue sequence number of each queue of the first link is not adjusted; the second queue serial number of each queue of the second link is down-regulated by slide_qid0 number of the queue, the second queue serial number of each queue of the third link is down-regulated by slide_qid0+slide_qid1 number of the queue, and the original queue serial number of each queue of each link is restored by pushing the second queue serial number.

Since the second queue number of the queue is not the original queue number of the data packet, the first queue number needs to be recovered after the data packet is read out from the queue, because the first queue number corresponds to the multi-element information of the data packet.

Based on the same inventive concept, as shown in fig. 8, an embodiment of the present application provides a multi-queue data processing device based on an FPGA network card, including:

an parsing unit 201, configured to parse a received data packet to obtain multi-tuple information of the data packet;

a first determining unit 202, configured to determine, according to the multi-element group information of the data packet, a first queue sequence number of a queue to which the data packet belongs;

a second determining unit 203, configured to determine, according to the first queue sequence number and a preset number, a shared memory area to which the queue belongs;

the processing unit 204 is configured to write the data packet into a queue of the first queue sequence number in the shared memory region.

Further, the device further comprises: the first distribution unit is specifically configured to:

and setting a first queue sequence number of the queue.

Further, the device further comprises: the first data packet reading unit is specifically configured to:

and reading the data packet from the queue of the first queue serial number.

Further, the FPGA network card includes a plurality of links; the apparatus further comprises: the second distribution unit is specifically used for:

Further, the FPGA network card includes a plurality of links; the second determining unit is specifically configured to:

Further, the FPGA network card includes a plurality of links; the apparatus further comprises: the second data packet reading unit is specifically configured to:

reading the data packet from the queue of the second queue serial number;

Specifically, determining the first queue sequence number of the queue according to the second queue sequence number of the queue and the link to which the data packet belongs, includes:

Further, the first determining unit is specifically configured to:

Based on the same inventive concept, the embodiment of the present application further provides an FPGA network card, including: a memory and a processor, the memory for storing an executable program; the processor executes the executable program to implement the steps of the methods of embodiments of the present application.

The processor may be a general purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL) or any combination thereof. The general purpose processor may be a microprocessor or any conventional processor or the like.

The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.

Based on the same inventive concept, the embodiments of the present application provide a storage medium, which is a computer readable medium, storing a computer program, which when executed by a processor, implements the method provided by any of the embodiments of the present application.

Alternatively, in the present embodiment, the storage medium may include, but is not limited to: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes. Optionally, in this embodiment, the processor performs the method steps described in the above embodiment according to the program code stored in the storage medium. Alternatively, specific examples in this embodiment may refer to examples described in the foregoing embodiments and optional implementations, and this embodiment is not described herein. It will be appreciated by those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be centralized on a single computing device, or distributed across a network of computing devices, or they may alternatively be implemented in program code executable by computing devices, such that they may be stored in a memory device for execution by the computing devices and, in some cases, the steps shown or described may be performed in a different order than what is shown or described, or they may be implemented as individual integrated circuit modules, or as individual integrated circuit modules. Thus, the present application is not limited to any specific combination of hardware and software.

Furthermore, although exemplary embodiments have been described herein, the scope thereof includes any and all embodiments having equivalent elements, modifications, omissions, combinations (e.g., of the various embodiments across), adaptations or alterations as pertains to the present application. Elements in the claims are to be construed broadly based on the language employed in the claims and are not limited to examples described in the present specification or during the practice of the present application, which examples are to be construed as non-exclusive. It is intended, therefore, that the specification and examples be considered as exemplary only, with a true scope and spirit being indicated by the following claims and their full scope of equivalents.

The above description is intended to be illustrative and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. For example, other embodiments may be used by those of ordinary skill in the art upon reading the above description. In addition, in the above detailed description, various features may be grouped together to streamline the application. This is not to be interpreted as an intention that the disclosed features not being claimed are essential to any claim. Rather, the subject matter of the present application is capable of less than all of the features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that these embodiments may be combined with one another in various combinations or permutations. The scope of the application should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

While various embodiments of the present application have been described in detail, the present application is not limited to these specific embodiments, and various modifications and embodiments can be made by those skilled in the art based on the conception of the present application, which modifications and modifications are within the scope of the present application as defined in the appended claims.

Claims

1. A multi-queue data processing method based on an FPGA network card comprises the following steps:

2. The method for processing multi-queue data based on FPGA network card according to claim 1, wherein before parsing the received data packet to obtain the multi-tuple information of the data packet, the method further comprises:

and setting a first queue sequence number of the queue.

3. The FPGA network card-based multi-queue data processing method according to claim 1, after writing the data packet into the queue of the first queue serial number in the shared memory region, further comprising:

and reading the data packet from the queue of the first queue serial number.

4. The multi-queue data processing method based on the FPGA network card according to claim 1, wherein the FPGA network card comprises a plurality of links; before the received data packet is parsed to obtain the multi-group information of the data packet, the method further comprises:

5. The multi-queue data processing method based on the FPGA network card according to claim 1, wherein the FPGA network card comprises a plurality of links; determining, according to the first queue sequence number and the preset number, a shared memory area to which the queue belongs, including:

6. The FPGA network card-based multi-queue data processing method of claim 5, after writing the data packet into the queue of the first queue sequence number in the shared memory region, further comprising:

reading the data packet from the queue of the second queue serial number;

7. The FPGA network card-based multi-queue data processing method according to claim 6, wherein determining the first queue sequence number of the queue according to the second queue sequence number of the queue and the link to which the data packet belongs includes:

8. The method for processing multi-queue data based on FPGA network card according to claim 1, wherein the determining, according to the multi-group information of the data packet, the first queue sequence number of the queue to which the data packet belongs includes:

9. A multi-queue data processing device based on an FPGA network card, comprising:

10. An FPGA network card, comprising: a memory and a processor, the memory for storing an executable program; the processor executes the executable program to implement the steps of the method of any one of claims 1 to 8.