CN117650049A

CN117650049A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN117650049A
Application number: CN202311311542.6A
Authority: CN
Inventors: 范妙璇; 庄严; 林媛翎; 龚达翔
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-11-10
Filing date: 2023-10-11
Publication date: 2024-03-05

Abstract

The present disclosure relates to a semiconductor device and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming three-dimensional conductive vias parallel to each other and coated with a conformal sacrificial layer, the three-dimensional conductive vias coated with the conformal sacrificial layer being formed on a semiconductor substrate; depositing a dielectric material to fill voids between the three-dimensional conductive channels coated with the conformal sacrificial layer, wherein a portion or all of the deposited dielectric material is doped with boron, lithium, or beryllium; performing a chemical mechanical polish to remove the top of the deposited dielectric material and expose the top of the three-dimensional conductive via; after chemical mechanical polishing, the conformal sacrificial layer coating the three-dimensional conductive via is removed by etching to form a three-dimensional dielectric feature separate from the three-dimensional conductive via and comprising the deposited dielectric material.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present disclosure relates to semiconductor devices and methods of manufacturing the same, and in particular to semiconductor devices having three-dimensional transistors.

Background

The following relates to integrated circuit (integrated circuit) technology, fin-field-effect transistor (finFET) and other non-planar or three-dimensional (3D) transistor technology, integrated circuit and/or fin-field-effect transistor and/or three-dimensional transistor fabrication technology, and related techniques.

Disclosure of Invention

According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device includes the following steps. And forming a plurality of three-dimensional conductive channels which are parallel to each other and coated with the conformal sacrificial layer, wherein the three-dimensional conductive channels coated with the conformal sacrificial layer are formed on the semiconductor substrate. A dielectric material is deposited to fill the plurality of voids between the three-dimensional conductive channels coated with the conformal sacrificial layer, wherein a portion or all of the deposited dielectric material is doped with boron, lithium, or beryllium. A chemical mechanical polish is performed to remove the top of the deposited dielectric material and expose the top of the three-dimensional conductive via. After chemical mechanical polishing, the conformal sacrificial layer coating the three-dimensional conductive via is removed by etching to form a plurality of three-dimensional dielectric features separate from the three-dimensional conductive via and including the deposited dielectric material.

According to some embodiments of the present disclosure, a semiconductor device includes a plurality of three-dimensional conductive vias disposed on a semiconductor substrate, and a dielectric material Si separate from the three-dimensional conductive vias _1-x-y C _x N _y Wherein 0.ltoreq.x.ltoreq.1 and 0.ltoreq.y.ltoreq.1. Dielectric material Si of part or all of three-dimensional dielectric characteristics _1-x-y C _x N _y Doped with boron, lithium or beryllium.

According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device includes the following steps. Forming a plurality of fins coated with a conformal sacrificial layerThe fins of the layer are formed on the semiconductor substrate. Depositing a dielectric material to fill a plurality of voids between the conformal sacrificial layer coated fins, wherein a portion or all of the deposited dielectric material is doped with boron at a concentration of 10 ¹³ atoms/cm ³ To 10 ¹⁸ atoms/cm ³ And (3) the room(s). Planarization is performed to remove the top of the deposited dielectric material and expose the top of the fins. After planarization, the conformal sacrificial layer coating the fins is removed by etching to form a plurality of dummy fins separated from the fins and comprising the deposited dielectric material. A plurality of fin field effect transistors having fins as a plurality of conductive channels are fabricated.

Drawings

Aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features are not drawn to scale according to standard methods in the industry. Indeed, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 schematically illustrates a method of manufacturing a semiconductor device;

FIGS. 2,3, 4 and 5 schematically illustrate cross-sectional views of examples of states of various steps in the method of FIG. 1 for devices under manufacture;

fig. 6 schematically illustrates the mechanism by which boron doping improves the tolerance of the three-dimensional virtual fin;

FIG. 7 shows the results of the experiments described herein;

FIGS. 8, 9 and 10 schematically illustrate cross-sectional views of examples of states of various steps in the method of FIG. 1 for devices under manufacture;

FIGS. 11, 12, 13 and 14 schematically illustrate cross-sectional views of examples of states of various steps in the method of FIG. 1 for devices under manufacture;

figures 15 and 16 schematically illustrate cross-sectional views of some suitable parameters of three-dimensional virtual fins formed by the methods disclosed herein;

fig. 17 schematically illustrates a cross-sectional view of some geometric variations of a three-dimensional virtual fin formed by the methods disclosed herein.

[ symbolic description ]

10,12,14,16,18,20,22,28,30,32,34 step 38 substrate

40 three-dimensional conductive vias/three-dimensional conductive structures/fins

42 conformal sacrificial layer

44 void space

46,46 _ref Dielectric material

50,50 _ref Virtual fin

54 gap of

60 dummy gate line

62 gate cut

64 gate isolation plug

70 base dielectric layer

72 dielectric material

B is boron atom

d _swell Thickness of (A)

Height H

O is an oxygen atom

t is thickness

W is width

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter. Specific examples of components, configurations, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features are formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein to facilitate describing the relationship of one element or feature to another element or feature as illustrated. In addition to the orientations shown in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other directions) and the spatially relative descriptors used herein interpreted accordingly.

The manufacturing workflow of fin-field-effect transistor (finFET) devices, gate-all-around (GAA) transistors and other types of non-planar or three-dimensional (3D) transistors generally includes channels in the form of fins, wherein the fins of the finFET are surrounded on three sides by a gate, the fins of the gate-all-around are surrounded on all sides by a gate, or similar designs. In a typical integrated circuit (integrated circuit, IC) design employing three-dimensional transistors, a set of mutually parallel fins is made of a semiconductor material, such as etching a semiconductor substrate to expose the fins or depositing polysilicon on the substrate as fins. In the replacement gate workflow, dummy gate lines with surrounding spacers are formed over the fins, wherein the dummy gate lines are oriented perpendicular to the fins. The source and drain regions of the fin and the epitaxially deposited transistor are then etched back on opposite sides of the dummy gate line, and the dummy gate line is then replaced with a gate conductor material.

Integrated circuit fabrication workflow employing three-dimensional transistor arrays also benefits from forming dummy fins. The dummy fins are structures arranged in parallel with the "active" fins. To distinguish from dummy fins, the term "active fins" is used herein to refer to fins that are conductive transistor channels in the final integrated circuit, whereas dummy fins are not active channels of transistors in the final integrated circuit. The dummy fins may be made of a different material than the active fins, e.g., the dummy fins may sometimes be made of an electrical insulator, while the active fins are made of a semiconductor material. The dummy fins may serve multiple purposes in an integrated circuit manufacturing workflow. For example, dummy fins may be used to form electrically insulating gate isolation structures that electrically separate the plurality of gate line segments to electrically separate individual gates or groups of gates of the plurality of completed transistor devices according to the integrated circuit design. In other applications, dummy fins may be used for optical proximity correction (optical proximity correction, OPC) to enhance pattern density and pattern uniformity, or to improve chemical-mechanical polishing performance during chemical-mechanical polishing (CMP) steps of transistor fabrication processes, and/or the like.

The various embodiments disclosed herein provide improved dummy fin formation (or, more generally, improved three-dimensional dielectric feature formation that is generally aligned parallel to the three-dimensional conductive channels of a three-dimensional transistor). The various embodiments disclosed herein provide dummy fins with improved reliability and thus improve device yield in the fabrication of integrated circuits. For example, the dummy fins fabricated in accordance with the present disclosure have improved resistance to oxygen penetration and dummy fin oxidation, maintain lithographically determined critical dimensions (critical dimension, CD), and can withstand a wide range of process temperatures. These benefits may be achieved in some embodiments by incorporating interstitial (inter-plane) dopants such as boron, lithium, or beryllium into some or all of the dielectric material deposited to form the dummy fins. In other words, some or all of the dummy fins contain boron, lithium, or beryllium.

Referring to fig. 1, a non-limiting exemplary example of a method of manufacturing a semiconductor device is shown in the drawing. In step 10, three-dimensional conductive vias are formed. The three-dimensional conductive channel may be a fin for a conductive channel of a fin field effect transistor, or the three-dimensional conductive channel may be a multi-layer structure for a channel of a gate all around transistor, or may be a nanoplate structure for a channel of a nanostructure device, or the like. In some demonstrative examples herein, the three-dimensional conductive channel is a fin of a conductive channel for a fin field effect transistor. Generally, a three-dimensional conductive via is a raised structure disposed on a semiconductor substrate (e.g., a silicon wafer). As is known in the art, the use of three-dimensional conductive channels in three-dimensional transistors (e.g., fin field effect transistors or gate all around transistors or nanoplatelet transistors) may provide more contact between the surrounding gate than planar transistorsSurface area, and thus provide various transistor performance advantages. Fins or other three-dimensional conductive structures typically comprise semiconductor materials, such as silicon, silicon germanium (Si _1-x Ge _x Wherein 0 is<x<1) A group iii-v compound semiconductor such as gallium arsenide (GaAs), or the like.

In step 12, three-dimensional dielectric features (e.g., three-dimensional dummy fins) are formed. The three-dimensional dielectric features may be separate from the three-dimensional conductive vias formed in step 10, and the three-dimensional dielectric features may include a dielectric material. In the case of finfet designs, the three-dimensional dielectric feature is sometimes referred to as a dummy fin. In a non-limiting exemplary design layout, fins or other three-dimensional conductive channels are parallel to each other (at least within a designated area of the semiconductor substrate), while dummy fins are parallel to the fins and interposed between adjacent fins. As described above, the dummy fins formed in step 12 may serve several purposes, such as for forming electrically insulating gate isolation structures to electrically separate gate line segments corresponding to different transistors, providing optical proximity correction to enhance pattern density and pattern uniformity, improving cmp performance during the cmp step of the transistor manufacturing process, and/or the like.

In step 14, for a non-limiting exemplary example of a replacement gate process, a dummy gate line is formed. The dummy gate lines may, for example, include polysilicon lines, wherein the sides of the polysilicon lines are coated with silicon nitride spacers. In a non-limiting exemplary fabrication, the dummy gate lines are oriented vertically (i.e., at 90 °) to the three-dimensional conductive channels formed in step 10 and thus span over the three-dimensional conductive channels formed in step 10 and the parallel dummy fins formed in step 12, respectively. In step 16, source and drain regions are epitaxially grown on the fin or other three-dimensional conductive channel formed in step 10. For fabricating a given transistor, source and drain regions are epitaxially grown on opposite sides of a dummy gate line that passes through the region of the transistor. In step 18, dummy gate lines located at the dummy fins formed in step 12 are cut, and in step 20, gate isolation plugs are formed on the dummy fins. For example, step 18 may involve etching away dummy gate lines that cross portions of the dummy fins (thus forming openings or "cuts" in the dummy gate lines), while step 20 may involve filling these openings with an insulating material. Steps 18 and 20 thus divide the dummy gate line into a plurality of sections electrically isolated from each other. For example, each segment may be used for the gate of a single transistor. In a replacement gate process step 22, the dummy gate lines are removed, for example, polysilicon is etched using silicon nitride spacers as etch stop layers, and the resulting openings are filled with gate metal (thus "replacing" the polysilicon dummy gate with gate metal). Additional steps, not shown in fig. 1, such as forming a metallization interconnect layer of an integrated circuit to connect back end-of-line (BEOL) processes of a fin field effect transistor or other fabricated transistor may then be performed.

The semiconductor device fabrication workflow described with reference to fig. 1 is merely a non-limiting exemplary example of a fabrication workflow that may be used for virtual fins or other three-dimensional dielectric features formed in step 12 and parallel to the three-dimensional conductive vias formed in step 10.

With continued reference to fig. 1 and with further reference to fig. 2, an exemplary example of step 10 of fig. 1 is schematically depicted in fig. 2. Step 10 of fig. 1 includes forming three-dimensional conductive vias 40 parallel to each other on a substrate 38, wherein the three-dimensional conductive vias 40 are coated with a conformal sacrificial layer 42. In a non-limiting example, the substrate 38 may be, for example, a silicon substrate 38. The three-dimensional conductive path 40 may include silicon, si _1-x Ge _x Or other semiconductor material. In the illustrated embodiment, the three-dimensional conductive via 40 is a fin 40 that functions as a finfet. As other examples, the three-dimensional conductive channel may be a gate full-surrounding structure that serves as a channel for a gate full-surrounding transistor, or a nanoplate structure that serves as a channel for a nanoplate transistor. Fig. 2 shows two exemplary three-dimensional conductive vias 40 (e.g., two exemplary fins 40), however the number of three-dimensional conductive vias 40 may be greater than two. The three-dimensional conductive vias 40 are parallel to each other in some areas or regions of the fabricated integrated circuit, but the three-dimensional conductive vias of the transistors of the fabricated integrated circuit are integratedDifferent areas or regions of the circuit may have different orientations. It should also be noted that fig. 2 shows a cross-sectional view of the three-dimensional conductive via 40, wherein the cross-sectional direction is perpendicular to the long axis direction of the three-dimensional conductive via 40. In other words, the cross-section of the cross-sectional view of fig. 2 (as in fig. 3-5 discussed later) is perpendicular to the channel direction of the three-dimensional conductive channel 40. In this illustrative example, it is assumed that step 10 of forming the three-dimensional conductive via 40 also includes coating the three-dimensional conductive via 40 with a conformal sacrificial layer 42 in step 28 (referring to fig. 1). For example, the conformal sacrificial layer 42 may be a silicon nitride material or other material that may be selectively etched with respect to the semiconductor material of the three-dimensional conductive via 40. The conformal sacrificial layer 42 so coated will be removed by, for example, selective etching. The conformal sacrificial layer 42 coating the three-dimensional conductive structure 40 is conformal in that the conformal sacrificial layer 42 covers the top and sides of the three-dimensional conductive structure 40. In the illustrative example, the conformal sacrificial layer 42 is coated over the entire surface and thus also conformally coats the surface of the substrate 38 between the three-dimensional conductive structures 40. It is worth mentioning that the conformal sacrificial layer 42 does not fill the voids 44 between the three-dimensional conductive structures 40. These voids 44 serve as locations for dummy fins (or, more generally, three-dimensional dielectric features that are separate from the three-dimensional conductive channels).

The purpose of fig. 2, including the superimposed vertical split dashed lines, will be further pointed out and explained below.

With continued reference to fig. 1 and with further reference to fig. 3, 4 and 5, fig. 3-5 schematically depict exemplary examples of step 12 of fig. 1. As further shown in fig. 1, in the deposition step 30, illustratively shown in fig. 3, a dielectric material 46 is deposited to fill the voids 44 between the three-dimensional conductive vias coated with the conformal sacrificial layer. In embodiments disclosed herein, a portion or all of the deposited dielectric material is doped with boron, lithium, or beryllium. The dielectric material so deposited and doped with boron, lithium or beryllium is depicted in fig. 3 as doped dielectric material 46. Doped dielectric material 46 is shown in the left portion of fig. 3, that is, overlapping the left portion of the vertical separation dashed line. By contrast, the right-hand portion of FIG. 3 (i.e., the right-hand portion of the superimposed vertical separation dashed line) shows the reference work for a deposited and undoped boron, lithium or beryllium dielectric materialAnd (5) a flow. This is illustrated in fig. 3 as reference to deposited undoped dielectric material 46 _ref . The right-hand portion of fig. 3 is merely a schematic representation for comparison, and in an actual semiconductor device fabrication process, the deposition step 30 only deposits the doped dielectric material 46. The dopant should have a small atomic number (Z) and be included as a gap dopant in the dielectric material. Examples of interstitial dopants provided herein include lithium (z=3), beryllium (z=4), and boron (z=5). In some non-limiting exemplary embodiments, the deposited dielectric material 46 is Si _1-x-y C _x N _y Wherein x is more than or equal to 0 and less than or equal to 1, and y is more than or equal to 0 and less than or equal to 1. Deposited dielectric material 46 as a reference _ref Is Si (Si) _1-x-y C _x N _y While the deposited and doped dielectric material may be suitably designated as Si _1-x-y C _x N _y Li (lithium doped), or Si _1-x-y C _x N _y Be (beryllium doping), or Si _1-x-y C _x N _y B (boron doping). In some non-limiting exemplary embodiments, the deposited dielectric material 46 is doped with boron, lithium, or beryllium at a concentration of between 10 per cubic centimeter ¹³ Atomic number (atoms/cm) ³ ) To 10 ¹⁸ atoms/cm ³ And (3) the room(s).

In a non-limiting exemplary manner, one method of performing the deposition step 30 is chemical vapor deposition (chemical vapor deposition, CVD) of Si _1-x-y C _x N _y . In this example, the precursor may be hexamethyldisilazane (1, 3-hexamethyldisilazane) ([ (CH) ₃ ) ₃ Si] ₂ NH) or tetramethyldisilazane (1, 3-tetramethyldisilazane) ([ (CH) ₃ ) ₂ SiH] ₂ NH), siC and Si ₃ N ₄ . In this illustrative example, the dopant of the deposited dielectric material 46 is boron, which may be represented by B ₂ H ₆ 、BF ₄ Or a B precursor provides the dopant. In this non-limiting example, the flow rate is in the range of 10mL/min to 1000mL/min, the temperature is in the range of 600 ℃ to 2000 ℃, and the deposition time is in the range of 10 seconds to 1 hour. But this is merely a non-limiting exemplary example.

As shown in fig. 3, the deposited dielectric material 46 is thick enough to "bury" the three-dimensional conductive via 40 such that some of the deposited dielectric material 46 is coated on top of the three-dimensional conductive via 40. In the planarization step 32 depicted in fig. 1 and the exemplary example depicted in fig. 4, a chemical mechanical polish is performed to remove the top of the deposited dielectric material and expose the top of the three-dimensional conductive via. Although chemical mechanical polishing is described herein, other types of planarization are contemplated, such as mechanical polishing without included chemical aids. The planarizing step 32 removes enough material to expose the tops of the three-dimensional conductive vias 40, including removing portions of the conformal sacrificial layer 42 deposited on top of the three-dimensional conductive vias 40, as shown by the differences in fig. 3 and 4. This results in portions of deposited dielectric material 46 (as compared to fig. 2) that fill voids 44 between three-dimensional conductive vias 40 being separated. The remaining portion of these deposited dielectric material 46 will serve as dummy fins. However, the remaining portions of these deposited dielectric materials 46 remain physically connected to the three-dimensional conductive via 40 by the remaining portions of the conformal sacrificial layer 42 that still coat the sides of the three-dimensional conductive via 40, as shown in fig. 4. That is, after the planarization step 32, the remaining portion of the conformal sacrificial layer 42 that remains coating the sides of the three-dimensional conductive via 40 is interposed between the three-dimensional conductive via 40 and the remaining portion of the deposited and doped dielectric material 46.

In the exemplary example of the etching step 34 depicted in fig. 1 and shown in fig. 5, after the chemical mechanical polishing step 32, the (remaining) conformal sacrificial layer 42 coating the three-dimensional conductive via 40 is removed by etching to form a dummy fin 50 comprising the remaining deposited dielectric material. In a non-limiting exemplary manner, the etching step 34 may be a dry etching using argon (Ar), ammonia (NH 3), or Hydrogen Fluoride (HF) etching gas, with the performing temperature being in the range of 20 ℃ to 90 ℃. After the etching step 34, the dummy fins 50 are separated from the three-dimensional conductive vias 40 by gaps 54, as shown in fig. 5. These gaps 54 correspond to the removed conformal sacrificial layer 42 coating the sides of the three-dimensional conductive via 40. As illustrated in the left portion of fig. 5 (i.e., overlapping the left portion of the vertical separation dashed line), the deposited and doped dielectric material 46 may be resistant to the etching step 34The dummy fins 50 remaining after the etching step 34 therefore retain their shape and dimensions (i.e., critical dimensions). In contrast, as illustrated in the right-hand portion of FIG. 5 (i.e., overlapping the right-hand portion of the vertical separation dashed line), the deposited and undoped dielectric material 46 _ref The etching step 34 cannot be tolerated, and the etching step 34 instead attacks the undoped dielectric material 46 _ref And removing a portion of dielectric material 46 _ref . Thus, undoped dielectric material 46 is used _ref And dummy fins 50 remaining after etching step 34 _ref The shape and size (i.e., critical dimension) cannot be maintained, which instead results in a reduction in critical dimension.

Referring to fig. 6, without being limited to any particular theory of operation, it is believed that the improved tolerance of the deposited and doped lithium, beryllium, or boron doped dielectric material 46 results from the inclusion of lithium, beryllium, or boron dopant in the doped dielectric material 46 as a interstitial dopant, and the interstitial lithium, beryllium, or boron dopant atoms block oxygen atoms from penetrating the doped dielectric material 46. The foregoing is schematically illustrated in fig. 6, where the upper drawing shows a reference to undoped dielectric material 46 _ref While the lower drawing shows doped dielectric material 46. Oxygen atoms can permeate into the undoped dielectric material 46 as a reference _ref And causes undoped dielectric material 46 as a reference _ref Is a metal oxide semiconductor device. Thus, oxidized undoped dielectric material 46 _ref More easily damaged during the etching step 34. In the upper drawing of fig. 6, undoped dielectric material 46 is depicted _ref Is impregnated into the dielectric material 46 _ref Is denoted by the symbol "O" in FIG. 6).

In contrast, in doped dielectric material 46, lithium, beryllium, or boron interstitial dopants tend to react with oxygen proximate to the surface of dielectric material 46. An example of a boron dopant is shown in the lower drawing of fig. 6, wherein boron dopant atoms at or near the surface are labeled as symbol "B" in the lower drawing of fig. 6. The boron atom reacting with oxygen to form B ₂ O ₃ A surface layer that blocks oxygen from further penetration into the doped dielectric material 46, thus forming a B-rich layer ₂ O ₃ Surface protection of (C)And (5) protecting the layer. Similar B if oxygen may migrate from other materials into doped dielectric material 46 ₂ O ₃ Formation may also occur at or near interfaces with other materials.

Referring briefly back to fig. 3, a further benefit of lithium, beryllium or boron doping is the B-enrichment ₂ O ₃ The surface layer (or lithium oxide or beryllium oxide, respectively, in the lithium or beryllium doping) forms an additional thickness (and/or density) that can act as a sacrificial etch layer during the etching step 34. As shown in fig. 3, the deposited and doped dielectric material 46 is compared to the undoped dielectric material 46 as a reference _ref With an additional thickness d _swell . The additional thickness d can be directly observed on the upper surface _swell Additional density is also expected to accumulate on the sides of the deposited and doped dielectric material 46 in contact with the conformal sacrificial layer 42.

A further benefit of lithium, beryllium or boron doping is improved temperature stability. Since Si-B-C-N compounds generally have higher specific strength (specific strength) -temperature characteristics than Si-C-N compounds.

Referring to fig. 7, these benefits are demonstrated experimentally below. As shown in the bottom of fig. 7, the sample is prepared by (a) starting with a silicon wafer, (B) depositing a SiCN dielectric layer, (C) performing boron implantation to dope the boron (except for the "dummy only (DMY) fin" sample), and (D) performing etching according to the etching step 34 of fig. 1. A transmission electron microscope (transmission electron microscopy, TEM) was used to measure SiCN thickness before and after etching step (D). The graph of fig. 7 shows the results for four samples: only dummy fin samples (skipping boron implantation step (C)), and with sequentially increasing boron concentrations (at 10) ¹³ atoms/cm ³ To 10 ¹⁸ atoms/cm ³ In the range of (2) boron doped sample 1, boron doped sample 2 and boron doped sample 3. In the graph of fig. 7, the left bar of each sample is the thickness measured by the transmission electron microscope before the etching step (D), and the right bar is the thickness measured by the transmission electron microscope after the etching step (D). The left side of the graph shows the thickness scale (in the range 315 nm to 345 nm). Left strip (in)The difference in height between the thickness before etching and the right bar (thickness after etching) is the etching loss, which is also depicted in the graph as dots connected by lines. The right side of the graph shows the etch loss scale (in the range of-2.0 nm to 16 nm).

As shown in fig. 7, only the dummy fin samples that did not receive boron doping had an etch loss of about 13 nanometers. Boron doped sample 1, boron doped sample 2 and boron doped sample 3 show decreasing etching losses corresponding to increasing boron concentrations, wherein the boron doped sample 3 with the highest boron concentration has substantially no etching losses (actually shows an increase in thickness after etching, but such an increase is below 1 nanometer, and can therefore be considered to be within the error range of the transmission electron microscope thickness measurement). This shows that boron doping resists etching loss.

As further shown in fig. 7, the pre-etch thickness increases with increasing boron concentration, from about 323 nm for undoped samples (dummy fins only) to about 340 nm for boron doped sample 3. This can reflect the increased growth thickness d depicted in FIG. 2 _swell 。

Fig. 7 shows the results of boron doping. However, similar benefits may be obtained with lithium doping or beryllium doping. This is because lithium, beryllium and boron are atoms of similar size (the atomic order Z of lithium, beryllium and boron is z=3, z=4 and z=5, respectively), so that lithium and beryllium should also be taken as Si _1-x-y C _x N _y Is included in the semiconductor device. In addition, when boron reacts with oxygen to form B ₂ O ₃ Lithium can similarly react with oxygen to form Li ₂ O, and beryllium may similarly react with oxygen to form BeO. Thus, it is contemplated that lithium or beryllium dopant atoms at or near the surface of the dielectric material (or at or near the interface of the dielectric material and another material) will react with oxygen, thereby forming an oxide that protects the surface from further infiltration of oxygen into the deposited and doped dielectric material 46. Li with protective force ₂ O or BeO is also expected to provide surface growth. Thus, the lithium or beryllium doping can also reach the boron doping experimental results shown in fig. 7.

As a non-limiting exemplary quantization example, the three-dimensional conductive channel 40 formed in step 10 of fig. 1 may be a fin of a finfet having a fin width of about 10nm to 20 nm, and the dummy fin 50 or other three-dimensional dielectric feature formed in step 12 may also have a width of about 10nm to 40nm, while the gap 54 (refer to fig. 5) from the edge of the fin 40 to the edge of the adjacent dummy fin 50 facing the fin 40 (i.e., the thickness of the conformal sacrificial layer 42 coating the fin 40 in fig. 2-4) may be about 10nm to 40nm.

Referring to fig. 8, 9 and 10, exemplary examples of step 14, step 18 and step 20 of fig. 1 are shown. Fig. 8 shows the device in manufacture as shown in fig. 5 (with the left part of dummy fin 50 doped), extended to include three-dimensional conductive structures 40 parallel to each other, and two dummy fins 50 interposed therebetween and arranged parallel to the three-dimensional conductive structures 40. Fig. 8 shows the device after step 14, wherein a dummy gate line 60 is formed over three-dimensional conductive structures 40 (e.g., fins when fabricating a finfet) and two dummy fins 50 interposed therebetween (e.g., dummy fins when fabricating a finfet). The dummy gate lines 60 are oriented perpendicular to the fins 40 and perpendicular to the dummy fins 50. Note that dummy gate line 60 extends over fin 40 and dummy fin 50. Fig. 9 shows the device state in fabrication after step 18, wherein dummy gate lines 60 located in dummy fins 50 are cut to form gate cuts 62. Fig. 10 shows the device state in the fabrication after step 20, in which the dielectric material of the gate isolation plug 64 is formed to fill in the gate cutout 62. A replacement gate process step 22 of fig. 1 may then be performed to replace the dummy gate lines with gate conductor material. Figures 8-10 illustrate one non-limiting exemplary application of dummy fins 50. As previously described, dummy fins 50 may serve a number of purposes, such as optical proximity correction to enhance pattern density and pattern uniformity, or to improve cmp performance during the cmp step of the transistor fabrication process, and/or the like.

Referring to fig. 11, 12, 13 and 14, an alternate embodiment of forming dummy fins 50 in step 12 of fig. 1 is shown. This variant embodiment starts from the device state in the manufacture shown in fig. 2Three-dimensional conductive vias 40 coated with conformal sacrificial layers 42 and parallel to each other are provided on the semiconductor substrate 38. However, in the variant embodiment of fig. 11 to 14, the dielectric material deposition step 30 of fig. 3 is performed in two steps corresponding to the method of fig. 2 to 5. In the first step of fig. 11, a base dielectric layer 70 is formed. The base dielectric layer 70 comprises a boron, lithium or beryllium doped dielectric material (e.g., si _1-x-y C _x N _y ) Wherein a dielectric material is formed over the conformal sacrificial layer 42 coating the three-dimensional conductive via 40. The base dielectric layer 70 does not fill the voids 44 between the three-dimensional conductive vias 40. In some embodiments, the base dielectric layer 70 is formed by depositing an initial layer of dielectric material that does not have boron, lithium, or beryllium doping (this initial layer does not fill the voids 44 between the three-dimensional conductive vias 40), followed by implanting boron, lithium, or beryllium atoms into the initial layer to form a dielectric material in the base dielectric layer that is doped with boron, lithium, or beryllium, as shown in fig. 11. Next, as shown in fig. 12, after forming the base dielectric layer 70, a dielectric material without boron, lithium or beryllium doping is deposited to fill the voids between the three-dimensional conductive vias, with a dielectric material 72 that is undoped with boron, lithium or beryllium being deposited. Next, fig. 13 shows a planarization step 32, such as performing chemical mechanical polishing. Next, fig. 14 shows the result of the etching step 34. The results of fig. 14 should be similar to those shown in fig. 5. That is, as shown in the left part of fig. 14, in the left part of the superimposed vertical separation dashed line, the base dielectric layer 70 is a protective layer rich in lithium, beryllium or boron dopant, which should be Li with protective power, respectively ₂ O, beO or B ₂ O ₃ An oxide. In contrast, the undoped example of the right-hand portion of fig. 14 as a reference is the same as the right-hand portion shown in fig. 5.

Referring to fig. 15, the finfet structure in fabrication depicted in the drawings includes fins 40 formed on a substrate 38 and dummy fins 50 having boron doping, as described with reference to fig. 2-5. The dummy fins 50 are formed with boron doping levels of 10 ¹³ atoms/cm ³ To 10 ¹⁸ atoms/cm ³ Is in the range of (2). In some embodiments, the dummy fins 50 have a width W of 10nm to 20 nm, and in someIn embodiments having a height H of 20 nm to 60 nm. These are merely non-limiting exemplary ranges.

Referring to fig. 16, the finfet structure in fabrication depicted in the drawings includes fins 40 formed on a substrate 38 and dummy fins 50 having boron doping as described with reference to fig. 2 and 11-14. In some embodiments, the dummy fin 50 is formed with a base dielectric layer 70, wherein the base dielectric layer 70 has a boron doping level of 10 ¹³ atoms/cm ³ To 10 ¹⁸ atoms/cm ³ For example, in some embodiments, has a thickness t of about 0nm to about 10 nm. In some embodiments, the dummy fins 50 have a width W of 10nm to 20 nm, and in some embodiments have a height H of 20 nm to 60 nm. These are merely non-limiting exemplary ranges.

Referring to fig. 17, it should be noted that in the embodiments of fig. 11-14 and 16, the detailed shape of the boron-rich (or lithium-rich or beryllium-rich) surface (e.g., the base dielectric layer 70) over the undoped region (e.g., the dielectric material 72) of the dummy fin 50 may vary depending on the boron concentration, the detailed parameters used to form the base dielectric layer 70, and the like. Examples 1 to 8 shown in fig. 17 demonstrate some possible shapes.

Hereinafter, some further embodiments will be described.

In a non-limiting exemplary embodiment, a method of manufacturing a semiconductor device is disclosed, the method including the following steps. Three-dimensional conductive channels parallel to each other and coated with a conformal sacrificial layer are formed, and the three-dimensional conductive channels coated with the conformal sacrificial layer are formed on a semiconductor substrate. A dielectric material is deposited to fill the voids between the three-dimensional conductive channels coated with the conformal sacrificial layer, wherein some or all of the deposited dielectric material is doped with boron, lithium, or beryllium. A chemical mechanical polish is performed to remove the top of the deposited dielectric material and expose the top of the three-dimensional conductive via. After chemical mechanical polishing, the conformal sacrificial layer coating the three-dimensional conductive via is removed by etching to form a three-dimensional dielectric feature separate from the three-dimensional conductive via and comprising the deposited dielectric material.

In one placeIn some embodiments, all of the deposited dielectric material is doped with boron, lithium, or beryllium. In some embodiments, depositing the dielectric material includes forming a base dielectric layer over the conformal sacrificial layer coating the three-dimensional conductive vias, the base dielectric layer being a boron, lithium, or beryllium doped dielectric material, the base dielectric layer not filling voids between the three-dimensional conductive vias, and after forming the base dielectric layer, depositing the boron, lithium, or beryllium undoped dielectric material such that the boron, lithium, or beryllium undoped dielectric material fills voids between the three-dimensional conductive vias. In some embodiments, forming the base dielectric layer includes depositing an initiation layer of a dielectric material that is undoped with boron, lithium, or beryllium, the initiation layer not filling the voids between the three-dimensional conductive channels, and implanting boron, lithium, or beryllium atoms into the initiation layer to form the base dielectric layer of the boron, lithium, or beryllium doped dielectric material. In some embodiments, some or all of the deposited dielectric material doped with boron, lithium or beryllium has a concentration of between 10 ¹³ atoms/cm ³ To 10 ¹⁸ atoms/cm ³ And (3) the room(s). In some embodiments, some or all of the deposited dielectric material doped with boron, lithium, or beryllium is doped with boron. In some embodiments, the deposited dielectric material is Si _1-x-y C _x N _y Wherein x is more than or equal to 0 and less than or equal to 1, and y is more than or equal to 0 and less than or equal to 1. In some embodiments, the conformal sacrificial layer coating the three-dimensional conductive via comprises a silicon nitride material. In some embodiments, depositing the dielectric material includes depositing the dielectric material by chemical vapor deposition, and includes during chemical vapor deposition by providing a dielectric layer including B, B ₂ H ₆ Or BF ₄ To dope some or all of the deposited and boron doped dielectric material. In some embodiments, the method further includes fabricating a plurality of transistors on the semiconductor substrate, the transistors including a plurality of transistor channels formed from the three-dimensional conductive channels. In some embodiments, the transistor further includes a plurality of transistor gates having a plurality of gate isolation structures, the gate isolation structures aligned with the three-dimensional dielectric feature. In some embodiments, the transistor is a plurality of fin field effect transistors, the three-dimensional conductive channel is a fin of the fin field effect transistor, and the three-dimensional dielectric is uniqueThe features are virtual fins.

In a non-limiting exemplary embodiment, a semiconductor device includes a three-dimensional conductive via disposed on a semiconductor substrate, and a three-dimensional dielectric feature separated from the three-dimensional conductive via and including a dielectric material. The dielectric material of some or all of the three-dimensional dielectric features is doped with boron, lithium, or beryllium. In some embodiments, the three-dimensional conductive channel is a fin of a finfet and the three-dimensional dielectric feature is a dummy fin.

In some embodiments, the entire dielectric material Si of the three-dimensional dielectric feature _1-x-y C _x N _y Doped with boron, lithium or beryllium. In some embodiments, each of the three-dimensional dielectric features includes a three-dimensional dielectric body and a base layer disposed on the three-dimensional dielectric body, wherein the three-dimensional dielectric body includes a dielectric material Si that is undoped with boron, lithium, or beryllium _1-x-y C _x N _y The substrate layer comprises dielectric material Si doped with boron, lithium or beryllium _1-x-y C _x N _y . In some embodiments, a dielectric material Si doped with some or all of boron, lithium, or beryllium of a three-dimensional dielectric feature _1-x-y C _x N _y The concentration of doped boron, lithium or beryllium is between 10 ¹³ atoms/cm ³ To 10 ¹⁸ atoms/cm ³ And (3) the room(s). In some embodiments, the three-dimensional conductive channel is a fin of a finfet and the three-dimensional dielectric feature is a dummy fin.

In a non-limiting exemplary embodiment, a method of manufacturing a semiconductor device includes the following steps. And forming a fin coated with the conformal sacrificial layer, wherein the fin coated with the conformal sacrificial layer is formed on the semiconductor substrate. Depositing a dielectric material to fill voids between the conformal sacrificial layer coated fins, wherein a portion or all of the deposited dielectric material is doped with boron at a concentration of 10 ¹³ atoms/cm ³ To 10 ¹⁸ atoms/cm ³ And (3) the room(s). Planarization is performed to remove the top of the deposited dielectric material and expose the top of the fins. After planarization, the conformal sacrificial layer coating the fins is removed by etching to form dummy fins. Manufacturing fins with fins as conductive channelsA field effect transistor.

In some embodiments, all of the deposited dielectric material is doped with boron, or only an initial layer of dielectric material is doped with boron. In some embodiments, the deposited dielectric material is Si _1-x-y C _x N _y Wherein x is equal to or less than 1 and y is equal to or less than 0 and equal to or less than 1, and the conformal sacrificial layer coating the fins comprises a silicon nitride material.

The foregoing outlines features of some embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be understood by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a plurality of three-dimensional conductive channels parallel to each other and coated with a conformal sacrificial layer, the plurality of three-dimensional conductive channels coated with the conformal sacrificial layer being formed on a semiconductor substrate;

depositing a dielectric material to fill a plurality of voids between the plurality of three-dimensional conductive vias coated with the conformal sacrificial layer, wherein a portion or all of the deposited dielectric material is doped with boron, lithium, or beryllium;

performing a chemical mechanical polish to remove a top portion of the deposited dielectric material and expose top portions of the plurality of three-dimensional conductive vias; and

After the chemical mechanical polishing, the conformal sacrificial layer coating the plurality of three-dimensional conductive vias is removed by etching to form a plurality of three-dimensional dielectric features separate from the plurality of three-dimensional conductive vias and including the deposited dielectric material.

2. The method of claim 1, wherein all of the deposited dielectric material is doped with boron, lithium, or beryllium.

3. The method of claim 1, wherein depositing the dielectric material comprises:

forming a base dielectric layer over the conformal sacrificial layer coating the plurality of three-dimensional conductive vias, the base dielectric layer being the dielectric material doped with boron, lithium, or beryllium, the base dielectric layer not filling the plurality of voids between the plurality of three-dimensional conductive vias; and

After forming the base dielectric layer, depositing the dielectric material that is undoped with boron, lithium or beryllium such that the dielectric material that is undoped with boron, lithium or beryllium fills the plurality of voids between the plurality of three-dimensional conductive channels.

4. The method of claim 3, wherein forming the base dielectric layer comprises:

depositing an initiation layer of the dielectric material that is undoped with boron, lithium or beryllium, the initiation layer not filling the plurality of voids between the plurality of three-dimensional conductive channels; and

Boron, lithium or beryllium atoms are implanted into the initiation layer to form the base dielectric layer of the dielectric material doped with boron, lithium or beryllium.

5. The method of claim 1, wherein the conformal sacrificial layer coating the plurality of three-dimensional conductive vias comprises a silicon nitride material.

6. The method of claim 1, wherein depositing the dielectric material comprises depositing the dielectric material by chemical vapor deposition and comprising depositing the dielectric material during chemical vapor deposition by providing a dielectric layer comprising B, B ₂ H ₆ Or BF ₄ To dope some or all of the deposited and boron doped dielectric material.

7. The method as recited in claim 1, further comprising:

a plurality of transistors is fabricated on the semiconductor substrate, the plurality of transistors including a plurality of transistor channels formed from the plurality of three-dimensional conductive channels.

8. A semiconductor device, comprising:

a plurality of three-dimensional conductive vias disposed on a semiconductor substrate; and

Separate from the plurality of three-dimensional conductive vias and comprising a dielectric material Si _1-x-y C _x N _y Wherein 0.ltoreq.x.ltoreq.1 and 0.ltoreq.y.ltoreq.1;

wherein the dielectric material Si is part or all of the plurality of three-dimensional dielectric features _1-x-y C _x N _y Doped with boron, lithium or beryllium.

9. The semiconductor device of claim 8, wherein the dielectric material Si doped with the portion or all of boron, lithium, or beryllium of the plurality of three-dimensional dielectric features _1-x-y C _x N _y The concentration of doped boron, lithium or beryllium is between 10 ¹³ atoms/cm ³ To 10 ¹⁸ atoms/cm ³ And (3) the room(s).

10. A method of manufacturing a semiconductor device, comprising:

forming a plurality of fins coated with a conformal sacrificial layer, the plurality of fins coated with the conformal sacrificial layer being formed on a semiconductor substrate;

depositing a dielectric material to fill the gaps between the fins coated with the conformal sacrificial layer, wherein a portion or all of the deposited dielectric material has a boron concentration of 10 ¹³ atoms/cm ³ To 10 ¹⁸ atoms/cm ³ A compartment;

performing a planarization to remove a top portion of the deposited dielectric material and expose top portions of the fins;

after the planarizing, removing the conformal sacrificial layer coating the plurality of fins by etching to form a plurality of dummy fins separated from the plurality of fins and comprising the deposited dielectric material; and

And manufacturing a plurality of fin field effect transistors with the fins serving as a plurality of conductive channels.