CN117648263B

CN117648263B - Test method and device for design to be tested, electronic equipment and storage medium

Info

Publication number: CN117648263B
Application number: CN202410122991.4A
Authority: CN
Inventors: 郑德品; 周春怡; 夏仁涛
Original assignee: Suzhou Lianyun Technology Co ltd
Current assignee: Suzhou Lianyun Technology Co ltd
Priority date: 2024-01-29
Filing date: 2024-01-29
Publication date: 2024-05-10
Anticipated expiration: 2044-01-29
Also published as: CN117648263A

Abstract

The invention discloses a test method and device for a design to be tested, electronic equipment and a storage medium, and belongs to the field of computers. The method comprises the following steps: obtaining a target test of a design to be tested, wherein the target test comprises: at least one of a single function test of a single module, an interaction test of different functions of the single module, an interaction test between multiple modules, and an interaction test of different functions between multiple modules; acquiring a target test case corresponding to the target test based on the constructed system basic test case; the target test case at least partially inherits the system basic test case; executing target test on the to-be-tested design by using the target test case; the system basic test case comprises a basic verification environment, wherein the basic verification environment comprises: the method comprises the steps of controlling a variable library by a basic environment and verifying environments by M modules aiming at M modules in a design to be tested; the M module verification environments are in one-to-one correspondence with the M modules in the design to be tested; the base environment control variable library provides base environment control variables for controlling the M modules.

Description

Test method and device for design to be tested, electronic equipment and storage medium

Technical Field

The application belongs to the field of Internet, and particularly relates to a test method and device for a design to be tested, electronic equipment and a storage medium.

Background

With the development of technology, products are gradually designed to be more and more complex, and before the products are brought out, the functions of the products often need to be tested and verified. For example, a chip usually comprises a plurality of modules with different functions, and in the testing process of the chip, not only basic functions of each module are required to be disassembled for verification respectively, but also interaction functions among the modules are required to be tested, so that the chip can work normally under various scenes. Each module contains many functional points, and the interaction between modules has more functions, so that the interaction between the modules needs to be tested in the process of testing the functions of the chip. In order to be able to improve the chip quality, it is necessary to cover as much interaction scenarios as possible during the testing of the chip.

In the related art, it is generally necessary to generate corresponding test cases for each test scenario of a product, which easily causes a problem of a long test period.

Disclosure of Invention

The embodiment of the application provides a test method for a design to be tested, which can solve the problem of long test period caused by generating corresponding test cases aiming at various scenes in the related technology.

In a first aspect, an embodiment of the present application provides a method for testing a design to be tested, including: obtaining a target test of a design to be tested, wherein the target test comprises: at least one of a single function test of a single module, an interaction test of different functions of the single module, an interaction test between multiple modules, and an interaction test of different functions between multiple modules; acquiring a target test case corresponding to the target test based on the constructed system basic test case; the target test case at least partially inherits the system basic test case;

executing the target test on the design to be tested by utilizing the target test case; the system basic test case comprises a basic verification environment, wherein the basic verification environment comprises: a basic environment control variable library and M module verification environments for M modules in the design to be tested; the M module verification environments are in one-to-one correspondence with the M modules in the design to be tested; the base environment control variable library provides base environment control variables for controlling the M modules in the design under test.

In a second aspect, an embodiment of the present application provides a test apparatus for a design under test, including: the device comprises an acquisition module, a test module and a test module, wherein the acquisition module is used for acquiring a target test of a design to be tested, and the target test comprises: at least one of a single function test of a single module, an interaction test of different functions of the single module, an interaction test between multiple modules, and an interaction test of different functions between multiple modules; acquiring a target test case corresponding to the target test based on the constructed system basic test case; the target test case at least partially inherits the system basic test case;

The processing module is used for executing the target test on the design to be tested by utilizing the target test case; the system basic test case comprises a basic verification environment, wherein the basic verification environment comprises: a basic environment control variable library and M module verification environments for M modules in the design to be tested; the M module verification environments are in one-to-one correspondence with M modules in the design to be tested; the base environment control variable library provides base environment control variables for controlling the M modules.

In a third aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory storing a program or instructions that, when executed by the processor, implement the steps of the method according to the first aspect.

In a fourth aspect, embodiments of the present application provide a computer readable storage medium having stored thereon a program or instructions which when executed perform the steps of the method according to the first aspect.

In the embodiment of the application, a target test of a design to be tested is obtained, wherein the target test comprises the following steps: at least one of a single function test of a single module, an interaction test of different functions of the single module, an interaction test between multiple modules, and an interaction test of different functions between multiple modules; acquiring a target test case corresponding to the target test based on the constructed system basic test case; the target test case at least partially inherits the system basic test case; executing the target test on the design to be tested by utilizing the target test case; the system basic test case comprises a basic verification environment, wherein the basic verification environment comprises: a basic environment control variable library and M module verification environments for M modules in the design to be tested; the M module verification environments are in one-to-one correspondence with the M modules in the design to be tested; the base environment control variable library provides base environment control variables for controlling the M modules in the design under test. In this way, in the process of carrying out target test on a to-be-tested design (such as a product) by using the target test case each time, the target test case can select to inherit part of the content of the basic test case of the system, so that the time for generating the test case for each scene is properly reduced, the test period is shortened, and the problem that the test period is longer due to the fact that the corresponding test case is generated for each scene of the to-be-tested design in the related technology can be solved to a certain extent.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a test method for a design under test according to an embodiment of the present application;

FIG. 2 is a conceptual diagram of a system basic test case according to an embodiment of the present application;

FIG. 3 is a conceptual diagram of a module verification environment and a design under test provided by an embodiment of the present application;

FIG. 4 is a conceptual diagram of a basic verification environment and a design under test provided by an embodiment of the present application;

FIG. 5 is a flow chart of a test method for a design under test according to an embodiment of the present application;

FIG. 6 is a conceptual diagram of a module control variable library provided by an embodiment of the present application;

FIG. 7 is a conceptual diagram of a single module single function test case provided by an embodiment of the present application;

FIG. 8 is a flow chart of a test method for a design under test according to an embodiment of the present application;

FIG. 9 is a flow chart of a test method for a design under test according to an embodiment of the present application;

FIG. 10 is a conceptual diagram of a multi-module interaction test case provided by an embodiment of the present application;

FIG. 11 is a flow chart of a test method for a design under test according to an embodiment of the present application;

FIG. 12 is a flow chart of a test method for a design under test according to an embodiment of the present application;

FIG. 13 is a block diagram of a test apparatus for a design under test according to an embodiment of the present application;

Fig. 14 is a schematic diagram of an electronic device according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

As described in the background, with the development of technology, products are gradually designed to be more and more complex, and before the products come out, test verification on the functions of the products is often needed. For example, a chip usually comprises a plurality of modules with different functions, and in the testing process of the chip, not only basic functions of each module are required to be disassembled for verification respectively, but also interaction functions among the modules are required to be tested, so that the chip can work normally under various scenes. Each module contains many functional points, and the interaction between modules has more functions, so that the interaction between the modules needs to be tested in the process of testing the functions of the chip. In order to be able to improve the chip quality, it is necessary to cover as much interaction scenarios as possible during the testing of the chip. In the related art, it is generally necessary to generate corresponding test cases for each test scenario of a product, which easily causes a problem of a long test period. The embodiment of the application provides a test method for a design to be tested, which can solve the problem of long test period caused by generating corresponding test cases aiming at various scenes in the related technology to a certain extent.

The embodiment of the application provides a test case with reusability, which not only can realize the test of a single functional point, but also can realize the full-coverage interactive test of the functions of a plurality of functional points and a plurality of modules. Specifically, in the embodiment of the present application, a target test of a design to be tested is obtained, where the target test includes: at least one of a single function test of a single module, an interaction test of different functions of the single module, an interaction test between multiple modules, and an interaction test of different functions between multiple modules; acquiring a target test case corresponding to the target test based on the constructed system basic test case; the target test case at least partially inherits the system basic test case; executing the target test on the design to be tested by utilizing the target test case; the system basic test case comprises a basic verification environment, wherein the basic verification environment comprises: a basic environment control variable library and M module verification environments for M modules in the design to be tested; the M module verification environments are in one-to-one correspondence with the M modules in the design to be tested; the base environment control variable library provides base environment control variables for controlling the M modules in the design under test. In this way, in the process of carrying out target test on a to-be-tested design (such as a product) by using the target test case each time, the target test case can select to inherit part of the content of the basic test case of the system, so that the time for generating the test case for each scene is properly reduced, the test period is shortened, and the problem that the test period is longer due to the fact that the corresponding test case is generated for each scene of the to-be-tested design in the related technology can be solved to a certain extent.

In addition, all configuration parameters can be unified and random in the related art, and although more scenes can be covered, the workload is too large to cause dependence on a large number of regression, and the rapid convergence of coverage rate cannot be realized without testing emphasis. In the embodiment of the application, the target test case corresponding to the target test can be obtained according to the target test, wherein the target test comprises at least one of a single-function test of a single module, an interaction test of different functions of the single module, an interaction test among multiple modules and an interaction test of different functions among multiple modules. Therefore, the test method of the design to be tested provided by the embodiment of the application can acquire the target test case according to the test key point (target test) and execute according to the target test case, so that more scenes can be covered, the coverage rate can be converged according to the test key point, and the test efficiency is improved.

In the embodiment of the application, the basic environment control variable comprises a first control variable corresponding to the target test, the M module verification environments have target verification environments corresponding to the target test, and the target verification environments comprise a second control variable; and a target module corresponding to the target test exists in the M modules, and a target register controlled by a second control variable exists in the target module. The first control variable may be associated with the second control variable, which may be associated with a control factor of the design under test. For example, the second control variable may be associated with a target register within the design under test, the second control variable may also be associated with a control signal for the design under test, the control signal may be a high-low signal to an external connection. By associating the first control variable with the second control variable, the system basic test case can control the behavior of each module verification environment by uniformly setting the first control variable. Correspondingly, the second control variable is associated with the target register, so that the behavior of the module verification environment is consistent with the behavior of the design to be tested, and the purpose that the behavior of the system basic test case is consistent with the behavior of the design to be tested can be achieved. Furthermore, the target test cases inheriting part of the system basic test cases can influence the behavior of the design to be tested, and the purpose of carrying out target test on the design to be tested is achieved.

The method provided by the embodiment of the application is described in detail through specific embodiments and application scenes thereof with reference to the accompanying drawings. The test method of the design to be tested provided by the embodiment of the application can be executed by the target equipment, wherein the target equipment can be one electronic equipment or a plurality of electronic equipment. That is, the test method for the design to be tested provided in the embodiment of the application can be executed by one electronic device or can be executed by a plurality of electronic devices in a mutually matched manner. The electronic device may be, for example, a terminal device such as a notebook computer or a tablet, or may be a server.

Fig. 1 is a flowchart of a test method of a design under test according to an embodiment of the present application. As shown in fig. 1, the test method for a design to be tested provided in the embodiment of the present application may include the following steps:

Step 110, obtaining a target test of a design to be tested, wherein the target test comprises: at least one of a single function test of a single module, an interaction test of different functions of a single module, an interaction test of multiple modules, and an interaction test of different functions of multiple modules.

In an embodiment of the present application, the design under test (Design Under Test, DUT for short) may be a multi-module design product, such as a chip, a computer, or other complex design. When the design to be tested is a software product, the target equipment can directly test the design to be tested. When the design to be tested is a hardware product, the software logic of the design to be tested can be stored on the target equipment through simulation and treatment, and the target equipment performs test treatment.

The target test may be a test verification process for the design under test. The target test includes: at least one of a single function test of a single module, an interaction test of different functions of a single module, an interaction test of multiple modules, and an interaction test of different functions of multiple modules. For example, the design under test may include multiple modules such as module 1, module 2, module 3, and so on. When the target test is a single-function test of a single module, the function 1 of the module 1 to be designed can be tested and verified. For example, when the chip is designed to be tested, the chip includes a message receiving module, a message processing module, and a message sending module, and the target test may be a function of testing the analysis message of the message receiving module.

When the target test is an interaction test of different functions of a single module, the interaction between the function 1 of the module 1 and the function 2 of the module 1 of the design to be tested can be tested. For example, when the to-be-tested design is a switch chip, the target test may be an interaction scenario between the parsing function of the received message module and the parsing function of the received message module.

When the target test is an interaction test among multiple modules, the interaction scene between the module 1 function 1 and the module 2 of the design to be tested can be tested. For example, when the to-be-tested design is a chip, the target test may be a test of the parsing function of the receiving message module and the interaction function of the processing message module.

The target test can also be an interaction test among multiple modules, and can test interaction scenes between the function 1 and the function 2 of the module 2 of the design to be tested. For example, when the to-be-tested design is a switch chip, the target test may be an interaction scenario between the parsing function of the test receiving message module and the processing function of the processing message module.

After the design to be tested and the target test are obtained, the target test processing can be performed on the design to be tested.

Step 120, acquiring a target test case corresponding to the target test based on the constructed system basic test case; the target test case at least partially inherits the system basic test case, the system basic test case comprises a basic verification environment, and the basic verification environment comprises: a basic environment control variable library and M module verification environments for M modules in the design to be tested; the M module verification environments are in one-to-one correspondence with the M modules in the design to be tested; the base environment control variable library provides base environment control variables for controlling the M modules in the design under test.

In the embodiment of the application, the system basic test case can comprise a basic verification environment and also can comprise a design to be tested. In order to better understand the system basic test cases provided by the embodiment of the application, examples are now provided. The architecture of the system basic test case provided by the embodiment of the application can be shown in fig. 2, and the system basic test case provided by the embodiment of the application can comprise a basic verification environment and a design to be tested. The system basic test case provided by the embodiment of the application can be constructed on a verification platform development framework taking SystemVerilog (a language for verifying design functions) as a main body, for example, on a UVM platform. In the basic verification environment provided by the embodiment of the application, a basic environment control variable library can be included, and M module verification environments aiming at M modules in the design to be tested can be also included.

The basic environment control variable library provided by the embodiment of the application can comprise basic environment control variables for controlling M modules in the design to be tested, one basic environment control variable can control one module of the design to be tested, and a plurality of basic environment control variables can control one module of the design to be tested. The value range of the basic environment control variable can be a value range capable of ensuring normal operation of the design function to be tested. In the embodiment of the application, when the design to be tested is a chip, the basic environment control variable in the basic environment control variable library can control the module in the design to be tested in a wired mode, can also control the module in the design to be tested in a mode of writing an address into a register on the module in the design to be tested, and can also be related with the module in the design to be tested in other related modes referring to the specification of the chip design.

In the embodiment of the application, the module verification environment can comprise verification environment control variables with binding relation with basic environment control variables, and in the module verification environment, test processing can be performed by modifying the verification environment control variables. A monitor may also be included in the module verification environment to monitor whether or not the underlying environmental control variable changes, and how it changes, in order to verify that the environmental control variable changes to the same operation. The module verification environment can also comprise a reference model of a corresponding module of the design to be tested and a comparator, when the module verification environment control variable is modified, the modified verification environment control variable can be input into the reference model of the corresponding module to be tested, the module verification environment can acquire the output result of the reference model of the module to be tested, and the output result can be further sent to the comparator for further processing by the comparator.

After the system basic test case is constructed, a target test case corresponding to the target test can be obtained based on the constructed system basic test case, wherein the target test case at least partially inherits the system basic test case. In the embodiment of the application, the target test case can comprise a target test variable, and the target test variable can be a control variable in the design to be tested related to influencing the target test. The target test case can partially inherit the system basic test case, and can also fully inherit the system basic test case. For example, the target test case may inherit the basic environment control variable 1 and the basic environment control variable 2, and may also inherit the basic environment control variable 1, and obtain the control variable of the design to be tested corresponding to the basic environment control variable 2 from outside the system basic test case (for example, directly associated with the control variable of the design to be tested).

After the target test case is obtained, step 130 may be executed to execute the target test process on the design to be tested according to the target test case.

And 130, executing the target test on the design to be tested by utilizing the target test case.

In the embodiment of the application, after the target test case is obtained, the target test can be executed on the design to be tested according to the target test case. For example, when the target test is the function 1 of the module 1, after the target test variable in the target test case inherits the basic environment control variable 1, the value of the basic environment control variable 1 can be modified by modifying the value of the target test variable, and then the corresponding control variable of the function 1 in the design to be tested is further modified, so that the target test purpose of the design to be tested is obtained.

In the embodiment of the application, when the control variable in the design to be tested is modified, the result can be output. The module verification environment (e.g., module 1 verification environment) corresponding to the modified control variables in the design to be tested may obtain the output result of the design to be tested, and in the corresponding module verification environment, compare the output result with the output result of the reference model of the module of the design to be tested in the module verification environment. In the embodiment of the application, the module verification environment can carry out transaction-level processing aiming at the design to be tested, and the comparison result output by the module verification environment can be used as the output result of the target test, so that the user can check the comparison result conveniently.

In the embodiment of the application, a target test of a design to be tested is obtained, wherein the target test comprises the following steps: at least one of a single function test of a single module, an interaction test of different functions of the single module, an interaction test between multiple modules, and an interaction test of different functions between multiple modules; acquiring a target test case corresponding to the target test based on the constructed system basic test case; the target test case at least partially inherits the system basic test case; executing the target test on the design to be tested by utilizing the target test case; the system basic test case comprises a basic verification environment, wherein the basic verification environment comprises: a basic environment control variable library and M module verification environments for M modules in the design to be tested; the M module verification environments are in one-to-one correspondence with the M modules in the design to be tested; the base environment control variable library provides base environment control variables for controlling the M modules in the design under test. In this way, in the process of carrying out target test on a to-be-tested design (such as a product) by using the target test case each time, the target test case can select to inherit part of the content of the basic test case of the system, so that the time for generating the test case for each scene is properly reduced, the test period is shortened, and the problem that the test period is longer due to the fact that the corresponding test case is generated for each scene of the to-be-tested design in the related technology can be solved to a certain extent. Meanwhile, in the embodiment of the application, the parameter configuration aiming at the design to be tested is not random, a large number of regression can be not relied on, the coverage rate can be converged rapidly, and the verification efficiency is improved while the coverage rate is ensured.

In the embodiment of the application, the basic environment control variable comprises a first control variable corresponding to the target test, the M module verification environments have target verification environments corresponding to the target test, and the target verification environments comprise a second control variable; a target module corresponding to the target test exists in the M modules, and a target register controlled by a second control variable exists in the target module; the second control variable may be associated with a control factor of the design under test. For example, the second control variable may be associated with a target register within the design under test, the second control variable may also be associated with a control signal for the design under test, the control signal may be a high-low signal to an external connection.

In the embodiment of the present application, in the system basic test case shown in fig. 2, the first control variable and the second control variable may be associated in a binding manner. The second control variable may be associated with the destination register by adding an address to the destination register.

For a better understanding of the association of the second control variable with the target register provided by the embodiments of the present application, it is to be understood that the examples are not limiting. If the to-be-tested design is a switch chip, the target test is a message parsing function of a chip receiving message module, and accordingly, the target verification environment is a message receiving module verification environment, and the target module is a message receiving module. Fig. 3 is a block diagram of a module verification environment and a design to be tested according to an embodiment of the present application, and in fig. 3, a module verification environment for receiving a message includes: the system comprises an excitation generator, a message analyzer, a message receiving monitor, a message receiving score board and the like. The behavior of the various components in the verification environment is controlled by sub-environment control variables (i.e., second control variables). The variables may be implemented using classes (class), a type of data in a language that validates design functions (e.g., systemVerilog). For example, variable a, i.e., class a, defines p_load, pkt_num, pkt_len, to control the format, number, and length of messages sent by the stimulus generator, respectively; the variable B, namely class B, defines control variables a, B and C for controlling the message parser to parse the message, so as to control the messages in the parsing formats A, B and C respectively, and determines how to parse the messages A, B and C according to the control variables. In this way, the sub-environment control variables (i.e., the second control variables) can be associated with the registers in the design under test, ensuring that the content of the control variables in the design under test and the verification environment are consistent, i.e., class b.a=register a, class b.b=register B, class b.c=register C, registers a, B, C being the control registers used to control the design under test parse messages a, B, C.

For a better understanding of the association of the first control variable with the second control variable provided by the embodiments of the present application, examples will now be given, with the understanding that examples are not limiting. If the to-be-tested design is a switch chip, the association relationship between the first control variable and the second control variable provided in the embodiment of the present application may be as shown in fig. 4. The base environment control variable is bound to the child environment control variable, e.g., class sa=class a, class sb=class B.

By associating the first control variable with the second control variable, the system basic test case can control the behavior of each module verification environment by uniformly setting the first control variable. Correspondingly, the second control variable is associated with the target register, so that the behavior of the module verification environment is consistent with the behavior of the design to be tested, and the behavior of the system basic test case is consistent with the behavior of the design to be tested. Furthermore, the target test cases inheriting part of the system basic test cases can influence the behavior of the design to be tested, and the purpose of carrying out target test on the design to be tested is achieved.

Fig. 5 is a flowchart of a test method of a design under test according to an embodiment of the present application. As shown in fig. 5, the test method for a design to be tested provided in the embodiment of the present application may include the following steps:

step 510, obtaining a target test of the design to be tested, where the target test includes: single function testing of a single module.

Step 520, based on the constructed system basic test case, acquiring a first test case corresponding to the single-function test of the single module, and determining the first test case as a target test case.

In step 520 provided by the embodiment of the present application, the first test case inherits a pre-built target module basic test case, where the target module basic test case corresponds to the single module, and inherits the system basic test case; the target module basic test case comprises a module control variable library inheriting the basic environment control variable library. For example, when the design to be tested is a chip, the target test is the receiving function of the receiving message module. Before the first test case is obtained, a target module basic test case which corresponds to the single module and inherits the system basic test case is obtained, namely a receiving message module basic test case, and the receiving message module basic test case inherits the system basic test case.

The target module base test case (i.e., the received message module base test case) includes a module control variable library that inherits the base environment control variable library, which may be as shown in FIG. 6. It should be understood that the figures are only examples. For example, the function of the message receiving module is related to conditions such as the content of the message received by the chip, the length of the message, the setting of a related register of the message analyzed by the chip, and the like, and the test conditions are bound with a control variable 1, a control variable 2, a control variable 3 and a control variable 4 in the design to be tested. Then the module control variables that inherit the corresponding base environment control variable library (i.e., base environment control variable 1, base environment control variable 2, base environment control variable 3, and base environment control variable 4) are included in the module control variable library of the receiving message module. Because of the control variable inheritance mechanism, modification of the module control variables in the module control variable library can affect the basic environment control variables and further affect the corresponding control variables in the design to be tested. In the embodiment of the application, the verification coverage rate can be improved by constructing the module basic test case, various single functions can inherit the module test case for testing, and the reusability of the test case is improved.

After the target module basic test case is built, the first test case can inherit the pre-built target module basic test case. The first test case comprises a first target control variable library inheriting the module control variable library; the first target control variable library includes modified first target control variables, which are variables that affect the single function test. Accordingly, the first target control variable may include a variable of the inherited base environment control variable 1, a variable of the inherited base environment control variable 2, a variable of the inherited base environment control variable 3, and a variable of the inherited base environment control variable 4.

The first test case can be obtained by inheriting a pre-constructed target module basic test case, can also be obtained by directly inheriting a system basic test case, and can also be obtained by inheriting a basic environment control variable library.

And step 530, executing the target test on the design to be tested by using the target test case.

In the embodiment of the application, the first target control variable related to the target test can be randomly set in the first target control variable library inherited by the module control variable library, so that the purpose of randomly setting the basic environment control variable related to the function is achieved, and the target test is executed on the design to be tested. For example, the example of step 520, the first target controlled variable library includes a first target controlled variable that inherits the base environment controlled variable 1, a first target controlled variable that inherits the base environment controlled variable 2, a variable that inherits the base environment controlled variable 3, and a variable that inherits the base environment controlled variable 4. To achieve testing of a single function, only the first target control variable that inherits the base environment control variable 1 (when the single function of the design under test to which the base environment control variable 1 corresponds) may be modified.

In the embodiment of the application, after the target test is executed on the design to be tested by using the target test case, the first target control variable carries out the reloading processing on the basic environment control variable related to the function, i.e. the basic environment control variable value can not restore the default value. As shown in fig. 7, the architecture relationship among the first test case, the first target control variable library and the module control variable library is shown in the figure, where the first test case may be the module 1_functionally 1 test case in fig. 7, the first target control variable library may be the function 1 control variable library in fig. 7, and the module control variable library may be the module 1 control variable library in fig. 7. In the embodiment of the application, the first test case is acquired according to the target test, so that the specific environment position and output of the specific function of the design to be tested can be tested, and the pertinence of the test is increased.

Fig. 8 is a flowchart of a test method of a design under test according to an embodiment of the present application. As shown in fig. 8, the test method for a design under test provided in the embodiment of the present application may include the following steps:

step 810, obtaining a target test of a design to be tested, wherein the target test comprises: interactive testing of different functions of a single module.

Step 820, based on the constructed system basic test case, obtaining a second test case corresponding to the interaction test of different functions of the single module, and determining the second test case as a target test case.

In step 820 provided by the embodiment of the present application, the second test case inherits a pre-built target module basic test case, where the target module basic test case corresponds to the single module, and inherits the system basic test case; the target module basic test case comprises a module control variable library inheriting the basic environment control variable library.

The second test case comprises a second target control variable library inheriting the module control variable library; the second target control variable library includes modified second target control variables including a first sub-variable affecting a first function within the single module and a second sub-variable affecting a second function within the single module. The second target controlled variable library may inherit a module controlled variable library as shown in fig. 6, for example, when the target test is an interaction scenario of the module 1 function 1 and the module 1 function 2, the second target controlled variable may inherit a second target controlled variable library of the module 1 controlled variable library, for example, the module 1 controlled variable library shown in fig. 6 includes 4 module controlled variables, and then in the second target controlled variable library, 4 controlled variables may also be included, including inherited the module 1 controlled variable 1, a first sub-variable capable of affecting the first function in the single module, and inherited the module 1 controlled variable 2, and a second sub-variable capable of affecting the second function in the single module.

The second test case can be obtained by inheriting a pre-constructed target module basic test case, and can also be obtained by directly inheriting a system basic test case. If the first test case exists, the second test case can also be obtained by inheriting the first test case. Correspondingly, the second target control variable library can also be obtained by directly inheriting the basic environment control variable library, and can also be obtained by inheriting the first target control variable library. After the second target control variable library is obtained, step 830 may be performed to target the design under test.

And step 830, executing the target test on the design to be tested by using the target test case.

In the embodiment of the present application, the second target controlled variable library may also include 4 controlled variables, including a first sub-variable that inherits the controlled variable 1 of the module 1 and is capable of affecting the first function in the single module, and a second sub-variable that inherits the controlled variable 2 of the module 1 and is capable of affecting the second function in the single module. If the second controlled variable library inherits the basic environment controlled variable library and/or the module controlled variable library, the target test can be executed by sequentially changing the values of the first sub-variable and the second sub-variable in a traversing manner. If the second controlled variable library inherits the first target controlled variable library, only the values of the second sub-variables may be changed when the target test is performed on the design under test (because the values of the first sub-variables have been cyclically changed within the first target controlled variable library, each time the values of the second sub-variables are changed, the first sub-variables correspondingly complete a cycle of changing values, and the value traversal is completed by sequentially changing the values of the second sub-variables), thereby completing the target test.

In the embodiment of the application, the corresponding test cases and the control variable library are acquired according to different target tests, so that the target test is more accurately completed aiming at the design to be tested, the coverage of the target test is improved, and the test process is more comprehensive.

Fig. 9 is a flowchart of a test method of a design under test according to an embodiment of the present application. As shown in fig. 9, the test method for a design under test provided in the embodiment of the present application may include the following steps:

Step 910, obtaining a target test of the design to be tested, where the target test further includes: testing interaction among multiple modules; the multi-module includes a first module and a second module.

And step 920, acquiring a third test case corresponding to the first module based on the constructed system basic test case.

In the embodiment of the application, the third test case inherits a pre-constructed target module basic test case, the target module basic test case corresponds to the first module, and inherits the system basic test case; the target module basic test case comprises a module control variable library inheriting the basic environment control variable library. When the target test is the interaction scenario test between the module 1 function 1 and the module 2, the third test case may be the test case corresponding to the module 1, that is, the first test case in step 520, and may also be the module 1_function 1 test case on the module function test case shown in fig. 7. The third test case may be obtained by inheriting a pre-built target module basic test case (as shown in fig. 6), or may be obtained by inheriting a system basic test case shown in fig. 2, which is not particularly limited by the embodiment of the present application.

The third test case comprises a third target control variable library inheriting the target module control variable library; the third target control variable library includes modified third target control variables, which are variables that affect the function of the first module. The third target control variable library can be obtained by inheriting the target module control variable library, can be obtained by inheriting the first target control variable library, and can be obtained by inheriting the basic environment control variable library.

After the third test case and the third target control variable library are obtained, the related test case and the control variable library of the second module related to the target test can be obtained.

Step 930, obtaining a fourth test case for implementing interaction between the first module and the second module, where the fourth test case inherits the third test case, and determining the fourth test case as a target test case.

The fourth test case can also comprise a module control variable library corresponding to the second module, wherein the control variable library corresponding to the second module can be inherited from the module control variable library and can also be inherited from a basic environment control variable library. The architecture diagram of the fourth test case may be shown in fig. 10, and the module 1 function 1_module 2 interaction test case shown in fig. 10 may be the fourth test case.

And step 940, executing the target test on the design to be tested by using the target test case.

When the target test is the interaction scene test of the module 1 function 1 and the module 2, the fourth test case comprises a module 1 control variable library and a module 2 control variable library, in the process of executing the target design on the to-be-tested design, the control variable (namely, the third target control variable) related to the module 1 function 1 can be randomly set, and finally the module 1 control variable library is reloaded, so that the function interaction test of the module 1 function 1 and the module 2 can be realized. Because the fourth test case comprises the module control variable library corresponding to the second module, when the third target control variable is modified each time, the traversing cycle of the control variable of the second module is executed, so that the purpose of carrying out target test on the design to be tested can be achieved by modifying the third target control variable. In this way, the full coverage of the interaction scene between the module and other module functions can be realized.

Fig. 11 is a flowchart of a test method of a design under test according to an embodiment of the present application. As shown in fig. 11, the test method for a design under test provided in the embodiment of the present application may include the following steps:

Step 1110, obtaining a target test of a design to be tested, where the target test includes: interactive testing of different functions among multiple modules; the multi-module includes a first module and a second module.

Step 1120, obtaining a third test case corresponding to the first module based on the constructed system basic test case.

In step 1120 provided in the embodiment of the present application, the third test case inherits a pre-built target module basic test case, where the target module basic test case corresponds to the first module, and inherits the system basic test case; the target module basic test case comprises a module control variable library inheriting the basic environment control variable library; the third test case comprises a third target control variable library inheriting the module control variable library; the third target control variable library includes modified third target control variables, which are variables that affect the function of the first module. For example, when the target test is an interaction scenario test between the function 1 of the module 1 and the function 2 of the module 2, the third test case may be a test case corresponding to the function 1 of the module 1, and the third target control variable library includes a third target control variable affecting the function 1 of the design module 1 to be tested.

The third test case may further inherit a system basic test case, and the third target control variable library may further inherit a basic environment control variable library, which is not specifically limited by the embodiment of the present application. After the third test case is obtained, the third test case can be inherited again, so that the test cases corresponding to the function 1 and the function 2 of the module 1 are gradually obtained.

Step 1130, obtaining a fourth test case for implementing interaction between the first module and the second module, where the fourth test case inherits the third test case.

In step 1130 provided by the embodiment of the present application, the fourth test case includes a fourth target control variable library inheriting the third target control variable library; the fourth target control variable library includes modified fourth target control variables that are variables that affect the function of the second module. The fourth test case may be a test case corresponding to the module 2 and the function of the module 1, for example, the fourth test case in step 930 may inherit a system basic test case. The fourth test case includes a fourth target control variable library, which may inherit the underlying environment control variable library, accordingly. The fourth target controlled variable library may further comprise variables that can affect the function of the second module, i.e. the variables corresponding to module 2.

Step 1140, obtaining a fifth test case for implementing interaction of different functions between the first module and the second module, where the fifth test case inherits the fourth test case, and determines the fifth test case as a target test case.

The fifth test case inherits the fourth test case shown in fig. 10, and the fifth test case may be an interaction test case of the module 1 function 1 and the module 2 function 2. The fifth test case may include a fifth target control variable library, which may include variables that can affect the function of the second module, i.e., variables corresponding to the function 2 of the module 2.

And step 1150, executing the target test on the design to be tested by using the target test case.

In the embodiment of the application, the control variable related to the function 2 of the module 2 can be randomly set in the fifth target control variable library, and then the fifth target control variable library reloads the function 1_module 2 control variable library (i.e. the fourth target control variable library), so that all possible interactive function combinations between the function 1 of the module 1 and the function 2 of the module 2 can be realized, and further, more comprehensive test can be performed on the design to be tested. The variables in the basic environment control variable library can be indirectly reloaded through the reloading module 1 and the function 1_module 2 control variable library, so that the test of the to-be-tested design is completed.

Fig. 12 is a flowchart of a test method of a design under test according to an embodiment of the present application. As shown in fig. 12, the test method for a design under test provided in the embodiment of the present application may include the following steps:

step 1210, obtaining a target test of the design under test, where the target test includes: at least one of a single function test of a single module, an interaction test of different functions of a single module, an interaction test of multiple modules, and an interaction test of different functions of multiple modules.

If the target test is a single module single function test, e.g., the target test is a module 1 function 1 test, steps 1215 and 1250 are performed;

if the target test is an interactive test of different functions of a single module, for example, the target test is an interactive test of module 1 function 1 and module 1 function 2, step 1220 and step 1250 are performed;

If the target test is an inter-module interaction test, for example, the target test is an interaction test of module 1 function 1 and module 2, performing step 1225, step 1230 and step 1250;

If the target test is an interactive test with different functions between multiple modules, for example, the target test is an interactive test with function 1 and function 2 of module 1, steps 1235 to 1250 are performed.

In the embodiment of the application, the basic environment control variable comprises a first control variable corresponding to the target test, the M module verification environments have target verification environments corresponding to the target test, and the target verification environments comprise a second control variable; a target module corresponding to the target test exists in the M modules, and a target register controlled by a second control variable exists in the target module; the first control variable is associated with the second control variable, which is associated with the target register.

Step 1215, if the target test is a single-function test of a single module, acquiring a first test case corresponding to a single function of the single module based on the constructed system basic test case, and determining the first test case as a target test case.

The first test case inherits a pre-built target module basic test case, the target module basic test case corresponds to the single module, and inherits the system basic test case; the target module basic test case comprises a module control variable library inheriting the basic environment control variable library;

the first test case comprises a first target control variable library inheriting the module control variable library; the first target control variable library includes modified first target control variables, which are variables that affect the single function test.

Step 1220, if the target test is an interaction test with different functions of the single module, obtaining a second test case corresponding to the interaction test with different functions of the single module based on the constructed system foundation and the constructed system foundation test case based on the constructed system foundation test case, and determining the second test case as the target test case.

The second test case inherits a pre-built target module basic test case, the target module basic test case corresponds to the single module, and inherits the system basic test case; the target module basic test case comprises a module control variable library inheriting the basic environment control variable library;

The second test case comprises a second target control variable library inheriting the module control variable library; the second target control variable library includes modified second target control variables including a first sub-variable affecting a first function within the single module and a second sub-variable affecting a second function within the single module.

Step 1225, the objective test further includes: testing interaction among multiple modules; the multi-module comprises a first module and a second module, and a third test case corresponding to the first module is obtained based on the constructed system basic test case.

The third test case inherits a pre-built target module basic test case, the target module basic test case corresponds to the first module, and inherits the system basic test case; the target module basic test case comprises a module control variable library inheriting the basic environment control variable library;

The third test case comprises a third target control variable library inheriting the module control variable library; the third target control variable library includes modified third target control variables, which are variables that affect the function of the first module.

Step 1230, obtaining a fourth test case for implementing interaction between the first module and the second module, where the fourth test case inherits the third test case, and determining the fourth test case as a target test case.

Step 1235, the target test comprises: interactive testing of different functions among multiple modules; the multi-module comprises a first module and a second module, and a third test case corresponding to the first module is obtained based on the constructed system basic test case.

Step 1240, obtaining a fourth test case for implementing interaction between the first module and the second module, where the fourth test case inherits the third test case.

The fourth test case comprises a fourth target control variable library inheriting the third target control variable library; the fourth target control variable library includes modified fourth target control variables that are variables that affect the function of the second module.

Step 1245, obtaining a fifth test case for implementing interaction of different functions between the first module and the second module, where the fifth test case inherits the fourth test case, and determining the fifth test case as a target test case.

And step 1250, executing the target test on the design to be tested by using the target test case.

In the test method of the design to be tested provided by the embodiment of the application, the system basic test case and the basic environment control variable can be repeatedly inherited, so that the test case has certain reusability. Meanwhile, the value range of the basic environment control variable depends on the design to be tested, and is not a uniform random value range. Therefore, the test method of the design to be tested provided by the embodiment of the application can cover all the functional points without omission, the test has functional emphasis points, the parameter configuration is not random, the method does not depend on a large number of regression, the coverage rate can be converged rapidly, and the verification efficiency is improved while the coverage rate is ensured.

In order to better understand the test method of the design to be tested provided in the embodiment of the present application, examples will now be given, and it should be understood that the examples are not limiting. In the following examples, the design to be tested is a chip.

According to the chip design specification, a system verification environment is built based on UVM, the system verification environment comprises verification environments of all sub-modules, and in addition, the behaviors of different sub-modules and chips to be tested are controlled through basic environment control variables.

Binding the basic environment control variable with the control variable of the chip to be tested, and binding the basic environment control variable with the control variable in the module verification environment to ensure that the reference model in the verification environment is consistent with the behavior of the chip to be tested. Taking a switch chip as an example, the switch chip comprises a plurality of modules, such as a message receiving module, a message processing module, a message sending module and the like; the modules can build corresponding module verification environments, and behavior control of each component in different module verification environments is controlled by control variables inside each module.

Chip control variables generally comprise register configuration, configuration of SRAM/FLASH/MEM and the like which influence chip functions, software program loading configuration, chip interface control variables, chip data flow attribute control variables and the like; the system environment control variable library is realized in a class (class) mode, wherein the values of the system environment variables are limited to a range capable of ensuring the basic functions of the chip.

Taking a received message module as an example, the received message module verification environment includes: the system comprises an excitation generator, a message analyzer, a message receiving monitor, a message receiving score board and the like. As shown in FIG. 3, the behavior of the various components in the verification environment may be controlled by environment control variables. The variables may be implemented using classes (class), a type of data in a language that validates design functions (e.g., systemVerilog). For example, variable a, i.e., class a, defines p_load, pkt_num, pkt_len, to control the format, number, and length of messages sent by the stimulus generator, respectively; a variable B, namely class B, wherein control variables a, B and C for controlling the message behaviors analyzed by the message analyzer are defined to control the messages in the analysis formats A, B and C respectively, and how to analyze the messages A, B and C is determined by the control variables; and then, associating the module verification environment control variable with a register in the design to be tested, so as to ensure that the content of the control variable in the design to be tested is consistent with that of the control variable in the verification environment, namely, class b.a=register a, class b.b=register B, class b.c=register C, wherein the registers a, B and C are control registers used for controlling analysis messages A, B and C of the design to be tested, and ensure that the behavior of the verification environment is consistent with that of the design to be tested.

The system environment control variables and the sub-environment control variables are associated, as shown in fig. 4, a basic environment control variable class sa=a module verification control variable class a, and a basic environment control variable class sb=a module verification control variable classB.

And developing a system basic test case based on the UVM platform.

The module control variable library shown in fig. 6 is constructed, different control variable libraries are constructed according to different module functions, and the control variable libraries inherit the environment control variable library of the system. For example, the function of module 1 may be controlled by a plurality of control variables, and only the system environment control variables that have an effect on the function of module 1 may be modified in the module 1 control variable library, with modules 2,3. Taking a switch chip as an example, when the test module is a message receiving module, the function of the module is related to conditions such as the content of a message received by the chip, the length of the message, the setting of a related register of a message analyzed by the chip and the like. The test conditions are bound with control variables of control message content, message length and register content, and in the control variable library of the module 1, only the control variables related to the content can be set randomly, namely, the variables of the system environment control variables related to the function are set randomly, and other component modules of the same chip, such as a message processing module, a test case library of a message sending module and the like, are set according to the mode.

By constructing a module control variable library of the receiving message module, control variables can be set to control the setting of register specific parameters for these test conditions. That is, the function of the module control variable library is to test a specific environment setting of a specific function.

And constructing module basic test cases of different modules according to different module functions. The module basic test case inherits the system basic test case, and in the module basic test case, the module control variable library shown in fig. 6 is used for reloading the basic environment control variable library, so that the constructed module test case can realize the test of various random combinations of control variables of the module. Taking a switch chip as an example, when a test module is a message receiving module, the module test case randomly combines the message content, the message length and the settings set by related registers, and various combined full coverage effects can be achieved through multiple rounds of test; by the method, not only can the verification coverage rate be improved, but also the test case constructed by the method has strong reusability, and various single functions can be set by inheriting the test case.

The module function test case shown in fig. 7 is constructed to test a certain function of a module. For example, the module 1 has N functions, each of which is associated with a different setting of a control variable. The basic test case is a random test, so that the design defect of a single function cannot be rapidly positioned. Constructing a module function test case, for example, a test case of a function 1 of a module 1, inheriting from a module 1 basic test case, defining a new test case control variable library (namely, a first target control variable library) in the function 1 test case (namely, a first test case) of the module 1, inheriting from the module 1 control variable library, randomly setting settings related to the function 1 in the variable library, and keeping other control variables at default values; finally, the variable library (namely, a first target control variable library) is reloaded by the control variable library of the module 1; by the method, the coverage test of the single function can be realized, and the single function is ensured to have no problem.

Taking a switch chip as an example, testing the function of analyzing messages of a message receiving module, firstly defining a new test case, wherein the test case is inherited to a basic test case of the message receiving module, defining a new first target control variable library in the test case, and inheriting the first target control variable library to a control variable library of the message receiving module; the control variables for controlling the message content are set randomly, and other control variables keep default values, so that the basic test function of the module for receiving various messages can be tested. The same method for constructing test cases is used for testing other functions. This approach not only enables traversing all functions but also testing the orientation of various functional interactions in the module. For example, the combination of the message analysis function of the message receiving module and the message processing function of receiving messages with different lengths can randomly set the variable of the control message content and the variable of the control message length, so that different messages with different lengths can be randomly combined to realize the full coverage of various conditions.

The above description is directed to a single function of a single module and an interactive test of different functions of a single module, but a chip is interacted by a plurality of modules to realize various functions. To implement the interactive test of various different modules, a module function interactive test case as shown in fig. 10 may be constructed. Exemplified by the interaction between function 1 of module 1 and module 2. The new module 1_functionally 1_module 2 interactive test case (i.e., the fourth test case) inherits from the module 1 functionally 1 test case. In the test case, a new target controlled variable library (i.e., a fourth target controlled variable library) is created, inherited from the module 2 controlled variable library, then the controlled variables related to the function 1 of the module 1 are randomly set, and finally the module 1 controlled variable library is reloaded. In this way, functional interaction testing of the module 1 and the module 2 can be achieved. Taking a switch chip as an example, testing the analysis message function of the message receiving module and the interaction function of the message processing module, newly establishing a test case (namely, a fourth test case), inheriting the test case of the analysis message function of the test message receiving module, and newly establishing a target control variable library (namely, a fourth target control variable library) in the test case, wherein the variable library inherits the control variable library of the test message processing module. And then resetting variables related to the message analysis of the received message module in the variable library, so that the variables are random in the effective range specified by the specification of the chip, for example, randomly setting a message format, a message length and a register for analyzing the message. And finally, the variable library reloads the control variable library of the message receiving module. By the method, whether the message processing module can normally process various messages after the message receiving module analyzes different messages can be tested. By the method, under the condition that the analysis message registers are randomly configured for different messages with different lengths, the functions of the message receiving module are processed, and the full coverage of interaction between the analysis message functions of the message receiving module and the processing message module is ensured.

Interactions between module functions may also be tested. For example, the interaction between the test module 1 function 1 and the module 2 function 2 newly builds a test case (i.e., a fifth test case), which is inherited from the test module 1 function 1_module 2 test case (i.e., a fourth test case). The new target control variable library (i.e., the fifth target control variable library) is inherited from the module 1 function 1_mm2 control variable library (i.e., the fourth target control variable library) in the module 1 function 1_mm2 test case, the control variables related to the module 2 function 2 are randomly set in the fifth target control variable library, and the fifth target control variable library can be used to override the module 1 function 1_mm2 control variable library (i.e., the fourth target control variable library). In this way all possible combinations of interaction functions between module 1 function 1 and module 2 function 2, interactions between other modules, or interactions between module functions can be achieved in this way.

By the test method of the design to be tested, all the functional points can be covered, omission is avoided, the test has functional emphasis points, parameter configuration is not random, the method does not depend on a large number of regression, coverage rate can be converged rapidly, and verification efficiency is improved while coverage rate is ensured.

Fig. 13 is a block diagram of a test apparatus for a design under test according to an embodiment of the present application, and as shown in fig. 13, a test apparatus 1300 for a design under test according to an embodiment of the present application includes an obtaining module 1310 and a processing module 1320.

An obtaining module 1310, configured to obtain a target test of a design to be tested, where the target test includes: at least one of a single function test of a single module, an interaction test of different functions of the single module, an interaction test between multiple modules, and an interaction test of different functions between multiple modules; acquiring a target test case corresponding to the target test based on the constructed system basic test case; the target test case at least partially inherits the system basic test case;

A processing module 1320, configured to execute the target test on the design under test using the target test case;

The system basic test case comprises a basic verification environment, wherein the basic verification environment comprises: a basic environment control variable library and M module verification environments for M modules in the design to be tested; the M module verification environments are in one-to-one correspondence with M modules in the design to be tested;

the base environment control variable library provides base environment control variables for controlling the M modules.

In the test device for a design to be tested provided in the embodiment of the present application, the obtaining module 1310 obtains a target test for the design to be tested, where the target test includes: at least one of a single function test of a single module, an interaction test of different functions of the single module, an interaction test between multiple modules, and an interaction test of different functions between multiple modules; acquiring a target test case corresponding to the target test based on the constructed system basic test case; the target test case at least partially inherits the system basic test case; a processing module 1320 that performs the target test on the design under test using the target test case; the system basic test case comprises a basic verification environment, wherein the basic verification environment comprises: a basic environment control variable library and M module verification environments for M modules in the design to be tested; the M module verification environments are in one-to-one correspondence with the M modules in the design to be tested; the base environment control variable library provides base environment control variables for controlling the M modules in the design under test. In this way, in the process of carrying out target test on a to-be-tested design (such as a product) by using the target test case each time, the target test case can select to inherit part of the content of the basic test case of the system, so that the time for generating the test case for each scene is properly reduced, the test period is shortened, and the problem that the test period is longer due to the fact that the corresponding test case is generated for each scene of the to-be-tested design in the related technology can be solved to a certain extent.

Optionally, in one embodiment of the present application, the basic environment control variable includes a first control variable corresponding to the target test, and the M module verification environments include a target verification environment corresponding to the target test, and the target verification environment includes a second control variable; a target module corresponding to the target test exists in the M modules, and a target register controlled by a second control variable exists in the target module; the first control variable is associated with the second control variable, which is associated with the target register.

It should be noted that, in the present specification, the embodiment of the device for testing the to-be-tested design and the embodiment of the method for testing the to-be-tested design in the present specification are based on the same inventive concept, so that the specific implementation of the embodiment may refer to the implementation of the corresponding method for testing the to-be-tested design, and the repetition is omitted.

Fig. 14 is a schematic diagram of an electronic device according to an embodiment of the present application. As shown in fig. 14, an electronic device 1400 provided by an embodiment of the application may include a processor 1410 and a memory 1420. The memory stores a computer program that when executed implements the steps in any of the methods for testing a design under test provided in the embodiments of the present application (e.g., the method for testing a design under test shown in any of fig. 1, 5, 8, 9, 11, and 12).

The memory is used for storing programs or data, and may be, but is not limited to, random access memory (RandomAccessMemory, RAM), read-only memory (ReadOnlyMemory, ROM), programmable read-only memory (ProgrammableRead-OnlyMemory, PROM), erasable read-only memory (ErasableProgrammableRead-OnlyMemory, EPROM), electrically erasable read-only memory (ElectricErasableProgrammableRead-OnlyMemory, EEPROM), and the like.

The embodiment of the application also provides a computer readable storage medium, on which a program or an instruction is stored, which when executed by a processor, implements each process of the above method embodiment, and can achieve the same technical effects, and in order to avoid repetition, a detailed description is omitted here.

Wherein the processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium such as a computer Read Only Memory (ROM), random Access Memory (RAM), magnetic or optical disk, etc.

The embodiment of the application further provides a chip, which comprises a processor and a communication interface, wherein the communication interface is coupled with the processor, and the processor is used for running programs or instructions to realize the processes of the embodiment of the method, and can achieve the same technical effects, so that repetition is avoided, and the description is omitted here.

Embodiments of the present application provide a computer program product stored in a storage medium, where the program product is executed by at least one processor to implement the respective processes of the above method embodiments, and achieve the same technical effects, and for avoiding repetition, a detailed description is omitted herein.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a computer software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims

1. A method of testing a design under test, comprising:

Obtaining a target test of a design to be tested, wherein the target test comprises: at least one of a single function test of a single module, an interaction test of different functions of the single module, an interaction test between multiple modules, and an interaction test of different functions between multiple modules;

Acquiring a target test case corresponding to the target test based on the constructed system basic test case; the target test case at least partially inherits the system basic test case;

executing the target test on the design to be tested by utilizing the target test case;

The system basic test case comprises a basic verification environment, wherein the basic verification environment comprises: a basic environment control variable library and M module verification environments for M modules in the design to be tested; the M module verification environments are in one-to-one correspondence with the M modules in the design to be tested;

the basic environment control variable library provides basic environment control variables for controlling M modules in the design to be tested;

the basic environment control variables comprise first control variables corresponding to the target test, the M module verification environments comprise target verification environments corresponding to the target test, and the target verification environments comprise second control variables; a target module corresponding to the target test exists in the M modules, and a target register controlled by a second control variable exists in the target module;

The first control variable is associated with the second control variable, which is associated with the target register.

2. The method of claim 1, wherein the target test comprises: single function testing of a single module;

The obtaining the target test case corresponding to the target test based on the constructed system basic test case comprises the following steps:

based on the constructed system basic test cases, acquiring first test cases corresponding to the single-function test of the single module, and determining the first test cases as target test cases;

3. The method of claim 1, wherein the target test comprises: interactive testing of different functions of a single module;

Based on the constructed system basic test cases, acquiring second test cases corresponding to the interaction tests with different functions of the single module, and determining the second test cases as target test cases;

4. The method of claim 1, wherein the target test further comprises: testing interaction among multiple modules; the multi-module comprises a first module and a second module;

Acquiring a third test case corresponding to the first module based on the constructed system basic test case;

Acquiring a fourth test case for realizing interaction between the first module and the second module, wherein the fourth test case inherits the third test case, and the fourth test case is determined to be a target test case;

5. The method of claim 1, wherein the target test comprises: interactive testing of different functions among multiple modules; the multi-module comprises a first module and a second module;

acquiring a fourth test case for realizing interaction between the first module and the second module, wherein the fourth test case inherits the third test case;

Acquiring a fifth test case for realizing interaction of different functions between the first module and the second module, wherein the fifth test case inherits the fourth test case, and the fifth test case is determined to be a target test case;

the third test case comprises a third target control variable library inheriting the module control variable library; the third target control variable library includes modified third target control variables, the third target control variables being variables that affect the function of the first module;

6. A test device for a design under test, comprising:

The device comprises an acquisition module, a test module and a test module, wherein the acquisition module is used for acquiring a target test of a design to be tested, and the target test comprises: at least one of a single function test of a single module, an interaction test of different functions of the single module, an interaction test between multiple modules, and an interaction test of different functions between multiple modules; acquiring a target test case corresponding to the target test based on the constructed system basic test case; the target test case at least partially inherits the system basic test case;

the processing module is used for executing the target test on the design to be tested by utilizing the target test case;

The base environment control variable library provides base environment control variables for controlling the M modules;

7. An electronic device comprising a memory and a processor, the memory storing a program that when executed by the processor implements the method of any of claims 1-5.

8. A storage medium storing a program which when executed implements the method of any one of claims 1-5.