CN1176426C - Method of suspending bus appearance requirement - Google Patents

Abstract

The present invention relates to a method of suspending bus appearance requirements. A bus priority signal line is used for notifying a central processing unit to suspend the transmission of a requirement to a front bus. By using the present invention, a control chip for blocking a next requirement signal line for notifying the central processing unit to suspend the transmission of the requirement to the front bus is completely replaced. Moreover, the drive in the control chip for blocking a drive circuit of the next requirement signal line can be omitted. Therefore, the present invention reduces the area of the control chip, the cost of encapsulating the chip, and the power consumption of the drive circuit.

Description

The method of suspending bus appearance requirement

Technical field

The present invention relates to a kind of method of suspending bus appearance requirement, especially refer to be used between control chip and the central processing unit, temporarily stop the method that requirement appears in Front Side Bus.

Background technology

Many institutes know that all in the computer system, central processing unit is connected with control chip (being generally bridging chip) with Front Side Bus (Front Side Bus) now.And central processing unit can send many requirements (Request), and these requirements comprise that the read-write requirement of internal memory, the read-write of I/O device require or the like.Therefore, control chip can come the action of reading and writing to internal memory or peripheral device according to the requirement of central processing unit.

In general, central processing unit has multi-line (Pipeline) design, and therefore, central processing unit can be handled a plurality of requirements simultaneously.And for the multi-line of the central processing unit of arranging in pairs or groups designs, control chip also must have the ability of handling a plurality of requirements.Therefore, must there be a sequence in the control chip, be used for temporarily storing, and handles other requirement respectively by a plurality of requirements that central processing unit sent.

Yet the ability of central processing unit and control chip processing requirements all has certain limit.When control chip simultaneously processing requirements ability less than central processing unit (promptly, the number of control chip while processing requirements is less than central processing unit) time, the control chip notice central processing unit that just must be in due course requires central processing unit temporarily to stop to send requiring to control chip.Therefore, central processing unit just provides the signal wire (Block Next Request is hereinafter to be referred as the BNR signal wire) of next requirement of prevention, makes control chip can limit central processing unit and sends requirement.Certainly, central processing unit also can send the action that stops next requirement with the BNR signal wire to other device (control chip) voluntarily.

Please refer to Fig. 1, it is the operating principle of BNR signal wire between known central processing unit and the control chip.In Fig. 1, the requirement that ADS (address strobe, i.e. address strobe) signal is sent by bus owner (Bus Owner), this bus owner can be central processing unit or control chip.Suppose that this moment, the bus owner was central processing unit, promptly central processing unit whenever sends a requirement, all the ADS signal wire can be pulled to the electronegative potential one-period, is used to notify new requirement of control chip to be sent by central processing unit.

As shown in the figure, when the 2nd cycle, central processing unit sends a requirement.And at this moment, control chip finds that the number required in its sequence has arrived its limit.Therefore control chip also can utilize the BNR signal wire to send the electronegative potential of one-period in the 2nd cycle, is used to notify central processing unit to suspend and sends next requirement.Because central processing unit has been pulled to electronegative potential in the 2nd cycle detection (Sample) to the BNR signal wire, so the 4th cycle was central processing unit, and last can send the time of requirement.Promptly by the 5th cycle, central processing unit will suspend and sends requirement.When central processing unit detects on the BNR signal wire to after the electronegative potential, it must every next but two cycle detection BNR signal wire, and when the BNR signal wire was detected noble potential, central processing unit just can send new requirement again.As shown in the figure, when the 4th, 6 cycles, central processing unit detects on the BNR signal wire and is electronegative potential, i.e. the new requirement of control chip this moment impotentia reception still, and therefore, central processing unit can not send new requirement.And when the 8th cycle, central processing unit detects the BNR signal wire at noble potential, and promptly control chip can receive new requirement, and therefore, central processing unit can begin to send new requirement in the 10th cycle.

In like manner, 22 cycles of the 16th cycle to the also are another examples, require the bus owner to suspend and send new requirement.See Fig. 1, utilize to drive the BNR signal wire, can make Front Side Bus between 9 cycles of the 5th cycle to the, any requirement can not occur.In like manner, any requirement can not appear between 21 cycles of the 19th cycle to the yet.

Yet in order to make central processing unit to suspend to send new requirement, the deviser of control chip must design one drive circuit and be used to be in due course the BNR signal wire is pulled low to electronegative potential, makes central processing unit suspend and sends new requirement.And this BNR signal wire is except making the many pin positions of control chip, more can the account for area of control chip of the design of drive circuit of BNR signal wire, and driving circuit also can consume more electric energy.Therefore, how to use in the central processing unit other signal wire outside the BNR signal wire to reach can not occur any new requirement on the Front Side Bus and be the target that the present invention will reach.

Summary of the invention

The object of the present invention is to provide a kind of method of suspending bus appearance requirement, other signal wire in the utilization central processing unit outside the BNR signal wire reaches and can not occur any new requirement on the Front Side Bus.

The present invention discloses a kind of method of suspending bus appearance requirement, be used for the bus between master control set and the control device, comprise the following steps: that at first control device drives a time-out master control set and sends the signal wire of requirement, this master control set is suspended send requirement to this bus; And suspend at this master control set and to send requirement to the cycle of this bus, promptly suspend this master control set send requirement signal wire driving time and within following one-period, forbid that this control device sends requirement to this bus.

According to above-mentioned conception, this master control set can be central processing unit, and control device can be control chip, can be trunk priority power signal wire and suspend the signal wire that master control set sends requirement, also is the BPRI signal wire.

The present invention also discloses a kind of method of suspending bus appearance requirement, be used for the Front Side Bus between a central processing unit and the control chip, comprise the following steps: that control chip drives this central processing unit of time-out and sends the signal wire of requirement, this central processing unit is suspended send requirement to this Front Side Bus; And begin to drive this suspend the signal wire that this central processing unit sends requirement after two cycles to stopping to drive within this time of suspending two cycles after the signal wire that this central processing unit sends requirement, forbid that this control chip sends requirement to this Front Side Bus.

According to above-mentioned conception, the signal wire that this time-out central processing unit sends requirement can be trunk priority power signal wire (BPRI signal wire), and this control chip can be a bridging chip.

Description of drawings

The present invention utilizes following accompanying drawing and detailed description, is able to more deep explanation:

Fig. 1 is the operating principle of BNR signal wire between known central processing unit and the control chip;

Fig. 2 is the operating principle of BPRI signal wire between central processing unit and the control chip;

The ratio that Fig. 3 comes the distribution bus frequency range for known driving BPRI signal wire; And

Fig. 4 finishes the synoptic diagram that suspending bus sends requirement for the present invention utilizes the BPRI signal wire.

Embodiment

In general, central processing unit can provide unidirectional (unidirectional) trunk priority power signal wire (Bus Priority, hereinafter to be referred as the BPRI signal wire), allow control chip that real-time requirement can be provided, for example I/O device spies upon (Snoop) or delays to reply (Defer Reply), to central processing unit, take Front Side Bus for a long time to avoid central processing unit, and influence the efficient of control chip.Please refer to Fig. 2, it is the operating principle of BPRI signal wire between central processing unit and the control chip.

As shown in the figure, when the 1st, 3 cycles, central processing unit respectively sends a requirement.And when the 3rd cycle, control chip need provide real-time requirement, therefore, at the 4th periodic Control chip the BPRI central processor has been pulled to electronegative potential in the 4th cycle detection (Sample) to the BPRI signal wire, therefore it can not stop the requirement in the 5th cycle to be sent, therefore, central processing unit only can wait for that control chip sends requirement since the 6th cycle.In this example, control chip is pulled to noble potential with the BPRI signal wire by electronegative potential in the 12nd cycle after sending a requirement in the 11st cycle.This means that promptly the requirement in the 13rd cycle is sent last requirement by control chip.Therefore, central processing unit has been got back to noble potential to the BPRI signal wire in the 13rd cycle detection, and central processing unit begins after the 15th cycle and can send new requirement to control chip.

From the above, the function of BPRI signal wire allows central processing unit device in addition notify central processing unit with real-time requirement, in order to avoid cause central processing unit to take Front Side Bus for a long time, and influence the efficient of control chip.Relevant utilization can be open referring on November 7th, 2000, the patent of the United States Patent (USP) number " 6,145,040 " that Micron Technology company is had " method and apparatus of Distribution Calculation machine bus bandwidth ".This patent disclosure one bus controller is used for the monitor bus frequency range, and utilizes the BPRI signal wire to force to distribute a part of bus bandwidth to provide to claimed apparatus (Requester), and another frequency range partly then offers destination apparatus (Target).And (During a defined period) monitors the use amount (promptly two individual device are sent the shared time that requires on bus) of claimed apparatus and destination apparatus within a schedule time, and adjusts the time that two devices uses bus dynamically with the BPRI signal wire.

According to above-mentioned United States Patent (USP),, can learn clearly that bus controller is pulled to electronegative potential with the BBPRI signal wire at a fixed time as illustrating of Fig. 3, make claimed apparatus can send requirement.And utilize this mechanism to reach destination apparatus and use 5/6 bus bandwidth, and claimed apparatus uses 1/6 bus bandwidth.Certainly, bus controller can distribute this two devices to take the ratio of bus bandwidth dynamically.

The open function of BPRI signal wire on Front Side Bus of above-mentioned explanation, except control chip is sent the real-time requirement, control chip more can come balance central processing unit and control chip to take the ratio of Front Side Bus frequency range by electronegative potential that the BPRI signal wire is pulled to regularly, also is the ratio that central processing unit and control chip send requirement.

Must the additional designs one drive circuit be used to be in due course the BNR signal wire is pulled low to electronegative potential in order to solve known BNR signal wire, make the disappearance that can not occur new requirement on the Front Side Bus.The present invention utilizes the function of BPRI signal wire to reach this purpose especially.Please refer to Fig. 4, it finishes the synoptic diagram that suspending bus sends requirement for the present invention utilizes the BPRI signal wire.

As shown in the figure, when the 2nd, 4,6 cycles, central processing unit respectively sends a requirement.And when the 6th cycle, control chip finds that the number required in its sequence has soon arrived its limit, and this internal signal by control chip (the bridge sequence is faced limited signal, and Bridge Queue Threshold is called for short the BQT signal) monitors.In the 8th cycle, the BQT signal is pulled to noble potential, when the 9th cycle, control chip can be pulled to electronegative potential with the BPRI signal wire according to the indication of BQT signal, and central processing unit is electronegative potential in the 9th cycle detection to the BPRI signal wire, therefore, last requirement meeting of central processing unit was sent in the 10th cycle.Therefore, central processing unit only can send requirement since the 11st cycle time-out.When the 16th periodic Control chip can receive new the requirement, the BQT signal promptly was back to electronegative potential by noble potential.When the 18th cycle, control chip can be pulled to noble potential with the BPRI signal wire according to the indication of BQT signal.And central processing unit finds that when the 18th cycle the BPRI signal wire has returned back to noble potential, and therefore, central processing unit can begin to send new requirement again after the 20th cycle.

At above-mentioned motion flow, though control chip is pulled to electronegative potential with the BPRI signal wire, yet control chip does not send any requirement to bus.Therefore in 19 cycles of the 11st cycle to the, any requirement can't appear in front end.Therefore, use this mode, can reach the present invention, do not utilize the driving circuit of BNR signal wire, and can limit the central processing unit time-out on any suitable opportunity and send new requiring, to reach the interval that can not occur any requirement on the Front Side Bus to bus.

Described above comprehensive, the present invention utilizes the BPRI signal wire to suspend central processing unit and sends new requirement, and when the BPRI signal wire drives, control chip can not send any requirement, therefore, can realize that the present invention suspends the target of sending requirement on the bus, and the driving circuit that drives the BNR signal wire can be omitted fully, therefore can reduce the area of control chip, the cost of Chip Packaging, and the consumption of drive circuit power.

Claims (7)

1. the method for a suspending bus appearance requirement is used for the bus between a master control set and the control device, it is characterized in that, comprises the following steps:

Control device drives a time-out master control set and sends the signal wire of requirement, this master control set is suspended send requirement to this bus; And

Send requirement to the cycle of this bus at this master control set time-out, forbid that this control device sends requirement to this bus.

2. the method for suspending bus appearance requirement as claimed in claim 1 is characterized in that, this master control set is a central processing unit.

3. the method for suspending bus appearance requirement as claimed in claim 1 is characterized in that, this control device is a control chip.

4. the method for suspending bus appearance requirement as claimed in claim 1 is characterized in that, the signal wire that this time-out master control set sends requirement is a trunk priority power signal wire.

5. the method for a suspending bus appearance requirement is used for the Front Side Bus between a central processing unit and the control chip, it is characterized in that, comprises the following steps:

Control chip drives a time-out central processing unit and sends the signal wire of requirement, this central processing unit is suspended send requirement to this Front Side Bus; And

After beginning to drive the signal wire that this time-out central processing unit sends requirement, within the time in two cycles after stopping to drive the signal wire that this time-out central processing unit sends requirement in two cycles, forbid that this control chip sends requirement to this Front Side Bus.

6. the method for suspending bus appearance requirement as claimed in claim 5 is characterized in that, the signal wire that this time-out central processing unit sends requirement is a trunk priority power signal wire.

7. the method for suspending bus appearance requirement as claimed in claim 5 is characterized in that, this control chip is a bridging chip.

Images