CN1095125C - Extendible type arbitration device of sharing system memorizer - Google Patents
Extendible type arbitration device of sharing system memorizer Download PDFInfo
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- CN1095125C CN1095125C CN 95117203 CN95117203A CN1095125C CN 1095125 C CN1095125 C CN 1095125C CN 95117203 CN95117203 CN 95117203 CN 95117203 A CN95117203 A CN 95117203A CN 1095125 C CN1095125 C CN 1095125C
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Abstract
The present invention relates to an extendible arbitration device of sharing system memorizers. A sharing system memorizer of peripheral devices is arranged between the peripheral devices and a main logic chip group by two or three arbitration holding signals by the arrangement of an arbitration bus between the peripheral devices and the main logic chip group; the main logic chip group is used for arbitrating the control power of the peripheral devices to the system memorizer. In addition, the present invention also has a preoccupying function. The control power of the peripheral devices is delayed within some prescribed time. Finally, the peripheral devices are respectively coupled into RAS-IN on the main logic chip group by RAS signals in the mode of a collector broken circuit.
Description
The present invention is relevant for computer system, particularly relevant for a kind of expansible type arbitration device that is applicable to the sharing system memory of computer system.
Please refer to Fig. 1, be depicted as the block diagram of knowing a computer system structure.This computer system comprises a CPU (central processing unit) 10 (CPU), a main logic chipset 11 (CoreLogic Chipset), a system storage 12 and a plurality of peripheral unit 13,14,15 etc., each peripheral unit 13,14,15 is provided with exclusive regional memory 13M, 14M, 15M etc. respectively, usefulness as data storing and buffering, in addition, still have a main bus 16 (Host Bus), a peripheral cell interface bus 17 (PeripheralComponentInterface Bus:PCI Bus) and a memory bus 18.CPU (central processing unit) 10 is carried out the exchange of data via main bus 16 and main logic chipset 11, and main logic chipset 11 carries out exchanges data via memory bus 18 and system storage 12, moreover each peripheral unit 13-15 carries out exchanges data via peripheral cell interface bus 17 and main logic chipset 11 respectively.
Yet, in this computer architecture of knowing, each peripheral unit (is a display system for example, regional network system, mpeg system etc.) all has exclusive regional memory, and the required data of this regional memory must by self driver, after seeing through CPU (central processing unit) 10 execution, arrive peripheral unit 13 through main logic chipset 11 and peripheral cell interface bus 17 in regular turn, 14,15 receive, be sent to its exclusive regional memory 13M more respectively, 14M, in the 15M, this data transfer path can be shown: CPU (central processing unit) 10 → main bus 16 → main logic chipset 11 → peripheral cell interface bus 17 → peripheral unit 13-15 → regional memory 13M-15M, in this way, transmit by CPU (central processing unit) 10 and to this very long path of regional memory 13M-15M palpus process, with regard to the efficient of data transmission, can expend the time that is transformed on each bus, moreover each peripheral unit is provided with exclusive regional memory individually and does not also meet considering of economic benefit.
Because the general required storer of peripheral unit is all little, so on the whole peripheral unit only provides a row address strobe RAS (Row Address Strobe) signal wire, correspond to a groups of memories to couple, the regional memory if want to sublate and shared with system storage, because of system storage 12 has several groups, and can change along with user's expansion, knowing some practice all can limit the user and must plug storer in specific group, perhaps must use bonding line (Jumper) mode to adjust, thereby cause user's inconvenience.
In view of this, fundamental purpose of the present invention, be to provide a kind of expansible type arbitration device of sharing system memory, only need to obtain the purpose that makes the peripheral unit sharing system memory by two or three arbitration handshake are set between main logic chipset and each peripheral unit.
And another object of the present invention is to provide a kind of method that improves sharing system memory efficient, shortens CPU (central processing unit) and makes memory-aided transmission level to peripheral unit, and can improve overall system efficiency.
In addition, a further object of the present invention, be to provide a kind of expansible type arbitration device of sharing system memory, the peripheral unit that can automatically switch corresponds to the group under the system storage, make the group that the employed system storage of peripheral unit needn't be confined to fix, and preferable application elasticity can be arranged.
For realizing above-mentioned purpose of the present invention, a kind of expansible type arbitration device of sharing system memory is provided, comprising: a memory bus; One system storage is coupled on this memory bus; One main logic chipset is coupled on this memory bus, does exchanges data via this memory bus and this system storage; A plurality of peripheral units are coupled to this memory bus, do exchanges data with this system storage respectively via this memory bus; Obtaining fair signal with one first request signal, one second request signal and between each this peripheral unit and this main logic chipset couples each other, wherein, described first and second request signals are to this main logic chipset by this peripheral unit, require to use the signal of this system storage, and this obtain fair signal be by this main logic chipset to this peripheral unit, fairly count the signal that this peripheral unit uses this system storage; When this peripheral unit makes this first request signal effective, when requiring to use this system storage, then to make this obtain fair signal in a very first time at interval effective for this main logic chipset, informs that this peripheral unit can use this system storage; When this peripheral unit makes this second request signal effective, when requiring to use this system storage, then to make this obtain fair signal in one second time interval effective for this main logic chipset, informs that this peripheral unit can use this system storage, and this in second time interval system less than this very first time at interval; And, when this main logic chipset must use this system storage, then this main logic chipset makes this obtain fair invalidating signal, and person one of in this first and second request signal that has been effective, must in one the 3rd time interval, make it invalid, also can comprise: a memory bus by the expansible type arbitration device that a kind of sharing system memory is provided; One system storage is coupled on this memory bus; One main logic chipset is coupled on this memory bus, does exchanges data via this memory bus and this system storage; A plurality of peripheral units are coupled to this memory bus, do exchanges data with this system storage respectively via this memory bus; Obtaining fair signal with a request signal and between each this peripheral unit and this main logic chipset couples each other, wherein, this request signal is to this main logic chipset by this peripheral unit, require to use the request signal of this system storage, and this obtain fair signal be by this main logic chipset to this peripheral unit, allow this peripheral unit to use the handshaking signal of this system storage; When this peripheral unit makes this request signal effective, when requiring to use this system storage, then to make this obtain fair signal in a very first time at interval effective for this main logic chipset, informs that this peripheral unit can use this system storage; When this peripheral unit gating and after triggering this request signal, when requiring to use this system storage, then to make this obtain fair signal in one second time interval effective for this main logic chipset, informs that this peripheral unit can use this system storage, and this second time interval less than this very first time at interval; And when this main logic chipset must use this system storage, then this main logic chipset made this obtain fair invalidating signal, and this request signal that has been effective must make it invalid in one the 3rd time interval.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Brief Description Of Drawings:
Fig. 1 is a block diagram of knowing a computer system structure;
Fig. 2 is the block diagram according to a computer system of the present invention;
Fig. 3 is the block scheme according to an arbitration device of the present invention;
Fig. 4 files a request and through obtaining fair sequential chart according to Fig. 3 normal priority;
Fig. 5 files a request and through obtaining fair sequential chart according to Fig. 3 high priority;
Fig. 6 is badly in need of system storage according to Fig. 3 when the main logic chipset to cause peripheral unit to abdicate the sequential chart of control;
Fig. 7 is the circuit diagram that no high low priority makes HPREQ# lose efficacy;
Fig. 8 is the block scheme of another arbitration device according to the present invention;
Fig. 9 files a request and through obtaining fair sequential chart according to Fig. 8 normal priority;
Figure 10 files a request and through obtaining fair sequential chart according to Fig. 8 high priority;
Figure 11 is badly in need of system storage according to Fig. 8 when the main logic chipset to cause peripheral unit to abdicate the sequential chart of control; And
Figure 12 automaticallyes switch shared storage to suitable system storage group structural representation by peripheral unit.
Please refer to Fig. 2, be depicted as block diagram according to a computer system structure of the present invention.Computer system according to the present invention comprises a CPU (central processing unit) 20 (CPU), a main logic chipset 21 (CoreLogic Chipset), a system storage 22 and a plurality of peripheral unit 23,24,25 etc., this figure is an example with three peripheral units only, the number of right peripheral unit does not exceed with three, one, two and even greater than all being applicable to the present invention more than three; In addition, still have a main bus 26 (Host Bus), a peripheral cell interface bus 27, one shared memory bus 28 and an arbitration bus 29 (ArbitrationBus); CPU (central processing unit) 20 is carried out the exchange of data via main bus 26 and main logic chipset 21, main logic chipset 21 and each peripheral unit 23-25 carry out exchanges data through shared storage bus 28 and system storage 22, moreover, main logic chipset 21 and each peripheral unit 23-25 branch are clipped to peripheral cell interface bus 27, carry out the running of various I/O.In addition, still make each peripheral unit 23,24,25 RAS that is exported (Row AddressStrobe) signal RAS0, RAS1, RAS2 according to the present invention, mode with open collector (Open-collector) links together, and becomes a RAS_IN signal to main logic chipset 21.
For making peripheral unit energy shared system storer 22, then must control by being provided with of arbitration bus 29, please refer to Fig. 3, be depicted as the block scheme of one arbitration device according to the present invention, wherein, the arbitration agreement (arbitration protocol) of three exclusive arbitration handshake GNT#, REQ# and HPREQ# is set respectively between main logic chipset 21 and peripheral unit 23-25, and and close these the arbitration handshake be arbitration bus shown in Figure 2 29; Fig. 3 is only with a peripheral unit 23 and 21 three set arbitration handshake GNT# of main logic chipset, REQ#, HPREQ# is an example, wherein, REQ# and HPREQ# are by the signal of peripheral unit 23 to main logic chipset 21, GNT# is the signal of main logic chipset 21 to peripheral unit 23, and being peripheral unit 23, REQ# requires the normal priority control signal of using system storer 22, HPREQ# is the high priority control signal that peripheral unit 23 requires using system storer 22, GNT# is then for allowing the control signal of peripheral unit 23 using system storeies 22, and annotate behind each arbitrating signals with " # " person, represent that this signal is negative logic action (active-low).
Yet, according to two settings that require signal REQ# and HPREQ# of Fig. 3, it is the processing that to distinguish peripheral unit normal priority (normal priority) and high priority (highpriority), be for a display system (GraphicSystem) is that example is done an explanation with peripheral unit 23 for example, display system need be used the storer person can divide into following several such as:
(1) cathode-ray tube (CRT) upgrades (CRT refresh) action, causes screen can not glimmer or beat.
(2) position display of hardware cursor (Hardware cursor), for example position of slide-mouse vernier under form (windows) operating system.
(3) figure quickens processing (Graphic engine activity) etc.
In the above-mentioned action, higher with the right of priority of (1) and (2), can to make the user directly experience screen out of joint because of it, and therefore the processing about (1) and (2) is the request of sending using system storer 22 with the HPREQ# signal; (3) then be the action that needs a large amount of access memories, can take 28 considerable times of memory bus, right user also arrives than unsusceptibility, moreover, also for avoiding CPU (central processing unit) 20 to rob chance less than the using system storer, cause total system efficient to reduce, therefore, (3) action only need be sent REQ# and be got final product, treat the neutral gear after CPU (central processing unit) 20 is finished system storage 22 accesses, reply GNT# by main logic chipset 21 again, and the control of system's storage is yielded display system.
Figure 4 shows that the sequential chart of REQ# and GNT#, file a request by REQ# and begin only to reply, through T by GNT#
1Time; Figure 5 shows that the sequential chart of HPREQ# and GNT#, file a request by HPREQ# and begin only to reply, only pass through T by GNT#
2Time, and make T
1＞＞T
2Value as for reality is " able to programme ", demand on peripheral unit 23 is decided, arbitration specification in this way is applicable to when same peripheral unit is distinguished the different processing demands of emergency to system memory access, can distinguish the order of its priority processing by REQ# and HPREQ#, and make GNT# do the different response of emergency, to improve the efficient of system.If peripheral unit 23 only must a kind of priority level, then peripheral unit only needs when resetting, be " height " logic level by a reset signal RESET and HPREQ# output, main logic chipset 21 just is not subjected to the influence of HPREQ# automatically in this way, whether need only differentiate REQ# is that negative logic gets final product, this reference line figure that makes HPREQ# invalid (disable) promptly as shown in Figure 7, it comprises: one or the door 32 and one latch 34, the HPREQ# signal simultaneously to or the door 32 and latch 34 on respectively as an input signal, RESET signal controlling latch becomes the output of one " height " logic level, and to or door 32 as its another input signal, then, again with or door 32 output signal to main logic chipset 21, replace the former mode that directly is coupled to main logic chipset 21 with HPREQ#; Otherwise, can also make main logic chipset 21 not be subjected to the influence of REQ# by identical circuit, only file a request, and make this arbitration structure have great elasticity with HPREQ#.
In addition, as shown in Figure 6, the present invention more proposes to get earlier the function of (Preempt), that is regulation is when main logic chipset 21 is badly in need of the control of system storage 22, for example be when CPU (central processing unit) 20 makes data register in the main logic chipset 21 that system storage 22 is done data access via main bus storer 26, main logic chipset 21 can will allow the signal GNT# that gives peripheral unit 23 using system storeies 22 to draw " height ", and peripheral unit 23 must be in T
3Time in, the control of system storage 22 is got out of the way, and simultaneously REQ# or HPREQ# level are drawn " height ", when main logic chipset 21 learns that REQ#/HPREQ# is " height " level, just can carry out the data access of 22 of itself and system storages, unlikelyly expended in the time of waiting for for a long time excessively, cause overall system efficiency to descend, also T
3Numerical value also be able to programme, be that the demand of viewing system is done flexible adjustment.
Moreover, please refer to Fig. 8, be depicted as the block scheme of another kind of arbitration device according to the present invention, wherein be respectively arranged with the arbitration agreement (arbitration protocol) of two REQ# and GNT# signal between main logic chipset 21 and peripheral unit 23-25, and and close these arbitrating signals and be arbitration bus shown in Figure 2 29; Fig. 8 only shows that with a peripheral unit 23 and 21 set two arbitration signal GNT# and REQ# of main logic chipset be example, wherein, REQ# is by the signal of peripheral unit 23 to main logic chipset 21, GNT# is the signal of main logic chipset 21 to peripheral unit 23, REQ# is the request signal that peripheral unit 23 requires using system storer 22, GNT# is the fair signal that obtains that peripheral unit 23 allows using system storer 22, represents that this signal is negative logic action (activelow) and annotate behind each signal with " # " person again.
Though and the arbitration device of Fig. 8 only has a request signal REQ#, also can distinguish the processing of peripheral unit normal priority and high priority, and the processing of high priority, for example be that the cathode-ray tube (CRT) of aforementioned display system upgrades or action such as hardware cursor position display, handling as for normal priority, for example is that figure quickens processing etc. in the display system.Figure 9 shows that according to Fig. 8 and file a request via normal priority and through obtaining fair sequential chart, file a request to reply via REQ# and end, through T to GNT#
4Time.And Figure 10 shows that according to Fig. 8 and file a request and through obtaining fair sequential chart through high priority, promptly be the triggering beginning of time T via REQ#, reply until GNT# and end, only pass through T
5Time, and make T
4＞＞T
5Value as for reality is " able to programme ", demand on peripheral unit 23 is decided, arbitration specification in this way also is applicable to that same peripheral unit distinguishes when the different processing demands of emergency is arranged system memory access, can be by the order of whether distinguishing its priority processing of REQ# triggering, make GNT# do the different response of emergency, use the efficient of raising system.
Moreover, the arbitration device of Fig. 8 also has earlier the function of getting (Preempt), that is be badly in need of the control of system storages 22 when main logic chipset 21, for example be to work as CPU (central processing unit) 20 via main bus 26, when the data register in main logic chipset 21 is done data access to system storage 22, main logic chipset 21 can will allow the signal GNT# that gives peripheral unit 23 using system storeies 22 to draw " height ", and peripheral unit 23 must be in T
6Time in, the control of system storage 22 is got out of the way, promptly as shown in figure 11, and simultaneously the REQ# level is drawn " height "; When main logic chipset 21 learns that REQ# is " height " level, make the data access that can carry out 22 of itself and system storages, unlikelyly expend the too much stand-by period, cause overall system efficiency to descend, furthermore T
6Numerical value can be programmed, the demand of viewing system is done flexible adjustment.
As the well known structures that Fig. 1 disclosed, for example if through CPU (central processing unit) 10 data are filled out in its regional memory 13M by the driver (driver) of peripheral unit 13, via the path be CPU (central processing unit) 10 → main bus 16 → main logic chipset 11 → peripheral cell interface bus 17 → peripheral unit 13 → regional memory 13M etc., the efficient of system is quite bad.Yet, the present invention proposes the path of a high speed, be CPU (central processing unit) 20 → main bus 26 → main logic chipset 21 → memory bus 28 → system storage 22, as being example with peripheral unit 23, it can be by a shared base memory address register (Share Memory Base Address Registor:SMBAR) and a peripheral unit 23 required memory span registers (Share Memory Size Register:SMSR) row are provided, as long as the address that CPU (central processing unit) 20 is sent is the numerical value that is positioned at SMBAR+SMSR, main logic chipset 21 just can directly be delivered to its pairing data in the zone of peripheral unit 23 employed system storages 22, if the address is not in this scope, just follow old path to send, in this way, cooperation that need only driver just can significantly improve overall system efficiency.
Once as shown in Figure 2, each peripheral unit 23-25 is respectively with RAS signal RAS0, RAS1, RAS2, be coupled to a RAS IN signal to main logic chipset 21 in open-collector mode, the required storer of peripheral unit that can automatically switch in this way corresponds in the suitable system storage group, usually the employed storer of peripheral unit is all little, general situation is on the whole all less than a group (bank), so only have a line RAS line, and system storage 22 all has several groups usually, and can increase along with user's expansion, the RAS0 of peripheral unit 23 does not know and will receive that group in this way, otherwise just must limit storer is inserted in the fixing group, not only lose the elasticity of using, most inconvenience when operating with regard to the user, therefore, please refer to Figure 12, only show that peripheral unit 23 is example with RAS0 to the RAS_IN of main logic chipset 21 end, automatically it being switched in suitable system storage 22 groups via main logic chipset 21, is that " able to programme " is to increase the elasticity of system applies.
In sum, sharing system memory expansible type arbitration device of the present invention, utilize the setting of arbitration bus between peripheral unit and main logic chipset, obtain the purpose of peripheral unit energy sharing system memory, and according to arbitration structure of the present invention, only must arbitrate handshake and be arranged between peripheral unit and the main logic chipset, by the control of main logic chipset arbitration peripheral unit system storage with two or three.Moreover, when the present invention also can have the different processing demands of emergency to system memory access according to same peripheral unit, distinguish the processing sequence of a dish right of priority and high priority, make the main logic chipset can do the different response of emergency, use the raising system effectiveness.In addition, when the main logic chipset was badly in need of the control of system storage, the present invention also had the function of getting earlier, makes the control of peripheral unit get out of the way in advance, and the unlikely system cost that makes is of a specified duration excessively in the time of waiting for.In addition, structure of the present invention proposes the path of a high speed, makes to know by CPU (central processing unit) between peripheral unit affiliated area storer, only need via main bus, main logic chipset and memory bus row it, transmit therebetween the spent time to shorten.At last, respectively with the RAS signal, be coupled to a RAS_IN signal to main logic chipset through open-collector mode according to peripheral unit of the present invention, the required storer of peripheral unit that can automatically switch in this way corresponds in the suitable system storage group.
Though the present invention discloses as above with some preferred embodiments; right its is not in order to limit the present invention; anyly know this operator; in not breaking away from design of the present invention and scope; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining of the present invention.
Claims (7)
1, a kind of expansible type arbitration device of sharing system memory comprises:
One memory bus;
One system storage is coupled on this memory bus;
One main logic chipset is coupled on this memory bus, does exchanges data via this memory bus and this system storage;
A plurality of peripheral units are coupled to this memory bus, do exchanges data with this system storage respectively via this memory bus; Obtaining fair signal with one first request signal, one second request signal and between each this peripheral unit and this main logic chipset couples each other, wherein, described first and second request signals are to this main logic chipset by this peripheral unit, require to use the signal of this system storage, and this obtain fair signal be by this main logic chipset to this peripheral unit, allow this peripheral unit to use the signal of this system storage; When this peripheral unit makes this first request signal effective, when requiring to use this system storage, then to make this obtain fair signal in a very first time at interval effective for this main logic chipset, informs that this peripheral unit can use this system storage; When this peripheral unit makes this second request signal effective, when requiring to use this system storage, then to make this obtain fair signal in one second time interval effective for this main logic chipset, informs that this peripheral unit can use this system storage; And this second time interval is less than this very first time interval; And when this main logic chipset must use this system storage, then this main logic chipset made this obtain fair invalidating signal, and person one of in described first and second request signals that have been effective must make it invalid in one the 3rd time interval.
2, according to the expansible type arbitration device of the described sharing system memory of claim 1, wherein, each this peripheral unit dodges control RAS signal with a row address, is coupled to an input signal each other to this main logic chipset by open-collector mode.
3, the expansible type arbitration device of sharing system memory according to claim 1, wherein, described first and second request signals are in order to distinguish the processing of normal priority and high priority in this peripheral unit.
4, the expansible type arbitration device of sharing system memory according to claim 1, wherein, when if this peripheral unit one of only must have in this normal priority and this high priority person's processing, then can one of make in this second request signal and this first request signal the person keep invalid state respectively by a circuit.
5, a kind of expansible type arbitration device of sharing system memory comprises:
One memory bus;
One system storage is coupled on this memory bus;
One main logic chipset is coupled on this memory bus, does exchanges data via this memory bus and this system storage;
A plurality of peripheral units are coupled to this memory bus, do exchanges data with this system storage respectively via this memory bus; Obtaining fair signal with a request signal and between each this peripheral unit and this main logic chipset couples each other, wherein, this request signal is to this main logic chipset by this peripheral unit, require to use the request signal of this system storage, and this obtain fair signal be by this main logic chipset to this peripheral unit, allow this peripheral unit to use the handshaking signal of this system storage; When this peripheral unit makes this request signal effective, when requiring to use this system storage, then to make this obtain fair signal in a very first time at interval effective for this main logic chipset, informs that this peripheral unit can use this system storage; When this peripheral unit gating and after triggering this request signal, when require using this system storage, then to make this obtain fair signal in one second time interval effective for this main logic chipset, informs that this peripheral unit can use this system storage; And this second time interval is less than this very first time interval; And when this main logic chipset must use this system storage, then this main logic chipset made this obtain fair invalidating signal, and this request signal that has been effective must make it invalid in one the 3rd time interval.
6, the expansible type arbitration device of sharing system memory according to claim 5, wherein, each this peripheral unit is coupled to an input signal to this main logic chipset with a rwo address strobe signals each other by open-collector mode.
7, the expansible type arbitration device of sharing system memory according to claim 5, wherein, be by this request signal gating and triggering whether, distinguish the processing of high priority and normal priority in this peripheral unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 95117203 CN1095125C (en) | 1995-09-28 | 1995-09-28 | Extendible type arbitration device of sharing system memorizer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 95117203 CN1095125C (en) | 1995-09-28 | 1995-09-28 | Extendible type arbitration device of sharing system memorizer |
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| CN1146578A CN1146578A (en) | 1997-04-02 |
| CN1095125C true CN1095125C (en) | 2002-11-27 |
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| CN 95117203 Expired - Lifetime CN1095125C (en) | 1995-09-28 | 1995-09-28 | Extendible type arbitration device of sharing system memorizer |
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| US6330646B1 (en) * | 1999-01-08 | 2001-12-11 | Intel Corporation | Arbitration mechanism for a computer system having a unified memory architecture |
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