CN117637771A - Display panel and display terminal - Google Patents
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- CN117637771A CN117637771A CN202311669534.9A CN202311669534A CN117637771A CN 117637771 A CN117637771 A CN 117637771A CN 202311669534 A CN202311669534 A CN 202311669534A CN 117637771 A CN117637771 A CN 117637771A
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- 239000000758 substrate Substances 0.000 claims abstract description 77
- 229910052751 metal Inorganic materials 0.000 claims description 56
- 239000002184 metal Substances 0.000 claims description 56
- 238000009413 insulation Methods 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 16
- 238000004519 manufacturing process Methods 0.000 abstract description 14
- 239000010410 layer Substances 0.000 description 64
- 238000000059 patterning Methods 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000010354 integration Effects 0.000 description 5
- 239000011651 chromium Substances 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- -1 polyethylene terephthalate Polymers 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052779 Neodymium Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920000636 poly(norbornene) polymer Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Abstract
The application discloses a display panel and a display terminal. The display panel comprises a substrate and a driving device, wherein the driving device comprises an active part, a grid electrode insulating layer, a source electrode and a drain electrode, and a groove penetrates through a first contact part, a channel part and a second contact part of the active part; the grid electrode at least comprises a first grid part arranged in the groove, and the projection of the first grid part on the inner wall of the groove at least covers the projection of the channel part on the inner wall of the groove; the grid insulating layer is at least arranged between the grid and the channel part; the source electrode is electrically connected with the first contact portion, and the drain electrode is electrically connected with the second contact portion. By providing a trench over the active portion and forming a gate in the trench, the gate covers at least the channel portion, so that the channel length is the thickness of the channel portion, a driving device having a smaller channel length can be manufactured. By using the perimeter of the trench as the channel width, the channel width can be increased without increasing the volume of the drive device, thereby manufacturing a short-channel, small-volume drive device under the existing process.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display terminal.
Background
SOG technology (system on glass) refers to the integration of chip circuits such as a gate driving circuit, a source driving circuit, a timing controller and the like on a glass substrate, which can improve the integration level of a display panel, reduce the dependency on chips and reduce the cost. Implementing SOG technology requires increasing the maximum operating frequency and current density of the driving device. These all require a drive device with a shorter channel length, higher mobility and smaller volume.
The existing driving device is limited by the manufacturing process, and it is difficult to achieve the above requirements, so a new driving device having a short channel, small size, and high on-state current performance is needed.
Disclosure of Invention
The application provides a display panel and a display terminal, through optimizing the structure of a driving device, a short-channel and small-volume driving device can be manufactured under the existing manufacturing process, and the electrical property of the driving device is improved, so that the integrated chip circuit in the display panel is facilitated.
In order to solve the technical problems, the technical scheme provided by the application is as follows:
the application provides a display panel, the display panel includes:
a substrate on which a plurality of driving devices are provided;
the driving device includes:
an active portion disposed on the substrate, the active portion including a first contact portion, a channel portion, and a second contact portion that are stacked, the active portion having a trench, the trench penetrating through the first contact portion, the channel portion, and the second contact portion, the first contact portion being disposed on a side of the channel portion that is close to the substrate, and the second contact portion being disposed on a side of the channel portion that is away from the substrate;
the grid electrode at least comprises a first grid part, the first grid part is arranged in the groove, and the projection of the first grid part on the inner wall of the groove at least covers the projection of the channel part on the inner wall of the groove;
a gate insulating layer provided at least between the gate electrode and the channel portion;
a source electrically connected to the first contact and a drain electrically connected to the second contact;
a first metal trace electrically connected to the gate of the driving device;
and the second metal wire is electrically connected with the source electrode or the drain electrode of the driving device.
In the display panel of the present application, the gate electrode further includes a second gate portion located at one end of the first gate portion, and a third gate portion located at the opposite end of the first gate portion;
the second gate part is positioned in the groove and is electrically connected with the first gate part;
the third gate part is positioned at the outer edge of the opening of the groove and is electrically connected with the first gate part.
In the display panel of the application, the first metal wire is disposed on the substrate and located at one side of the active portion, which is close to the substrate, and the first metal wire is electrically connected with the second gate portion.
In the display panel of the application, the first metal wire is arranged on one side, far away from the substrate, of the driving device, and the first metal wire is electrically connected with the third grid part through a via hole.
In the display panel of the application, the first metal wire is disposed on the gate insulating layer and is located at a side of the active portion away from the substrate, and the first metal wire is electrically connected with the third gate portion.
In the display panel of the present application, the source electrode and the drain electrode are located on the same side of the driving device, and the source electrode and the drain electrode are electrically connected to the active portion through a via hole.
In the display panel of the application, the gate insulating layer is arranged in the groove in a closed mode, and the gate is located in an insulator formed in the groove by the gate insulating layer.
In the display panel of the present application, the source electrode and the drain electrode are located at different sides of the driving device, and the source electrode and the drain electrode are electrically connected to the active portion through a via hole.
In the display panel of the application, the gate insulating layer is arranged at the bottom of the groove and is provided with an opening, and the opening of the gate insulating layer is positioned on the second gate part of the gate.
In the display panel of the application, an included angle between the inner wall of the groove and the substrate is a right angle or an obtuse angle.
In the display panel of the present application, the orthographic projection of the groove on the substrate has any one of a circle, a rectangle, and a sector.
The application also provides a display terminal, which comprises the display panel.
The beneficial effects are that: the application discloses a display panel and a display terminal. The display panel comprises a substrate, a first metal wire and a second metal wire, wherein a plurality of driving devices are arranged on the substrate, each driving device comprises an active part, a grid electrode insulating layer, a source electrode and a drain electrode, the active part is arranged on the substrate and comprises a first contact part, a channel part and a second contact part which are stacked, the active part is provided with a groove, the groove penetrates through the first contact part, the channel part and the second contact part, the first contact part is arranged on one side, close to the substrate, of the channel part, and the second contact part is arranged on one side, deviating from the substrate, of the channel part; the grid electrode at least comprises a first grid part, the first grid part is arranged in the groove, and the projection of the first grid part on the inner wall of the groove at least covers the projection of the channel part on the inner wall of the groove; a gate insulating layer is provided at least between the gate electrode and the channel portion; the source electrode is electrically connected with the first contact part, and the drain electrode is electrically connected with the second contact part; the first metal wire is electrically connected with the grid electrode of the driving device; and the second metal wire is electrically connected with the source electrode or the drain electrode of the driving device. The trench is formed in the active portion, the gate insulating layer and the gate are formed in the trench, the projection of the first gate portion of the gate on the inner wall of the trench at least covers the projection of the channel portion on the inner wall of the trench, and the active portion comprises the first contact portion, the channel portion and the second contact portion which are sequentially stacked, so that the channel length is the thickness of the channel portion. By using the perimeter of the groove as the channel width, the channel width can be increased without increasing the volume of the driving device, so that the driving device with short channel and small volume can be manufactured by the existing manufacturing process, the electrical property of the driving device is improved, and the integration of the driving device in the display panel is facilitated.
Drawings
Technical solutions and other advantageous effects of the present application will be made apparent from the following detailed description of specific embodiments of the present application with reference to the accompanying drawings.
FIG. 1a is a schematic top view of a display panel according to the related art;
FIG. 1b is a schematic cross-sectional view of section A-A of FIG. 1 a;
FIG. 1c is a schematic cross-sectional view of section B-B of FIG. 1 a;
FIG. 2a is a schematic diagram illustrating a partial top view of a first display panel according to an embodiment of the present disclosure;
FIG. 2b is a schematic cross-sectional view of section C-C of FIG. 2 a;
FIG. 2c is a schematic cross-sectional view of the section D-D of FIG. 2 a;
FIG. 3a is a schematic top view of a second display panel according to an embodiment of the present disclosure;
FIG. 3b is a schematic cross-sectional view of the second E-E section of FIG. 3 a;
FIG. 3c is a schematic cross-sectional view of the second F-F section of FIG. 3 a;
FIG. 4a is a schematic cross-sectional view of the third E-E section of FIG. 3 a;
FIG. 4b is a schematic cross-sectional view of the third F-F section of FIG. 3 a;
FIG. 5a is a schematic cross-sectional view of the fourth E-E section of FIG. 3 a;
FIG. 5b is a schematic cross-sectional view of the fourth F-F section of FIG. 3 a;
fig. 6a to 6c are flowcharts illustrating a first manufacturing process of a display panel according to an embodiment of the present application.
Reference numerals illustrate:
the semiconductor device includes a substrate 11, a buffer layer 12, an active portion 20, a first contact portion 21, a channel portion 22, a second contact portion 23, a trench 30, a gate insulating layer 40, a first insulating portion 41, a second insulating portion 42, a third insulating portion 43, a gate 50, a first gate portion 51, a third gate portion 53, a second gate portion 52, a first metal wire 60, a source electrode 70, a drain electrode 80, and an interlayer insulating layer 90.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and explanation only and is not intended to limit the present application. In this application, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower positions of the device in actual use or operation, and specifically the orientation of the drawing figures; while "inner" and "outer" are for the outline of the device.
In the related art, a display panel includes a plurality of driving devices, which may be used for a pixel architecture, a gate driving circuit, and the like. SOG technology puts higher demands on the driving devices, and implementing SOG requires improving the integration level, maximum operating frequency and current density of the existing driving devices. These all require a drive device with shorter channel length, higher mobility and smaller volume.
As shown in fig. 1a to 1c, fig. 1a is a schematic view of a partial top view structure of a display panel in the related art; FIG. 1b is a schematic cross-sectional view of section A-A of FIG. 1 a; FIG. 1c is a schematic cross-sectional view of section B-B of FIG. 1 a. The active layer of the driving device in the related art is in a linear shape, the active layer ACT includes a channel S1 and doped portions S2 at both ends of the channel S1, and the two doped portions S2 are electrically connected to the source or drain of the source/drain layer SD, respectively. As shown in fig. 1b, the channel length L1 refers to the distance between the two doped portions S2, i.e., the distance over which current flows between the two doped portions S2. As shown in fig. 1c, the channel width W1 refers to the dimension of the channel S1 along a direction perpendicular to the channel length L1. The channel length L1 is generally greater than 2 microns, and increasing the channel width W1 requires a larger area, which is affected by the accuracy of the patterning process.
Aiming at the technical problems, the application provides the following scheme.
Referring to fig. 2a to 5b, the present application provides a display panel, the display panel includes a substrate 11, a first metal trace 60 and a second metal trace, a plurality of driving devices are disposed on the substrate 11, the driving devices include an active portion 20, a gate insulating layer 40 and a gate 50, the active portion 20 is disposed on the substrate 11, the active portion 20 includes a stacked first contact portion 21, a channel portion 22 and a second contact portion 23, the first contact portion 21 is disposed on a side of the channel portion 22 close to the substrate 11, the second contact portion 23 is disposed on a side of the channel portion 22 facing away from the substrate 11, the active portion 20 is provided with a trench 30, and the trench 30 penetrates through the first contact portion 21, the channel portion 22 and the second contact portion 23; the gate 50 includes at least a first gate portion 51, the first gate portion 51 being disposed in the trench 30, a projection of the first gate portion 51 onto an inner wall of the trench 30 at least covering a projection of the channel portion 22 onto the inner wall of the trench 30; the gate insulating layer 40 is disposed at least between the gate 50 and the channel portion 22; the source electrode 70 is electrically connected to the first contact portion 21, the drain electrode 80 is electrically connected to the second contact portion 23, the first metal trace 60 is electrically connected to the gate 50 of the driving device, and the second metal trace is electrically connected to the source electrode 70 or the drain electrode 80 of the driving device.
In the present embodiment, the surface of the substrate 11 is used to carry various film layers as a carrying surface, and the surface of the substrate 11 is parallel to the display surface of the display panel. The substrate 11 may be a flexible substrate or a rigid substrate. The material of the flexible substrate may be one of colorless Polyimide (PI), polycarbonate (PC), polynorbornene (PNB), polyethylene terephthalate (PET), and the like. The material of the rigid substrate may be glass or the like.
In the present embodiment, the active portion 20 includes a first contact portion 21, a channel portion 22, and a second contact portion 23 stacked in this order. With the above arrangement, the thickness of the channel portion 22 can be made the channel length. The thickness of the channel portion 22 refers to the dimension of the channel portion 22 in a direction perpendicular to the plane of the substrate 11. Since the process accuracy of the thickness dimension of the channel portion 22 is greater than the process accuracy of the dimension of the channel portion 22 in the direction parallel to the plane of the substrate 11 when the channel portion 22 is fabricated, a driving device having a smaller channel length can be fabricated.
The channel portion 22 may be polysilicon. The first contact portion 21 and the second contact portion 23 may be formed by ion doping the polysilicon, and conductivity of the doped first contact portion 21 and second contact portion 23 may be improved, so that ohmic contacts may be formed with the source electrode 70 and the drain electrode 80 of the driving device. The doped ions may be, but are not limited to, phosphorus ions, boron ions, and the like. The doping may be in the form of light doping or heavy doping, as this application is not limited.
The polysilicon of the channel portion 22 may be formed of amorphous silicon through an Excimer Laser Annealing (ELA) process. After the excimer laser annealing process is adopted, amorphous silicon is melted and recrystallized, no grain boundary can be realized in the direction of the channel part 22 perpendicular to the plane of the substrate 11, namely, the channel length direction is realized as a single grain, the grain size is about 0.3 micron, a short channel is realized, and the electrical property of a driving device is improved.
In the present embodiment, the active portion 20 is provided with a trench 30, and the trench 30 penetrates the first contact portion 21, the channel portion 22, and the second contact portion 23. Note that, the trench 30 may be disposed in a middle region of the three-layer stack of the active portion 20, that is, the trench 30 forms a hole in the active portion 20, and the trench 30 is located in the active portion 20. The trench 30 may also be provided in an edge region of the three-layer stack of the active portion 20, i.e. the trench 30 partially overlaps the active portion 20. When the trench 30 is located in the active portion 20, the perimeter of the trench 30 can be used as the width of the channel, so that the width-to-length ratio of the channel can be further increased, the width-to-length ratio of the channel is the ratio of the width of the channel to the length of the channel, and the on-state current of the driving device is in direct proportion to the width-to-length ratio of the channel, so that the on-state current of the driving device can be further improved, and the electrical property of the driving device is improved.
It should be understood that the shape of the active portion 20 may be set as desired. For example, the shape of the orthographic projection of the active portion 20 on the substrate 11 may be a circle, a rectangle, a sector, or the like. Correspondingly, the shape of the trench 30 may also be adapted to the shape of the active portion 20. For example, the contour line of the trench 30 is uniformly spaced from the contour line of the active portion 20, but is not limited thereto. The trench 30 may be formed in a shape having a larger circumference in the same area, thereby increasing the width-to-length ratio of the channel, which is the ratio of the channel width to the channel length.
Alternatively, the shape of the orthographic projection of the trench 30 on the substrate 11 is a circle, a rectangle, a sector.
In some embodiments, the inner walls of the trench 30 form a right or obtuse angle with the substrate 11. The angle of the obtuse angle can be adjusted according to the patterning process. When the inner wall of the trench 30 forms a right angle with the substrate 11, the volume of the driving device can be reduced. When the included angle between the inner wall of the trench 30 and the substrate 11 is an obtuse angle, the gate 50 is easy to cover the inner wall of the trench 30, so as to avoid the gate 50 from being broken.
In the present embodiment, the gate insulating layer 40 is disposed between the gate electrode 50 and the channel portion 22. The gate insulating layer 40 may be formed of a stack of one or more layers of materials such as silicon nitride, silicon oxide, and silicon oxynitride, but is not limited thereto. The gate insulating layer 40 may separate the gate 50 and the channel portion 22, achieving insulation between the gate 50 and the channel portion 22.
By the arrangement, the perimeter of the groove 30 is used as the channel width, so that the channel width can be increased without increasing the volume of the driving device, and the driving device with short channel and small volume can be manufactured by the existing manufacturing process, so that the electrical property of the driving device is improved, and the integration of a chip circuit in the display panel is facilitated.
In the present embodiment, the gate 50 includes at least a first gate portion 51, the first gate portion 51 is disposed in the trench 30, and the first gate portion 51 is disposed at least corresponding to the channel portion 22.
The gate electrode 50 is a conductive material, and the gate electrode 50 may be formed of any one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but is not limited thereto.
In the present embodiment, the source electrode 70 and the drain electrode 80 are conductive materials, and the source electrode 70 and the drain electrode 80 may be formed of any one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but are not limited thereto.
In this embodiment, the driving device may be a thin film transistor or the like.
In the present embodiment, the first metal trace 60 is electrically connected to the gate. The first metal trace 60 may be disposed on the same layer as the gate or on a different layer.
In the present embodiment, the second metal trace is electrically connected to the source 70 or the drain 80. The second metal trace may be disposed in the same layer as the source electrode 70 or in different layers, or the second metal trace may be disposed in the same layer as the drain electrode 80 or in different layers.
In the display panel of the present application, as shown in fig. 2a to 5b, the gate electrode 50 further includes a second gate portion 52 located at one end of the first gate portion 51, and a third gate portion 53 located at the opposite end of the first gate portion 51; the second gate portion 52 is located in the trench 30 and is electrically connected to the first gate portion 51; the third gate portion 53 is located at an opening outer edge of the trench 30 and is electrically connected to the first gate portion 51.
In the present embodiment, the gate 50 includes a first gate portion 51, a second gate portion 52, and a third gate portion 53 connected. That is, the gate 50 continuously covers the bottom and inner walls of the trench 30 and extends to the outer edge of the opening of the trench 30. The first, second, and third gate portions 51, 52, and 53 may be formed by the same patterning process.
In the display panel of the present application, as shown in fig. 2a to 3c, the first metal trace 60 is disposed on the substrate 11 and is located on a side of the active portion 20 near the substrate 11, and the first metal trace 60 is electrically connected to the second gate portion 52.
In this embodiment, as shown in fig. 2a to 2C, fig. 2a is a schematic partial top view of a first display panel provided in the embodiment of the present application, fig. 2b is a schematic cross-sectional structure of a C-C section in fig. 2a, and fig. 2C is a schematic cross-sectional structure of a D-D section in fig. 2 a. The front projection of the first contact portion 21 on the substrate 11 coincides with the front projection of the second contact portion 23 on the substrate 11, and the active portion 20 may be manufactured by the same patterning process, thereby simplifying the manufacturing process of the display panel. The first contact portion 21 is substantially identical in shape to the second contact portion 23, and the first contact portion 21 is flush with the side wall of the second contact portion 23.
In this embodiment, as shown in fig. 3a to 3c, fig. 3a is a schematic partial top view of a second display panel provided in the embodiment of the present application, fig. 3b is a schematic cross-sectional structure of a second E-E section in fig. 3a, and fig. 3c is a schematic cross-sectional structure of a second F-F section in fig. 3 a. The second display panel is different from the first display panel in that the projection area of the second contact portion 23 is smaller than the projection area of the first contact portion 21, the display panel includes a first metal trace 60, the first metal trace 60 is disposed on the substrate 11 and is located on a side of the active portion 20 near the substrate 11, the trench 30 exposes the first metal trace 60, and the first metal trace 60 is electrically connected to the first gate portion 51.
In the present embodiment, the first metal trace 60 is electrically connected to the second gate portion 52. By the arrangement, the connection between the first metal wire 60 and the gate 50 does not occupy extra wiring space, and the size of the driving device is reduced.
In this embodiment, a buffer layer 12 is further disposed between the substrate 11 and the active portion 20, and the trench 30 penetrates the buffer layer 12 to expose the first metal trace 60.
In the display panel of the present application, as shown in fig. 4a to 4b, the first metal trace 60 is disposed on the gate insulating layer 40 and is located on a side of the active portion 20 away from the substrate 11, and the first metal trace 60 is electrically connected to the third gate portion 53.
In this embodiment, as shown in fig. 4a and 4b, fig. 4a is a schematic cross-sectional structure of the third E-E section in fig. 3a, and fig. 4b is a schematic cross-sectional structure of the third F-F section in fig. 3 a. The first metal trace 60 is electrically connected to the third gate portion 53. In this embodiment, the first metal wire 60 and the third gate portion 53 are disposed on the same layer, so that the same Zhang Guangzhao can be used to manufacture the first metal wire 60 and the third gate portion 53, thereby simplifying the manufacturing process of the display panel.
In the display panel of the present application, as shown in fig. 5a to 5b, the first metal trace 60 is disposed on a side of the driving device away from the substrate 11, and the first metal trace 60 is electrically connected to the third gate portion 53 through a via hole.
In this embodiment, as shown in fig. 5a and 5b, fig. 5a is a schematic cross-sectional structure of the fourth E-E section in fig. 3a, and fig. 5b is a schematic cross-sectional structure of the fourth F-F section in fig. 3 a. The first metal trace 60 is disposed in the same layer as the source electrode 70 and the drain electrode 80, and the first metal trace 60 is electrically connected to the third gate portion 53 through a via. By providing the first metal wiring 60, the source electrode 70, and the drain electrode 80 in the same layer, the first metal wiring 60, the source electrode 70, and the drain electrode 80 can be formed by the same layer Zhang Guangzhao, and the process for manufacturing the display panel can be simplified.
In all embodiments of the present application, the source electrode 70 and the drain electrode 80 are located on the same side of the driving device, and the source electrode 70 and the drain electrode 80 are electrically connected to the active portion 20 through vias.
Alternatively, in some embodiments, the source electrode 70 and the drain electrode 80 may be disposed at a side of the active portion 20 near the substrate 11, the source electrode 70 may be electrically connected to the first contact portion 21 through a via, and the drain electrode 80 may be electrically connected to the second contact portion 23 through a via. The orthographic projection of the second contact portion 23 on the substrate 11 covers the orthographic projection of the first contact portion 21 on the substrate 11, and the orthographic projection area of the second contact portion 23 is larger than the orthographic projection area of the first contact portion 21.
Alternatively, in other embodiments, the source electrode 70 and the drain electrode 80 may be disposed on a side of the active portion 20 facing away from the substrate 11, the source electrode 70 may be electrically connected to the first contact portion 21 through a via, and the drain electrode 80 may be electrically connected to the second contact portion 23 through a via. The orthographic projection of the first contact portion 21 on the substrate 11 covers the orthographic projection of the second contact portion 23 on the substrate 11, and the orthographic projection area of the first contact portion 21 is larger than the orthographic projection area of the second contact portion 23.
In the display panel of the present application, the gate insulating layer 40 is disposed in the trench 30 in a closed manner, and the gate 50 is located in the insulator formed in the trench 30 by the gate insulating layer 40.
In the present embodiment, the gate insulating layer 40 is disposed in a closed manner in the trench 30. That is, the gate insulating layer 40 includes the first insulating portion 41, the second insulating portion 42, and the third insulating portion 43 in succession, the first insulating portion 41 and the second insulating portion 42 being disposed between the gate 50 and the channel portion 22, the first insulating portion 41 being disposed corresponding to the first gate portion 51, and the second insulating portion 42 being disposed corresponding to the third gate portion 53. The first insulating portion 41 covers the inner wall of the trench 30. The second insulating portion 42 covers a surface of the active portion 20 on a side facing away from the substrate 11. The third insulating portion 43 is provided in the trench 30 and covers the bottom surface of the trench 30.
In the display panel of the present application, the source electrode 70 and the drain electrode 80 are located at different sides of the driving device, and the source electrode 70 and the drain electrode 80 are electrically connected to the active portion 20 through the via hole.
In some embodiments, the source 70 is disposed on a side of the active portion 20 near the substrate 11, and the drain 80 is disposed on a side of the active portion 20 away from the substrate 11.
In some embodiments, the source 70 is disposed on a side of the active portion 20 facing away from the substrate 11, and the drain 80 is disposed on a side of the active portion 20 adjacent to the substrate 11.
It should be appreciated that when the source 70 and the drain 80 are located on different sides of the drive device, the shape of the first contact 21 and the second contact 23 may be substantially the same, and the first contact 21 is flush with the sidewall of the second contact 23. That is, the front projection of the first contact portion 21 on the substrate 11 and the front projection of the second contact portion 23 on the substrate 11 are substantially coincident, and the active portion 20 may be manufactured by the same patterning process, thereby simplifying the manufacturing process of the display panel.
Further, the orthographic projections of the source electrode 70 and the drain electrode 80 on the substrate 11 may be located in the orthographic projection of the first contact portion 21 on the substrate 11, so as to reduce the volume of the driving device.
In the display panel of the present application, the gate insulating layer 40 is disposed at the bottom of the trench 30 with an opening, and the opening of the gate insulating layer 40 is located on the second gate portion 52 of the gate 50.
In some embodiments, the gate insulating layer 40 includes a continuous first insulating portion 41 and second insulating portion 42, where the first insulating portion 41 and the second insulating portion 42 are disposed between the gate 50 and the channel portion 22, the first insulating portion 41 is disposed corresponding to the first gate portion 51, and the second insulating portion 42 is disposed corresponding to the third gate portion 53. The first insulating portion 41 covers the inner wall of the trench 30. The second insulating portion 42 covers a surface of the active portion 20 on a side facing away from the substrate 11.
The gate insulating layer 40 is provided to be open at the bottom of the trench 30 means that the gate insulating layer 40 does not cover the bottom surface of the trench 30.
In some embodiments, an interlayer insulating layer 90 may be disposed on a side of the driving device facing away from the substrate 11, and the interlayer insulating layer 90 is an insulating film layer. The interlayer insulating layer 90 may be formed of a stack of one or more layers of materials such as silicon nitride, silicon oxide, and silicon oxynitride, but is not limited thereto.
In the present application, the metal layer may be formed by physical vapor deposition (Physical Vapor Deposition, PVD), and the semiconductor layer may be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD).
As shown in fig. 6a to 6c, a process for manufacturing the display panel of the present application will be described below by taking a first display panel as an example.
In step S10, a substrate 11 is provided, and a patterning process is used to form the first metal trace 60 and the source electrode 70 on the substrate 11.
In step S20, a buffer layer 12 is formed on the first metal trace 60 and the source electrode 70, and the buffer layer 12 is patterned to form a via hole, wherein the via hole is disposed opposite to the source electrode 70.
In step S30, the stacked first contact portion 21, channel portion 22, and second contact portion 23 are formed on the buffer layer 12, and the first contact portion 21 fills the via hole and is electrically connected to the source electrode 70.
Alternatively, the orthographic projections of the first contact portion 21, the channel portion 22, and the second contact portion 23 on the substrate 11 are all overlapped, so that one photomask may be used to pattern the active portion 20, thereby simplifying the manufacturing process of the display panel.
In step S40, a trench 30 is formed on the active portion 20, and the trench 30 penetrates the second contact portion 23, the channel portion 22, and the first contact portion 21 in order, and exposes the first metal trace 60.
In step S50, a gate insulating layer 40 is formed on the active portion 20, the first insulating portion 41 of the gate insulating layer 40 located in the trench 30 covers the inner wall of the trench 30, and the first metal trace 60 is exposed by the gate insulating layer 40.
In step S60, the gate 50 is formed on the gate insulating layer 40, the first gate portion 51 of the gate 50 located in the trench 30 covers the first insulating portion 41, and the first gate portion 51 is electrically connected to the first metal trace 60. The gate 50 is formed at the edge of the trench 30 with a third gate portion 53 continuous with the first gate portion 51.
In step S70, an interlayer insulating layer 90 is formed on the gate electrode 50, and a via hole is formed on the interlayer insulating layer 90 by a patterning process, the via hole being disposed opposite to the second contact portion 23, the via hole exposing the second contact portion 23.
The via hole is spaced apart from the third gate portion 53.
In step S80, the drain electrode 80 is formed on the interlayer insulating layer 90, and the drain electrode 80 is filled with a via hole to electrically connect to the second contact portion 23.
In the present application, the patterning process includes the steps of coating photoresist, exposing, developing, etching, stripping photoresist, etc., and a desired pattern can be formed on the film layer through the patterning process.
The manufacturing processes of the second display panel, the third display panel and the fourth display panel are similar, and will not be repeated here.
The application also provides a display terminal, which comprises the display panel.
In this embodiment, the display terminal may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The display panel and the display terminal provided by the embodiments of the present application are described in detail, and specific examples are applied to illustrate the principles and the implementation of the present application, and the description of the above embodiments is only used to help understand the technical solution and the core idea of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (12)
1. A display panel, comprising:
a substrate on which a plurality of driving devices are provided;
the driving device includes:
an active portion disposed on the substrate, the active portion including a first contact portion, a channel portion, and a second contact portion that are stacked, the active portion having a trench, the trench penetrating through the first contact portion, the channel portion, and the second contact portion, the first contact portion being disposed on a side of the channel portion that is close to the substrate, and the second contact portion being disposed on a side of the channel portion that is away from the substrate;
the grid electrode at least comprises a first grid part, the first grid part is arranged in the groove, and the projection of the first grid part on the inner wall of the groove at least covers the projection of the channel part on the inner wall of the groove;
a gate insulating layer provided at least between the gate electrode and the channel portion;
a source electrically connected to the first contact and a drain electrically connected to the second contact;
a first metal trace electrically connected to the gate of the driving device;
and the second metal wire is electrically connected with the source electrode or the drain electrode of the driving device.
2. The display panel of claim 1, wherein the gate electrode further comprises a second gate portion at one end of the first gate portion and a third gate portion at an opposite end of the first gate portion;
the second gate part is positioned in the groove and is electrically connected with the first gate part;
the third gate part is positioned at the outer edge of the opening of the groove and is electrically connected with the first gate part.
3. The display panel of claim 2, wherein the first metal trace is disposed on the substrate and on a side of the active portion adjacent to the substrate, the first metal trace being electrically connected to the second gate portion.
4. The display panel of claim 2, wherein the first metal trace is disposed on a side of the driving device away from the substrate, the first metal trace being electrically connected to the third gate portion through a via.
5. The display panel of claim 2, wherein the first metal trace is disposed on the gate insulating layer and on a side of the active portion away from the substrate, the first metal trace being electrically connected to the third gate portion.
6. The display panel according to any one of claims 3 to 5, wherein the source and the drain are located on the same side of the driving device, and the source and the drain are each electrically connected to the active portion through a via.
7. The display panel of claim 6, wherein the gate insulation layer is disposed closed within the trench, and the gate is located within an insulator formed by the gate insulation layer within the trench.
8. The display panel according to any one of claims 3 to 5, wherein the source and the drain are located on different sides of the driving device, the source and the drain each being electrically connected to the active portion through a via.
9. The display panel of claim 8, wherein the gate insulating layer is provided with an opening at the bottom of the trench, the opening of the gate insulating layer being located on the second gate portion of the gate.
10. The display panel of claim 1, wherein an angle between an inner wall of the trench and the substrate is a right angle or an obtuse angle.
11. The display panel of claim 1, wherein the orthographic projection of the trench on the substrate has any one of a circular shape, a rectangular shape, and a fan shape.
12. A display terminal comprising the display panel according to any one of claims 1 to 11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311669534.9A CN117637771A (en) | 2023-12-05 | 2023-12-05 | Display panel and display terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311669534.9A CN117637771A (en) | 2023-12-05 | 2023-12-05 | Display panel and display terminal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117637771A true CN117637771A (en) | 2024-03-01 |
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ID=90033709
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311669534.9A Pending CN117637771A (en) | 2023-12-05 | 2023-12-05 | Display panel and display terminal |
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| Country | Link |
|---|---|
| CN (1) | CN117637771A (en) |
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2023
- 2023-12-05 CN CN202311669534.9A patent/CN117637771A/en active Pending
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